1 /*-
2 * Copyright (c) 2015, 2019 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Synopsys® DesignWare® APB General Purpose Programming I/O
33 * (DW_apb_gpio) peripheral.
34 *
35 * Chapter 22, Cyclone V Device Handbook (CV-5V2 2014.07.22)
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/bus.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/rman.h>
45 #include <sys/timeet.h>
46 #include <sys/timetc.h>
47 #include <sys/watchdog.h>
48 #include <sys/mutex.h>
49 #include <sys/gpio.h>
50 #include <sys/reboot.h>
51
52 #include <dev/gpio/gpiobusvar.h>
53 #include <dev/ofw/openfirm.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
60
61 #include "gpio_if.h"
62 #include "dwgpio_if.h"
63
64 #define READ4(_sc, _reg) DWGPIO_READ((_sc)->parent, _reg)
65 #define WRITE4(_sc, _reg, _val) DWGPIO_WRITE((_sc)->parent, _reg, _val)
66
67 #define GPIO_SWPORT_DR(n) (0x00 + 0xc * (n)) /* Port n Data Register */
68 #define GPIO_SWPORT_DDR(n) (0x04 + 0xc * (n)) /* Port n Data Direction */
69 #define GPIO_INTEN 0x30 /* Interrupt Enable Register */
70 #define GPIO_INTMASK 0x34 /* Interrupt Mask Register */
71 #define GPIO_INTTYPE_LEVEL 0x38 /* Interrupt Level Register */
72 #define GPIO_INT_POLARITY 0x3C /* Interrupt Polarity Register */
73 #define GPIO_INTSTATUS 0x40 /* Interrupt Status Register */
74 #define GPIO_RAW_INTSTATUS 0x44 /* Raw Interrupt Status Register */
75 #define GPIO_DEBOUNCE 0x48 /* Debounce Enable Register */
76 #define GPIO_PORTA_EOI 0x4C /* Clear Interrupt Register */
77 #define GPIO_EXT_PORT(n) (0x50 + 0x4 * (n)) /* External Port n */
78 #define GPIO_LS_SYNC 0x60 /* Synchronization Level Register */
79 #define GPIO_ID_CODE 0x64 /* ID Code Register */
80 #define GPIO_VER_ID_CODE 0x6C /* GPIO Version Register */
81 #define GPIO_CONFIG_REG2 0x70 /* Configuration Register 2 */
82 #define ENCODED_ID_PWIDTH_M 0x1f /* Width of GPIO Port N Mask */
83 #define ENCODED_ID_PWIDTH_S(n) (5 * n) /* Width of GPIO Port N Shift */
84 #define GPIO_CONFIG_REG1 0x74 /* Configuration Register 1 */
85
86 #define NR_GPIO_MAX 32 /* Maximum pins per port */
87
88 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
89 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
90
91 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
92
93 /*
94 * GPIO interface
95 */
96 static device_t dwgpio_get_bus(device_t);
97 static int dwgpio_pin_max(device_t, int *);
98 static int dwgpio_pin_getcaps(device_t, uint32_t, uint32_t *);
99 static int dwgpio_pin_getname(device_t, uint32_t, char *);
100 static int dwgpio_pin_getflags(device_t, uint32_t, uint32_t *);
101 static int dwgpio_pin_setflags(device_t, uint32_t, uint32_t);
102 static int dwgpio_pin_set(device_t, uint32_t, unsigned int);
103 static int dwgpio_pin_get(device_t, uint32_t, unsigned int *);
104 static int dwgpio_pin_toggle(device_t, uint32_t pin);
105
106 struct dwgpio_softc {
107 device_t dev;
108 device_t busdev;
109 device_t parent;
110 struct mtx sc_mtx;
111 int gpio_npins;
112 struct gpio_pin gpio_pins[NR_GPIO_MAX];
113 phandle_t node;
114 int port;
115 };
116
117 static int
dwgpio_probe(device_t dev)118 dwgpio_probe(device_t dev)
119 {
120
121 if (!ofw_bus_status_okay(dev))
122 return (ENXIO);
123
124 if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio-port"))
125 return (ENXIO);
126
127 device_set_desc(dev, "DesignWare General-Purpose I/O Interface");
128 return (BUS_PROBE_DEFAULT);
129 }
130
131 static int
dwgpio_attach(device_t dev)132 dwgpio_attach(device_t dev)
133 {
134 struct dwgpio_softc *sc;
135 int version;
136 int nr_pins;
137 int cfg2;
138 int i;
139
140 sc = device_get_softc(dev);
141 sc->parent = device_get_parent(dev);
142 sc->node = ofw_bus_get_node(dev);
143 sc->dev = dev;
144 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
145
146 if ((OF_getencprop(sc->node, "reg", &sc->port, sizeof(sc->port))) <= 0)
147 return (ENXIO);
148
149 printf("port %d\n", sc->port);
150
151 version = READ4(sc, GPIO_VER_ID_CODE);
152 if (boothowto & RB_VERBOSE)
153 device_printf(sc->dev, "Version = 0x%08x\n", version);
154
155 /* Grab number of pins from hardware. */
156 cfg2 = READ4(sc, GPIO_CONFIG_REG2);
157 nr_pins = (cfg2 >> ENCODED_ID_PWIDTH_S(sc->port)) & \
158 ENCODED_ID_PWIDTH_M;
159 sc->gpio_npins = nr_pins + 1;
160
161 for (i = 0; i < sc->gpio_npins; i++) {
162 sc->gpio_pins[i].gp_pin = i;
163 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
164 sc->gpio_pins[i].gp_flags =
165 (READ4(sc, GPIO_SWPORT_DDR(sc->port)) & (1 << i)) ?
166 GPIO_PIN_OUTPUT: GPIO_PIN_INPUT;
167 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
168 "dwgpio%d.%d", device_get_unit(dev), i);
169 }
170 sc->busdev = gpiobus_add_bus(dev);
171 if (sc->busdev == NULL) {
172 mtx_destroy(&sc->sc_mtx);
173 return (ENXIO);
174 }
175
176 bus_attach_children(dev);
177 return (0);
178 }
179
180 static device_t
dwgpio_get_bus(device_t dev)181 dwgpio_get_bus(device_t dev)
182 {
183 struct dwgpio_softc *sc;
184
185 sc = device_get_softc(dev);
186
187 return (sc->busdev);
188 }
189
190 static int
dwgpio_pin_max(device_t dev,int * maxpin)191 dwgpio_pin_max(device_t dev, int *maxpin)
192 {
193 struct dwgpio_softc *sc;
194
195 sc = device_get_softc(dev);
196
197 *maxpin = sc->gpio_npins - 1;
198
199 return (0);
200 }
201
202 static int
dwgpio_pin_getname(device_t dev,uint32_t pin,char * name)203 dwgpio_pin_getname(device_t dev, uint32_t pin, char *name)
204 {
205 struct dwgpio_softc *sc;
206 int i;
207
208 sc = device_get_softc(dev);
209 for (i = 0; i < sc->gpio_npins; i++) {
210 if (sc->gpio_pins[i].gp_pin == pin)
211 break;
212 }
213
214 if (i >= sc->gpio_npins)
215 return (EINVAL);
216
217 GPIO_LOCK(sc);
218 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
219 GPIO_UNLOCK(sc);
220
221 return (0);
222 }
223
224 static int
dwgpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)225 dwgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
226 {
227 struct dwgpio_softc *sc;
228 int i;
229
230 sc = device_get_softc(dev);
231 for (i = 0; i < sc->gpio_npins; i++) {
232 if (sc->gpio_pins[i].gp_pin == pin)
233 break;
234 }
235
236 if (i >= sc->gpio_npins)
237 return (EINVAL);
238
239 GPIO_LOCK(sc);
240 *caps = sc->gpio_pins[i].gp_caps;
241 GPIO_UNLOCK(sc);
242
243 return (0);
244 }
245
246 static int
dwgpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)247 dwgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
248 {
249 struct dwgpio_softc *sc;
250 int i;
251
252 sc = device_get_softc(dev);
253 for (i = 0; i < sc->gpio_npins; i++) {
254 if (sc->gpio_pins[i].gp_pin == pin)
255 break;
256 }
257
258 if (i >= sc->gpio_npins)
259 return (EINVAL);
260
261 GPIO_LOCK(sc);
262 *flags = sc->gpio_pins[i].gp_flags;
263 GPIO_UNLOCK(sc);
264
265 return (0);
266 }
267
268 static int
dwgpio_pin_get(device_t dev,uint32_t pin,unsigned int * val)269 dwgpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
270 {
271 struct dwgpio_softc *sc;
272 int i;
273
274 sc = device_get_softc(dev);
275 for (i = 0; i < sc->gpio_npins; i++) {
276 if (sc->gpio_pins[i].gp_pin == pin)
277 break;
278 }
279
280 if (i >= sc->gpio_npins)
281 return (EINVAL);
282
283 GPIO_LOCK(sc);
284 *val = (READ4(sc, GPIO_EXT_PORT(sc->port)) & (1 << i)) ? 1 : 0;
285 GPIO_UNLOCK(sc);
286
287 return (0);
288 }
289
290 static int
dwgpio_pin_toggle(device_t dev,uint32_t pin)291 dwgpio_pin_toggle(device_t dev, uint32_t pin)
292 {
293 struct dwgpio_softc *sc;
294 int reg;
295 int i;
296
297 sc = device_get_softc(dev);
298 for (i = 0; i < sc->gpio_npins; i++) {
299 if (sc->gpio_pins[i].gp_pin == pin)
300 break;
301 }
302
303 if (i >= sc->gpio_npins)
304 return (EINVAL);
305
306 GPIO_LOCK(sc);
307 reg = READ4(sc, GPIO_SWPORT_DR(sc->port));
308 if (reg & (1 << i))
309 reg &= ~(1 << i);
310 else
311 reg |= (1 << i);
312 WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);
313 GPIO_UNLOCK(sc);
314
315 return (0);
316 }
317
318
319 static void
dwgpio_pin_configure(struct dwgpio_softc * sc,struct gpio_pin * pin,unsigned int flags)320 dwgpio_pin_configure(struct dwgpio_softc *sc,
321 struct gpio_pin *pin, unsigned int flags)
322 {
323 int reg;
324
325 GPIO_LOCK(sc);
326
327 /*
328 * Manage input/output
329 */
330
331 reg = READ4(sc, GPIO_SWPORT_DDR(sc->port));
332 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
333 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
334 if (flags & GPIO_PIN_OUTPUT) {
335 pin->gp_flags |= GPIO_PIN_OUTPUT;
336 reg |= (1 << pin->gp_pin);
337 } else {
338 pin->gp_flags |= GPIO_PIN_INPUT;
339 reg &= ~(1 << pin->gp_pin);
340 }
341 }
342
343 WRITE4(sc, GPIO_SWPORT_DDR(sc->port), reg);
344 GPIO_UNLOCK(sc);
345 }
346
347
348 static int
dwgpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)349 dwgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
350 {
351 struct dwgpio_softc *sc;
352 int i;
353
354 sc = device_get_softc(dev);
355 for (i = 0; i < sc->gpio_npins; i++) {
356 if (sc->gpio_pins[i].gp_pin == pin)
357 break;
358 }
359
360 if (i >= sc->gpio_npins)
361 return (EINVAL);
362
363 dwgpio_pin_configure(sc, &sc->gpio_pins[i], flags);
364
365 return (0);
366 }
367
368 static int
dwgpio_pin_set(device_t dev,uint32_t pin,unsigned int value)369 dwgpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
370 {
371 struct dwgpio_softc *sc;
372 int reg;
373 int i;
374
375 sc = device_get_softc(dev);
376
377 for (i = 0; i < sc->gpio_npins; i++) {
378 if (sc->gpio_pins[i].gp_pin == pin)
379 break;
380 }
381
382 if (i >= sc->gpio_npins)
383 return (EINVAL);
384
385 GPIO_LOCK(sc);
386 reg = READ4(sc, GPIO_SWPORT_DR(sc->port));
387 if (value)
388 reg |= (1 << i);
389 else
390 reg &= ~(1 << i);
391 WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);
392 GPIO_UNLOCK(sc);
393
394 return (0);
395 }
396
397 static device_method_t dwgpio_methods[] = {
398 DEVMETHOD(device_probe, dwgpio_probe),
399 DEVMETHOD(device_attach, dwgpio_attach),
400
401 /* GPIO protocol */
402 DEVMETHOD(gpio_get_bus, dwgpio_get_bus),
403 DEVMETHOD(gpio_pin_max, dwgpio_pin_max),
404 DEVMETHOD(gpio_pin_getname, dwgpio_pin_getname),
405 DEVMETHOD(gpio_pin_getcaps, dwgpio_pin_getcaps),
406 DEVMETHOD(gpio_pin_getflags, dwgpio_pin_getflags),
407 DEVMETHOD(gpio_pin_get, dwgpio_pin_get),
408 DEVMETHOD(gpio_pin_toggle, dwgpio_pin_toggle),
409 DEVMETHOD(gpio_pin_setflags, dwgpio_pin_setflags),
410 DEVMETHOD(gpio_pin_set, dwgpio_pin_set),
411 { 0, 0 }
412 };
413
414 static driver_t dwgpio_driver = {
415 "gpio",
416 dwgpio_methods,
417 sizeof(struct dwgpio_softc),
418 };
419
420 DRIVER_MODULE(dwgpio, dwgpiobus, dwgpio_driver, 0, 0);
421