1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2005-2014, 2018-2023, 2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #ifndef __iwl_trans_h__
8 #define __iwl_trans_h__
9
10 #include <linux/ieee80211.h>
11 #include <linux/mm.h> /* for page_address */
12 #include <linux/lockdep.h>
13 #include <linux/kernel.h>
14
15 #include "iwl-debug.h"
16 #include "iwl-config.h"
17 #include "fw/img.h"
18 #include "iwl-op-mode.h"
19 #include <linux/firmware.h>
20 #include "fw/api/cmdhdr.h"
21 #include "fw/api/txq.h"
22 #include "fw/api/dbg-tlv.h"
23 #include "iwl-dbg-tlv.h"
24
25 /**
26 * DOC: Transport layer - what is it ?
27 *
28 * The transport layer is the layer that deals with the HW directly. It provides
29 * the PCIe access to the underlying hardwarwe. The transport layer doesn't
30 * provide any policy, algorithm or anything of this kind, but only mechanisms
31 * to make the HW do something. It is not completely stateless but close to it.
32 */
33
34 /**
35 * DOC: Life cycle of the transport layer
36 *
37 * The transport layer has a very precise life cycle.
38 *
39 * 1) A helper function is called during the module initialization and
40 * registers the bus driver's ops with the transport's alloc function.
41 * 2) Bus's probe calls to the transport layer's allocation functions.
42 * Of course this function is bus specific.
43 * 3) This allocation functions will spawn the upper layer which will
44 * register mac80211.
45 *
46 * 4) At some point (i.e. mac80211's start call), the op_mode will call
47 * the following sequence:
48 * start_hw
49 * start_fw
50 *
51 * 5) Then when finished (or reset):
52 * stop_device
53 *
54 * 6) Eventually, the free function will be called.
55 */
56
57 /* default preset 0 (start from bit 16)*/
58 #define IWL_FW_DBG_DOMAIN_POS 16
59 #define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS)
60
61 #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON
62
63 #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */
64 #define FH_RSCSR_FRAME_INVALID 0x55550000
65 #define FH_RSCSR_FRAME_ALIGN 0x40
66 #define FH_RSCSR_RPA_EN BIT(25)
67 #define FH_RSCSR_RADA_EN BIT(26)
68 #define FH_RSCSR_RXQ_POS 16
69 #define FH_RSCSR_RXQ_MASK 0x3F0000
70
71 struct iwl_rx_packet {
72 /*
73 * The first 4 bytes of the RX frame header contain both the RX frame
74 * size and some flags.
75 * Bit fields:
76 * 31: flag flush RB request
77 * 30: flag ignore TC (terminal counter) request
78 * 29: flag fast IRQ request
79 * 28-27: Reserved
80 * 26: RADA enabled
81 * 25: Offload enabled
82 * 24: RPF enabled
83 * 23: RSS enabled
84 * 22: Checksum enabled
85 * 21-16: RX queue
86 * 15-14: Reserved
87 * 13-00: RX frame size
88 */
89 __le32 len_n_flags;
90 struct iwl_cmd_header hdr;
91 u8 data[];
92 } __packed;
93
iwl_rx_packet_len(const struct iwl_rx_packet * pkt)94 static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
95 {
96 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
97 }
98
iwl_rx_packet_payload_len(const struct iwl_rx_packet * pkt)99 static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
100 {
101 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
102 }
103
104 /**
105 * enum CMD_MODE - how to send the host commands ?
106 *
107 * @CMD_ASYNC: Return right away and don't wait for the response
108 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
109 * the response. The caller needs to call iwl_free_resp when done.
110 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill.
111 * @CMD_BLOCK_TXQS: Block TXQs while the comment is executing.
112 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to
113 * SUSPEND and RESUME commands. We are in D3 mode when we set
114 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3.
115 */
116 enum CMD_MODE {
117 CMD_ASYNC = BIT(0),
118 CMD_WANT_SKB = BIT(1),
119 CMD_SEND_IN_RFKILL = BIT(2),
120 CMD_BLOCK_TXQS = BIT(3),
121 CMD_SEND_IN_D3 = BIT(4),
122 };
123 #define CMD_MODE_BITS 5
124
125 #define DEF_CMD_PAYLOAD_SIZE 320
126
127 /**
128 * struct iwl_device_cmd
129 *
130 * For allocation of the command and tx queues, this establishes the overall
131 * size of the largest command we send to uCode, except for commands that
132 * aren't fully copied and use other TFD space.
133 *
134 * @hdr: command header
135 * @payload: payload for the command
136 * @hdr_wide: wide command header
137 * @payload_wide: payload for the wide command
138 */
139 struct iwl_device_cmd {
140 union {
141 struct {
142 struct iwl_cmd_header hdr; /* uCode API */
143 u8 payload[DEF_CMD_PAYLOAD_SIZE];
144 };
145 struct {
146 struct iwl_cmd_header_wide hdr_wide;
147 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
148 sizeof(struct iwl_cmd_header_wide) +
149 sizeof(struct iwl_cmd_header)];
150 };
151 };
152 } __packed;
153
154 /**
155 * struct iwl_device_tx_cmd - buffer for TX command
156 * @hdr: the header
157 * @payload: the payload placeholder
158 *
159 * The actual structure is sized dynamically according to need.
160 */
161 struct iwl_device_tx_cmd {
162 struct iwl_cmd_header hdr;
163 u8 payload[];
164 } __packed;
165
166 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
167
168 /*
169 * number of transfer buffers (fragments) per transmit frame descriptor;
170 * this is just the driver's idea, the hardware supports 20
171 */
172 #define IWL_MAX_CMD_TBS_PER_TFD 2
173
174 /**
175 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
176 *
177 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
178 * ring. The transport layer doesn't map the command's buffer to DMA, but
179 * rather copies it to a previously allocated DMA buffer. This flag tells
180 * the transport layer not to copy the command, but to map the existing
181 * buffer (that is passed in) instead. This saves the memcpy and allows
182 * commands that are bigger than the fixed buffer to be submitted.
183 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
184 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
185 * chunk internally and free it again after the command completes. This
186 * can (currently) be used only once per command.
187 * Note that a TFD entry after a DUP one cannot be a normal copied one.
188 */
189 enum iwl_hcmd_dataflag {
190 IWL_HCMD_DFL_NOCOPY = BIT(0),
191 IWL_HCMD_DFL_DUP = BIT(1),
192 };
193
194 enum iwl_error_event_table_status {
195 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
196 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
197 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
198 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3),
199 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4),
200 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5),
201 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6),
202 };
203
204 /**
205 * struct iwl_host_cmd - Host command to the uCode
206 *
207 * @data: array of chunks that composes the data of the host command
208 * @resp_pkt: response packet, if %CMD_WANT_SKB was set
209 * @_rx_page_order: (internally used to free response packet)
210 * @_rx_page_addr: (internally used to free response packet)
211 * @flags: can be CMD_*
212 * @len: array of the lengths of the chunks in data
213 * @dataflags: IWL_HCMD_DFL_*
214 * @id: command id of the host command, for wide commands encoding the
215 * version and group as well
216 */
217 struct iwl_host_cmd {
218 const void *data[IWL_MAX_CMD_TBS_PER_TFD];
219 struct iwl_rx_packet *resp_pkt;
220 unsigned long _rx_page_addr;
221 u32 _rx_page_order;
222
223 u32 flags;
224 u32 id;
225 u16 len[IWL_MAX_CMD_TBS_PER_TFD];
226 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
227 };
228
iwl_free_resp(struct iwl_host_cmd * cmd)229 static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
230 {
231 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
232 }
233
234 struct iwl_rx_cmd_buffer {
235 struct page *_page;
236 int _offset;
237 bool _page_stolen;
238 u32 _rx_page_order;
239 unsigned int truesize;
240 };
241
rxb_addr(struct iwl_rx_cmd_buffer * r)242 static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
243 {
244 return (void *)((unsigned long)page_address(r->_page) + r->_offset);
245 }
246
rxb_offset(struct iwl_rx_cmd_buffer * r)247 static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
248 {
249 return r->_offset;
250 }
251
rxb_steal_page(struct iwl_rx_cmd_buffer * r)252 static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
253 {
254 r->_page_stolen = true;
255 get_page(r->_page);
256 return r->_page;
257 }
258
iwl_free_rxb(struct iwl_rx_cmd_buffer * r)259 static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
260 {
261 __free_pages(r->_page, r->_rx_page_order);
262 }
263
264 #define MAX_NO_RECLAIM_CMDS 6
265
266 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
267
268 /*
269 * Maximum number of HW queues the transport layer
270 * currently supports
271 */
272 #define IWL_MAX_HW_QUEUES 32
273 #define IWL_MAX_TVQM_QUEUES 512
274
275 #define IWL_MAX_TID_COUNT 8
276 #define IWL_MGMT_TID 15
277 #define IWL_FRAME_LIMIT 64
278 #define IWL_MAX_RX_HW_QUEUES 16
279 #define IWL_9000_MAX_RX_HW_QUEUES 1
280
281 /**
282 * enum iwl_d3_status - WoWLAN image/device status
283 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
284 * @IWL_D3_STATUS_RESET: device was reset while suspended
285 */
286 enum iwl_d3_status {
287 IWL_D3_STATUS_ALIVE,
288 IWL_D3_STATUS_RESET,
289 };
290
291 /**
292 * enum iwl_trans_status: transport status flags
293 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
294 * @STATUS_DEVICE_ENABLED: APM is enabled
295 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
296 * @STATUS_INT_ENABLED: interrupts are enabled
297 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
298 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
299 * @STATUS_FW_ERROR: the fw is in error state
300 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
301 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once,
302 * e.g. for testing
303 * @STATUS_IN_SW_RESET: device is undergoing reset, cleared by opmode
304 * via iwl_trans_finish_sw_reset()
305 * @STATUS_RESET_PENDING: reset worker was scheduled, but didn't dump
306 * the firmware state yet
307 */
308 enum iwl_trans_status {
309 STATUS_SYNC_HCMD_ACTIVE,
310 STATUS_DEVICE_ENABLED,
311 STATUS_TPOWER_PMI,
312 STATUS_INT_ENABLED,
313 STATUS_RFKILL_HW,
314 STATUS_RFKILL_OPMODE,
315 STATUS_FW_ERROR,
316 STATUS_TRANS_DEAD,
317 STATUS_SUPPRESS_CMD_ERROR_ONCE,
318 STATUS_IN_SW_RESET,
319 STATUS_RESET_PENDING,
320 };
321
322 static inline int
iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)323 iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
324 {
325 switch (rb_size) {
326 case IWL_AMSDU_2K:
327 return get_order(2 * 1024);
328 case IWL_AMSDU_4K:
329 return get_order(4 * 1024);
330 case IWL_AMSDU_8K:
331 case IWL_AMSDU_12K:
332 return get_order(16 * 1024);
333 default:
334 WARN_ON(1);
335 return -1;
336 }
337 }
338
339 static inline int
iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)340 iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)
341 {
342 switch (rb_size) {
343 case IWL_AMSDU_2K:
344 return 2 * 1024;
345 case IWL_AMSDU_4K:
346 return 4 * 1024;
347 case IWL_AMSDU_8K:
348 return 8 * 1024;
349 case IWL_AMSDU_12K:
350 return 16 * 1024;
351 default:
352 WARN_ON(1);
353 return 0;
354 }
355 }
356
357 struct iwl_hcmd_names {
358 u8 cmd_id;
359 const char *const cmd_name;
360 };
361
362 #define HCMD_NAME(x) \
363 { .cmd_id = x, .cmd_name = #x }
364
365 struct iwl_hcmd_arr {
366 const struct iwl_hcmd_names *arr;
367 int size;
368 };
369
370 #define HCMD_ARR(x) \
371 { .arr = x, .size = ARRAY_SIZE(x) }
372
373 /**
374 * struct iwl_dump_sanitize_ops - dump sanitization operations
375 * @frob_txf: Scrub the TX FIFO data
376 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header
377 * but that might be short or long (&struct iwl_cmd_header or
378 * &struct iwl_cmd_header_wide)
379 * @frob_mem: Scrub memory data
380 */
381 struct iwl_dump_sanitize_ops {
382 void (*frob_txf)(void *ctx, void *buf, size_t buflen);
383 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen);
384 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen);
385 };
386
387 /**
388 * struct iwl_trans_config - transport configuration
389 *
390 * @op_mode: pointer to the upper layer.
391 * @cmd_queue: the index of the command queue.
392 * Must be set before start_fw.
393 * @cmd_fifo: the fifo for host commands
394 * @no_reclaim_cmds: Some devices erroneously don't set the
395 * SEQ_RX_FRAME bit on some notifications, this is the
396 * list of such notifications to filter. Max length is
397 * %MAX_NO_RECLAIM_CMDS.
398 * @n_no_reclaim_cmds: # of commands in list
399 * @rx_buf_size: RX buffer size needed for A-MSDUs
400 * if unset 4k will be the RX buffer size
401 * @bc_table_dword: set to true if the BC table expects the byte count to be
402 * in DWORD (as opposed to bytes)
403 * @scd_set_active: should the transport configure the SCD for HCMD queue
404 * @command_groups: array of command groups, each member is an array of the
405 * commands in the group; for debugging only
406 * @command_groups_size: number of command groups, to avoid illegal access
407 * @cb_data_offs: offset inside skb->cb to store transport data at, must have
408 * space for at least two pointers
409 * @fw_reset_handshake: firmware supports reset flow handshake
410 * @queue_alloc_cmd_ver: queue allocation command version, set to 0
411 * for using the older SCD_QUEUE_CFG, set to the version of
412 * SCD_QUEUE_CONFIG_CMD otherwise.
413 */
414 struct iwl_trans_config {
415 struct iwl_op_mode *op_mode;
416
417 u8 cmd_queue;
418 u8 cmd_fifo;
419 const u8 *no_reclaim_cmds;
420 unsigned int n_no_reclaim_cmds;
421
422 enum iwl_amsdu_size rx_buf_size;
423 bool bc_table_dword;
424 bool scd_set_active;
425 const struct iwl_hcmd_arr *command_groups;
426 int command_groups_size;
427
428 u8 cb_data_offs;
429 bool fw_reset_handshake;
430 u8 queue_alloc_cmd_ver;
431 };
432
433 struct iwl_trans_dump_data {
434 u32 len;
435 u8 data[];
436 };
437
438 struct iwl_trans;
439
440 struct iwl_trans_txq_scd_cfg {
441 u8 fifo;
442 u8 sta_id;
443 u8 tid;
444 bool aggregate;
445 int frame_limit;
446 };
447
448 /**
449 * struct iwl_trans_rxq_dma_data - RX queue DMA data
450 * @fr_bd_cb: DMA address of free BD cyclic buffer
451 * @fr_bd_wid: Initial write index of the free BD cyclic buffer
452 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
453 * @ur_bd_cb: DMA address of used BD cyclic buffer
454 */
455 struct iwl_trans_rxq_dma_data {
456 u64 fr_bd_cb;
457 u32 fr_bd_wid;
458 u64 urbd_stts_wrptr;
459 u64 ur_bd_cb;
460 };
461
462 /* maximal number of DRAM MAP entries supported by FW */
463 #define IPC_DRAM_MAP_ENTRY_NUM_MAX 64
464
465 /**
466 * struct iwl_pnvm_image - contains info about the parsed pnvm image
467 * @chunks: array of pointers to pnvm payloads and their sizes
468 * @n_chunks: the number of the pnvm payloads.
469 * @version: the version of the loaded PNVM image
470 */
471 struct iwl_pnvm_image {
472 struct {
473 const void *data;
474 u32 len;
475 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX];
476 u32 n_chunks;
477 u32 version;
478 };
479
480 /**
481 * enum iwl_trans_state - state of the transport layer
482 *
483 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed
484 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet
485 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response
486 */
487 enum iwl_trans_state {
488 IWL_TRANS_NO_FW,
489 IWL_TRANS_FW_STARTED,
490 IWL_TRANS_FW_ALIVE,
491 };
492
493 /**
494 * DOC: Platform power management
495 *
496 * In system-wide power management the entire platform goes into a low
497 * power state (e.g. idle or suspend to RAM) at the same time and the
498 * device is configured as a wakeup source for the entire platform.
499 * This is usually triggered by userspace activity (e.g. the user
500 * presses the suspend button or a power management daemon decides to
501 * put the platform in low power mode). The device's behavior in this
502 * mode is dictated by the wake-on-WLAN configuration.
503 *
504 * The terms used for the device's behavior are as follows:
505 *
506 * - D0: the device is fully powered and the host is awake;
507 * - D3: the device is in low power mode and only reacts to
508 * specific events (e.g. magic-packet received or scan
509 * results found);
510 *
511 * These terms reflect the power modes in the firmware and are not to
512 * be confused with the physical device power state.
513 */
514
515 /**
516 * enum iwl_plat_pm_mode - platform power management mode
517 *
518 * This enumeration describes the device's platform power management
519 * behavior when in system-wide suspend (i.e WoWLAN).
520 *
521 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
522 * device. In system-wide suspend mode, it means that the all
523 * connections will be closed automatically by mac80211 before
524 * the platform is suspended.
525 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
526 */
527 enum iwl_plat_pm_mode {
528 IWL_PLAT_PM_MODE_DISABLED,
529 IWL_PLAT_PM_MODE_D3,
530 };
531
532 /**
533 * enum iwl_ini_cfg_state
534 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
535 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
536 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
537 * are corrupted. The rest of the debug TLVs will still be used
538 */
539 enum iwl_ini_cfg_state {
540 IWL_INI_CFG_STATE_NOT_LOADED,
541 IWL_INI_CFG_STATE_LOADED,
542 IWL_INI_CFG_STATE_CORRUPTED,
543 };
544
545 /* Max time to wait for nmi interrupt */
546 #define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
547
548 /**
549 * struct iwl_dram_data
550 * @physical: page phy pointer
551 * @block: pointer to the allocated block/page
552 * @size: size of the block/page
553 */
554 struct iwl_dram_data {
555 dma_addr_t physical;
556 void *block;
557 int size;
558 };
559
560 /**
561 * struct iwl_dram_regions - DRAM regions container structure
562 * @drams: array of several DRAM areas that contains the pnvm and power
563 * reduction table payloads.
564 * @n_regions: number of DRAM regions that were allocated
565 * @prph_scratch_mem_desc: points to a structure allocated in dram,
566 * designed to show FW where all the payloads are.
567 */
568 struct iwl_dram_regions {
569 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX];
570 struct iwl_dram_data prph_scratch_mem_desc;
571 u8 n_regions;
572 };
573
574 /**
575 * struct iwl_fw_mon - fw monitor per allocation id
576 * @num_frags: number of fragments
577 * @frags: an array of DRAM buffer fragments
578 */
579 struct iwl_fw_mon {
580 u32 num_frags;
581 struct iwl_dram_data *frags;
582 };
583
584 /**
585 * struct iwl_self_init_dram - dram data used by self init process
586 * @fw: lmac and umac dram data
587 * @fw_cnt: total number of items in array
588 * @paging: paging dram data
589 * @paging_cnt: total number of items in array
590 */
591 struct iwl_self_init_dram {
592 struct iwl_dram_data *fw;
593 int fw_cnt;
594 struct iwl_dram_data *paging;
595 int paging_cnt;
596 };
597
598 /**
599 * struct iwl_imr_data - imr dram data used during debug process
600 * @imr_enable: imr enable status received from fw
601 * @imr_size: imr dram size received from fw
602 * @sram_addr: sram address from debug tlv
603 * @sram_size: sram size from debug tlv
604 * @imr2sram_remainbyte: size remained after each dma transfer
605 * @imr_curr_addr: current dst address used during dma transfer
606 * @imr_base_addr: imr address received from fw
607 */
608 struct iwl_imr_data {
609 u32 imr_enable;
610 u32 imr_size;
611 u32 sram_addr;
612 u32 sram_size;
613 u32 imr2sram_remainbyte;
614 u64 imr_curr_addr;
615 __le64 imr_base_addr;
616 };
617
618 #define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32
619
620 /**
621 * struct iwl_pc_data - program counter details
622 * @pc_name: cpu name
623 * @pc_address: cpu program counter
624 */
625 struct iwl_pc_data {
626 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES];
627 u32 pc_address;
628 };
629
630 /**
631 * struct iwl_trans_debug - transport debug related data
632 *
633 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
634 * @rec_on: true iff there is a fw debug recording currently active
635 * @dest_tlv: points to the destination TLV for debug
636 * @lmac_error_event_table: addrs of lmacs error tables
637 * @umac_error_event_table: addr of umac error table
638 * @tcm_error_event_table: address(es) of TCM error table(s)
639 * @rcm_error_event_table: address(es) of RCM error table(s)
640 * @error_event_table_tlv_status: bitmap that indicates what error table
641 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status
642 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
643 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
644 * @fw_mon_cfg: debug buffer allocation configuration
645 * @fw_mon_ini: DRAM buffer fragments per allocation id
646 * @fw_mon: DRAM buffer for firmware monitor
647 * @hw_error: equals true if hw error interrupt was received from the FW
648 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
649 * @unsupported_region_msk: unsupported regions out of active_regions
650 * @active_regions: active regions
651 * @debug_info_tlv_list: list of debug info TLVs
652 * @time_point: array of debug time points
653 * @periodic_trig_list: periodic triggers list
654 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON
655 * @ucode_preset: preset based on ucode
656 * @restart_required: indicates debug restart is required
657 * @last_tp_resetfw: last handling of reset during debug timepoint
658 * @imr_data: IMR debug data allocation
659 * @dump_file_name_ext: dump file name extension
660 * @dump_file_name_ext_valid: dump file name extension if valid or not
661 * @num_pc: number of program counter for cpu
662 * @pc_data: details of the program counter
663 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded
664 */
665 struct iwl_trans_debug {
666 u8 n_dest_reg;
667 bool rec_on;
668
669 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
670
671 u32 lmac_error_event_table[2];
672 u32 umac_error_event_table;
673 u32 tcm_error_event_table[2];
674 u32 rcm_error_event_table[2];
675 unsigned int error_event_table_tlv_status;
676
677 enum iwl_ini_cfg_state internal_ini_cfg;
678 enum iwl_ini_cfg_state external_ini_cfg;
679
680 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];
681 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];
682
683 struct iwl_dram_data fw_mon;
684
685 bool hw_error;
686 enum iwl_fw_ini_buffer_location ini_dest;
687
688 u64 unsupported_region_msk;
689 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
690 struct list_head debug_info_tlv_list;
691 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM];
692 struct list_head periodic_trig_list;
693
694 u32 domains_bitmap;
695 u32 ucode_preset;
696 bool restart_required;
697 u32 last_tp_resetfw;
698 struct iwl_imr_data imr_data;
699 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME];
700 bool dump_file_name_ext_valid;
701 u32 num_pc;
702 struct iwl_pc_data *pc_data;
703 bool yoyo_bin_loaded;
704 };
705
706 struct iwl_dma_ptr {
707 dma_addr_t dma;
708 void *addr;
709 size_t size;
710 };
711
712 struct iwl_cmd_meta {
713 /* only for SYNC commands, iff the reply skb is wanted */
714 struct iwl_host_cmd *source;
715 u32 flags: CMD_MODE_BITS;
716 /* sg_offset is valid if it is non-zero */
717 u32 sg_offset: PAGE_SHIFT;
718 u32 tbs;
719 };
720
721 /*
722 * The FH will write back to the first TB only, so we need to copy some data
723 * into the buffer regardless of whether it should be mapped or not.
724 * This indicates how big the first TB must be to include the scratch buffer
725 * and the assigned PN.
726 * Since PN location is 8 bytes at offset 12, it's 20 now.
727 * If we make it bigger then allocations will be bigger and copy slower, so
728 * that's probably not useful.
729 */
730 #define IWL_FIRST_TB_SIZE 20
731 #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
732
733 struct iwl_pcie_txq_entry {
734 void *cmd;
735 struct sk_buff *skb;
736 /* buffer to free after command completes */
737 const void *free_buf;
738 struct iwl_cmd_meta meta;
739 };
740
741 struct iwl_pcie_first_tb_buf {
742 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
743 };
744
745 /**
746 * struct iwl_txq - Tx Queue for DMA
747 * @tfds: transmit frame descriptors (DMA memory)
748 * @first_tb_bufs: start of command headers, including scratch buffers, for
749 * the writeback -- this is DMA memory and an array holding one buffer
750 * for each command on the queue
751 * @first_tb_dma: DMA address for the first_tb_bufs start
752 * @entries: transmit entries (driver state)
753 * @lock: queue lock
754 * @reclaim_lock: reclaim lock
755 * @stuck_timer: timer that fires if queue gets stuck
756 * @trans: pointer back to transport (for timer)
757 * @need_update: indicates need to update read/write index
758 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
759 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
760 * @frozen: tx stuck queue timer is frozen
761 * @frozen_expiry_remainder: remember how long until the timer fires
762 * @block: queue is blocked
763 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport)
764 * @write_ptr: 1-st empty entry (index) host_w
765 * @read_ptr: last used entry (index) host_r
766 * @dma_addr: physical addr for BD's
767 * @n_window: safe queue window
768 * @id: queue id
769 * @low_mark: low watermark, resume queue if free space more than this
770 * @high_mark: high watermark, stop queue if free space less than this
771 * @overflow_q: overflow queue for handling frames that didn't fit on HW queue
772 * @overflow_tx: need to transmit from overflow
773 *
774 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
775 * descriptors) and required locking structures.
776 *
777 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
778 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
779 * there might be HW changes in the future). For the normal TX
780 * queues, n_window, which is the size of the software queue data
781 * is also 256; however, for the command queue, n_window is only
782 * 32 since we don't need so many commands pending. Since the HW
783 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
784 * This means that we end up with the following:
785 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
786 * SW entries: | 0 | ... | 31 |
787 * where N is a number between 0 and 7. This means that the SW
788 * data is a window overlayed over the HW queue.
789 */
790 struct iwl_txq {
791 void *tfds;
792 struct iwl_pcie_first_tb_buf *first_tb_bufs;
793 dma_addr_t first_tb_dma;
794 struct iwl_pcie_txq_entry *entries;
795 /* lock for syncing changes on the queue */
796 spinlock_t lock;
797 /* lock to prevent concurrent reclaim */
798 spinlock_t reclaim_lock;
799 unsigned long frozen_expiry_remainder;
800 struct timer_list stuck_timer;
801 struct iwl_trans *trans;
802 bool need_update;
803 bool frozen;
804 bool ampdu;
805 int block;
806 unsigned long wd_timeout;
807 struct sk_buff_head overflow_q;
808 struct iwl_dma_ptr bc_tbl;
809
810 int write_ptr;
811 int read_ptr;
812 dma_addr_t dma_addr;
813 int n_window;
814 u32 id;
815 int low_mark;
816 int high_mark;
817
818 bool overflow_tx;
819 };
820
821 /**
822 * struct iwl_trans - transport common data
823 *
824 * @csme_own: true if we couldn't get ownership on the device
825 * @op_mode: pointer to the op_mode
826 * @trans_cfg: the trans-specific configuration part
827 * @cfg: pointer to the configuration
828 * @drv: pointer to iwl_drv
829 * @state: current device state
830 * @status: a bit-mask of transport status flags
831 * @dev: pointer to struct device * that represents the device
832 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
833 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
834 * @hw_rf_id: a u32 with the device RF ID
835 * @hw_cnv_id: a u32 with the device CNV ID
836 * @hw_crf_id: a u32 with the device CRF ID
837 * @hw_wfpm_id: a u32 with the device wfpm ID
838 * @hw_id: a u32 with the ID of the device / sub-device.
839 * Set during transport allocation.
840 * @hw_id_str: a string with info about HW ID. Set during transport allocation.
841 * @sku_id: the SKU identifier (for PNVM matching)
842 * @pnvm_loaded: indicates PNVM was loaded
843 * @hw_rev: the revision data of the HW
844 * @hw_rev_step: The mac step of the HW
845 * @pm_support: set to true in start_hw if link pm is supported
846 * @ltr_enabled: set to true if the LTR is enabled
847 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed
848 * @reduce_power_loaded: indicates reduced power section was loaded
849 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed
850 * @command_groups: pointer to command group name list array
851 * @command_groups_size: array size of @command_groups
852 * @wide_cmd_header: true when ucode supports wide command header format
853 * @wait_command_queue: wait queue for sync commands
854 * @num_rx_queues: number of RX queues allocated by the transport;
855 * the transport must set this before calling iwl_drv_start()
856 * @iml_len: the length of the image loader
857 * @iml: a pointer to the image loader itself
858 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
859 * The user should use iwl_trans_{alloc,free}_tx_cmd.
860 * @dev_cmd_pool_name: name for the TX command allocation pool
861 * @dbgfs_dir: iwlwifi debugfs base dir for this device
862 * @sync_cmd_lockdep_map: lockdep map for checking sync commands
863 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
864 * starting the firmware, used for tracing
865 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
866 * start of the 802.11 header in the @rx_mpdu_cmd
867 * @dbg: additional debug data, see &struct iwl_trans_debug
868 * @init_dram: FW initialization DMA data
869 * @system_pm_mode: the system-wide power management mode in use.
870 * This mode is set dynamically, depending on the WoWLAN values
871 * configured from the userspace at runtime.
872 * @name: the device name
873 * @mbx_addr_0_step: step address data 0
874 * @mbx_addr_1_step: step address data 1
875 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*),
876 * only valid for discrete (not integrated) NICs
877 * @invalid_tx_cmd: invalid TX command buffer
878 * @reduced_cap_sku: reduced capability supported SKU
879 * @bw_limit: the max bandwidth
880 * @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz
881 * @restart: restart worker data
882 * @restart.wk: restart worker
883 * @restart.mode: reset/restart error mode information
884 * @restart.during_reset: error occurred during previous software reset
885 * @me_recheck_wk: worker to recheck WiAMT/CSME presence
886 * @me_present: WiAMT/CSME is detected as present (1), not present (0)
887 * or unknown (-1, so can still use it as a boolean safely)
888 * @trans_specific: data for the specific transport this is allocated for/with
889 * @dsbr_urm_fw_dependent: switch to URM based on fw settings
890 * @dsbr_urm_permanent: switch to URM permanently
891 * @ext_32khz_clock_valid: if true, the external 32 KHz clock can be used
892 */
893 struct iwl_trans {
894 bool csme_own;
895 struct iwl_op_mode *op_mode;
896 const struct iwl_cfg_trans_params *trans_cfg;
897 const struct iwl_cfg *cfg;
898 struct iwl_drv *drv;
899 enum iwl_trans_state state;
900 unsigned long status;
901
902 struct device *dev;
903 u32 max_skb_frags;
904 u32 hw_rev;
905 u32 hw_rev_step;
906 u32 hw_rf_id;
907 u32 hw_crf_id;
908 u32 hw_cnv_id;
909 u32 hw_wfpm_id;
910 u32 hw_id;
911 char hw_id_str[52];
912 u32 sku_id[3];
913 bool reduced_cap_sku;
914 u16 bw_limit;
915 bool step_urm;
916
917 u8 dsbr_urm_fw_dependent:1,
918 dsbr_urm_permanent:1;
919
920 bool ext_32khz_clock_valid;
921
922 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
923
924 bool pm_support;
925 bool ltr_enabled;
926 u8 pnvm_loaded:1;
927 u8 fail_to_parse_pnvm_image:1;
928 u8 reduce_power_loaded:1;
929 u8 failed_to_load_reduce_power_image:1;
930
931 const struct iwl_hcmd_arr *command_groups;
932 int command_groups_size;
933 bool wide_cmd_header;
934
935 wait_queue_head_t wait_command_queue;
936 u8 num_rx_queues;
937
938 size_t iml_len;
939 u8 *iml;
940
941 /* The following fields are internal only */
942 struct kmem_cache *dev_cmd_pool;
943 char dev_cmd_pool_name[50];
944
945 struct dentry *dbgfs_dir;
946
947 #ifdef CONFIG_LOCKDEP
948 struct lockdep_map sync_cmd_lockdep_map;
949 #endif
950
951 struct iwl_trans_debug dbg;
952 struct iwl_self_init_dram init_dram;
953
954 enum iwl_plat_pm_mode system_pm_mode;
955
956 const char *name;
957 u32 mbx_addr_0_step;
958 u32 mbx_addr_1_step;
959
960 u8 pcie_link_speed;
961
962 struct iwl_dma_ptr invalid_tx_cmd;
963
964 struct {
965 struct work_struct wk;
966 struct iwl_fw_error_dump_mode mode;
967 bool during_reset;
968 } restart;
969
970 struct delayed_work me_recheck_wk;
971 s8 me_present;
972
973 /* pointer to trans specific struct */
974 /*Ensure that this pointer will always be aligned to sizeof pointer */
975 char trans_specific[] __aligned(sizeof(void *));
976 };
977
978 const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
979 int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
980
981 void iwl_trans_configure(struct iwl_trans *trans,
982 const struct iwl_trans_config *trans_cfg);
983
984 int iwl_trans_start_hw(struct iwl_trans *trans);
985
986 void iwl_trans_op_mode_leave(struct iwl_trans *trans);
987
988 void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr);
989
990 int iwl_trans_start_fw(struct iwl_trans *trans, const struct fw_img *fw,
991 bool run_in_rfkill);
992
993 void iwl_trans_stop_device(struct iwl_trans *trans);
994
995 int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, bool reset);
996
997 int iwl_trans_d3_resume(struct iwl_trans *trans, enum iwl_d3_status *status,
998 bool test, bool reset);
999
1000 struct iwl_trans_dump_data *
1001 iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask,
1002 const struct iwl_dump_sanitize_ops *sanitize_ops,
1003 void *sanitize_ctx);
1004
1005 static inline struct iwl_device_tx_cmd *
iwl_trans_alloc_tx_cmd(struct iwl_trans * trans)1006 iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
1007 {
1008 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC);
1009 }
1010
1011 int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
1012
iwl_trans_free_tx_cmd(struct iwl_trans * trans,struct iwl_device_tx_cmd * dev_cmd)1013 static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
1014 struct iwl_device_tx_cmd *dev_cmd)
1015 {
1016 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
1017 }
1018
1019 int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
1020 struct iwl_device_tx_cmd *dev_cmd, int queue);
1021
1022 void iwl_trans_reclaim(struct iwl_trans *trans, int queue, int ssn,
1023 struct sk_buff_head *skbs, bool is_flush);
1024
1025 void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, int ptr);
1026
1027 void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1028 bool configure_scd);
1029
1030 bool iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1031 const struct iwl_trans_txq_scd_cfg *cfg,
1032 unsigned int queue_wdg_timeout);
1033
1034 int iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
1035 struct iwl_trans_rxq_dma_data *data);
1036
1037 void iwl_trans_txq_free(struct iwl_trans *trans, int queue);
1038
1039 int iwl_trans_txq_alloc(struct iwl_trans *trans, u32 flags, u32 sta_mask,
1040 u8 tid, int size, unsigned int wdg_timeout);
1041
1042 void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1043 int txq_id, bool shared_mode);
1044
iwl_trans_txq_enable(struct iwl_trans * trans,int queue,int fifo,int sta_id,int tid,int frame_limit,u16 ssn,unsigned int queue_wdg_timeout)1045 static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1046 int fifo, int sta_id, int tid,
1047 int frame_limit, u16 ssn,
1048 unsigned int queue_wdg_timeout)
1049 {
1050 struct iwl_trans_txq_scd_cfg cfg = {
1051 .fifo = fifo,
1052 .sta_id = sta_id,
1053 .tid = tid,
1054 .frame_limit = frame_limit,
1055 .aggregate = sta_id >= 0,
1056 };
1057
1058 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1059 }
1060
1061 static inline
iwl_trans_ac_txq_enable(struct iwl_trans * trans,int queue,int fifo,unsigned int queue_wdg_timeout)1062 void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1063 unsigned int queue_wdg_timeout)
1064 {
1065 struct iwl_trans_txq_scd_cfg cfg = {
1066 .fifo = fifo,
1067 .sta_id = -1,
1068 .tid = IWL_MAX_TID_COUNT,
1069 .frame_limit = IWL_FRAME_LIMIT,
1070 .aggregate = false,
1071 };
1072
1073 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1074 }
1075
1076 void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1077 unsigned long txqs, bool freeze);
1078
1079 int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs);
1080
1081 int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue);
1082
1083 void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val);
1084
1085 void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val);
1086
1087 u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs);
1088
1089 u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs);
1090
1091 void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);
1092
1093 int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1094 void *buf, int dwords);
1095
1096 int iwl_trans_read_config32(struct iwl_trans *trans, u32 ofs,
1097 u32 *val);
1098
1099 #ifdef CONFIG_IWLWIFI_DEBUGFS
1100 void iwl_trans_debugfs_cleanup(struct iwl_trans *trans);
1101 #endif
1102
1103 #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
1104 ({ \
1105 if (__builtin_constant_p(bufsize)) \
1106 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
1107 iwl_trans_read_mem(trans, addr, buf, \
1108 (bufsize) / sizeof(u32)); \
1109 })
1110
1111 int iwl_trans_write_imr_mem(struct iwl_trans *trans, u32 dst_addr,
1112 u64 src_addr, u32 byte_cnt);
1113
iwl_trans_read_mem32(struct iwl_trans * trans,u32 addr)1114 static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1115 {
1116 u32 value;
1117
1118 if (iwl_trans_read_mem(trans, addr, &value, 1))
1119 return 0xa5a5a5a5;
1120
1121 return value;
1122 }
1123
1124 int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1125 const void *buf, int dwords);
1126
iwl_trans_write_mem32(struct iwl_trans * trans,u32 addr,u32 val)1127 static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1128 u32 val)
1129 {
1130 return iwl_trans_write_mem(trans, addr, &val, 1);
1131 }
1132
1133 void iwl_trans_set_pmi(struct iwl_trans *trans, bool state);
1134
1135 int iwl_trans_sw_reset(struct iwl_trans *trans, bool retake_ownership);
1136
1137 void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg,
1138 u32 mask, u32 value);
1139
1140 bool _iwl_trans_grab_nic_access(struct iwl_trans *trans);
1141
1142 #define iwl_trans_grab_nic_access(trans) \
1143 __cond_lock(nic_access, \
1144 likely(_iwl_trans_grab_nic_access(trans)))
1145
1146 void __releases(nic_access)
1147 iwl_trans_release_nic_access(struct iwl_trans *trans);
1148
iwl_trans_schedule_reset(struct iwl_trans * trans,enum iwl_fw_error_type type)1149 static inline void iwl_trans_schedule_reset(struct iwl_trans *trans,
1150 enum iwl_fw_error_type type)
1151 {
1152 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1153 return;
1154
1155 trans->restart.mode.type = type;
1156 trans->restart.mode.context = IWL_ERR_CONTEXT_WORKER;
1157
1158 set_bit(STATUS_RESET_PENDING, &trans->status);
1159
1160 /*
1161 * keep track of whether or not this happened while resetting,
1162 * by the timer the worker runs it might have finished
1163 */
1164 trans->restart.during_reset = test_bit(STATUS_IN_SW_RESET,
1165 &trans->status);
1166 queue_work(system_unbound_wq, &trans->restart.wk);
1167 }
1168
iwl_trans_fw_error(struct iwl_trans * trans,enum iwl_fw_error_type type)1169 static inline void iwl_trans_fw_error(struct iwl_trans *trans,
1170 enum iwl_fw_error_type type)
1171 {
1172 if (WARN_ON_ONCE(!trans->op_mode))
1173 return;
1174
1175 /* prevent double restarts due to the same erroneous FW */
1176 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) {
1177 trans->state = IWL_TRANS_NO_FW;
1178 iwl_op_mode_nic_error(trans->op_mode, type);
1179 iwl_trans_schedule_reset(trans, type);
1180 }
1181 }
1182
iwl_trans_opmode_sw_reset(struct iwl_trans * trans,enum iwl_fw_error_type type)1183 static inline void iwl_trans_opmode_sw_reset(struct iwl_trans *trans,
1184 enum iwl_fw_error_type type)
1185 {
1186 if (WARN_ON_ONCE(!trans->op_mode))
1187 return;
1188
1189 set_bit(STATUS_IN_SW_RESET, &trans->status);
1190
1191 if (!trans->op_mode->ops->sw_reset ||
1192 !trans->op_mode->ops->sw_reset(trans->op_mode, type))
1193 clear_bit(STATUS_IN_SW_RESET, &trans->status);
1194 }
1195
iwl_trans_fw_running(struct iwl_trans * trans)1196 static inline bool iwl_trans_fw_running(struct iwl_trans *trans)
1197 {
1198 return trans->state == IWL_TRANS_FW_ALIVE;
1199 }
1200
1201 void iwl_trans_sync_nmi(struct iwl_trans *trans);
1202
1203 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
1204 u32 sw_err_bit);
1205
1206 int iwl_trans_load_pnvm(struct iwl_trans *trans,
1207 const struct iwl_pnvm_image *pnvm_data,
1208 const struct iwl_ucode_capabilities *capa);
1209
1210 void iwl_trans_set_pnvm(struct iwl_trans *trans,
1211 const struct iwl_ucode_capabilities *capa);
1212
1213 int iwl_trans_load_reduce_power(struct iwl_trans *trans,
1214 const struct iwl_pnvm_image *payloads,
1215 const struct iwl_ucode_capabilities *capa);
1216
1217 void iwl_trans_set_reduce_power(struct iwl_trans *trans,
1218 const struct iwl_ucode_capabilities *capa);
1219
iwl_trans_dbg_ini_valid(struct iwl_trans * trans)1220 static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1221 {
1222 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1223 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
1224 }
1225
1226 void iwl_trans_interrupts(struct iwl_trans *trans, bool enable);
1227
iwl_trans_finish_sw_reset(struct iwl_trans * trans)1228 static inline void iwl_trans_finish_sw_reset(struct iwl_trans *trans)
1229 {
1230 clear_bit(STATUS_IN_SW_RESET, &trans->status);
1231 }
1232
1233 /*****************************************************
1234 * transport helper functions
1235 *****************************************************/
1236 struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1237 struct device *dev,
1238 const struct iwl_cfg_trans_params *cfg_trans);
1239 int iwl_trans_init(struct iwl_trans *trans);
1240 void iwl_trans_free(struct iwl_trans *trans);
1241
iwl_trans_is_hw_error_value(u32 val)1242 static inline bool iwl_trans_is_hw_error_value(u32 val)
1243 {
1244 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50);
1245 }
1246
1247 void iwl_trans_free_restart_list(void);
1248
1249 /*****************************************************
1250 * PCIe handling
1251 *****************************************************/
1252 int __must_check iwl_pci_register_driver(void);
1253 void iwl_pci_unregister_driver(void);
1254
1255 /* Note: order matters */
1256 enum iwl_reset_mode {
1257 /* upper level modes: */
1258 IWL_RESET_MODE_SW_RESET,
1259 IWL_RESET_MODE_REPROBE,
1260 /* PCIE level modes: */
1261 IWL_RESET_MODE_REMOVE_ONLY,
1262 IWL_RESET_MODE_RESCAN,
1263 IWL_RESET_MODE_FUNC_RESET,
1264 IWL_RESET_MODE_PROD_RESET,
1265 };
1266
1267 void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode);
1268 void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans);
1269
1270 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans,
1271 struct iwl_host_cmd *cmd);
1272
1273 #endif /* __iwl_trans_h__ */
1274