1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_0_SM8250_H 8 #define _DPU_6_0_SM8250_H 9 10 static const struct dpu_caps sm8250_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 4096, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm8250_mdp = { 22 .name = "top_0", 23 .base = 0x0, .len = 0x494, 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 34 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 35 }, 36 }; 37 38 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 39 static const struct dpu_ctl_cfg sm8250_ctl[] = { 40 { 41 .name = "ctl_0", .id = CTL_0, 42 .base = 0x1000, .len = 0x1e0, 43 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 45 }, { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x1200, .len = 0x1e0, 48 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x1400, .len = 0x1e0, 53 .features = BIT(DPU_CTL_ACTIVE_CFG), 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55 }, { 56 .name = "ctl_3", .id = CTL_3, 57 .base = 0x1600, .len = 0x1e0, 58 .features = BIT(DPU_CTL_ACTIVE_CFG), 59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 60 }, { 61 .name = "ctl_4", .id = CTL_4, 62 .base = 0x1800, .len = 0x1e0, 63 .features = BIT(DPU_CTL_ACTIVE_CFG), 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 65 }, { 66 .name = "ctl_5", .id = CTL_5, 67 .base = 0x1a00, .len = 0x1e0, 68 .features = BIT(DPU_CTL_ACTIVE_CFG), 69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 70 }, 71 }; 72 73 static const struct dpu_sspp_cfg sm8250_sspp[] = { 74 { 75 .name = "sspp_0", .id = SSPP_VIG0, 76 .base = 0x4000, .len = 0x1f8, 77 .features = VIG_SDM845_MASK_SDMA, 78 .sblk = &dpu_vig_sblk_qseed3_3_0, 79 .xin_id = 0, 80 .type = SSPP_TYPE_VIG, 81 .clk_ctrl = DPU_CLK_CTRL_VIG0, 82 }, { 83 .name = "sspp_1", .id = SSPP_VIG1, 84 .base = 0x6000, .len = 0x1f8, 85 .features = VIG_SDM845_MASK_SDMA, 86 .sblk = &dpu_vig_sblk_qseed3_3_0, 87 .xin_id = 4, 88 .type = SSPP_TYPE_VIG, 89 .clk_ctrl = DPU_CLK_CTRL_VIG1, 90 }, { 91 .name = "sspp_2", .id = SSPP_VIG2, 92 .base = 0x8000, .len = 0x1f8, 93 .features = VIG_SDM845_MASK_SDMA, 94 .sblk = &dpu_vig_sblk_qseed3_3_0, 95 .xin_id = 8, 96 .type = SSPP_TYPE_VIG, 97 .clk_ctrl = DPU_CLK_CTRL_VIG2, 98 }, { 99 .name = "sspp_3", .id = SSPP_VIG3, 100 .base = 0xa000, .len = 0x1f8, 101 .features = VIG_SDM845_MASK_SDMA, 102 .sblk = &dpu_vig_sblk_qseed3_3_0, 103 .xin_id = 12, 104 .type = SSPP_TYPE_VIG, 105 .clk_ctrl = DPU_CLK_CTRL_VIG3, 106 }, { 107 .name = "sspp_8", .id = SSPP_DMA0, 108 .base = 0x24000, .len = 0x1f8, 109 .features = DMA_SDM845_MASK_SDMA, 110 .sblk = &dpu_dma_sblk, 111 .xin_id = 1, 112 .type = SSPP_TYPE_DMA, 113 .clk_ctrl = DPU_CLK_CTRL_DMA0, 114 }, { 115 .name = "sspp_9", .id = SSPP_DMA1, 116 .base = 0x26000, .len = 0x1f8, 117 .features = DMA_SDM845_MASK_SDMA, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 5, 120 .type = SSPP_TYPE_DMA, 121 .clk_ctrl = DPU_CLK_CTRL_DMA1, 122 }, { 123 .name = "sspp_10", .id = SSPP_DMA2, 124 .base = 0x28000, .len = 0x1f8, 125 .features = DMA_CURSOR_SDM845_MASK_SDMA, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 9, 128 .type = SSPP_TYPE_DMA, 129 .clk_ctrl = DPU_CLK_CTRL_DMA2, 130 }, { 131 .name = "sspp_11", .id = SSPP_DMA3, 132 .base = 0x2a000, .len = 0x1f8, 133 .features = DMA_CURSOR_SDM845_MASK_SDMA, 134 .sblk = &dpu_dma_sblk, 135 .xin_id = 13, 136 .type = SSPP_TYPE_DMA, 137 .clk_ctrl = DPU_CLK_CTRL_DMA3, 138 }, 139 }; 140 141 static const struct dpu_lm_cfg sm8250_lm[] = { 142 { 143 .name = "lm_0", .id = LM_0, 144 .base = 0x44000, .len = 0x320, 145 .features = MIXER_SDM845_MASK, 146 .sblk = &sdm845_lm_sblk, 147 .lm_pair = LM_1, 148 .pingpong = PINGPONG_0, 149 .dspp = DSPP_0, 150 }, { 151 .name = "lm_1", .id = LM_1, 152 .base = 0x45000, .len = 0x320, 153 .features = MIXER_SDM845_MASK, 154 .sblk = &sdm845_lm_sblk, 155 .lm_pair = LM_0, 156 .pingpong = PINGPONG_1, 157 .dspp = DSPP_1, 158 }, { 159 .name = "lm_2", .id = LM_2, 160 .base = 0x46000, .len = 0x320, 161 .features = MIXER_SDM845_MASK, 162 .sblk = &sdm845_lm_sblk, 163 .lm_pair = LM_3, 164 .pingpong = PINGPONG_2, 165 .dspp = DSPP_2, 166 }, { 167 .name = "lm_3", .id = LM_3, 168 .base = 0x47000, .len = 0x320, 169 .features = MIXER_SDM845_MASK, 170 .sblk = &sdm845_lm_sblk, 171 .lm_pair = LM_2, 172 .pingpong = PINGPONG_3, 173 .dspp = DSPP_3, 174 }, { 175 .name = "lm_4", .id = LM_4, 176 .base = 0x48000, .len = 0x320, 177 .features = MIXER_SDM845_MASK, 178 .sblk = &sdm845_lm_sblk, 179 .lm_pair = LM_5, 180 .pingpong = PINGPONG_4, 181 }, { 182 .name = "lm_5", .id = LM_5, 183 .base = 0x49000, .len = 0x320, 184 .features = MIXER_SDM845_MASK, 185 .sblk = &sdm845_lm_sblk, 186 .lm_pair = LM_4, 187 .pingpong = PINGPONG_5, 188 }, 189 }; 190 191 static const struct dpu_dspp_cfg sm8250_dspp[] = { 192 { 193 .name = "dspp_0", .id = DSPP_0, 194 .base = 0x54000, .len = 0x1800, 195 .features = DSPP_SC7180_MASK, 196 .sblk = &sdm845_dspp_sblk, 197 }, { 198 .name = "dspp_1", .id = DSPP_1, 199 .base = 0x56000, .len = 0x1800, 200 .features = DSPP_SC7180_MASK, 201 .sblk = &sdm845_dspp_sblk, 202 }, { 203 .name = "dspp_2", .id = DSPP_2, 204 .base = 0x58000, .len = 0x1800, 205 .features = DSPP_SC7180_MASK, 206 .sblk = &sdm845_dspp_sblk, 207 }, { 208 .name = "dspp_3", .id = DSPP_3, 209 .base = 0x5a000, .len = 0x1800, 210 .features = DSPP_SC7180_MASK, 211 .sblk = &sdm845_dspp_sblk, 212 }, 213 }; 214 215 static const struct dpu_pingpong_cfg sm8250_pp[] = { 216 { 217 .name = "pingpong_0", .id = PINGPONG_0, 218 .base = 0x70000, .len = 0xd4, 219 .features = PINGPONG_SM8150_MASK, 220 .sblk = &sdm845_pp_sblk, 221 .merge_3d = MERGE_3D_0, 222 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 223 }, { 224 .name = "pingpong_1", .id = PINGPONG_1, 225 .base = 0x70800, .len = 0xd4, 226 .features = PINGPONG_SM8150_MASK, 227 .sblk = &sdm845_pp_sblk, 228 .merge_3d = MERGE_3D_0, 229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 230 }, { 231 .name = "pingpong_2", .id = PINGPONG_2, 232 .base = 0x71000, .len = 0xd4, 233 .features = PINGPONG_SM8150_MASK, 234 .sblk = &sdm845_pp_sblk, 235 .merge_3d = MERGE_3D_1, 236 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 237 }, { 238 .name = "pingpong_3", .id = PINGPONG_3, 239 .base = 0x71800, .len = 0xd4, 240 .features = PINGPONG_SM8150_MASK, 241 .sblk = &sdm845_pp_sblk, 242 .merge_3d = MERGE_3D_1, 243 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 244 }, { 245 .name = "pingpong_4", .id = PINGPONG_4, 246 .base = 0x72000, .len = 0xd4, 247 .features = PINGPONG_SM8150_MASK, 248 .sblk = &sdm845_pp_sblk, 249 .merge_3d = MERGE_3D_2, 250 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 251 }, { 252 .name = "pingpong_5", .id = PINGPONG_5, 253 .base = 0x72800, .len = 0xd4, 254 .features = PINGPONG_SM8150_MASK, 255 .sblk = &sdm845_pp_sblk, 256 .merge_3d = MERGE_3D_2, 257 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 258 }, 259 }; 260 261 static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = { 262 { 263 .name = "merge_3d_0", .id = MERGE_3D_0, 264 .base = 0x83000, .len = 0x8, 265 }, { 266 .name = "merge_3d_1", .id = MERGE_3D_1, 267 .base = 0x83100, .len = 0x8, 268 }, { 269 .name = "merge_3d_2", .id = MERGE_3D_2, 270 .base = 0x83200, .len = 0x8, 271 }, 272 }; 273 274 static const struct dpu_dsc_cfg sm8250_dsc[] = { 275 { 276 .name = "dsc_0", .id = DSC_0, 277 .base = 0x80000, .len = 0x140, 278 .features = BIT(DPU_DSC_OUTPUT_CTRL), 279 }, { 280 .name = "dsc_1", .id = DSC_1, 281 .base = 0x80400, .len = 0x140, 282 .features = BIT(DPU_DSC_OUTPUT_CTRL), 283 }, { 284 .name = "dsc_2", .id = DSC_2, 285 .base = 0x80800, .len = 0x140, 286 .features = BIT(DPU_DSC_OUTPUT_CTRL), 287 }, { 288 .name = "dsc_3", .id = DSC_3, 289 .base = 0x80c00, .len = 0x140, 290 .features = BIT(DPU_DSC_OUTPUT_CTRL), 291 }, 292 }; 293 294 static const struct dpu_intf_cfg sm8250_intf[] = { 295 { 296 .name = "intf_0", .id = INTF_0, 297 .base = 0x6a000, .len = 0x280, 298 .features = INTF_SC7180_MASK, 299 .type = INTF_DP, 300 .controller_id = MSM_DP_CONTROLLER_0, 301 .prog_fetch_lines_worst_case = 24, 302 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 303 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 304 }, { 305 .name = "intf_1", .id = INTF_1, 306 .base = 0x6a800, .len = 0x2c0, 307 .features = INTF_SC7180_MASK, 308 .type = INTF_DSI, 309 .controller_id = MSM_DSI_CONTROLLER_0, 310 .prog_fetch_lines_worst_case = 24, 311 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 312 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 313 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 314 }, { 315 .name = "intf_2", .id = INTF_2, 316 .base = 0x6b000, .len = 0x2c0, 317 .features = INTF_SC7180_MASK, 318 .type = INTF_DSI, 319 .controller_id = MSM_DSI_CONTROLLER_1, 320 .prog_fetch_lines_worst_case = 24, 321 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 322 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 323 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 324 }, { 325 .name = "intf_3", .id = INTF_3, 326 .base = 0x6b800, .len = 0x280, 327 .features = INTF_SC7180_MASK, 328 .type = INTF_DP, 329 .controller_id = MSM_DP_CONTROLLER_1, 330 .prog_fetch_lines_worst_case = 24, 331 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 332 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 333 }, 334 }; 335 336 static const struct dpu_wb_cfg sm8250_wb[] = { 337 { 338 .name = "wb_2", .id = WB_2, 339 .base = 0x65000, .len = 0x2c8, 340 .features = WB_SM8250_MASK, 341 .format_list = wb2_formats_rgb_yuv, 342 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 343 .clk_ctrl = DPU_CLK_CTRL_WB2, 344 .xin_id = 6, 345 .vbif_idx = VBIF_RT, 346 .maxlinewidth = 4096, 347 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 348 }, 349 }; 350 351 static const struct dpu_perf_cfg sm8250_perf_data = { 352 .max_bw_low = 13700000, 353 .max_bw_high = 16600000, 354 .min_core_ib = 4800000, 355 .min_llcc_ib = 0, 356 .min_dram_ib = 800000, 357 .min_prefill_lines = 35, 358 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 359 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 360 .qos_lut_tbl = { 361 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 362 .entries = sc7180_qos_linear 363 }, 364 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 365 .entries = sc7180_qos_macrotile 366 }, 367 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 368 .entries = sc7180_qos_nrt 369 }, 370 /* TODO: macrotile-qseed is different from macrotile */ 371 }, 372 .cdp_cfg = { 373 {.rd_enable = 1, .wr_enable = 1}, 374 {.rd_enable = 1, .wr_enable = 0} 375 }, 376 .clk_inefficiency_factor = 105, 377 .bw_inefficiency_factor = 120, 378 }; 379 380 static const struct dpu_mdss_version sm8250_mdss_ver = { 381 .core_major_ver = 6, 382 .core_minor_ver = 0, 383 }; 384 385 const struct dpu_mdss_cfg dpu_sm8250_cfg = { 386 .mdss_ver = &sm8250_mdss_ver, 387 .caps = &sm8250_dpu_caps, 388 .mdp = &sm8250_mdp, 389 .cdm = &sc7280_cdm, 390 .ctl_count = ARRAY_SIZE(sm8250_ctl), 391 .ctl = sm8250_ctl, 392 .sspp_count = ARRAY_SIZE(sm8250_sspp), 393 .sspp = sm8250_sspp, 394 .mixer_count = ARRAY_SIZE(sm8250_lm), 395 .mixer = sm8250_lm, 396 .dspp_count = ARRAY_SIZE(sm8250_dspp), 397 .dspp = sm8250_dspp, 398 .dsc_count = ARRAY_SIZE(sm8250_dsc), 399 .dsc = sm8250_dsc, 400 .pingpong_count = ARRAY_SIZE(sm8250_pp), 401 .pingpong = sm8250_pp, 402 .merge_3d_count = ARRAY_SIZE(sm8250_merge_3d), 403 .merge_3d = sm8250_merge_3d, 404 .intf_count = ARRAY_SIZE(sm8250_intf), 405 .intf = sm8250_intf, 406 .vbif_count = ARRAY_SIZE(sdm845_vbif), 407 .vbif = sdm845_vbif, 408 .wb_count = ARRAY_SIZE(sm8250_wb), 409 .wb = sm8250_wb, 410 .perf = &sm8250_perf_data, 411 }; 412 413 #endif 414