1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _DPU_8_4_SA8775P_H 7 #define _DPU_8_4_SA8775P_H 8 9 static const struct dpu_caps sa8775p_dpu_caps = { 10 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 11 .max_mixer_blendstages = 0xb, 12 .has_src_split = true, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .has_3d_merge = true, 16 .max_linewidth = 5120, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_mdp_cfg sa8775p_mdp = { 21 .name = "top_0", 22 .base = 0x0, .len = 0x494, 23 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 35 }, 36 }; 37 38 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 39 static const struct dpu_ctl_cfg sa8775p_ctl[] = { 40 { 41 .name = "ctl_0", .id = CTL_0, 42 .base = 0x15000, .len = 0x204, 43 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 45 }, { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x16000, .len = 0x204, 48 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x17000, .len = 0x204, 53 .features = CTL_SC7280_MASK, 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55 }, { 56 .name = "ctl_3", .id = CTL_3, 57 .base = 0x18000, .len = 0x204, 58 .features = CTL_SC7280_MASK, 59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 60 }, { 61 .name = "ctl_4", .id = CTL_4, 62 .base = 0x19000, .len = 0x204, 63 .features = CTL_SC7280_MASK, 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 65 }, { 66 .name = "ctl_5", .id = CTL_5, 67 .base = 0x1a000, .len = 0x204, 68 .features = CTL_SC7280_MASK, 69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 70 }, 71 }; 72 73 static const struct dpu_sspp_cfg sa8775p_sspp[] = { 74 { 75 .name = "sspp_0", .id = SSPP_VIG0, 76 .base = 0x4000, .len = 0x32c, 77 .features = VIG_SDM845_MASK_SDMA, 78 .sblk = &dpu_vig_sblk_qseed3_3_1, 79 .xin_id = 0, 80 .type = SSPP_TYPE_VIG, 81 .clk_ctrl = DPU_CLK_CTRL_VIG0, 82 }, { 83 .name = "sspp_1", .id = SSPP_VIG1, 84 .base = 0x6000, .len = 0x32c, 85 .features = VIG_SDM845_MASK_SDMA, 86 .sblk = &dpu_vig_sblk_qseed3_3_1, 87 .xin_id = 4, 88 .type = SSPP_TYPE_VIG, 89 .clk_ctrl = DPU_CLK_CTRL_VIG1, 90 }, { 91 .name = "sspp_2", .id = SSPP_VIG2, 92 .base = 0x8000, .len = 0x32c, 93 .features = VIG_SDM845_MASK_SDMA, 94 .sblk = &dpu_vig_sblk_qseed3_3_1, 95 .xin_id = 8, 96 .type = SSPP_TYPE_VIG, 97 .clk_ctrl = DPU_CLK_CTRL_VIG2, 98 }, { 99 .name = "sspp_3", .id = SSPP_VIG3, 100 .base = 0xa000, .len = 0x32c, 101 .features = VIG_SDM845_MASK_SDMA, 102 .sblk = &dpu_vig_sblk_qseed3_3_1, 103 .xin_id = 12, 104 .type = SSPP_TYPE_VIG, 105 .clk_ctrl = DPU_CLK_CTRL_VIG3, 106 }, { 107 .name = "sspp_8", .id = SSPP_DMA0, 108 .base = 0x24000, .len = 0x32c, 109 .features = DMA_SDM845_MASK_SDMA, 110 .sblk = &dpu_dma_sblk, 111 .xin_id = 1, 112 .type = SSPP_TYPE_DMA, 113 .clk_ctrl = DPU_CLK_CTRL_DMA0, 114 }, { 115 .name = "sspp_9", .id = SSPP_DMA1, 116 .base = 0x26000, .len = 0x32c, 117 .features = DMA_SDM845_MASK_SDMA, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 5, 120 .type = SSPP_TYPE_DMA, 121 .clk_ctrl = DPU_CLK_CTRL_DMA1, 122 }, { 123 .name = "sspp_10", .id = SSPP_DMA2, 124 .base = 0x28000, .len = 0x32c, 125 .features = DMA_CURSOR_SDM845_MASK_SDMA, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 9, 128 .type = SSPP_TYPE_DMA, 129 .clk_ctrl = DPU_CLK_CTRL_DMA2, 130 }, { 131 .name = "sspp_11", .id = SSPP_DMA3, 132 .base = 0x2a000, .len = 0x32c, 133 .features = DMA_CURSOR_SDM845_MASK_SDMA, 134 .sblk = &dpu_dma_sblk, 135 .xin_id = 13, 136 .type = SSPP_TYPE_DMA, 137 .clk_ctrl = DPU_CLK_CTRL_DMA3, 138 }, 139 }; 140 141 static const struct dpu_lm_cfg sa8775p_lm[] = { 142 { 143 .name = "lm_0", .id = LM_0, 144 .base = 0x44000, .len = 0x400, 145 .features = MIXER_SDM845_MASK, 146 .sblk = &sdm845_lm_sblk, 147 .lm_pair = LM_1, 148 .pingpong = PINGPONG_0, 149 .dspp = DSPP_0, 150 }, { 151 .name = "lm_1", .id = LM_1, 152 .base = 0x45000, .len = 0x400, 153 .features = MIXER_SDM845_MASK, 154 .sblk = &sdm845_lm_sblk, 155 .lm_pair = LM_0, 156 .pingpong = PINGPONG_1, 157 .dspp = DSPP_1, 158 }, { 159 .name = "lm_2", .id = LM_2, 160 .base = 0x46000, .len = 0x400, 161 .features = MIXER_SDM845_MASK, 162 .sblk = &sdm845_lm_sblk, 163 .lm_pair = LM_3, 164 .pingpong = PINGPONG_2, 165 .dspp = DSPP_2, 166 }, { 167 .name = "lm_3", .id = LM_3, 168 .base = 0x47000, .len = 0x400, 169 .features = MIXER_SDM845_MASK, 170 .sblk = &sdm845_lm_sblk, 171 .lm_pair = LM_2, 172 .pingpong = PINGPONG_3, 173 .dspp = DSPP_3, 174 }, { 175 .name = "lm_4", .id = LM_4, 176 .base = 0x48000, .len = 0x400, 177 .features = MIXER_SDM845_MASK, 178 .sblk = &sdm845_lm_sblk, 179 .lm_pair = LM_5, 180 .pingpong = PINGPONG_4, 181 }, { 182 .name = "lm_5", .id = LM_5, 183 .base = 0x49000, .len = 0x400, 184 .features = MIXER_SDM845_MASK, 185 .sblk = &sdm845_lm_sblk, 186 .lm_pair = LM_4, 187 .pingpong = PINGPONG_5, 188 }, 189 }; 190 191 static const struct dpu_dspp_cfg sa8775p_dspp[] = { 192 { 193 .name = "dspp_0", .id = DSPP_0, 194 .base = 0x54000, .len = 0x1800, 195 .features = DSPP_SC7180_MASK, 196 .sblk = &sdm845_dspp_sblk, 197 }, { 198 .name = "dspp_1", .id = DSPP_1, 199 .base = 0x56000, .len = 0x1800, 200 .features = DSPP_SC7180_MASK, 201 .sblk = &sdm845_dspp_sblk, 202 }, { 203 .name = "dspp_2", .id = DSPP_2, 204 .base = 0x58000, .len = 0x1800, 205 .features = DSPP_SC7180_MASK, 206 .sblk = &sdm845_dspp_sblk, 207 }, { 208 .name = "dspp_3", .id = DSPP_3, 209 .base = 0x5a000, .len = 0x1800, 210 .features = DSPP_SC7180_MASK, 211 .sblk = &sdm845_dspp_sblk, 212 }, 213 }; 214 215 static const struct dpu_pingpong_cfg sa8775p_pp[] = { 216 { 217 .name = "pingpong_0", .id = PINGPONG_0, 218 .base = 0x69000, .len = 0, 219 .features = BIT(DPU_PINGPONG_DITHER), 220 .sblk = &sc7280_pp_sblk, 221 .merge_3d = MERGE_3D_0, 222 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 223 }, { 224 .name = "pingpong_1", .id = PINGPONG_1, 225 .base = 0x6a000, .len = 0, 226 .features = BIT(DPU_PINGPONG_DITHER), 227 .sblk = &sc7280_pp_sblk, 228 .merge_3d = MERGE_3D_0, 229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 230 }, { 231 .name = "pingpong_2", .id = PINGPONG_2, 232 .base = 0x6b000, .len = 0, 233 .features = BIT(DPU_PINGPONG_DITHER), 234 .sblk = &sc7280_pp_sblk, 235 .merge_3d = MERGE_3D_1, 236 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 237 }, { 238 .name = "pingpong_3", .id = PINGPONG_3, 239 .base = 0x6c000, .len = 0, 240 .features = BIT(DPU_PINGPONG_DITHER), 241 .sblk = &sc7280_pp_sblk, 242 .merge_3d = MERGE_3D_1, 243 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 244 }, { 245 .name = "pingpong_4", .id = PINGPONG_4, 246 .base = 0x6d000, .len = 0, 247 .features = BIT(DPU_PINGPONG_DITHER), 248 .sblk = &sc7280_pp_sblk, 249 .merge_3d = MERGE_3D_2, 250 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 251 }, { 252 .name = "pingpong_5", .id = PINGPONG_5, 253 .base = 0x6e000, .len = 0, 254 .features = BIT(DPU_PINGPONG_DITHER), 255 .sblk = &sc7280_pp_sblk, 256 .merge_3d = MERGE_3D_2, 257 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 258 }, { 259 .name = "pingpong_6", .id = PINGPONG_CWB_0, 260 .base = 0x65800, .len = 0, 261 .features = BIT(DPU_PINGPONG_DITHER), 262 .sblk = &sc7280_pp_sblk, 263 .merge_3d = MERGE_3D_3, 264 }, { 265 .name = "pingpong_7", .id = PINGPONG_CWB_1, 266 .base = 0x65c00, .len = 0, 267 .features = BIT(DPU_PINGPONG_DITHER), 268 .sblk = &sc7280_pp_sblk, 269 .merge_3d = MERGE_3D_3, 270 }, 271 }; 272 273 static const struct dpu_merge_3d_cfg sa8775p_merge_3d[] = { 274 { 275 .name = "merge_3d_0", .id = MERGE_3D_0, 276 .base = 0x4e000, .len = 0x8, 277 }, { 278 .name = "merge_3d_1", .id = MERGE_3D_1, 279 .base = 0x4f000, .len = 0x8, 280 }, { 281 .name = "merge_3d_2", .id = MERGE_3D_2, 282 .base = 0x50000, .len = 0x8, 283 }, { 284 .name = "merge_3d_3", .id = MERGE_3D_3, 285 .base = 0x65f00, .len = 0x8, 286 }, 287 }; 288 289 /* 290 * NOTE: Each display compression engine (DCE) contains dual hard 291 * slice DSC encoders so both share same base address but with 292 * its own different sub block address. 293 */ 294 static const struct dpu_dsc_cfg sa8775p_dsc[] = { 295 { 296 .name = "dce_0_0", .id = DSC_0, 297 .base = 0x80000, .len = 0x4, 298 .features = BIT(DPU_DSC_HW_REV_1_2), 299 .sblk = &dsc_sblk_0, 300 }, { 301 .name = "dce_0_1", .id = DSC_1, 302 .base = 0x80000, .len = 0x4, 303 .features = BIT(DPU_DSC_HW_REV_1_2), 304 .sblk = &dsc_sblk_1, 305 }, { 306 .name = "dce_1_0", .id = DSC_2, 307 .base = 0x81000, .len = 0x4, 308 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 309 .sblk = &dsc_sblk_0, 310 }, { 311 .name = "dce_1_1", .id = DSC_3, 312 .base = 0x81000, .len = 0x4, 313 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 314 .sblk = &dsc_sblk_1, 315 }, { 316 .name = "dce_2_0", .id = DSC_4, 317 .base = 0x82000, .len = 0x4, 318 .features = BIT(DPU_DSC_HW_REV_1_2), 319 .sblk = &dsc_sblk_0, 320 }, { 321 .name = "dce_2_1", .id = DSC_5, 322 .base = 0x82000, .len = 0x4, 323 .features = BIT(DPU_DSC_HW_REV_1_2), 324 .sblk = &dsc_sblk_1, 325 }, 326 }; 327 328 static const struct dpu_wb_cfg sa8775p_wb[] = { 329 { 330 .name = "wb_2", .id = WB_2, 331 .base = 0x65000, .len = 0x2c8, 332 .features = WB_SM8250_MASK, 333 .format_list = wb2_formats_rgb_yuv, 334 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 335 .clk_ctrl = DPU_CLK_CTRL_WB2, 336 .xin_id = 6, 337 .vbif_idx = VBIF_RT, 338 .maxlinewidth = 4096, 339 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 340 }, 341 }; 342 343 /* TODO: INTF 3, 6, 7 and 8 are used for MST, marked as INTF_NONE for now */ 344 static const struct dpu_intf_cfg sa8775p_intf[] = { 345 { 346 .name = "intf_0", .id = INTF_0, 347 .base = 0x34000, .len = 0x280, 348 .features = INTF_SC7280_MASK, 349 .type = INTF_DP, 350 .controller_id = MSM_DP_CONTROLLER_0, 351 .prog_fetch_lines_worst_case = 24, 352 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 353 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 354 }, { 355 .name = "intf_1", .id = INTF_1, 356 .base = 0x35000, .len = 0x300, 357 .features = INTF_SC7280_MASK, 358 .type = INTF_DSI, 359 .controller_id = MSM_DSI_CONTROLLER_0, 360 .prog_fetch_lines_worst_case = 24, 361 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 362 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 363 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 364 }, { 365 .name = "intf_2", .id = INTF_2, 366 .base = 0x36000, .len = 0x300, 367 .features = INTF_SC7280_MASK, 368 .type = INTF_DSI, 369 .controller_id = MSM_DSI_CONTROLLER_1, 370 .prog_fetch_lines_worst_case = 24, 371 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 372 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 373 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 374 }, { 375 .name = "intf_3", .id = INTF_3, 376 .base = 0x37000, .len = 0x280, 377 .features = INTF_SC7280_MASK, 378 .type = INTF_NONE, 379 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ 380 .prog_fetch_lines_worst_case = 24, 381 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 382 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 383 }, { 384 .name = "intf_4", .id = INTF_4, 385 .base = 0x38000, .len = 0x280, 386 .features = INTF_SC7280_MASK, 387 .type = INTF_DP, 388 .controller_id = MSM_DP_CONTROLLER_1, 389 .prog_fetch_lines_worst_case = 24, 390 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 391 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), 392 }, { 393 .name = "intf_6", .id = INTF_6, 394 .base = 0x3A000, .len = 0x280, 395 .features = INTF_SC7280_MASK, 396 .type = INTF_NONE, 397 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ 398 .prog_fetch_lines_worst_case = 24, 399 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), 400 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), 401 }, { 402 .name = "intf_7", .id = INTF_7, 403 .base = 0x3b000, .len = 0x280, 404 .features = INTF_SC7280_MASK, 405 .type = INTF_NONE, 406 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ 407 .prog_fetch_lines_worst_case = 24, 408 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), 409 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), 410 }, { 411 .name = "intf_8", .id = INTF_8, 412 .base = 0x3c000, .len = 0x280, 413 .features = INTF_SC7280_MASK, 414 .type = INTF_NONE, 415 .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ 416 .prog_fetch_lines_worst_case = 24, 417 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 418 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 419 }, 420 }; 421 422 static const struct dpu_perf_cfg sa8775p_perf_data = { 423 .max_bw_low = 13600000, 424 .max_bw_high = 18200000, 425 .min_core_ib = 2500000, 426 .min_llcc_ib = 0, 427 .min_dram_ib = 800000, 428 .min_prefill_lines = 35, 429 /* FIXME: lut tables */ 430 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 431 .safe_lut_tbl = {0xfff0, 0xfff0, 0x1}, 432 .qos_lut_tbl = { 433 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 434 .entries = sm6350_qos_linear_macrotile 435 }, 436 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 437 .entries = sm6350_qos_linear_macrotile 438 }, 439 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 440 .entries = sc7180_qos_nrt 441 }, 442 /* TODO: macrotile-qseed is different from macrotile */ 443 }, 444 .cdp_cfg = { 445 {.rd_enable = 1, .wr_enable = 1}, 446 {.rd_enable = 1, .wr_enable = 0} 447 }, 448 .clk_inefficiency_factor = 105, 449 .bw_inefficiency_factor = 120, 450 }; 451 452 static const struct dpu_mdss_version sa8775p_mdss_ver = { 453 .core_major_ver = 8, 454 .core_minor_ver = 4, 455 }; 456 457 const struct dpu_mdss_cfg dpu_sa8775p_cfg = { 458 .mdss_ver = &sa8775p_mdss_ver, 459 .caps = &sa8775p_dpu_caps, 460 .mdp = &sa8775p_mdp, 461 .cdm = &sc7280_cdm, 462 .ctl_count = ARRAY_SIZE(sa8775p_ctl), 463 .ctl = sa8775p_ctl, 464 .sspp_count = ARRAY_SIZE(sa8775p_sspp), 465 .sspp = sa8775p_sspp, 466 .mixer_count = ARRAY_SIZE(sa8775p_lm), 467 .mixer = sa8775p_lm, 468 .dspp_count = ARRAY_SIZE(sa8775p_dspp), 469 .dspp = sa8775p_dspp, 470 .pingpong_count = ARRAY_SIZE(sa8775p_pp), 471 .pingpong = sa8775p_pp, 472 .dsc_count = ARRAY_SIZE(sa8775p_dsc), 473 .dsc = sa8775p_dsc, 474 .merge_3d_count = ARRAY_SIZE(sa8775p_merge_3d), 475 .merge_3d = sa8775p_merge_3d, 476 .wb_count = ARRAY_SIZE(sa8775p_wb), 477 .wb = sa8775p_wb, 478 .intf_count = ARRAY_SIZE(sa8775p_intf), 479 .intf = sa8775p_intf, 480 .vbif_count = ARRAY_SIZE(sdm845_vbif), 481 .vbif = sdm845_vbif, 482 .perf = &sa8775p_perf_data, 483 }; 484 485 #endif 486