1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DPU_1_7_MSM8996_H 9 #define _DPU_1_7_MSM8996_H 10 11 static const struct dpu_caps msm8996_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x7, 14 .has_src_split = true, 15 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 16 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 17 .max_hdeci_exp = MAX_HORZ_DECIMATION, 18 .max_vdeci_exp = MAX_VERT_DECIMATION, 19 }; 20 21 static const struct dpu_mdp_cfg msm8996_mdp[] = { 22 { 23 .name = "top_0", 24 .base = 0x0, .len = 0x454, 25 .features = BIT(DPU_MDP_VSYNC_SEL), 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 }, 32 [DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 }, 33 [DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4 }, 34 [DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4 }, 35 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 36 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 37 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 38 [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, 39 }, 40 }, 41 }; 42 43 static const struct dpu_ctl_cfg msm8996_ctl[] = { 44 { 45 .name = "ctl_0", .id = CTL_0, 46 .base = 0x1000, .len = 0x64, 47 }, { 48 .name = "ctl_1", .id = CTL_1, 49 .base = 0x1200, .len = 0x64, 50 }, { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x1400, .len = 0x64, 53 }, { 54 .name = "ctl_3", .id = CTL_3, 55 .base = 0x1600, .len = 0x64, 56 }, { 57 .name = "ctl_4", .id = CTL_4, 58 .base = 0x1800, .len = 0x64, 59 }, 60 }; 61 62 static const struct dpu_sspp_cfg msm8996_sspp[] = { 63 { 64 .name = "sspp_0", .id = SSPP_VIG0, 65 .base = 0x4000, .len = 0x150, 66 .features = VIG_MSM8996_MASK, 67 .sblk = &dpu_vig_sblk_qseed2, 68 .xin_id = 0, 69 .type = SSPP_TYPE_VIG, 70 .clk_ctrl = DPU_CLK_CTRL_VIG0, 71 }, { 72 .name = "sspp_1", .id = SSPP_VIG1, 73 .base = 0x6000, .len = 0x150, 74 .features = VIG_MSM8996_MASK, 75 .sblk = &dpu_vig_sblk_qseed2, 76 .xin_id = 4, 77 .type = SSPP_TYPE_VIG, 78 .clk_ctrl = DPU_CLK_CTRL_VIG1, 79 }, { 80 .name = "sspp_2", .id = SSPP_VIG2, 81 .base = 0x8000, .len = 0x150, 82 .features = VIG_MSM8996_MASK, 83 .sblk = &dpu_vig_sblk_qseed2, 84 .xin_id = 8, 85 .type = SSPP_TYPE_VIG, 86 .clk_ctrl = DPU_CLK_CTRL_VIG2, 87 }, { 88 .name = "sspp_3", .id = SSPP_VIG3, 89 .base = 0xa000, .len = 0x150, 90 .features = VIG_MSM8996_MASK, 91 .sblk = &dpu_vig_sblk_qseed2, 92 .xin_id = 12, 93 .type = SSPP_TYPE_VIG, 94 .clk_ctrl = DPU_CLK_CTRL_VIG3, 95 }, { 96 .name = "sspp_4", .id = SSPP_RGB0, 97 .base = 0x14000, .len = 0x150, 98 .features = RGB_MSM8996_MASK, 99 .sblk = &dpu_rgb_sblk, 100 .xin_id = 1, 101 .type = SSPP_TYPE_RGB, 102 .clk_ctrl = DPU_CLK_CTRL_RGB0, 103 }, { 104 .name = "sspp_5", .id = SSPP_RGB1, 105 .base = 0x16000, .len = 0x150, 106 .features = RGB_MSM8996_MASK, 107 .sblk = &dpu_rgb_sblk, 108 .xin_id = 5, 109 .type = SSPP_TYPE_RGB, 110 .clk_ctrl = DPU_CLK_CTRL_RGB1, 111 }, { 112 .name = "sspp_6", .id = SSPP_RGB2, 113 .base = 0x18000, .len = 0x150, 114 .features = RGB_MSM8996_MASK, 115 .sblk = &dpu_rgb_sblk, 116 .xin_id = 9, 117 .type = SSPP_TYPE_RGB, 118 .clk_ctrl = DPU_CLK_CTRL_RGB2, 119 }, { 120 .name = "sspp_7", .id = SSPP_RGB3, 121 .base = 0x1a000, .len = 0x150, 122 .features = RGB_MSM8996_MASK, 123 .sblk = &dpu_rgb_sblk, 124 .xin_id = 13, 125 .type = SSPP_TYPE_RGB, 126 .clk_ctrl = DPU_CLK_CTRL_RGB3, 127 }, { 128 .name = "sspp_8", .id = SSPP_DMA0, 129 .base = 0x24000, .len = 0x150, 130 .features = DMA_MSM8996_MASK, 131 .sblk = &dpu_dma_sblk, 132 .xin_id = 2, 133 .type = SSPP_TYPE_DMA, 134 .clk_ctrl = DPU_CLK_CTRL_DMA0, 135 }, { 136 .name = "sspp_9", .id = SSPP_DMA1, 137 .base = 0x26000, .len = 0x150, 138 .features = DMA_MSM8996_MASK, 139 .sblk = &dpu_dma_sblk, 140 .xin_id = 10, 141 .type = SSPP_TYPE_DMA, 142 .clk_ctrl = DPU_CLK_CTRL_DMA1, 143 }, 144 }; 145 146 static const struct dpu_lm_cfg msm8996_lm[] = { 147 { 148 .name = "lm_0", .id = LM_0, 149 .base = 0x44000, .len = 0x320, 150 .features = MIXER_MSM8998_MASK, 151 .sblk = &msm8998_lm_sblk, 152 .lm_pair = LM_1, 153 .pingpong = PINGPONG_0, 154 .dspp = DSPP_0, 155 }, { 156 .name = "lm_1", .id = LM_1, 157 .base = 0x45000, .len = 0x320, 158 .features = MIXER_MSM8998_MASK, 159 .sblk = &msm8998_lm_sblk, 160 .lm_pair = LM_0, 161 .pingpong = PINGPONG_1, 162 .dspp = DSPP_1, 163 }, { 164 .name = "lm_2", .id = LM_2, 165 .base = 0x46000, .len = 0x320, 166 .features = MIXER_MSM8998_MASK, 167 .sblk = &msm8998_lm_sblk, 168 .lm_pair = LM_5, 169 .pingpong = PINGPONG_2, 170 }, { 171 .name = "lm_5", .id = LM_5, 172 .base = 0x49000, .len = 0x320, 173 .features = MIXER_MSM8998_MASK, 174 .sblk = &msm8998_lm_sblk, 175 .lm_pair = LM_2, 176 .pingpong = PINGPONG_3, 177 }, 178 }; 179 180 static const struct dpu_pingpong_cfg msm8996_pp[] = { 181 { 182 .name = "pingpong_0", .id = PINGPONG_0, 183 .base = 0x70000, .len = 0xd4, 184 .features = PINGPONG_MSM8996_MASK, 185 .sblk = &msm8996_pp_sblk, 186 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 187 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 188 }, { 189 .name = "pingpong_1", .id = PINGPONG_1, 190 .base = 0x70800, .len = 0xd4, 191 .features = PINGPONG_MSM8996_MASK, 192 .sblk = &msm8996_pp_sblk, 193 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 194 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 195 }, { 196 .name = "pingpong_2", .id = PINGPONG_2, 197 .base = 0x71000, .len = 0xd4, 198 .features = PINGPONG_MSM8996_MASK, 199 .sblk = &msm8996_pp_sblk, 200 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 201 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 202 }, { 203 .name = "pingpong_3", .id = PINGPONG_3, 204 .base = 0x71800, .len = 0xd4, 205 .features = PINGPONG_MSM8996_MASK, 206 .sblk = &msm8996_pp_sblk, 207 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 208 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), 209 }, 210 }; 211 212 static const struct dpu_dsc_cfg msm8996_dsc[] = { 213 { 214 .name = "dsc_0", .id = DSC_0, 215 .base = 0x80000, .len = 0x140, 216 }, { 217 .name = "dsc_1", .id = DSC_1, 218 .base = 0x80400, .len = 0x140, 219 }, 220 }; 221 222 static const struct dpu_dspp_cfg msm8996_dspp[] = { 223 { 224 .name = "dspp_0", .id = DSPP_0, 225 .base = 0x54000, .len = 0x1800, 226 .features = DSPP_SC7180_MASK, 227 .sblk = &msm8998_dspp_sblk, 228 }, { 229 .name = "dspp_1", .id = DSPP_1, 230 .base = 0x56000, .len = 0x1800, 231 .features = DSPP_SC7180_MASK, 232 .sblk = &msm8998_dspp_sblk, 233 }, 234 }; 235 236 static const struct dpu_intf_cfg msm8996_intf[] = { 237 { 238 .name = "intf_0", .id = INTF_0, 239 .base = 0x6a000, .len = 0x268, 240 .type = INTF_NONE, 241 .prog_fetch_lines_worst_case = 25, 242 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 243 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 244 }, { 245 .name = "intf_1", .id = INTF_1, 246 .base = 0x6a800, .len = 0x268, 247 .type = INTF_DSI, 248 .controller_id = MSM_DSI_CONTROLLER_0, 249 .prog_fetch_lines_worst_case = 25, 250 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 251 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 252 }, { 253 .name = "intf_2", .id = INTF_2, 254 .base = 0x6b000, .len = 0x268, 255 .type = INTF_DSI, 256 .controller_id = MSM_DSI_CONTROLLER_1, 257 .prog_fetch_lines_worst_case = 25, 258 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 259 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 260 }, { 261 .name = "intf_3", .id = INTF_3, 262 .base = 0x6b800, .len = 0x268, 263 .type = INTF_HDMI, 264 .prog_fetch_lines_worst_case = 25, 265 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 266 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 267 }, 268 }; 269 270 static const struct dpu_perf_cfg msm8996_perf_data = { 271 .max_bw_low = 9600000, 272 .max_bw_high = 9600000, 273 .min_core_ib = 2400000, 274 .min_llcc_ib = 0, /* No LLCC on this SoC */ 275 .min_dram_ib = 800000, 276 .undersized_prefill_lines = 2, 277 .xtra_prefill_lines = 2, 278 .dest_scale_prefill_lines = 3, 279 .macrotile_prefill_lines = 4, 280 .yuv_nv12_prefill_lines = 8, 281 .linear_prefill_lines = 1, 282 .downscaling_prefill_lines = 1, 283 .amortizable_threshold = 25, 284 .min_prefill_lines = 21, 285 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 286 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 287 .qos_lut_tbl = { 288 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 289 .entries = msm8998_qos_linear 290 }, 291 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 292 .entries = msm8998_qos_macrotile 293 }, 294 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 295 .entries = msm8998_qos_nrt 296 }, 297 }, 298 .cdp_cfg = { 299 {.rd_enable = 1, .wr_enable = 1}, 300 {.rd_enable = 1, .wr_enable = 0} 301 }, 302 .clk_inefficiency_factor = 105, 303 .bw_inefficiency_factor = 120, 304 }; 305 306 static const struct dpu_mdss_version msm8996_mdss_ver = { 307 .core_major_ver = 1, 308 .core_minor_ver = 7, 309 }; 310 311 const struct dpu_mdss_cfg dpu_msm8996_cfg = { 312 .mdss_ver = &msm8996_mdss_ver, 313 .caps = &msm8996_dpu_caps, 314 .mdp = msm8996_mdp, 315 .cdm = &dpu_cdm_1_x_4_x, 316 .ctl_count = ARRAY_SIZE(msm8996_ctl), 317 .ctl = msm8996_ctl, 318 .sspp_count = ARRAY_SIZE(msm8996_sspp), 319 .sspp = msm8996_sspp, 320 .mixer_count = ARRAY_SIZE(msm8996_lm), 321 .mixer = msm8996_lm, 322 .dspp_count = ARRAY_SIZE(msm8996_dspp), 323 .dspp = msm8996_dspp, 324 .pingpong_count = ARRAY_SIZE(msm8996_pp), 325 .pingpong = msm8996_pp, 326 .dsc_count = ARRAY_SIZE(msm8996_dsc), 327 .dsc = msm8996_dsc, 328 .intf_count = ARRAY_SIZE(msm8996_intf), 329 .intf = msm8996_intf, 330 .vbif_count = ARRAY_SIZE(msm8996_vbif), 331 .vbif = msm8996_vbif, 332 .perf = &msm8996_perf_data, 333 }; 334 335 #endif 336