xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c (revision e70140ba0d2b1a30467d4af6bcfe761327b9ec95)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
5  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6  *
7  * Author: Rob Clark <robdclark@gmail.com>
8  */
9 
10 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
11 
12 #include <linux/debugfs.h>
13 #include <linux/dma-buf.h>
14 #include <linux/of_irq.h>
15 #include <linux/pm_opp.h>
16 
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_file.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_vblank.h>
21 #include <drm/drm_writeback.h>
22 
23 #include "msm_drv.h"
24 #include "msm_mmu.h"
25 #include "msm_mdss.h"
26 #include "msm_gem.h"
27 #include "disp/msm_disp_snapshot.h"
28 
29 #include "dpu_core_irq.h"
30 #include "dpu_crtc.h"
31 #include "dpu_encoder.h"
32 #include "dpu_formats.h"
33 #include "dpu_hw_vbif.h"
34 #include "dpu_kms.h"
35 #include "dpu_plane.h"
36 #include "dpu_vbif.h"
37 #include "dpu_writeback.h"
38 
39 #define CREATE_TRACE_POINTS
40 #include "dpu_trace.h"
41 
42 /*
43  * To enable overall DRM driver logging
44  * # echo 0x2 > /sys/module/drm/parameters/debug
45  *
46  * To enable DRM driver h/w logging
47  * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
48  *
49  * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
50  */
51 #define DPU_DEBUGFS_DIR "msm_dpu"
52 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
53 
54 static int dpu_kms_hw_init(struct msm_kms *kms);
55 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
56 
57 #ifdef CONFIG_DEBUG_FS
_dpu_danger_signal_status(struct seq_file * s,bool danger_status)58 static int _dpu_danger_signal_status(struct seq_file *s,
59 		bool danger_status)
60 {
61 	struct dpu_danger_safe_status status;
62 	struct dpu_kms *kms = s->private;
63 	int i;
64 
65 	if (!kms->hw_mdp) {
66 		DPU_ERROR("invalid arg(s)\n");
67 		return 0;
68 	}
69 
70 	memset(&status, 0, sizeof(struct dpu_danger_safe_status));
71 
72 	pm_runtime_get_sync(&kms->pdev->dev);
73 	if (danger_status) {
74 		seq_puts(s, "\nDanger signal status:\n");
75 		if (kms->hw_mdp->ops.get_danger_status)
76 			kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
77 					&status);
78 	} else {
79 		seq_puts(s, "\nSafe signal status:\n");
80 		if (kms->hw_mdp->ops.get_safe_status)
81 			kms->hw_mdp->ops.get_safe_status(kms->hw_mdp,
82 					&status);
83 	}
84 	pm_runtime_put_sync(&kms->pdev->dev);
85 
86 	seq_printf(s, "MDP     :  0x%x\n", status.mdp);
87 
88 	for (i = SSPP_VIG0; i < SSPP_MAX; i++)
89 		seq_printf(s, "SSPP%d   :  0x%x  \n", i - SSPP_VIG0,
90 				status.sspp[i]);
91 	seq_puts(s, "\n");
92 
93 	return 0;
94 }
95 
dpu_debugfs_danger_stats_show(struct seq_file * s,void * v)96 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
97 {
98 	return _dpu_danger_signal_status(s, true);
99 }
100 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats);
101 
dpu_debugfs_safe_stats_show(struct seq_file * s,void * v)102 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
103 {
104 	return _dpu_danger_signal_status(s, false);
105 }
106 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
107 
_dpu_plane_danger_read(struct file * file,char __user * buff,size_t count,loff_t * ppos)108 static ssize_t _dpu_plane_danger_read(struct file *file,
109 			char __user *buff, size_t count, loff_t *ppos)
110 {
111 	struct dpu_kms *kms = file->private_data;
112 	int len;
113 	char buf[40];
114 
115 	len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
116 
117 	return simple_read_from_buffer(buff, count, ppos, buf, len);
118 }
119 
_dpu_plane_set_danger_state(struct dpu_kms * kms,bool enable)120 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
121 {
122 	struct drm_plane *plane;
123 
124 	drm_for_each_plane(plane, kms->dev) {
125 		if (plane->fb && plane->state) {
126 			dpu_plane_danger_signal_ctrl(plane, enable);
127 			DPU_DEBUG("plane:%d img:%dx%d ",
128 				plane->base.id, plane->fb->width,
129 				plane->fb->height);
130 			DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
131 				plane->state->src_x >> 16,
132 				plane->state->src_y >> 16,
133 				plane->state->src_w >> 16,
134 				plane->state->src_h >> 16,
135 				plane->state->crtc_x, plane->state->crtc_y,
136 				plane->state->crtc_w, plane->state->crtc_h);
137 		} else {
138 			DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
139 		}
140 	}
141 }
142 
_dpu_plane_danger_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)143 static ssize_t _dpu_plane_danger_write(struct file *file,
144 		    const char __user *user_buf, size_t count, loff_t *ppos)
145 {
146 	struct dpu_kms *kms = file->private_data;
147 	int disable_panic;
148 	int ret;
149 
150 	ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
151 	if (ret)
152 		return ret;
153 
154 	if (disable_panic) {
155 		/* Disable panic signal for all active pipes */
156 		DPU_DEBUG("Disabling danger:\n");
157 		_dpu_plane_set_danger_state(kms, false);
158 		kms->has_danger_ctrl = false;
159 	} else {
160 		/* Enable panic signal for all active pipes */
161 		DPU_DEBUG("Enabling danger:\n");
162 		kms->has_danger_ctrl = true;
163 		_dpu_plane_set_danger_state(kms, true);
164 	}
165 
166 	return count;
167 }
168 
169 static const struct file_operations dpu_plane_danger_enable = {
170 	.open = simple_open,
171 	.read = _dpu_plane_danger_read,
172 	.write = _dpu_plane_danger_write,
173 };
174 
dpu_debugfs_danger_init(struct dpu_kms * dpu_kms,struct dentry * parent)175 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
176 		struct dentry *parent)
177 {
178 	struct dentry *entry = debugfs_create_dir("danger", parent);
179 
180 	debugfs_create_file("danger_status", 0600, entry,
181 			dpu_kms, &dpu_debugfs_danger_stats_fops);
182 	debugfs_create_file("safe_status", 0600, entry,
183 			dpu_kms, &dpu_debugfs_safe_stats_fops);
184 	debugfs_create_file("disable_danger", 0600, entry,
185 			dpu_kms, &dpu_plane_danger_enable);
186 
187 }
188 
189 /*
190  * Companion structure for dpu_debugfs_create_regset32.
191  */
192 struct dpu_debugfs_regset32 {
193 	uint32_t offset;
194 	uint32_t blk_len;
195 	struct dpu_kms *dpu_kms;
196 };
197 
dpu_regset32_show(struct seq_file * s,void * data)198 static int dpu_regset32_show(struct seq_file *s, void *data)
199 {
200 	struct dpu_debugfs_regset32 *regset = s->private;
201 	struct dpu_kms *dpu_kms = regset->dpu_kms;
202 	void __iomem *base;
203 	uint32_t i, addr;
204 
205 	if (!dpu_kms->mmio)
206 		return 0;
207 
208 	base = dpu_kms->mmio + regset->offset;
209 
210 	/* insert padding spaces, if needed */
211 	if (regset->offset & 0xF) {
212 		seq_printf(s, "[%x]", regset->offset & ~0xF);
213 		for (i = 0; i < (regset->offset & 0xF); i += 4)
214 			seq_puts(s, "         ");
215 	}
216 
217 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
218 
219 	/* main register output */
220 	for (i = 0; i < regset->blk_len; i += 4) {
221 		addr = regset->offset + i;
222 		if ((addr & 0xF) == 0x0)
223 			seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
224 		seq_printf(s, " %08x", readl_relaxed(base + i));
225 	}
226 	seq_puts(s, "\n");
227 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
228 
229 	return 0;
230 }
231 DEFINE_SHOW_ATTRIBUTE(dpu_regset32);
232 
233 /**
234  * dpu_debugfs_create_regset32 - Create register read back file for debugfs
235  *
236  * This function is almost identical to the standard debugfs_create_regset32()
237  * function, with the main difference being that a list of register
238  * names/offsets do not need to be provided. The 'read' function simply outputs
239  * sequential register values over a specified range.
240  *
241  * @name:   File name within debugfs
242  * @mode:   File mode within debugfs
243  * @parent: Parent directory entry within debugfs, can be NULL
244  * @offset: sub-block offset
245  * @length: sub-block length, in bytes
246  * @dpu_kms: pointer to dpu kms structure
247  */
dpu_debugfs_create_regset32(const char * name,umode_t mode,void * parent,uint32_t offset,uint32_t length,struct dpu_kms * dpu_kms)248 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
249 		void *parent,
250 		uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
251 {
252 	struct dpu_debugfs_regset32 *regset;
253 
254 	if (WARN_ON(!name || !dpu_kms || !length))
255 		return;
256 
257 	regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL);
258 	if (!regset)
259 		return;
260 
261 	/* make sure offset is a multiple of 4 */
262 	regset->offset = round_down(offset, 4);
263 	regset->blk_len = length;
264 	regset->dpu_kms = dpu_kms;
265 
266 	debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
267 }
268 
dpu_debugfs_sspp_init(struct dpu_kms * dpu_kms,struct dentry * debugfs_root)269 static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
270 {
271 	struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
272 	int i;
273 
274 	if (IS_ERR(entry))
275 		return;
276 
277 	for (i = SSPP_NONE; i < SSPP_MAX; i++) {
278 		struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i);
279 
280 		if (!hw)
281 			continue;
282 
283 		_dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry);
284 	}
285 }
286 
dpu_kms_debugfs_init(struct msm_kms * kms,struct drm_minor * minor)287 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
288 {
289 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
290 	void *p = dpu_hw_util_get_log_mask_ptr();
291 	struct dentry *entry;
292 
293 	if (!p)
294 		return -EINVAL;
295 
296 	/* Only create a set of debugfs for the primary node, ignore render nodes */
297 	if (minor->type != DRM_MINOR_PRIMARY)
298 		return 0;
299 
300 	entry = debugfs_create_dir("debug", minor->debugfs_root);
301 
302 	debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
303 
304 	dpu_debugfs_danger_init(dpu_kms, entry);
305 	dpu_debugfs_vbif_init(dpu_kms, entry);
306 	dpu_debugfs_core_irq_init(dpu_kms, entry);
307 	dpu_debugfs_sspp_init(dpu_kms, entry);
308 
309 	return dpu_core_perf_debugfs_init(dpu_kms, entry);
310 }
311 #endif
312 
313 /* Global/shared object state funcs */
314 
315 /*
316  * This is a helper that returns the private state currently in operation.
317  * Note that this would return the "old_state" if called in the atomic check
318  * path, and the "new_state" after the atomic swap has been done.
319  */
320 struct dpu_global_state *
dpu_kms_get_existing_global_state(struct dpu_kms * dpu_kms)321 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
322 {
323 	return to_dpu_global_state(dpu_kms->global_state.state);
324 }
325 
326 /*
327  * This acquires the modeset lock set aside for global state, creates
328  * a new duplicated private object state.
329  */
dpu_kms_get_global_state(struct drm_atomic_state * s)330 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
331 {
332 	struct msm_drm_private *priv = s->dev->dev_private;
333 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
334 	struct drm_private_state *priv_state;
335 
336 	priv_state = drm_atomic_get_private_obj_state(s,
337 						&dpu_kms->global_state);
338 	if (IS_ERR(priv_state))
339 		return ERR_CAST(priv_state);
340 
341 	return to_dpu_global_state(priv_state);
342 }
343 
344 static struct drm_private_state *
dpu_kms_global_duplicate_state(struct drm_private_obj * obj)345 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
346 {
347 	struct dpu_global_state *state;
348 
349 	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
350 	if (!state)
351 		return NULL;
352 
353 	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
354 
355 	return &state->base;
356 }
357 
dpu_kms_global_destroy_state(struct drm_private_obj * obj,struct drm_private_state * state)358 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
359 				      struct drm_private_state *state)
360 {
361 	struct dpu_global_state *dpu_state = to_dpu_global_state(state);
362 
363 	kfree(dpu_state);
364 }
365 
dpu_kms_global_print_state(struct drm_printer * p,const struct drm_private_state * state)366 static void dpu_kms_global_print_state(struct drm_printer *p,
367 				       const struct drm_private_state *state)
368 {
369 	const struct dpu_global_state *global_state = to_dpu_global_state(state);
370 
371 	dpu_rm_print_state(p, global_state);
372 }
373 
374 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
375 	.atomic_duplicate_state = dpu_kms_global_duplicate_state,
376 	.atomic_destroy_state = dpu_kms_global_destroy_state,
377 	.atomic_print_state = dpu_kms_global_print_state,
378 };
379 
dpu_kms_global_obj_init(struct dpu_kms * dpu_kms)380 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
381 {
382 	struct dpu_global_state *state;
383 
384 	state = kzalloc(sizeof(*state), GFP_KERNEL);
385 	if (!state)
386 		return -ENOMEM;
387 
388 	drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
389 				    &state->base,
390 				    &dpu_kms_global_state_funcs);
391 
392 	state->rm = &dpu_kms->rm;
393 
394 	return 0;
395 }
396 
dpu_kms_global_obj_fini(struct dpu_kms * dpu_kms)397 static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms)
398 {
399 	drm_atomic_private_obj_fini(&dpu_kms->global_state);
400 }
401 
dpu_kms_parse_data_bus_icc_path(struct dpu_kms * dpu_kms)402 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
403 {
404 	struct icc_path *path0;
405 	struct icc_path *path1;
406 	struct device *dpu_dev = &dpu_kms->pdev->dev;
407 
408 	path0 = msm_icc_get(dpu_dev, "mdp0-mem");
409 	path1 = msm_icc_get(dpu_dev, "mdp1-mem");
410 
411 	if (IS_ERR_OR_NULL(path0))
412 		return PTR_ERR_OR_ZERO(path0);
413 
414 	dpu_kms->path[0] = path0;
415 	dpu_kms->num_paths = 1;
416 
417 	if (!IS_ERR_OR_NULL(path1)) {
418 		dpu_kms->path[1] = path1;
419 		dpu_kms->num_paths++;
420 	}
421 	return 0;
422 }
423 
dpu_kms_enable_vblank(struct msm_kms * kms,struct drm_crtc * crtc)424 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
425 {
426 	return dpu_crtc_vblank(crtc, true);
427 }
428 
dpu_kms_disable_vblank(struct msm_kms * kms,struct drm_crtc * crtc)429 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
430 {
431 	dpu_crtc_vblank(crtc, false);
432 }
433 
dpu_kms_enable_commit(struct msm_kms * kms)434 static void dpu_kms_enable_commit(struct msm_kms *kms)
435 {
436 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
437 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
438 }
439 
dpu_kms_disable_commit(struct msm_kms * kms)440 static void dpu_kms_disable_commit(struct msm_kms *kms)
441 {
442 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
443 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
444 }
445 
dpu_kms_flush_commit(struct msm_kms * kms,unsigned crtc_mask)446 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
447 {
448 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
449 	struct drm_crtc *crtc;
450 
451 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
452 		if (!crtc->state->active)
453 			continue;
454 
455 		trace_dpu_kms_commit(DRMID(crtc));
456 		dpu_crtc_commit_kickoff(crtc);
457 	}
458 }
459 
dpu_kms_complete_commit(struct msm_kms * kms,unsigned crtc_mask)460 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
461 {
462 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
463 	struct drm_crtc *crtc;
464 
465 	DPU_ATRACE_BEGIN("kms_complete_commit");
466 
467 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
468 		dpu_crtc_complete_commit(crtc);
469 
470 	DPU_ATRACE_END("kms_complete_commit");
471 }
472 
dpu_kms_wait_for_commit_done(struct msm_kms * kms,struct drm_crtc * crtc)473 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
474 		struct drm_crtc *crtc)
475 {
476 	struct drm_encoder *encoder;
477 	struct drm_device *dev;
478 	int ret;
479 
480 	if (!kms || !crtc || !crtc->state) {
481 		DPU_ERROR("invalid params\n");
482 		return;
483 	}
484 
485 	dev = crtc->dev;
486 
487 	if (!crtc->state->enable) {
488 		DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
489 		return;
490 	}
491 
492 	if (!drm_atomic_crtc_effectively_active(crtc->state)) {
493 		DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
494 		return;
495 	}
496 
497 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
498 		if (encoder->crtc != crtc)
499 			continue;
500 		/*
501 		 * Wait for post-flush if necessary to delay before
502 		 * plane_cleanup. For example, wait for vsync in case of video
503 		 * mode panels. This may be a no-op for command mode panels.
504 		 */
505 		trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
506 		ret = dpu_encoder_wait_for_commit_done(encoder);
507 		if (ret && ret != -EWOULDBLOCK) {
508 			DPU_ERROR("wait for commit done returned %d\n", ret);
509 			break;
510 		}
511 	}
512 }
513 
dpu_kms_wait_flush(struct msm_kms * kms,unsigned crtc_mask)514 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
515 {
516 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
517 	struct drm_crtc *crtc;
518 
519 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
520 		dpu_kms_wait_for_commit_done(kms, crtc);
521 }
522 
523 static const char *dpu_vsync_sources[] = {
524 	[DPU_VSYNC_SOURCE_GPIO_0] = "mdp_vsync_p",
525 	[DPU_VSYNC_SOURCE_GPIO_1] = "mdp_vsync_s",
526 	[DPU_VSYNC_SOURCE_GPIO_2] = "mdp_vsync_e",
527 	[DPU_VSYNC_SOURCE_INTF_0] = "mdp_intf0",
528 	[DPU_VSYNC_SOURCE_INTF_1] = "mdp_intf1",
529 	[DPU_VSYNC_SOURCE_INTF_2] = "mdp_intf2",
530 	[DPU_VSYNC_SOURCE_INTF_3] = "mdp_intf3",
531 	[DPU_VSYNC_SOURCE_WD_TIMER_0] = "timer0",
532 	[DPU_VSYNC_SOURCE_WD_TIMER_1] = "timer1",
533 	[DPU_VSYNC_SOURCE_WD_TIMER_2] = "timer2",
534 	[DPU_VSYNC_SOURCE_WD_TIMER_3] = "timer3",
535 	[DPU_VSYNC_SOURCE_WD_TIMER_4] = "timer4",
536 };
537 
dpu_kms_dsi_set_te_source(struct msm_display_info * info,struct msm_dsi * dsi)538 static int dpu_kms_dsi_set_te_source(struct msm_display_info *info,
539 				     struct msm_dsi *dsi)
540 {
541 	const char *te_source = msm_dsi_get_te_source(dsi);
542 	int i;
543 
544 	if (!te_source) {
545 		info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
546 		return 0;
547 	}
548 
549 	/* we can not use match_string since dpu_vsync_sources is a sparse array */
550 	for (i = 0; i < ARRAY_SIZE(dpu_vsync_sources); i++) {
551 		if (dpu_vsync_sources[i] &&
552 		    !strcmp(dpu_vsync_sources[i], te_source)) {
553 			info->vsync_source = i;
554 			return 0;
555 		}
556 	}
557 
558 	return -EINVAL;
559 }
560 
_dpu_kms_initialize_dsi(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)561 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
562 				    struct msm_drm_private *priv,
563 				    struct dpu_kms *dpu_kms)
564 {
565 	struct drm_encoder *encoder = NULL;
566 	struct msm_display_info info;
567 	int i, rc = 0;
568 
569 	if (!(priv->dsi[0] || priv->dsi[1]))
570 		return rc;
571 
572 	/*
573 	 * We support following confiurations:
574 	 * - Single DSI host (dsi0 or dsi1)
575 	 * - Two independent DSI hosts
576 	 * - Bonded DSI0 and DSI1 hosts
577 	 *
578 	 * TODO: Support swapping DSI0 and DSI1 in the bonded setup.
579 	 */
580 	for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
581 		int other = (i + 1) % 2;
582 
583 		if (!priv->dsi[i])
584 			continue;
585 
586 		if (msm_dsi_is_bonded_dsi(priv->dsi[i]) &&
587 		    !msm_dsi_is_master_dsi(priv->dsi[i]))
588 			continue;
589 
590 		memset(&info, 0, sizeof(info));
591 		info.intf_type = INTF_DSI;
592 
593 		info.h_tile_instance[info.num_of_h_tiles++] = i;
594 		if (msm_dsi_is_bonded_dsi(priv->dsi[i]))
595 			info.h_tile_instance[info.num_of_h_tiles++] = other;
596 
597 		info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
598 
599 		rc = dpu_kms_dsi_set_te_source(&info, priv->dsi[i]);
600 		if (rc) {
601 			DPU_ERROR("failed to identify TE source for dsi display\n");
602 			return rc;
603 		}
604 
605 		encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info);
606 		if (IS_ERR(encoder)) {
607 			DPU_ERROR("encoder init failed for dsi display\n");
608 			return PTR_ERR(encoder);
609 		}
610 
611 		rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
612 		if (rc) {
613 			DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
614 				i, rc);
615 			break;
616 		}
617 
618 		if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
619 			rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
620 			if (rc) {
621 				DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
622 					other, rc);
623 				break;
624 			}
625 		}
626 	}
627 
628 	return rc;
629 }
630 
_dpu_kms_initialize_displayport(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)631 static int _dpu_kms_initialize_displayport(struct drm_device *dev,
632 					    struct msm_drm_private *priv,
633 					    struct dpu_kms *dpu_kms)
634 {
635 	struct drm_encoder *encoder = NULL;
636 	struct msm_display_info info;
637 	bool yuv_supported;
638 	int rc;
639 	int i;
640 
641 	for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
642 		if (!priv->dp[i])
643 			continue;
644 
645 		memset(&info, 0, sizeof(info));
646 		info.num_of_h_tiles = 1;
647 		info.h_tile_instance[0] = i;
648 		info.intf_type = INTF_DP;
649 
650 		encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info);
651 		if (IS_ERR(encoder)) {
652 			DPU_ERROR("encoder init failed for dsi display\n");
653 			return PTR_ERR(encoder);
654 		}
655 
656 		yuv_supported = !!dpu_kms->catalog->cdm;
657 		rc = msm_dp_modeset_init(priv->dp[i], dev, encoder, yuv_supported);
658 		if (rc) {
659 			DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
660 			return rc;
661 		}
662 	}
663 
664 	return 0;
665 }
666 
_dpu_kms_initialize_hdmi(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)667 static int _dpu_kms_initialize_hdmi(struct drm_device *dev,
668 				    struct msm_drm_private *priv,
669 				    struct dpu_kms *dpu_kms)
670 {
671 	struct drm_encoder *encoder = NULL;
672 	struct msm_display_info info;
673 	int rc;
674 
675 	if (!priv->hdmi)
676 		return 0;
677 
678 	memset(&info, 0, sizeof(info));
679 	info.num_of_h_tiles = 1;
680 	info.h_tile_instance[0] = 0;
681 	info.intf_type = INTF_HDMI;
682 
683 	encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info);
684 	if (IS_ERR(encoder)) {
685 		DPU_ERROR("encoder init failed for HDMI display\n");
686 		return PTR_ERR(encoder);
687 	}
688 
689 	rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
690 	if (rc) {
691 		DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
692 		return rc;
693 	}
694 
695 	return 0;
696 }
697 
_dpu_kms_initialize_writeback(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms,const u32 * wb_formats,int n_formats)698 static int _dpu_kms_initialize_writeback(struct drm_device *dev,
699 		struct msm_drm_private *priv, struct dpu_kms *dpu_kms,
700 		const u32 *wb_formats, int n_formats)
701 {
702 	struct drm_encoder *encoder = NULL;
703 	struct msm_display_info info;
704 	const enum dpu_wb wb_idx = WB_2;
705 	u32 maxlinewidth;
706 	int rc;
707 
708 	memset(&info, 0, sizeof(info));
709 
710 	info.num_of_h_tiles = 1;
711 	/* use only WB idx 2 instance for DPU */
712 	info.h_tile_instance[0] = wb_idx;
713 	info.intf_type = INTF_WB;
714 
715 	maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth;
716 
717 	encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL, &info);
718 	if (IS_ERR(encoder)) {
719 		DPU_ERROR("encoder init failed for dsi display\n");
720 		return PTR_ERR(encoder);
721 	}
722 
723 	rc = dpu_writeback_init(dev, encoder, wb_formats, n_formats, maxlinewidth);
724 	if (rc) {
725 		DPU_ERROR("dpu_writeback_init, rc = %d\n", rc);
726 		return rc;
727 	}
728 
729 	return 0;
730 }
731 
732 /**
733  * _dpu_kms_setup_displays - create encoders, bridges and connectors
734  *                           for underlying displays
735  * @dev:        Pointer to drm device structure
736  * @priv:       Pointer to private drm device data
737  * @dpu_kms:    Pointer to dpu kms structure
738  * Returns:     Zero on success
739  */
_dpu_kms_setup_displays(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)740 static int _dpu_kms_setup_displays(struct drm_device *dev,
741 				    struct msm_drm_private *priv,
742 				    struct dpu_kms *dpu_kms)
743 {
744 	int rc = 0;
745 	int i;
746 
747 	rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
748 	if (rc) {
749 		DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
750 		return rc;
751 	}
752 
753 	rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
754 	if (rc) {
755 		DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
756 		return rc;
757 	}
758 
759 	rc = _dpu_kms_initialize_hdmi(dev, priv, dpu_kms);
760 	if (rc) {
761 		DPU_ERROR("initialize HDMI failed, rc = %d\n", rc);
762 		return rc;
763 	}
764 
765 	/* Since WB isn't a driver check the catalog before initializing */
766 	if (dpu_kms->catalog->wb_count) {
767 		for (i = 0; i < dpu_kms->catalog->wb_count; i++) {
768 			if (dpu_kms->catalog->wb[i].id == WB_2) {
769 				rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms,
770 						dpu_kms->catalog->wb[i].format_list,
771 						dpu_kms->catalog->wb[i].num_formats);
772 				if (rc) {
773 					DPU_ERROR("initialize_WB failed, rc = %d\n", rc);
774 					return rc;
775 				}
776 			}
777 		}
778 	}
779 
780 	return rc;
781 }
782 
783 #define MAX_PLANES 20
_dpu_kms_drm_obj_init(struct dpu_kms * dpu_kms)784 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
785 {
786 	struct drm_device *dev;
787 	struct drm_plane *primary_planes[MAX_PLANES], *plane;
788 	struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
789 	struct drm_crtc *crtc;
790 	struct drm_encoder *encoder;
791 	unsigned int num_encoders;
792 
793 	struct msm_drm_private *priv;
794 	const struct dpu_mdss_cfg *catalog;
795 
796 	int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
797 	int max_crtc_count;
798 	dev = dpu_kms->dev;
799 	priv = dev->dev_private;
800 	catalog = dpu_kms->catalog;
801 
802 	/*
803 	 * Create encoder and query display drivers to create
804 	 * bridges and connectors
805 	 */
806 	ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
807 	if (ret)
808 		return ret;
809 
810 	num_encoders = 0;
811 	drm_for_each_encoder(encoder, dev)
812 		num_encoders++;
813 
814 	max_crtc_count = min(catalog->mixer_count, num_encoders);
815 
816 	/* Create the planes, keeping track of one primary/cursor per crtc */
817 	for (i = 0; i < catalog->sspp_count; i++) {
818 		enum drm_plane_type type;
819 
820 		if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
821 			&& cursor_planes_idx < max_crtc_count)
822 			type = DRM_PLANE_TYPE_CURSOR;
823 		else if (primary_planes_idx < max_crtc_count)
824 			type = DRM_PLANE_TYPE_PRIMARY;
825 		else
826 			type = DRM_PLANE_TYPE_OVERLAY;
827 
828 		DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
829 			  type, catalog->sspp[i].features,
830 			  catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
831 
832 		plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
833 				       (1UL << max_crtc_count) - 1);
834 		if (IS_ERR(plane)) {
835 			DPU_ERROR("dpu_plane_init failed\n");
836 			ret = PTR_ERR(plane);
837 			return ret;
838 		}
839 
840 		if (type == DRM_PLANE_TYPE_CURSOR)
841 			cursor_planes[cursor_planes_idx++] = plane;
842 		else if (type == DRM_PLANE_TYPE_PRIMARY)
843 			primary_planes[primary_planes_idx++] = plane;
844 	}
845 
846 	max_crtc_count = min(max_crtc_count, primary_planes_idx);
847 
848 	/* Create one CRTC per encoder */
849 	for (i = 0; i < max_crtc_count; i++) {
850 		crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
851 		if (IS_ERR(crtc)) {
852 			ret = PTR_ERR(crtc);
853 			return ret;
854 		}
855 		priv->num_crtcs++;
856 	}
857 
858 	/* All CRTCs are compatible with all encoders */
859 	drm_for_each_encoder(encoder, dev)
860 		encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
861 
862 	return 0;
863 }
864 
_dpu_kms_hw_destroy(struct dpu_kms * dpu_kms)865 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
866 {
867 	int i;
868 
869 	dpu_kms->hw_intr = NULL;
870 
871 	/* safe to call these more than once during shutdown */
872 	_dpu_kms_mmu_destroy(dpu_kms);
873 
874 	for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
875 		dpu_kms->hw_vbif[i] = NULL;
876 	}
877 
878 	dpu_kms_global_obj_fini(dpu_kms);
879 
880 	dpu_kms->catalog = NULL;
881 
882 	dpu_kms->hw_mdp = NULL;
883 }
884 
dpu_kms_destroy(struct msm_kms * kms)885 static void dpu_kms_destroy(struct msm_kms *kms)
886 {
887 	struct dpu_kms *dpu_kms;
888 
889 	if (!kms) {
890 		DPU_ERROR("invalid kms\n");
891 		return;
892 	}
893 
894 	dpu_kms = to_dpu_kms(kms);
895 
896 	_dpu_kms_hw_destroy(dpu_kms);
897 
898 	msm_kms_destroy(&dpu_kms->base);
899 
900 	if (dpu_kms->rpm_enabled)
901 		pm_runtime_disable(&dpu_kms->pdev->dev);
902 }
903 
dpu_irq_postinstall(struct msm_kms * kms)904 static int dpu_irq_postinstall(struct msm_kms *kms)
905 {
906 	struct msm_drm_private *priv;
907 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
908 
909 	if (!dpu_kms || !dpu_kms->dev)
910 		return -EINVAL;
911 
912 	priv = dpu_kms->dev->dev_private;
913 	if (!priv)
914 		return -EINVAL;
915 
916 	return 0;
917 }
918 
dpu_kms_mdp_snapshot(struct msm_disp_state * disp_state,struct msm_kms * kms)919 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms)
920 {
921 	int i;
922 	struct dpu_kms *dpu_kms;
923 	const struct dpu_mdss_cfg *cat;
924 	void __iomem *base;
925 
926 	dpu_kms = to_dpu_kms(kms);
927 
928 	cat = dpu_kms->catalog;
929 
930 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
931 
932 	/* dump CTL sub-blocks HW regs info */
933 	for (i = 0; i < cat->ctl_count; i++)
934 		msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
935 				dpu_kms->mmio + cat->ctl[i].base, cat->ctl[i].name);
936 
937 	/* dump DSPP sub-blocks HW regs info */
938 	for (i = 0; i < cat->dspp_count; i++) {
939 		base = dpu_kms->mmio + cat->dspp[i].base;
940 		msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base, cat->dspp[i].name);
941 
942 		if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0)
943 			msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len,
944 						    base + cat->dspp[i].sblk->pcc.base, "%s_%s",
945 						    cat->dspp[i].name,
946 						    cat->dspp[i].sblk->pcc.name);
947 	}
948 
949 	/* dump INTF sub-blocks HW regs info */
950 	for (i = 0; i < cat->intf_count; i++)
951 		msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
952 				dpu_kms->mmio + cat->intf[i].base, cat->intf[i].name);
953 
954 	/* dump PP sub-blocks HW regs info */
955 	for (i = 0; i < cat->pingpong_count; i++) {
956 		base = dpu_kms->mmio + cat->pingpong[i].base;
957 		msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base,
958 					    cat->pingpong[i].name);
959 
960 		/* TE2 sub-block has length of 0, so will not print it */
961 
962 		if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0)
963 			msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len,
964 						    base + cat->pingpong[i].sblk->dither.base,
965 						    "%s_%s", cat->pingpong[i].name,
966 						    cat->pingpong[i].sblk->dither.name);
967 	}
968 
969 	/* dump SSPP sub-blocks HW regs info */
970 	for (i = 0; i < cat->sspp_count; i++) {
971 		base = dpu_kms->mmio + cat->sspp[i].base;
972 		msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base, cat->sspp[i].name);
973 
974 		if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0)
975 			msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len,
976 						    base + cat->sspp[i].sblk->scaler_blk.base,
977 						    "%s_%s", cat->sspp[i].name,
978 						    cat->sspp[i].sblk->scaler_blk.name);
979 
980 		if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0)
981 			msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len,
982 						    base + cat->sspp[i].sblk->csc_blk.base,
983 						    "%s_%s", cat->sspp[i].name,
984 						    cat->sspp[i].sblk->csc_blk.name);
985 	}
986 
987 	/* dump LM sub-blocks HW regs info */
988 	for (i = 0; i < cat->mixer_count; i++)
989 		msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
990 				dpu_kms->mmio + cat->mixer[i].base, cat->mixer[i].name);
991 
992 	/* dump WB sub-blocks HW regs info */
993 	for (i = 0; i < cat->wb_count; i++)
994 		msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
995 				dpu_kms->mmio + cat->wb[i].base, cat->wb[i].name);
996 
997 	if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
998 		msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
999 				dpu_kms->mmio + cat->mdp[0].base, "top");
1000 		msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END,
1001 				dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2");
1002 	} else {
1003 		msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
1004 				dpu_kms->mmio + cat->mdp[0].base, "top");
1005 	}
1006 
1007 	/* dump DSC sub-blocks HW regs info */
1008 	for (i = 0; i < cat->dsc_count; i++) {
1009 		base = dpu_kms->mmio + cat->dsc[i].base;
1010 		msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, cat->dsc[i].name);
1011 
1012 		if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
1013 			struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
1014 			struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
1015 
1016 			msm_disp_snapshot_add_block(disp_state, enc.len, base + enc.base, "%s_%s",
1017 						    cat->dsc[i].name, enc.name);
1018 			msm_disp_snapshot_add_block(disp_state, ctl.len, base + ctl.base, "%s_%s",
1019 						    cat->dsc[i].name, ctl.name);
1020 		}
1021 	}
1022 
1023 	if (cat->cdm)
1024 		msm_disp_snapshot_add_block(disp_state, cat->cdm->len,
1025 					    dpu_kms->mmio + cat->cdm->base, cat->cdm->name);
1026 
1027 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1028 }
1029 
1030 static const struct msm_kms_funcs kms_funcs = {
1031 	.hw_init         = dpu_kms_hw_init,
1032 	.irq_preinstall  = dpu_core_irq_preinstall,
1033 	.irq_postinstall = dpu_irq_postinstall,
1034 	.irq_uninstall   = dpu_core_irq_uninstall,
1035 	.irq             = dpu_core_irq,
1036 	.enable_commit   = dpu_kms_enable_commit,
1037 	.disable_commit  = dpu_kms_disable_commit,
1038 	.flush_commit    = dpu_kms_flush_commit,
1039 	.wait_flush      = dpu_kms_wait_flush,
1040 	.complete_commit = dpu_kms_complete_commit,
1041 	.enable_vblank   = dpu_kms_enable_vblank,
1042 	.disable_vblank  = dpu_kms_disable_vblank,
1043 	.destroy         = dpu_kms_destroy,
1044 	.snapshot        = dpu_kms_mdp_snapshot,
1045 #ifdef CONFIG_DEBUG_FS
1046 	.debugfs_init    = dpu_kms_debugfs_init,
1047 #endif
1048 };
1049 
_dpu_kms_mmu_destroy(struct dpu_kms * dpu_kms)1050 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
1051 {
1052 	struct msm_mmu *mmu;
1053 
1054 	if (!dpu_kms->base.aspace)
1055 		return;
1056 
1057 	mmu = dpu_kms->base.aspace->mmu;
1058 
1059 	mmu->funcs->detach(mmu);
1060 	msm_gem_address_space_put(dpu_kms->base.aspace);
1061 
1062 	dpu_kms->base.aspace = NULL;
1063 }
1064 
_dpu_kms_mmu_init(struct dpu_kms * dpu_kms)1065 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
1066 {
1067 	struct msm_gem_address_space *aspace;
1068 
1069 	aspace = msm_kms_init_aspace(dpu_kms->dev);
1070 	if (IS_ERR(aspace))
1071 		return PTR_ERR(aspace);
1072 
1073 	dpu_kms->base.aspace = aspace;
1074 
1075 	return 0;
1076 }
1077 
1078 /**
1079  * dpu_kms_get_clk_rate() - get the clock rate
1080  * @dpu_kms:  pointer to dpu_kms structure
1081  * @clock_name: clock name to get the rate
1082  *
1083  * Return: current clock rate
1084  */
dpu_kms_get_clk_rate(struct dpu_kms * dpu_kms,char * clock_name)1085 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
1086 {
1087 	struct clk *clk;
1088 
1089 	clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name);
1090 	if (!clk)
1091 		return 0;
1092 
1093 	return clk_get_rate(clk);
1094 }
1095 
1096 #define	DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE	412500000
1097 
dpu_kms_hw_init(struct msm_kms * kms)1098 static int dpu_kms_hw_init(struct msm_kms *kms)
1099 {
1100 	struct dpu_kms *dpu_kms;
1101 	struct drm_device *dev;
1102 	int i, rc = -EINVAL;
1103 	unsigned long max_core_clk_rate;
1104 	u32 core_rev;
1105 
1106 	if (!kms) {
1107 		DPU_ERROR("invalid kms\n");
1108 		return rc;
1109 	}
1110 
1111 	dpu_kms = to_dpu_kms(kms);
1112 	dev = dpu_kms->dev;
1113 
1114 	dev->mode_config.cursor_width = 512;
1115 	dev->mode_config.cursor_height = 512;
1116 
1117 	rc = dpu_kms_global_obj_init(dpu_kms);
1118 	if (rc)
1119 		return rc;
1120 
1121 	atomic_set(&dpu_kms->bandwidth_ref, 0);
1122 
1123 	rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev);
1124 	if (rc < 0)
1125 		goto error;
1126 
1127 	core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
1128 
1129 	pr_info("dpu hardware revision:0x%x\n", core_rev);
1130 
1131 	dpu_kms->catalog = of_device_get_match_data(dev->dev);
1132 	if (!dpu_kms->catalog) {
1133 		DPU_ERROR("device config not known!\n");
1134 		rc = -EINVAL;
1135 		goto err_pm_put;
1136 	}
1137 
1138 	/*
1139 	 * Now we need to read the HW catalog and initialize resources such as
1140 	 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
1141 	 */
1142 	rc = _dpu_kms_mmu_init(dpu_kms);
1143 	if (rc) {
1144 		DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
1145 		goto err_pm_put;
1146 	}
1147 
1148 	dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent);
1149 	if (IS_ERR(dpu_kms->mdss)) {
1150 		rc = PTR_ERR(dpu_kms->mdss);
1151 		DPU_ERROR("failed to get MDSS data: %d\n", rc);
1152 		goto err_pm_put;
1153 	}
1154 
1155 	if (!dpu_kms->mdss) {
1156 		rc = -EINVAL;
1157 		DPU_ERROR("NULL MDSS data\n");
1158 		goto err_pm_put;
1159 	}
1160 
1161 	rc = dpu_rm_init(dev, &dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio);
1162 	if (rc) {
1163 		DPU_ERROR("rm init failed: %d\n", rc);
1164 		goto err_pm_put;
1165 	}
1166 
1167 	dpu_kms->hw_mdp = dpu_hw_mdptop_init(dev,
1168 					     dpu_kms->catalog->mdp,
1169 					     dpu_kms->mmio,
1170 					     dpu_kms->catalog->mdss_ver);
1171 	if (IS_ERR(dpu_kms->hw_mdp)) {
1172 		rc = PTR_ERR(dpu_kms->hw_mdp);
1173 		DPU_ERROR("failed to get hw_mdp: %d\n", rc);
1174 		dpu_kms->hw_mdp = NULL;
1175 		goto err_pm_put;
1176 	}
1177 
1178 	for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
1179 		struct dpu_hw_vbif *hw;
1180 		const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i];
1181 
1182 		hw = dpu_hw_vbif_init(dev, vbif, dpu_kms->vbif[vbif->id]);
1183 		if (IS_ERR(hw)) {
1184 			rc = PTR_ERR(hw);
1185 			DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc);
1186 			goto err_pm_put;
1187 		}
1188 
1189 		dpu_kms->hw_vbif[vbif->id] = hw;
1190 	}
1191 
1192 	/* TODO: use the same max_freq as in dpu_kms_hw_init */
1193 	max_core_clk_rate = dpu_kms_get_clk_rate(dpu_kms, "core");
1194 	if (!max_core_clk_rate) {
1195 		DPU_DEBUG("max core clk rate not determined, using default\n");
1196 		max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
1197 	}
1198 
1199 	rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate);
1200 	if (rc) {
1201 		DPU_ERROR("failed to init perf %d\n", rc);
1202 		goto err_pm_put;
1203 	}
1204 
1205 	/*
1206 	 * We need to program DP <-> PHY relationship only for SC8180X since it
1207 	 * has fewer DP controllers than DP PHYs.
1208 	 * If any other platform requires the same kind of programming, or if
1209 	 * the INTF <->DP relationship isn't static anymore, this needs to be
1210 	 * configured through the DT.
1211 	 */
1212 	if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,sc8180x-dpu"))
1213 		dpu_kms->hw_mdp->ops.dp_phy_intf_sel(dpu_kms->hw_mdp, (unsigned int[]){ 1, 2, });
1214 
1215 	dpu_kms->hw_intr = dpu_hw_intr_init(dev, dpu_kms->mmio, dpu_kms->catalog);
1216 	if (IS_ERR(dpu_kms->hw_intr)) {
1217 		rc = PTR_ERR(dpu_kms->hw_intr);
1218 		DPU_ERROR("hw_intr init failed: %d\n", rc);
1219 		dpu_kms->hw_intr = NULL;
1220 		goto err_pm_put;
1221 	}
1222 
1223 	dev->mode_config.min_width = 0;
1224 	dev->mode_config.min_height = 0;
1225 
1226 	dev->mode_config.max_width = DPU_MAX_IMG_WIDTH;
1227 	dev->mode_config.max_height = DPU_MAX_IMG_HEIGHT;
1228 
1229 	dev->max_vblank_count = 0xffffffff;
1230 	/* Disable vblank irqs aggressively for power-saving */
1231 	dev->vblank_disable_immediate = true;
1232 
1233 	/*
1234 	 * _dpu_kms_drm_obj_init should create the DRM related objects
1235 	 * i.e. CRTCs, planes, encoders, connectors and so forth
1236 	 */
1237 	rc = _dpu_kms_drm_obj_init(dpu_kms);
1238 	if (rc) {
1239 		DPU_ERROR("modeset init failed: %d\n", rc);
1240 		goto err_pm_put;
1241 	}
1242 
1243 	dpu_vbif_init_memtypes(dpu_kms);
1244 
1245 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1246 
1247 	return 0;
1248 
1249 err_pm_put:
1250 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1251 error:
1252 	_dpu_kms_hw_destroy(dpu_kms);
1253 
1254 	return rc;
1255 }
1256 
dpu_kms_init(struct drm_device * ddev)1257 static int dpu_kms_init(struct drm_device *ddev)
1258 {
1259 	struct msm_drm_private *priv = ddev->dev_private;
1260 	struct device *dev = ddev->dev;
1261 	struct platform_device *pdev = to_platform_device(dev);
1262 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1263 	struct dev_pm_opp *opp;
1264 	int ret = 0;
1265 	unsigned long max_freq = ULONG_MAX;
1266 
1267 	opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
1268 	if (!IS_ERR(opp))
1269 		dev_pm_opp_put(opp);
1270 
1271 	dev_pm_opp_set_rate(dev, max_freq);
1272 
1273 	ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1274 	if (ret) {
1275 		DPU_ERROR("failed to init kms, ret=%d\n", ret);
1276 		return ret;
1277 	}
1278 	dpu_kms->dev = ddev;
1279 
1280 	pm_runtime_enable(&pdev->dev);
1281 	dpu_kms->rpm_enabled = true;
1282 
1283 	return 0;
1284 }
1285 
dpu_kms_mmap_mdp5(struct dpu_kms * dpu_kms)1286 static int dpu_kms_mmap_mdp5(struct dpu_kms *dpu_kms)
1287 {
1288 	struct platform_device *pdev = dpu_kms->pdev;
1289 	struct platform_device *mdss_dev;
1290 	int ret;
1291 
1292 	if (!dev_is_platform(dpu_kms->pdev->dev.parent))
1293 		return -EINVAL;
1294 
1295 	mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent);
1296 
1297 	dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys");
1298 	if (IS_ERR(dpu_kms->mmio)) {
1299 		ret = PTR_ERR(dpu_kms->mmio);
1300 		DPU_ERROR("mdp register memory map failed: %d\n", ret);
1301 		dpu_kms->mmio = NULL;
1302 		return ret;
1303 	}
1304 	DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
1305 
1306 	dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev,
1307 						  dpu_kms->pdev,
1308 						  "vbif_phys");
1309 	if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
1310 		ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
1311 		DPU_ERROR("vbif register memory map failed: %d\n", ret);
1312 		dpu_kms->vbif[VBIF_RT] = NULL;
1313 		return ret;
1314 	}
1315 
1316 	dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev,
1317 						   dpu_kms->pdev,
1318 						   "vbif_nrt_phys");
1319 	if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
1320 		dpu_kms->vbif[VBIF_NRT] = NULL;
1321 		DPU_DEBUG("VBIF NRT is not defined");
1322 	}
1323 
1324 	return 0;
1325 }
1326 
dpu_kms_mmap_dpu(struct dpu_kms * dpu_kms)1327 static int dpu_kms_mmap_dpu(struct dpu_kms *dpu_kms)
1328 {
1329 	struct platform_device *pdev = dpu_kms->pdev;
1330 	int ret;
1331 
1332 	dpu_kms->mmio = msm_ioremap(pdev, "mdp");
1333 	if (IS_ERR(dpu_kms->mmio)) {
1334 		ret = PTR_ERR(dpu_kms->mmio);
1335 		DPU_ERROR("mdp register memory map failed: %d\n", ret);
1336 		dpu_kms->mmio = NULL;
1337 		return ret;
1338 	}
1339 	DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
1340 
1341 	dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif");
1342 	if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
1343 		ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
1344 		DPU_ERROR("vbif register memory map failed: %d\n", ret);
1345 		dpu_kms->vbif[VBIF_RT] = NULL;
1346 		return ret;
1347 	}
1348 
1349 	dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt");
1350 	if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
1351 		dpu_kms->vbif[VBIF_NRT] = NULL;
1352 		DPU_DEBUG("VBIF NRT is not defined");
1353 	}
1354 
1355 	return 0;
1356 }
1357 
dpu_dev_probe(struct platform_device * pdev)1358 static int dpu_dev_probe(struct platform_device *pdev)
1359 {
1360 	struct device *dev = &pdev->dev;
1361 	struct dpu_kms *dpu_kms;
1362 	int irq;
1363 	int ret = 0;
1364 
1365 	if (!msm_disp_drv_should_bind(&pdev->dev, true))
1366 		return -ENODEV;
1367 
1368 	dpu_kms = devm_kzalloc(dev, sizeof(*dpu_kms), GFP_KERNEL);
1369 	if (!dpu_kms)
1370 		return -ENOMEM;
1371 
1372 	dpu_kms->pdev = pdev;
1373 
1374 	ret = devm_pm_opp_set_clkname(dev, "core");
1375 	if (ret)
1376 		return ret;
1377 	/* OPP table is optional */
1378 	ret = devm_pm_opp_of_add_table(dev);
1379 	if (ret && ret != -ENODEV)
1380 		return dev_err_probe(dev, ret, "invalid OPP table in device tree\n");
1381 
1382 	ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);
1383 	if (ret < 0)
1384 		return dev_err_probe(dev, ret, "failed to parse clocks\n");
1385 
1386 	dpu_kms->num_clocks = ret;
1387 
1388 	irq = platform_get_irq(pdev, 0);
1389 	if (irq < 0)
1390 		return dev_err_probe(dev, irq, "failed to get irq\n");
1391 
1392 	dpu_kms->base.irq = irq;
1393 
1394 	if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5"))
1395 		ret = dpu_kms_mmap_mdp5(dpu_kms);
1396 	else
1397 		ret = dpu_kms_mmap_dpu(dpu_kms);
1398 	if (ret)
1399 		return ret;
1400 
1401 	ret = dpu_kms_parse_data_bus_icc_path(dpu_kms);
1402 	if (ret)
1403 		return ret;
1404 
1405 	return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base);
1406 }
1407 
dpu_dev_remove(struct platform_device * pdev)1408 static void dpu_dev_remove(struct platform_device *pdev)
1409 {
1410 	component_master_del(&pdev->dev, &msm_drm_ops);
1411 }
1412 
dpu_runtime_suspend(struct device * dev)1413 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1414 {
1415 	int i;
1416 	struct platform_device *pdev = to_platform_device(dev);
1417 	struct msm_drm_private *priv = platform_get_drvdata(pdev);
1418 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1419 
1420 	/* Drop the performance state vote */
1421 	dev_pm_opp_set_rate(dev, 0);
1422 	clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks);
1423 
1424 	for (i = 0; i < dpu_kms->num_paths; i++)
1425 		icc_set_bw(dpu_kms->path[i], 0, 0);
1426 
1427 	return 0;
1428 }
1429 
dpu_runtime_resume(struct device * dev)1430 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1431 {
1432 	int rc = -1;
1433 	struct platform_device *pdev = to_platform_device(dev);
1434 	struct msm_drm_private *priv = platform_get_drvdata(pdev);
1435 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1436 	struct drm_encoder *encoder;
1437 	struct drm_device *ddev;
1438 
1439 	ddev = dpu_kms->dev;
1440 
1441 	rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks);
1442 	if (rc) {
1443 		DPU_ERROR("clock enable failed rc:%d\n", rc);
1444 		return rc;
1445 	}
1446 
1447 	dpu_vbif_init_memtypes(dpu_kms);
1448 
1449 	drm_for_each_encoder(encoder, ddev)
1450 		dpu_encoder_virt_runtime_resume(encoder);
1451 
1452 	return rc;
1453 }
1454 
1455 static const struct dev_pm_ops dpu_pm_ops = {
1456 	SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1457 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1458 				pm_runtime_force_resume)
1459 	.prepare = msm_kms_pm_prepare,
1460 	.complete = msm_kms_pm_complete,
1461 };
1462 
1463 static const struct of_device_id dpu_dt_match[] = {
1464 	{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
1465 	{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
1466 	{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
1467 	{ .compatible = "qcom,msm8996-mdp5", .data = &dpu_msm8996_cfg, },
1468 	{ .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1469 	{ .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1470 	{ .compatible = "qcom,sa8775p-dpu", .data = &dpu_sa8775p_cfg, },
1471 	{ .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, },
1472 	{ .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, },
1473 	{ .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
1474 	{ .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1475 	{ .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
1476 	{ .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
1477 	{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
1478 	{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
1479 	{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
1480 	{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
1481 	{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
1482 	{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
1483 	{ .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
1484 	{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
1485 	{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
1486 	{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
1487 	{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
1488 	{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
1489 	{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
1490 	{ .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
1491 	{}
1492 };
1493 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1494 
1495 static struct platform_driver dpu_driver = {
1496 	.probe = dpu_dev_probe,
1497 	.remove = dpu_dev_remove,
1498 	.shutdown = msm_kms_shutdown,
1499 	.driver = {
1500 		.name = "msm_dpu",
1501 		.of_match_table = dpu_dt_match,
1502 		.pm = &dpu_pm_ops,
1503 	},
1504 };
1505 
msm_dpu_register(void)1506 void __init msm_dpu_register(void)
1507 {
1508 	platform_driver_register(&dpu_driver);
1509 }
1510 
msm_dpu_unregister(void)1511 void __exit msm_dpu_unregister(void)
1512 {
1513 	platform_driver_unregister(&dpu_driver);
1514 }
1515