1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
8 #include <linux/debugfs.h>
9
10 #include <drm/drm_framebuffer.h>
11 #include <drm/drm_managed.h>
12
13 #include "dpu_encoder_phys.h"
14 #include "dpu_formats.h"
15 #include "dpu_hw_top.h"
16 #include "dpu_hw_wb.h"
17 #include "dpu_hw_lm.h"
18 #include "dpu_hw_merge3d.h"
19 #include "dpu_hw_interrupts.h"
20 #include "dpu_core_irq.h"
21 #include "dpu_vbif.h"
22 #include "dpu_crtc.h"
23 #include "disp/msm_disp_snapshot.h"
24
25 #define to_dpu_encoder_phys_wb(x) \
26 container_of(x, struct dpu_encoder_phys_wb, base)
27
28 /**
29 * dpu_encoder_phys_wb_is_master - report wb always as master encoder
30 * @phys_enc: Pointer to physical encoder
31 */
dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys * phys_enc)32 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
33 {
34 /* there is only one physical enc for dpu_writeback */
35 return true;
36 }
37
_dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb * wb,struct dpu_hw_mdp * mdp,bool enable,bool * forced_on)38 static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb,
39 struct dpu_hw_mdp *mdp,
40 bool enable, bool *forced_on)
41 {
42 if (wb->ops.setup_clk_force_ctrl) {
43 *forced_on = wb->ops.setup_clk_force_ctrl(wb, enable);
44 return true;
45 }
46
47 if (mdp->ops.setup_clk_force_ctrl) {
48 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable);
49 return true;
50 }
51
52 return false;
53 }
54
55 /**
56 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
57 * @phys_enc: Pointer to physical encoder
58 */
dpu_encoder_phys_wb_set_ot_limit(struct dpu_encoder_phys * phys_enc)59 static void dpu_encoder_phys_wb_set_ot_limit(
60 struct dpu_encoder_phys *phys_enc)
61 {
62 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
63 struct dpu_vbif_set_ot_params ot_params;
64 bool forced_on = false;
65
66 memset(&ot_params, 0, sizeof(ot_params));
67 ot_params.xin_id = hw_wb->caps->xin_id;
68 ot_params.num = hw_wb->idx - WB_0;
69 ot_params.width = phys_enc->cached_mode.hdisplay;
70 ot_params.height = phys_enc->cached_mode.vdisplay;
71 ot_params.is_wfd = true;
72 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
73 ot_params.vbif_idx = hw_wb->caps->vbif_idx;
74 ot_params.rd = false;
75
76 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
77 true, &forced_on))
78 return;
79
80 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
81
82 if (forced_on)
83 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
84 false, &forced_on);
85 }
86
87 /**
88 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
89 * @phys_enc: Pointer to physical encoder
90 */
dpu_encoder_phys_wb_set_qos_remap(struct dpu_encoder_phys * phys_enc)91 static void dpu_encoder_phys_wb_set_qos_remap(
92 struct dpu_encoder_phys *phys_enc)
93 {
94 struct dpu_hw_wb *hw_wb;
95 struct dpu_vbif_set_qos_params qos_params;
96 bool forced_on = false;
97
98 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
99 DPU_ERROR("invalid arguments\n");
100 return;
101 }
102
103 if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {
104 DPU_ERROR("invalid writeback hardware\n");
105 return;
106 }
107
108 hw_wb = phys_enc->hw_wb;
109
110 memset(&qos_params, 0, sizeof(qos_params));
111 qos_params.vbif_idx = hw_wb->caps->vbif_idx;
112 qos_params.xin_id = hw_wb->caps->xin_id;
113 qos_params.num = hw_wb->idx - WB_0;
114 qos_params.is_rt = false;
115
116 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
117 qos_params.num,
118 qos_params.vbif_idx,
119 qos_params.xin_id, qos_params.is_rt);
120
121 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
122 true, &forced_on))
123 return;
124
125 dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
126
127 if (forced_on)
128 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
129 false, &forced_on);
130 }
131
132 /**
133 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
134 * @phys_enc: Pointer to physical encoder
135 */
dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys * phys_enc)136 static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
137 {
138 struct dpu_hw_wb *hw_wb;
139 struct dpu_hw_qos_cfg qos_cfg;
140 const struct dpu_mdss_cfg *catalog;
141 const struct dpu_qos_lut_tbl *qos_lut_tb;
142
143 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
144 DPU_ERROR("invalid parameter(s)\n");
145 return;
146 }
147
148 catalog = phys_enc->dpu_kms->catalog;
149
150 hw_wb = phys_enc->hw_wb;
151
152 memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));
153 qos_cfg.danger_safe_en = true;
154 qos_cfg.danger_lut =
155 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
156
157 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
158
159 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
160 qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
161
162 if (hw_wb->ops.setup_qos_lut)
163 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
164 }
165
166 /**
167 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer
168 * @phys_enc: Pointer to physical encoder
169 * @format: Format of the framebuffer
170 */
dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys * phys_enc,const struct msm_format * format)171 static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
172 const struct msm_format *format)
173 {
174 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
175 struct dpu_hw_wb *hw_wb;
176 struct dpu_hw_wb_cfg *wb_cfg;
177
178 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
179 DPU_ERROR("invalid encoder\n");
180 return;
181 }
182
183 hw_wb = phys_enc->hw_wb;
184 wb_cfg = &wb_enc->wb_cfg;
185
186 wb_cfg->intf_mode = phys_enc->intf_mode;
187 wb_cfg->roi.x1 = 0;
188 wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;
189 wb_cfg->roi.y1 = 0;
190 wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;
191
192 if (hw_wb->ops.setup_roi)
193 hw_wb->ops.setup_roi(hw_wb, wb_cfg);
194
195 if (hw_wb->ops.setup_outformat)
196 hw_wb->ops.setup_outformat(hw_wb, wb_cfg, format);
197
198 if (hw_wb->ops.setup_cdp) {
199 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;
200
201 hw_wb->ops.setup_cdp(hw_wb, format,
202 perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);
203 }
204
205 if (hw_wb->ops.setup_outaddress)
206 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
207 }
208
209 /**
210 * dpu_encoder_phys_wb_setup_ctl - setup wb pipeline for ctl path
211 * @phys_enc:Pointer to physical encoder
212 */
dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys * phys_enc)213 static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
214 {
215 struct dpu_hw_wb *hw_wb;
216 struct dpu_hw_ctl *ctl;
217 struct dpu_hw_cdm *hw_cdm;
218
219 if (!phys_enc) {
220 DPU_ERROR("invalid encoder\n");
221 return;
222 }
223
224 hw_wb = phys_enc->hw_wb;
225 ctl = phys_enc->hw_ctl;
226 hw_cdm = phys_enc->hw_cdm;
227
228 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
229 (phys_enc->hw_ctl &&
230 phys_enc->hw_ctl->ops.setup_intf_cfg)) {
231 struct dpu_hw_intf_cfg intf_cfg = {0};
232 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
233 enum dpu_3d_blend_mode mode_3d;
234
235 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
236
237 intf_cfg.intf = DPU_NONE;
238 intf_cfg.wb = hw_wb->idx;
239
240 if (mode_3d && hw_pp && hw_pp->merge_3d)
241 intf_cfg.merge_3d = hw_pp->merge_3d->idx;
242
243 if (hw_cdm)
244 intf_cfg.cdm = hw_cdm->idx;
245
246 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)
247 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
248 mode_3d);
249
250 /* setup which pp blk will connect to this wb */
251 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk)
252 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb,
253 phys_enc->hw_pp->idx);
254
255 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
256 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
257 struct dpu_hw_intf_cfg intf_cfg = {0};
258
259 intf_cfg.intf = DPU_NONE;
260 intf_cfg.wb = hw_wb->idx;
261 intf_cfg.mode_3d =
262 dpu_encoder_helper_get_3d_blend_mode(phys_enc);
263 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
264 }
265 }
266
267 /**
268 * _dpu_encoder_phys_wb_update_flush - flush hardware update
269 * @phys_enc: Pointer to physical encoder
270 */
_dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys * phys_enc)271 static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
272 {
273 struct dpu_hw_wb *hw_wb;
274 struct dpu_hw_ctl *hw_ctl;
275 struct dpu_hw_pingpong *hw_pp;
276 struct dpu_hw_cdm *hw_cdm;
277 u32 pending_flush = 0;
278 u32 mode_3d;
279
280 if (!phys_enc)
281 return;
282
283 hw_wb = phys_enc->hw_wb;
284 hw_pp = phys_enc->hw_pp;
285 hw_ctl = phys_enc->hw_ctl;
286 hw_cdm = phys_enc->hw_cdm;
287 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
288
289 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
290
291 if (!hw_ctl) {
292 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
293 return;
294 }
295
296 if (hw_ctl->ops.update_pending_flush_wb)
297 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);
298
299 if (mode_3d && hw_ctl->ops.update_pending_flush_merge_3d &&
300 hw_pp && hw_pp->merge_3d)
301 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
302 hw_pp->merge_3d->idx);
303
304 if (hw_cdm && hw_ctl->ops.update_pending_flush_cdm)
305 hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx);
306
307 if (hw_ctl->ops.get_pending_flush)
308 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);
309
310 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
311 hw_ctl->idx - CTL_0, pending_flush,
312 hw_wb->idx - WB_0);
313 }
314
315 /**
316 * dpu_encoder_phys_wb_setup - setup writeback encoder
317 * @phys_enc: Pointer to physical encoder
318 */
dpu_encoder_phys_wb_setup(struct dpu_encoder_phys * phys_enc)319 static void dpu_encoder_phys_wb_setup(
320 struct dpu_encoder_phys *phys_enc)
321 {
322 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
323 struct drm_display_mode mode = phys_enc->cached_mode;
324 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
325 const struct msm_format *format;
326
327 format = msm_framebuffer_format(wb_enc->wb_job->fb);
328
329 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
330 hw_wb->idx - WB_0, mode.name,
331 mode.hdisplay, mode.vdisplay);
332
333 dpu_encoder_phys_wb_set_ot_limit(phys_enc);
334
335 dpu_encoder_phys_wb_set_qos_remap(phys_enc);
336
337 dpu_encoder_phys_wb_set_qos(phys_enc);
338
339 dpu_encoder_phys_wb_setup_fb(phys_enc, format);
340
341 dpu_encoder_helper_phys_setup_cdm(phys_enc, format, CDM_CDWN_OUTPUT_WB);
342
343 dpu_encoder_phys_wb_setup_ctl(phys_enc);
344 }
345
346 /**
347 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler
348 * @arg: Pointer to writeback encoder
349 */
dpu_encoder_phys_wb_done_irq(void * arg)350 static void dpu_encoder_phys_wb_done_irq(void *arg)
351 {
352 struct dpu_encoder_phys *phys_enc = arg;
353 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
354
355 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
356 unsigned long lock_flags;
357 u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
358
359 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
360
361 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event);
362
363 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
364
365 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
366 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
367 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
368
369 if (wb_enc->wb_conn)
370 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
371
372 /* Signal any waiting atomic commit thread */
373 wake_up_all(&phys_enc->pending_kickoff_wq);
374 }
375
376 /**
377 * dpu_encoder_phys_wb_irq_enable - irq control of WB
378 * @phys: Pointer to physical encoder
379 */
dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys * phys)380 static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys)
381 {
382
383 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
384
385 if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
386 dpu_core_irq_register_callback(phys->dpu_kms,
387 phys->irq[INTR_IDX_WB_DONE],
388 dpu_encoder_phys_wb_done_irq,
389 phys);
390 }
391
392 /**
393 * dpu_encoder_phys_wb_irq_disable - irq control of WB
394 * @phys: Pointer to physical encoder
395 */
dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys * phys)396 static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys)
397 {
398
399 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
400
401 if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
402 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
403 }
404
dpu_encoder_phys_wb_atomic_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)405 static void dpu_encoder_phys_wb_atomic_mode_set(
406 struct dpu_encoder_phys *phys_enc,
407 struct drm_crtc_state *crtc_state,
408 struct drm_connector_state *conn_state)
409 {
410
411 phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
412 }
413
_dpu_encoder_phys_wb_handle_wbdone_timeout(struct dpu_encoder_phys * phys_enc)414 static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
415 struct dpu_encoder_phys *phys_enc)
416 {
417 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
418 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
419
420 wb_enc->wb_done_timeout_cnt++;
421
422 if (wb_enc->wb_done_timeout_cnt == 1)
423 msm_disp_snapshot_state(phys_enc->parent->dev);
424
425 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
426
427 /* request a ctl reset before the next kickoff */
428 phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
429
430 if (wb_enc->wb_conn)
431 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
432
433 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event);
434 }
435
436 /**
437 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed
438 * @phys_enc: Pointer to physical encoder
439 */
dpu_encoder_phys_wb_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)440 static int dpu_encoder_phys_wb_wait_for_commit_done(
441 struct dpu_encoder_phys *phys_enc)
442 {
443 unsigned long ret;
444 struct dpu_encoder_wait_info wait_info;
445 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
446
447 wait_info.wq = &phys_enc->pending_kickoff_wq;
448 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
449 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
450
451 ret = dpu_encoder_helper_wait_for_irq(phys_enc,
452 phys_enc->irq[INTR_IDX_WB_DONE],
453 dpu_encoder_phys_wb_done_irq, &wait_info);
454 if (ret == -ETIMEDOUT)
455 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
456 else if (!ret)
457 wb_enc->wb_done_timeout_cnt = 0;
458
459 return ret;
460 }
461
462 /**
463 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
464 * @phys_enc: Pointer to physical encoder
465 * Returns: Zero on success
466 */
dpu_encoder_phys_wb_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)467 static void dpu_encoder_phys_wb_prepare_for_kickoff(
468 struct dpu_encoder_phys *phys_enc)
469 {
470 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
471 struct drm_connector *drm_conn;
472 struct drm_connector_state *state;
473
474 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
475
476 if (!wb_enc->wb_conn || !wb_enc->wb_job) {
477 DPU_ERROR("invalid wb_conn or wb_job\n");
478 return;
479 }
480
481 drm_conn = &wb_enc->wb_conn->base;
482 state = drm_conn->state;
483
484 if (wb_enc->wb_conn && wb_enc->wb_job)
485 drm_writeback_queue_job(wb_enc->wb_conn, state);
486
487 dpu_encoder_phys_wb_setup(phys_enc);
488
489 _dpu_encoder_phys_wb_update_flush(phys_enc);
490 }
491
492 /**
493 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing
494 * @phys_enc: Pointer to physical encoder
495 */
dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys * phys_enc)496 static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)
497 {
498 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
499 return false;
500 }
501
502 /**
503 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
504 * @phys_enc: Pointer to physical encoder
505 */
dpu_encoder_phys_wb_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)506 static void dpu_encoder_phys_wb_handle_post_kickoff(
507 struct dpu_encoder_phys *phys_enc)
508 {
509 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
510
511 }
512
513 /**
514 * dpu_encoder_phys_wb_enable - enable writeback encoder
515 * @phys_enc: Pointer to physical encoder
516 */
dpu_encoder_phys_wb_enable(struct dpu_encoder_phys * phys_enc)517 static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
518 {
519 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
520 phys_enc->enable_state = DPU_ENC_ENABLED;
521 }
522 /**
523 * dpu_encoder_phys_wb_disable - disable writeback encoder
524 * @phys_enc: Pointer to physical encoder
525 */
dpu_encoder_phys_wb_disable(struct dpu_encoder_phys * phys_enc)526 static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
527 {
528 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
529 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
530
531 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
532
533 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
534 DPU_ERROR("encoder is already disabled\n");
535 return;
536 }
537
538 /* reset h/w before final flush */
539 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
540
541 /*
542 * New CTL reset sequence from 5.0 MDP onwards.
543 * If has_3d_merge_reset is not set, legacy reset
544 * sequence is executed.
545 *
546 * Legacy reset sequence has not been implemented yet.
547 * Any target earlier than SM8150 will need it and when
548 * WB support is added to those targets will need to add
549 * the legacy teardown sequence as well.
550 */
551 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
552 dpu_encoder_helper_phys_cleanup(phys_enc);
553
554 phys_enc->enable_state = DPU_ENC_DISABLED;
555 }
556
dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)557 static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,
558 struct drm_writeback_job *job)
559 {
560 const struct msm_format *format;
561 struct msm_gem_address_space *aspace;
562 struct dpu_hw_wb_cfg *wb_cfg;
563 int ret;
564 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
565
566 if (!job->fb)
567 return;
568
569 wb_enc->wb_job = job;
570 wb_enc->wb_conn = job->connector;
571 aspace = phys_enc->dpu_kms->base.aspace;
572
573 wb_cfg = &wb_enc->wb_cfg;
574
575 memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
576
577 ret = msm_framebuffer_prepare(job->fb, aspace, false);
578 if (ret) {
579 DPU_ERROR("prep fb failed, %d\n", ret);
580 return;
581 }
582
583 format = msm_framebuffer_format(job->fb);
584
585 ret = dpu_format_populate_plane_sizes(job->fb, &wb_cfg->dest);
586 if (ret) {
587 DPU_DEBUG("failed to populate plane sizes%d\n", ret);
588 return;
589 }
590
591 dpu_format_populate_addrs(aspace, job->fb, &wb_cfg->dest);
592
593 wb_cfg->dest.width = job->fb->width;
594 wb_cfg->dest.height = job->fb->height;
595 wb_cfg->dest.num_planes = format->num_planes;
596
597 if ((format->fetch_type == MDP_PLANE_PLANAR) &&
598 (format->element[0] == C1_B_Cb))
599 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
600
601 DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
602 wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],
603 wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);
604
605 DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
606 wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],
607 wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);
608 }
609
dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)610 static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,
611 struct drm_writeback_job *job)
612 {
613 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
614 struct msm_gem_address_space *aspace;
615
616 if (!job->fb)
617 return;
618
619 aspace = phys_enc->dpu_kms->base.aspace;
620
621 msm_framebuffer_cleanup(job->fb, aspace, false);
622 wb_enc->wb_job = NULL;
623 wb_enc->wb_conn = NULL;
624 }
625
dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys * phys_enc)626 static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)
627 {
628 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
629
630 if (wb_enc->wb_job)
631 return true;
632 else
633 return false;
634 }
635
636 /**
637 * dpu_encoder_phys_wb_init_ops - initialize writeback operations
638 * @ops: Pointer to encoder operation table
639 */
dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops * ops)640 static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
641 {
642 ops->is_master = dpu_encoder_phys_wb_is_master;
643 ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
644 ops->enable = dpu_encoder_phys_wb_enable;
645 ops->disable = dpu_encoder_phys_wb_disable;
646 ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
647 ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
648 ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
649 ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;
650 ops->trigger_start = dpu_encoder_helper_trigger_start;
651 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
652 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
653 ops->irq_enable = dpu_encoder_phys_wb_irq_enable;
654 ops->irq_disable = dpu_encoder_phys_wb_irq_disable;
655 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
656
657 }
658
659 /**
660 * dpu_encoder_phys_wb_init - initialize writeback encoder
661 * @dev: Corresponding device for devres management
662 * @p: Pointer to init info structure with initialization params
663 */
dpu_encoder_phys_wb_init(struct drm_device * dev,struct dpu_enc_phys_init_params * p)664 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
665 struct dpu_enc_phys_init_params *p)
666 {
667 struct dpu_encoder_phys *phys_enc = NULL;
668 struct dpu_encoder_phys_wb *wb_enc = NULL;
669
670 DPU_DEBUG("\n");
671
672 if (!p || !p->parent) {
673 DPU_ERROR("invalid params\n");
674 return ERR_PTR(-EINVAL);
675 }
676
677 wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL);
678 if (!wb_enc) {
679 DPU_ERROR("failed to allocate wb phys_enc enc\n");
680 return ERR_PTR(-ENOMEM);
681 }
682
683 phys_enc = &wb_enc->base;
684
685 dpu_encoder_phys_init(phys_enc, p);
686
687 dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
688 phys_enc->intf_mode = INTF_MODE_WB_LINE;
689
690 atomic_set(&wb_enc->wbirq_refcount, 0);
691
692 wb_enc->wb_done_timeout_cnt = 0;
693
694 DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);
695
696 return phys_enc;
697 }
698