| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp_cm.c | 51 struct dpp *dpp_base) in dpp2_enable_cm_block() 65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() 86 struct dpp *dpp_base, in dpp2_program_degamma_lut() 117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() 135 struct dpp *dpp_base, in dpp2_set_degamma() 214 struct dpp *dpp_base, in dpp2_cm_set_gamut_remap() 273 void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, in dpp2_cm_get_gamut_remap() 293 struct dpp *dpp_base, in dpp2_program_input_csc() 366 struct dpp *dpp_base, in dpp20_power_on_blnd_lut() 377 struct dpp *dpp_base, in dpp20_configure_blnd_lut() [all …]
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| H A D | dcn20_dpp.c | 51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() 78 struct dpp *dpp_base, in dpp2_power_on_obuf() 93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() 98 struct dpp *dpp_base, in dpp2_cnv_setup() 317 struct dpp *dpp_base, in dpp2_cnv_set_alpha_keyer() 340 struct dpp *dpp_base, in dpp2_set_cursor_attributes()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_cm.c | 161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() 233 void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, in dpp1_cm_get_gamut_remap() 308 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() 378 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() 386 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut() 396 void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, in dpp1_cm_program_regamma_lut() 420 struct dpp *dpp_base, in dpp1_cm_configure_regamma_lut() 434 struct dpp *dpp_base, in dpp1_cm_program_regamma_luta_settings() 463 struct dpp *dpp_base, in dpp1_cm_program_regamma_lutb_settings() 490 struct dpp *dpp_base, in dpp1_program_input_csc() [all …]
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| H A D | dcn10_dpp.c | 94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument 188 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument 207 dpp1_cm_set_regamma_pwl(struct dpp * dpp_base,const struct pwl_params * params,enum opp_regamma mode) dpp1_cm_set_regamma_pwl() argument 263 dpp1_set_degamma_format_float(struct dpp * dpp_base,bool is_float) dpp1_set_degamma_format_float() argument 278 dpp1_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut) dpp1_cnv_setup() argument 414 dpp1_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes) dpp1_set_cursor_attributes() argument 435 dpp1_set_cursor_position(struct dpp * dpp_base,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param,uint32_t width,uint32_t height) dpp1_set_cursor_position() argument 494 dpp1_cnv_set_optional_cursor_attributes(struct dpp * dpp_base,struct dpp_cursor_attributes * attr) dpp1_cnv_set_optional_cursor_attributes() argument 506 dpp1_dppclk_control(struct dpp * dpp_base,bool dppclk_div,bool enable) dpp1_dppclk_control() argument 523 dpp_force_disable_cursor(struct dpp * dpp_base) dpp_force_disable_cursor() argument [all...] |
| H A D | dcn10_dpp_dscl.c | 124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() 158 struct dpp *dpp_base, in dpp1_power_on_dscl() 613 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.c | 44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state() argument 89 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc() argument 162 dpp3_set_pre_degam(struct dpp * dpp_base,enum dc_transfer_func_predefined tr) dpp3_set_pre_degam() argument 205 dpp3_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut) dpp3_cnv_setup() argument 385 dpp3_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes) dpp3_set_cursor_attributes() argument 520 dpp3_deferred_update(struct dpp * dpp_base) dpp3_deferred_update() argument 568 dpp3_power_on_blnd_lut(struct dpp * dpp_base,bool power_on) dpp3_power_on_blnd_lut() argument 585 dpp3_power_on_hdr3dlut(struct dpp * dpp_base,bool power_on) dpp3_power_on_hdr3dlut() argument 602 dpp3_power_on_shaper(struct dpp * dpp_base,bool power_on) dpp3_power_on_shaper() argument 619 dpp3_configure_blnd_lut(struct dpp * dpp_base,bool is_ram_a) dpp3_configure_blnd_lut() argument 632 dpp3_program_blnd_pwl(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num) dpp3_program_blnd_pwl() argument 696 dpp3_program_blnd_luta_settings(struct dpp * dpp_base,const struct pwl_params * params) dpp3_program_blnd_luta_settings() argument 724 dpp3_program_blnd_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params) dpp3_program_blnd_lutb_settings() argument 750 dpp3_get_blndgam_current(struct dpp * dpp_base) dpp3_get_blndgam_current() argument 781 dpp3_program_blnd_lut(struct dpp * dpp_base,const struct pwl_params * params) dpp3_program_blnd_lut() argument 820 dpp3_program_shaper_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num) dpp3_program_shaper_lut() argument 851 dpp3_get_shaper_current(struct dpp * dpp_base) dpp3_get_shaper_current() argument 878 dpp3_configure_shaper_lut(struct dpp * dpp_base,bool is_ram_a) dpp3_configure_shaper_lut() argument 893 dpp3_program_shaper_luta_settings(struct dpp * dpp_base,const struct pwl_params * params) dpp3_program_shaper_luta_settings() argument 1043 dpp3_program_shaper_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params) dpp3_program_shaper_lutb_settings() argument 1193 dpp3_program_shaper(struct dpp * dpp_base,const struct pwl_params * params) dpp3_program_shaper() argument 1234 get3dlut_config(struct dpp * dpp_base,bool * is_17x17x17,bool * is_12bits_color_channel) get3dlut_config() argument 1281 dpp3_set_3dlut_mode(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17) dpp3_set_3dlut_mode() argument 1302 dpp3_select_3dlut_ram(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits) dpp3_select_3dlut_ram() argument 1317 dpp3_set3dlut_ram12(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries) dpp3_set3dlut_ram12() argument 1351 dpp3_set3dlut_ram10(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries) dpp3_set3dlut_ram10() argument 1372 dpp3_select_3dlut_ram_mask(struct dpp * dpp_base,uint32_t ram_selection_mask) dpp3_select_3dlut_ram_mask() argument 1382 dpp3_program_3dlut(struct dpp * dpp_base,const struct tetrahedral_params * params) dpp3_program_3dlut() argument [all...] |
| H A D | dcn30_dpp_cm.c | 44 struct dpp *dpp_base) in dpp3_enable_cm_block() 57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current() 78 struct dpp *dpp_base, in dpp3_program_gammcor_lut() 127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() 146 struct dpp *dpp_base, in dpp3_program_cm_dealpha() 157 struct dpp *dpp_base, in dpp3_program_cm_bias() 202 struct dpp *dpp_base, in dpp3_configure_gamcor_lut() 216 struct dpp *dpp_base, const struct pwl_params *params) in dpp3_program_gamcor_lut() 305 struct dpp *dpp_base, in dpp3_set_hdr_multiplier() 374 struct dpp *dpp_base, in dpp3_cm_set_gamut_remap() [all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 45 struct dpp *dpp_base, in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 1072 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut() local 1092 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut() local 1120 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_input_transfer_func() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 407 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts() local 611 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts() local
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