| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp_cm.c | 51 struct dpp *dpp_base) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl()
135 struct dpp *dpp_base, in dpp2_set_degamma()
214 struct dpp *dpp_base, in dpp2_cm_set_gamut_remap()
273 void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, in dpp2_cm_get_gamut_remap()
293 struct dpp *dpp_base, in dpp2_program_input_csc()
366 struct dpp *dpp_base, in dpp20_power_on_blnd_lut()
377 struct dpp *dpp_base, in dpp20_configure_blnd_lut()
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| H A D | dcn20_dpp.c | 51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state()
78 struct dpp *dpp_base, in dpp2_power_on_obuf()
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
98 struct dpp *dpp_base, in dpp2_cnv_setup()
317 struct dpp *dpp_base, in dpp2_cnv_set_alpha_keyer()
340 struct dpp *dpp_base, in dpp2_set_cursor_attributes()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_cm.c | 161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap()
233 void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, in dpp1_cm_get_gamut_remap()
308 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default()
378 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment()
386 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut()
396 void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, in dpp1_cm_program_regamma_lut()
420 struct dpp *dpp_base, in dpp1_cm_configure_regamma_lut()
434 struct dpp *dpp_base, in dpp1_cm_program_regamma_luta_settings()
463 struct dpp *dpp_base, in dpp1_cm_program_regamma_lutb_settings()
490 struct dpp *dpp_base, in dpp1_program_input_csc()
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| H A D | dcn10_dpp.c | 94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state()
188 void dpp_reset(struct dpp *dpp_base) in dpp_reset()
204 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) in dpp1_cm_set_regamma_pwl()
260 struct dpp *dpp_base, in dpp1_set_degamma_format_float()
275 struct dpp *dpp_base, in dpp1_cnv_setup()
411 struct dpp *dpp_base, in dpp1_set_cursor_attributes()
432 struct dpp *dpp_base, in dpp1_set_cursor_position()
490 struct dpp *dpp_base, in dpp1_cnv_set_optional_cursor_attributes()
502 struct dpp *dpp_base, in dpp1_dppclk_control()
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| H A D | dcn10_dpp_dscl.c | 124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl()
613 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.c | 44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state()
89 struct dpp *dpp_base, in dpp3_program_post_csc()
162 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) in dpp3_set_pre_degam()
205 struct dpp *dpp_base, in dpp3_cnv_setup()
385 struct dpp *dpp_base, in dpp3_set_cursor_attributes()
519 static void dpp3_deferred_update(struct dpp *dpp_base) in dpp3_deferred_update()
567 struct dpp *dpp_base, in dpp3_power_on_blnd_lut()
587 struct dpp *dpp_base, in dpp3_power_on_hdr3dlut()
604 struct dpp *dpp_base, in dpp3_power_on_shaper()
621 struct dpp *dpp_base, in dpp3_configure_blnd_lut()
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| H A D | dcn30_dpp_cm.c | 44 struct dpp *dpp_base) in dpp3_enable_cm_block()
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current()
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut()
146 struct dpp *dpp_base, in dpp3_program_cm_dealpha()
157 struct dpp *dpp_base, in dpp3_program_cm_bias()
202 struct dpp *dpp_base, in dpp3_configure_gamcor_lut()
216 struct dpp *dpp_base, const struct pwl_params *params) in dpp3_program_gamcor_lut()
305 struct dpp *dpp_base, in dpp3_set_hdr_multiplier()
374 struct dpp *dpp_base, in dpp3_cm_set_gamut_remap()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp_cm.c | 91 void dpp401_full_bypass(struct dpp *dpp_base) in dpp401_full_bypass()
116 struct dpp *dpp_base, in dpp401_set_cursor_attributes()
148 struct dpp *dpp_base, in dpp401_set_cursor_position()
163 struct dpp *dpp_base, in dpp401_set_optional_cursor_attributes()
178 struct dpp *dpp_base, in dpp401_program_cursor_csc()
244 struct dpp *dpp_base, in dpp401_set_cursor_matrix()
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| H A D | dcn401_dpp_dscl.c | 126 struct dpp *dpp_base, in dpp401_dscl_get_dscl_mode()
160 struct dpp *dpp_base, in dpp401_power_on_dscl()
668 static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data) in dpp401_dscl_program_easf_v()
783 static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data) in dpp401_dscl_program_easf_h()
888 static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data) in dpp401_dscl_program_easf()
917 static void dpp401_dscl_disable_easf(struct dpp *dpp_base, const struct scaler_data *scl_data) in dpp401_dscl_disable_easf()
960 static void dpp401_dscl_program_isharp(struct dpp *dpp_base, in dpp401_dscl_program_isharp()
1062 void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp401_dscl_set_scaler_manual_scale()
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| H A D | dcn401_dpp.c | 45 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp401_read_state()
56 struct dpp *dpp_base, in dpp401_dpp_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
| H A D | dcn35_dpp.c | 41 struct dpp *dpp_base, in dpp35_dppclk_control()
71 struct dpp *dpp_base, in dpp35_program_bias_and_scale_fcnv()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut() local
246 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut() local
308 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func() local
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 45 struct dpp *dpp_base, in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 1817 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn10_set_input_transfer_func() local
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