xref: /linux/drivers/gpu/drm/i915/display/intel_dp_link_training.c (revision 3ef7acec975bde28ab9cef92af76be8fc2ce684d)
1 /*
2  * Copyright © 2008-2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include <linux/debugfs.h>
25 
26 #include <drm/display/drm_dp_helper.h>
27 
28 #include "i915_utils.h"
29 #include "intel_display_core.h"
30 #include "intel_display_types.h"
31 #include "intel_dp.h"
32 #include "intel_dp_link_training.h"
33 #include "intel_encoder.h"
34 #include "intel_hotplug.h"
35 #include "intel_panel.h"
36 
37 #define LT_MSG_PREFIX			"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
38 #define LT_MSG_ARGS(_intel_dp, _dp_phy)	(_intel_dp)->attached_connector->base.base.id, \
39 					(_intel_dp)->attached_connector->base.name, \
40 					dp_to_dig_port(_intel_dp)->base.base.base.id, \
41 					dp_to_dig_port(_intel_dp)->base.base.name, \
42 					drm_dp_phy_name(_dp_phy)
43 
44 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \
45 	drm_dbg_kms(to_intel_display(_intel_dp)->drm, \
46 		    LT_MSG_PREFIX _format, \
47 		    LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__)
48 
49 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \
50 	if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \
51 		drm_err(to_intel_display(_intel_dp)->drm, \
52 			LT_MSG_PREFIX _format, \
53 			LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \
54 	else \
55 		lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \
56 } while (0)
57 
intel_dp_reset_lttpr_common_caps(struct intel_dp * intel_dp)58 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
59 {
60 	memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
61 }
62 
intel_dp_reset_lttpr_count(struct intel_dp * intel_dp)63 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
64 {
65 	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
66 				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
67 }
68 
intel_dp_lttpr_phy_caps(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)69 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
70 				   enum drm_dp_phy dp_phy)
71 {
72 	return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
73 }
74 
intel_dp_read_lttpr_phy_caps(struct intel_dp * intel_dp,const u8 dpcd[DP_RECEIVER_CAP_SIZE],enum drm_dp_phy dp_phy)75 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
76 					 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
77 					 enum drm_dp_phy dp_phy)
78 {
79 	u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
80 
81 	if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
82 		lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");
83 		return;
84 	}
85 
86 	lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",
87 	       (int)sizeof(intel_dp->lttpr_phy_caps[0]),
88 	       phy_caps);
89 }
90 
intel_dp_read_lttpr_common_caps(struct intel_dp * intel_dp,const u8 dpcd[DP_RECEIVER_CAP_SIZE])91 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,
92 					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
93 {
94 	int ret;
95 
96 	ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
97 					    intel_dp->lttpr_common_caps);
98 	if (ret < 0)
99 		goto reset_caps;
100 
101 	lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",
102 	       (int)sizeof(intel_dp->lttpr_common_caps),
103 	       intel_dp->lttpr_common_caps);
104 
105 	/* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
106 	if (intel_dp->lttpr_common_caps[0] < 0x14)
107 		goto reset_caps;
108 
109 	return true;
110 
111 reset_caps:
112 	intel_dp_reset_lttpr_common_caps(intel_dp);
113 	return false;
114 }
115 
116 static bool
intel_dp_set_lttpr_transparent_mode(struct intel_dp * intel_dp,bool enable)117 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
118 {
119 	u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
120 			  DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
121 
122 	if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1)
123 		return false;
124 
125 	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
126 				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val;
127 
128 	return true;
129 }
130 
intel_dp_lttpr_transparent_mode_enabled(struct intel_dp * intel_dp)131 static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)
132 {
133 	return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
134 					   DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] ==
135 		DP_PHY_REPEATER_MODE_TRANSPARENT;
136 }
137 
138 /*
139  * Read the LTTPR common capabilities and switch the LTTPR PHYs to
140  * non-transparent mode if this is supported. Preserve the
141  * transparent/non-transparent mode on an active link.
142  *
143  * Return the number of detected LTTPRs in non-transparent mode or 0 if the
144  * LTTPRs are in transparent mode or the detection failed.
145  */
intel_dp_init_lttpr_phys(struct intel_dp * intel_dp,const u8 dpcd[DP_RECEIVER_CAP_SIZE])146 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
147 {
148 	int lttpr_count;
149 
150 	if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
151 		return 0;
152 
153 	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
154 	/*
155 	 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
156 	 * detected as this breaks link training at least on the Dell WD19TB
157 	 * dock.
158 	 */
159 	if (lttpr_count == 0)
160 		return 0;
161 
162 	/*
163 	 * Don't change the mode on an active link, to prevent a loss of link
164 	 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR
165 	 * resetting its internal state when the mode is changed from
166 	 * non-transparent to transparent.
167 	 */
168 	if (intel_dp->link_trained) {
169 		if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp))
170 			goto out_reset_lttpr_count;
171 
172 		return lttpr_count;
173 	}
174 
175 	/*
176 	 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of
177 	 * non-transparent mode and the disable->enable non-transparent mode
178 	 * sequence.
179 	 */
180 	intel_dp_set_lttpr_transparent_mode(intel_dp, true);
181 
182 	/*
183 	 * In case of unsupported number of LTTPRs or failing to switch to
184 	 * non-transparent mode fall-back to transparent link training mode,
185 	 * still taking into account any LTTPR common lane- rate/count limits.
186 	 */
187 	if (lttpr_count < 0)
188 		goto out_reset_lttpr_count;
189 
190 	if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
191 		lt_dbg(intel_dp, DP_PHY_DPRX,
192 		       "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
193 
194 		intel_dp_set_lttpr_transparent_mode(intel_dp, true);
195 
196 		goto out_reset_lttpr_count;
197 	}
198 
199 	return lttpr_count;
200 
201 out_reset_lttpr_count:
202 	intel_dp_reset_lttpr_count(intel_dp);
203 
204 	return 0;
205 }
206 
intel_dp_init_lttpr(struct intel_dp * intel_dp,const u8 dpcd[DP_RECEIVER_CAP_SIZE])207 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
208 {
209 	int lttpr_count;
210 	int i;
211 
212 	lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd);
213 
214 	for (i = 0; i < lttpr_count; i++) {
215 		intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
216 		drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i));
217 	}
218 
219 	return lttpr_count;
220 }
221 
intel_dp_read_dprx_caps(struct intel_dp * intel_dp,u8 dpcd[DP_RECEIVER_CAP_SIZE])222 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
223 {
224 	struct intel_display *display = to_intel_display(intel_dp);
225 
226 	if (intel_dp_is_edp(intel_dp))
227 		return 0;
228 
229 	/*
230 	 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
231 	 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
232 	 */
233 	if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)
234 		if (drm_dp_dpcd_probe(&intel_dp->aux,
235 				      DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV))
236 			return -EIO;
237 
238 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
239 		return -EIO;
240 
241 	return 0;
242 }
243 
244 /**
245  * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
246  * @intel_dp: Intel DP struct
247  *
248  * Read the LTTPR common and DPRX capabilities and switch to non-transparent
249  * link training mode if any is detected and read the PHY capabilities for all
250  * detected LTTPRs. In case of an LTTPR detection error or if the number of
251  * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
252  * transparent mode link training mode.
253  *
254  * Returns:
255  *   >0  if LTTPRs were detected and the non-transparent LT mode was set. The
256  *       DPRX capabilities are read out.
257  *    0  if no LTTPRs or more than 8 LTTPRs were detected or in case of a
258  *       detection failure and the transparent LT mode was set. The DPRX
259  *       capabilities are read out.
260  *   <0  Reading out the DPRX capabilities failed.
261  */
intel_dp_init_lttpr_and_dprx_caps(struct intel_dp * intel_dp)262 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
263 {
264 	struct intel_display *display = to_intel_display(intel_dp);
265 	int lttpr_count = 0;
266 
267 	/*
268 	 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
269 	 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
270 	 */
271 	if (!intel_dp_is_edp(intel_dp) &&
272 	    (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) {
273 		u8 dpcd[DP_RECEIVER_CAP_SIZE];
274 		int err = intel_dp_read_dprx_caps(intel_dp, dpcd);
275 
276 		if (err != 0)
277 			return err;
278 
279 		lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
280 	}
281 
282 	/*
283 	 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
284 	 * it here.
285 	 */
286 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
287 		intel_dp_reset_lttpr_common_caps(intel_dp);
288 		return -EIO;
289 	}
290 
291 	return lttpr_count;
292 }
293 
dp_voltage_max(u8 preemph)294 static u8 dp_voltage_max(u8 preemph)
295 {
296 	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
297 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
298 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
299 	case DP_TRAIN_PRE_EMPH_LEVEL_1:
300 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
301 	case DP_TRAIN_PRE_EMPH_LEVEL_2:
302 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
303 	case DP_TRAIN_PRE_EMPH_LEVEL_3:
304 	default:
305 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
306 	}
307 }
308 
intel_dp_lttpr_voltage_max(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)309 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
310 				     enum drm_dp_phy dp_phy)
311 {
312 	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
313 
314 	if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
315 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
316 	else
317 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
318 }
319 
intel_dp_lttpr_preemph_max(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)320 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
321 				     enum drm_dp_phy dp_phy)
322 {
323 	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
324 
325 	if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
326 		return DP_TRAIN_PRE_EMPH_LEVEL_3;
327 	else
328 		return DP_TRAIN_PRE_EMPH_LEVEL_2;
329 }
330 
331 static bool
intel_dp_phy_is_downstream_of_source(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)332 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
333 				     enum drm_dp_phy dp_phy)
334 {
335 	struct intel_display *display = to_intel_display(intel_dp);
336 	int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
337 
338 	drm_WARN_ON_ONCE(display->drm,
339 			 lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);
340 
341 	return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
342 }
343 
intel_dp_phy_voltage_max(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy)344 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
345 				   const struct intel_crtc_state *crtc_state,
346 				   enum drm_dp_phy dp_phy)
347 {
348 	struct intel_display *display = to_intel_display(intel_dp);
349 	u8 voltage_max;
350 
351 	/*
352 	 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
353 	 * the DPRX_PHY we train.
354 	 */
355 	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
356 		voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
357 	else
358 		voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
359 
360 	drm_WARN_ON_ONCE(display->drm,
361 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
362 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
363 
364 	return voltage_max;
365 }
366 
intel_dp_phy_preemph_max(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)367 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
368 				   enum drm_dp_phy dp_phy)
369 {
370 	struct intel_display *display = to_intel_display(intel_dp);
371 	u8 preemph_max;
372 
373 	/*
374 	 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
375 	 * the DPRX_PHY we train.
376 	 */
377 	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
378 		preemph_max = intel_dp->preemph_max(intel_dp);
379 	else
380 		preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
381 
382 	drm_WARN_ON_ONCE(display->drm,
383 			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
384 			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
385 
386 	return preemph_max;
387 }
388 
has_per_lane_signal_levels(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)389 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
390 				       enum drm_dp_phy dp_phy)
391 {
392 	struct intel_display *display = to_intel_display(intel_dp);
393 
394 	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
395 		DISPLAY_VER(display) >= 10 || display->platform.broxton;
396 }
397 
398 /* 128b/132b */
intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE],int lane)399 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,
400 						 const struct intel_crtc_state *crtc_state,
401 						 enum drm_dp_phy dp_phy,
402 						 const u8 link_status[DP_LINK_STATUS_SIZE],
403 						 int lane)
404 {
405 	u8 tx_ffe = 0;
406 
407 	if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
408 		lane = min(lane, crtc_state->lane_count - 1);
409 		tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane);
410 	} else {
411 		for (lane = 0; lane < crtc_state->lane_count; lane++)
412 			tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane));
413 	}
414 
415 	return tx_ffe;
416 }
417 
418 /* 8b/10b */
intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE],int lane)419 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
420 						  const struct intel_crtc_state *crtc_state,
421 						  enum drm_dp_phy dp_phy,
422 						  const u8 link_status[DP_LINK_STATUS_SIZE],
423 						  int lane)
424 {
425 	u8 v = 0;
426 	u8 p = 0;
427 	u8 voltage_max;
428 	u8 preemph_max;
429 
430 	if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
431 		lane = min(lane, crtc_state->lane_count - 1);
432 
433 		v = drm_dp_get_adjust_request_voltage(link_status, lane);
434 		p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
435 	} else {
436 		for (lane = 0; lane < crtc_state->lane_count; lane++) {
437 			v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
438 			p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
439 		}
440 	}
441 
442 	preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
443 	if (p >= preemph_max)
444 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
445 
446 	v = min(v, dp_voltage_max(p));
447 
448 	voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
449 	if (v >= voltage_max)
450 		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
451 
452 	return v | p;
453 }
454 
intel_dp_get_lane_adjust_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE],int lane)455 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
456 					 const struct intel_crtc_state *crtc_state,
457 					 enum drm_dp_phy dp_phy,
458 					 const u8 link_status[DP_LINK_STATUS_SIZE],
459 					 int lane)
460 {
461 	if (intel_dp_is_uhbr(crtc_state))
462 		return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,
463 							      dp_phy, link_status, lane);
464 	else
465 		return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,
466 							       dp_phy, link_status, lane);
467 }
468 
469 #define TRAIN_REQ_FMT "%d/%d/%d/%d"
470 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
471 	(drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
472 #define TRAIN_REQ_VSWING_ARGS(link_status) \
473 	_TRAIN_REQ_VSWING_ARGS(link_status, 0), \
474 	_TRAIN_REQ_VSWING_ARGS(link_status, 1), \
475 	_TRAIN_REQ_VSWING_ARGS(link_status, 2), \
476 	_TRAIN_REQ_VSWING_ARGS(link_status, 3)
477 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
478 	(drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
479 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \
480 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
481 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
482 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
483 	_TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
484 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \
485 	drm_dp_get_adjust_tx_ffe_preset((link_status), (lane))
486 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \
487 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
488 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
489 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
490 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
491 
492 void
intel_dp_get_adjust_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE])493 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
494 			  const struct intel_crtc_state *crtc_state,
495 			  enum drm_dp_phy dp_phy,
496 			  const u8 link_status[DP_LINK_STATUS_SIZE])
497 {
498 	int lane;
499 
500 	if (intel_dp_is_uhbr(crtc_state)) {
501 		lt_dbg(intel_dp, dp_phy,
502 		       "128b/132b, lanes: %d, "
503 		       "TX FFE request: " TRAIN_REQ_FMT "\n",
504 		       crtc_state->lane_count,
505 		       TRAIN_REQ_TX_FFE_ARGS(link_status));
506 	} else {
507 		lt_dbg(intel_dp, dp_phy,
508 		       "8b/10b, lanes: %d, "
509 		       "vswing request: " TRAIN_REQ_FMT ", "
510 		       "pre-emphasis request: " TRAIN_REQ_FMT "\n",
511 		       crtc_state->lane_count,
512 		       TRAIN_REQ_VSWING_ARGS(link_status),
513 		       TRAIN_REQ_PREEMPH_ARGS(link_status));
514 	}
515 
516 	for (lane = 0; lane < 4; lane++)
517 		intel_dp->train_set[lane] =
518 			intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
519 						       dp_phy, link_status, lane);
520 }
521 
intel_dp_training_pattern_set_reg(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)522 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
523 					     enum drm_dp_phy dp_phy)
524 {
525 	return dp_phy == DP_PHY_DPRX ?
526 		DP_TRAINING_PATTERN_SET :
527 		DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
528 }
529 
530 static bool
intel_dp_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy,u8 dp_train_pat)531 intel_dp_set_link_train(struct intel_dp *intel_dp,
532 			const struct intel_crtc_state *crtc_state,
533 			enum drm_dp_phy dp_phy,
534 			u8 dp_train_pat)
535 {
536 	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
537 	u8 buf[sizeof(intel_dp->train_set) + 1];
538 	int len;
539 
540 	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
541 					       dp_phy, dp_train_pat);
542 
543 	buf[0] = dp_train_pat;
544 	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
545 	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
546 	len = crtc_state->lane_count + 1;
547 
548 	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
549 }
550 
dp_training_pattern_name(u8 train_pat)551 static char dp_training_pattern_name(u8 train_pat)
552 {
553 	switch (train_pat) {
554 	case DP_TRAINING_PATTERN_1:
555 	case DP_TRAINING_PATTERN_2:
556 	case DP_TRAINING_PATTERN_3:
557 		return '0' + train_pat;
558 	case DP_TRAINING_PATTERN_4:
559 		return '4';
560 	default:
561 		MISSING_CASE(train_pat);
562 		return '?';
563 	}
564 }
565 
566 void
intel_dp_program_link_training_pattern(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy,u8 dp_train_pat)567 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
568 				       const struct intel_crtc_state *crtc_state,
569 				       enum drm_dp_phy dp_phy,
570 				       u8 dp_train_pat)
571 {
572 	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
573 
574 	if (train_pat != DP_TRAINING_PATTERN_DISABLE)
575 		lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",
576 		       dp_training_pattern_name(train_pat));
577 
578 	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
579 }
580 
581 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s"
582 #define _TRAIN_SET_VSWING_ARGS(train_set) \
583 	((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \
584 	(train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : ""
585 #define TRAIN_SET_VSWING_ARGS(train_set) \
586 	_TRAIN_SET_VSWING_ARGS((train_set)[0]), \
587 	_TRAIN_SET_VSWING_ARGS((train_set)[1]), \
588 	_TRAIN_SET_VSWING_ARGS((train_set)[2]), \
589 	_TRAIN_SET_VSWING_ARGS((train_set)[3])
590 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \
591 	((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \
592 	(train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : ""
593 #define TRAIN_SET_PREEMPH_ARGS(train_set) \
594 	_TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \
595 	_TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \
596 	_TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \
597 	_TRAIN_SET_PREEMPH_ARGS((train_set)[3])
598 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \
599 	((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), ""
600 #define TRAIN_SET_TX_FFE_ARGS(train_set) \
601 	_TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
602 	_TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
603 	_TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
604 	_TRAIN_SET_TX_FFE_ARGS((train_set)[3])
605 
intel_dp_set_signal_levels(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy)606 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
607 				const struct intel_crtc_state *crtc_state,
608 				enum drm_dp_phy dp_phy)
609 {
610 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
611 
612 	if (intel_dp_is_uhbr(crtc_state)) {
613 		lt_dbg(intel_dp, dp_phy,
614 		       "128b/132b, lanes: %d, "
615 		       "TX FFE presets: " TRAIN_SET_FMT "\n",
616 		       crtc_state->lane_count,
617 		       TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
618 	} else {
619 		lt_dbg(intel_dp, dp_phy,
620 		       "8b/10b, lanes: %d, "
621 		       "vswing levels: " TRAIN_SET_FMT ", "
622 		       "pre-emphasis levels: " TRAIN_SET_FMT "\n",
623 		       crtc_state->lane_count,
624 		       TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
625 		       TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
626 	}
627 
628 	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
629 		encoder->set_signal_levels(encoder, crtc_state);
630 }
631 
632 static bool
intel_dp_reset_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy,u8 dp_train_pat)633 intel_dp_reset_link_train(struct intel_dp *intel_dp,
634 			  const struct intel_crtc_state *crtc_state,
635 			  enum drm_dp_phy dp_phy,
636 			  u8 dp_train_pat)
637 {
638 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
639 	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
640 	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
641 }
642 
643 static bool
intel_dp_update_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy)644 intel_dp_update_link_train(struct intel_dp *intel_dp,
645 			   const struct intel_crtc_state *crtc_state,
646 			   enum drm_dp_phy dp_phy)
647 {
648 	int reg = dp_phy == DP_PHY_DPRX ?
649 			    DP_TRAINING_LANE0_SET :
650 			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
651 	int ret;
652 
653 	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
654 
655 	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
656 				intel_dp->train_set, crtc_state->lane_count);
657 
658 	return ret == crtc_state->lane_count;
659 }
660 
661 /* 128b/132b */
intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)662 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)
663 {
664 	return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) ==
665 		DP_TX_FFE_PRESET_VALUE_MASK;
666 }
667 
668 /*
669  * 8b/10b
670  *
671  * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to
672  * have self contradicting tests around this area.
673  *
674  * In lieu of better ideas let's just stop when we've reached the max supported
675  * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on
676  * whether vswing level 3 is supported or not.
677  */
intel_dp_lane_max_vswing_reached(u8 train_set_lane)678 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)
679 {
680 	u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
681 		DP_TRAIN_VOLTAGE_SWING_SHIFT;
682 	u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
683 		DP_TRAIN_PRE_EMPHASIS_SHIFT;
684 
685 	if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0)
686 		return false;
687 
688 	if (v + p != 3)
689 		return false;
690 
691 	return true;
692 }
693 
intel_dp_link_max_vswing_reached(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)694 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
695 					     const struct intel_crtc_state *crtc_state)
696 {
697 	int lane;
698 
699 	for (lane = 0; lane < crtc_state->lane_count; lane++) {
700 		u8 train_set_lane = intel_dp->train_set[lane];
701 
702 		if (intel_dp_is_uhbr(crtc_state)) {
703 			if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
704 				return false;
705 		} else {
706 			if (!intel_dp_lane_max_vswing_reached(train_set_lane))
707 				return false;
708 		}
709 	}
710 
711 	return true;
712 }
713 
intel_dp_link_training_set_mode(struct intel_dp * intel_dp,int link_rate,bool is_vrr)714 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
715 {
716 	u8 link_config[2];
717 
718 	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
719 	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
720 			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
721 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
722 }
723 
intel_dp_update_downspread_ctrl(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)724 static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
725 					    const struct intel_crtc_state *crtc_state)
726 {
727 	intel_dp_link_training_set_mode(intel_dp,
728 					crtc_state->port_clock, crtc_state->vrr.flipline);
729 }
730 
intel_dp_link_training_set_bw(struct intel_dp * intel_dp,int link_bw,int rate_select,int lane_count,bool enhanced_framing)731 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
732 				   int link_bw, int rate_select, int lane_count,
733 				   bool enhanced_framing)
734 {
735 	if (enhanced_framing)
736 		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
737 
738 	if (link_bw) {
739 		/* DP and eDP v1.3 and earlier link bw set method. */
740 		u8 link_config[] = { link_bw, lane_count };
741 
742 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
743 				  ARRAY_SIZE(link_config));
744 	} else {
745 		/*
746 		 * eDP v1.4 and later link rate set method.
747 		 *
748 		 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if
749 		 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET.
750 		 *
751 		 * eDP v1.5 sinks allow choosing either, and the last choice
752 		 * shall be active.
753 		 */
754 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
755 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
756 	}
757 }
758 
intel_dp_update_link_bw_set(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 link_bw,u8 rate_select)759 static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
760 					const struct intel_crtc_state *crtc_state,
761 					u8 link_bw, u8 rate_select)
762 {
763 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,
764 				      crtc_state->enhanced_framing);
765 }
766 
767 /*
768  * Prepare link training by configuring the link parameters. On DDI platforms
769  * also enable the port here.
770  */
771 static bool
intel_dp_prepare_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)772 intel_dp_prepare_link_train(struct intel_dp *intel_dp,
773 			    const struct intel_crtc_state *crtc_state)
774 {
775 	u8 link_bw, rate_select;
776 
777 	if (intel_dp->prepare_link_retrain)
778 		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
779 
780 	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
781 			      &link_bw, &rate_select);
782 
783 	/*
784 	 * WaEdpLinkRateDataReload
785 	 *
786 	 * Parade PS8461E MUX (used on varius TGL+ laptops) needs
787 	 * to snoop the link rates reported by the sink when we
788 	 * use LINK_RATE_SET in order to operate in jitter cleaning
789 	 * mode (as opposed to redriver mode). Unfortunately it
790 	 * loses track of the snooped link rates when powered down,
791 	 * so we need to make it re-snoop often. Without this high
792 	 * link rates are not stable.
793 	 */
794 	if (!link_bw) {
795 		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
796 
797 		lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");
798 
799 		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
800 				 sink_rates, sizeof(sink_rates));
801 	}
802 
803 	if (link_bw)
804 		lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",
805 		       link_bw);
806 	else
807 		lt_dbg(intel_dp, DP_PHY_DPRX,
808 		       "Using LINK_RATE_SET value %02x\n",
809 		       rate_select);
810 	/*
811 	 * Spec DP2.1 Section 3.5.2.16
812 	 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
813 	 */
814 	intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
815 	intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
816 				    rate_select);
817 
818 	return true;
819 }
820 
intel_dp_adjust_request_changed(const struct intel_crtc_state * crtc_state,const u8 old_link_status[DP_LINK_STATUS_SIZE],const u8 new_link_status[DP_LINK_STATUS_SIZE])821 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
822 					    const u8 old_link_status[DP_LINK_STATUS_SIZE],
823 					    const u8 new_link_status[DP_LINK_STATUS_SIZE])
824 {
825 	int lane;
826 
827 	for (lane = 0; lane < crtc_state->lane_count; lane++) {
828 		u8 old, new;
829 
830 		if (intel_dp_is_uhbr(crtc_state)) {
831 			old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
832 			new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
833 		} else {
834 			old = drm_dp_get_adjust_request_voltage(old_link_status, lane) |
835 				drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane);
836 			new = drm_dp_get_adjust_request_voltage(new_link_status, lane) |
837 				drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane);
838 		}
839 
840 		if (old != new)
841 			return true;
842 	}
843 
844 	return false;
845 }
846 
847 void
intel_dp_dump_link_status(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE])848 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
849 			  const u8 link_status[DP_LINK_STATUS_SIZE])
850 {
851 	lt_dbg(intel_dp, dp_phy,
852 	       "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
853 	       link_status[0], link_status[1], link_status[2],
854 	       link_status[3], link_status[4], link_status[5]);
855 }
856 
857 /*
858  * Perform the link training clock recovery phase on the given DP PHY using
859  * training pattern 1.
860  */
861 static bool
intel_dp_link_training_clock_recovery(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy)862 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
863 				      const struct intel_crtc_state *crtc_state,
864 				      enum drm_dp_phy dp_phy)
865 {
866 	u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
867 	int voltage_tries, cr_tries, max_cr_tries;
868 	u8 link_status[DP_LINK_STATUS_SIZE];
869 	bool max_vswing_reached = false;
870 	int delay_us;
871 
872 	delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
873 						    intel_dp->dpcd, dp_phy,
874 						    intel_dp_is_uhbr(crtc_state));
875 
876 	/* clock recovery */
877 	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
878 				       DP_TRAINING_PATTERN_1 |
879 				       DP_LINK_SCRAMBLING_DISABLE)) {
880 		lt_err(intel_dp, dp_phy, "Failed to enable link training\n");
881 		return false;
882 	}
883 
884 	/*
885 	 * The DP 1.4 spec defines the max clock recovery retries value
886 	 * as 10 but for pre-DP 1.4 devices we set a very tolerant
887 	 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
888 	 * x 5 identical voltage retries). Since the previous specs didn't
889 	 * define a limit and created the possibility of an infinite loop
890 	 * we want to prevent any sync from triggering that corner case.
891 	 */
892 	if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
893 		max_cr_tries = 10;
894 	else
895 		max_cr_tries = 80;
896 
897 	voltage_tries = 1;
898 	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
899 		fsleep(delay_us);
900 
901 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
902 						     link_status) < 0) {
903 			lt_err(intel_dp, dp_phy, "Failed to get link status\n");
904 			return false;
905 		}
906 
907 		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
908 			lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
909 			return true;
910 		}
911 
912 		if (voltage_tries == 5) {
913 			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
914 			lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");
915 			return false;
916 		}
917 
918 		if (max_vswing_reached) {
919 			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
920 			lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");
921 			return false;
922 		}
923 
924 		/* Update training set as requested by target */
925 		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
926 					  link_status);
927 		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
928 			lt_err(intel_dp, dp_phy, "Failed to update link training\n");
929 			return false;
930 		}
931 
932 		if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
933 			++voltage_tries;
934 		else
935 			voltage_tries = 1;
936 
937 		memcpy(old_link_status, link_status, sizeof(link_status));
938 
939 		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
940 			max_vswing_reached = true;
941 	}
942 
943 	intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
944 	lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",
945 	       max_cr_tries);
946 
947 	return false;
948 }
949 
950 /*
951  * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
952  * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
953  * 1.2 devices that support it, TPS2 otherwise.
954  */
intel_dp_training_pattern(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy)955 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
956 				     const struct intel_crtc_state *crtc_state,
957 				     enum drm_dp_phy dp_phy)
958 {
959 	struct intel_display *display = to_intel_display(intel_dp);
960 	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
961 
962 	/* UHBR+ use separate 128b/132b TPS2 */
963 	if (intel_dp_is_uhbr(crtc_state))
964 		return DP_TRAINING_PATTERN_2;
965 
966 	/*
967 	 * TPS4 support is mandatory for all downstream devices that
968 	 * support HBR3. There are no known eDP panels that support
969 	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
970 	 * LTTPRs must support TPS4.
971 	 */
972 	source_tps4 = intel_dp_source_supports_tps4(display);
973 	sink_tps4 = dp_phy != DP_PHY_DPRX ||
974 		    drm_dp_tps4_supported(intel_dp->dpcd);
975 	if (source_tps4 && sink_tps4) {
976 		return DP_TRAINING_PATTERN_4;
977 	} else if (crtc_state->port_clock == 810000) {
978 		if (!source_tps4)
979 			lt_dbg(intel_dp, dp_phy,
980 			       "8.1 Gbps link rate without source TPS4 support\n");
981 		if (!sink_tps4)
982 			lt_dbg(intel_dp, dp_phy,
983 			       "8.1 Gbps link rate without sink TPS4 support\n");
984 	}
985 
986 	/*
987 	 * TPS3 support is mandatory for downstream devices that
988 	 * support HBR2. However, not all sinks follow the spec.
989 	 */
990 	source_tps3 = intel_dp_source_supports_tps3(display);
991 	sink_tps3 = dp_phy != DP_PHY_DPRX ||
992 		    drm_dp_tps3_supported(intel_dp->dpcd);
993 	if (source_tps3 && sink_tps3) {
994 		return  DP_TRAINING_PATTERN_3;
995 	} else if (crtc_state->port_clock >= 540000) {
996 		if (!source_tps3)
997 			lt_dbg(intel_dp, dp_phy,
998 			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
999 		if (!sink_tps3)
1000 			lt_dbg(intel_dp, dp_phy,
1001 			       ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
1002 	}
1003 
1004 	return DP_TRAINING_PATTERN_2;
1005 }
1006 
1007 /*
1008  * Perform the link training channel equalization phase on the given DP PHY
1009  * using one of training pattern 2, 3 or 4 depending on the source and
1010  * sink capabilities.
1011  */
1012 static bool
intel_dp_link_training_channel_equalization(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy)1013 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
1014 					    const struct intel_crtc_state *crtc_state,
1015 					    enum drm_dp_phy dp_phy)
1016 {
1017 	int tries;
1018 	u32 training_pattern;
1019 	u8 link_status[DP_LINK_STATUS_SIZE];
1020 	bool channel_eq = false;
1021 	int delay_us;
1022 
1023 	delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
1024 						intel_dp->dpcd, dp_phy,
1025 						intel_dp_is_uhbr(crtc_state));
1026 
1027 	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
1028 	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
1029 	if (training_pattern != DP_TRAINING_PATTERN_4)
1030 		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
1031 
1032 	/* channel equalization */
1033 	if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
1034 				     training_pattern)) {
1035 		lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");
1036 		return false;
1037 	}
1038 
1039 	for (tries = 0; tries < 5; tries++) {
1040 		fsleep(delay_us);
1041 
1042 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
1043 						     link_status) < 0) {
1044 			lt_err(intel_dp, dp_phy, "Failed to get link status\n");
1045 			break;
1046 		}
1047 
1048 		/* Make sure clock is still ok */
1049 		if (!drm_dp_clock_recovery_ok(link_status,
1050 					      crtc_state->lane_count)) {
1051 			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
1052 			lt_dbg(intel_dp, dp_phy,
1053 			       "Clock recovery check failed, cannot continue channel equalization\n");
1054 			break;
1055 		}
1056 
1057 		if (drm_dp_channel_eq_ok(link_status,
1058 					 crtc_state->lane_count)) {
1059 			channel_eq = true;
1060 			lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");
1061 			break;
1062 		}
1063 
1064 		/* Update training set as requested by target */
1065 		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
1066 					  link_status);
1067 		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
1068 			lt_err(intel_dp, dp_phy, "Failed to update link training\n");
1069 			break;
1070 		}
1071 	}
1072 
1073 	/* Try 5 times, else fail and try at lower BW */
1074 	if (tries == 5) {
1075 		intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
1076 		lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");
1077 	}
1078 
1079 	return channel_eq;
1080 }
1081 
intel_dp_disable_dpcd_training_pattern(struct intel_dp * intel_dp,enum drm_dp_phy dp_phy)1082 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
1083 						   enum drm_dp_phy dp_phy)
1084 {
1085 	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
1086 	u8 val = DP_TRAINING_PATTERN_DISABLE;
1087 
1088 	return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
1089 }
1090 
1091 static int
intel_dp_128b132b_intra_hop(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1092 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp,
1093 			    const struct intel_crtc_state *crtc_state)
1094 {
1095 	u8 sink_status;
1096 	int ret;
1097 
1098 	ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);
1099 	if (ret != 1) {
1100 		lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");
1101 		return ret < 0 ? ret : -EIO;
1102 	}
1103 
1104 	return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0;
1105 }
1106 
1107 /**
1108  * intel_dp_stop_link_train - stop link training
1109  * @intel_dp: DP struct
1110  * @crtc_state: state for CRTC attached to the encoder
1111  *
1112  * Stop the link training of the @intel_dp port, disabling the training
1113  * pattern in the sink's DPCD, and disabling the test pattern symbol
1114  * generation on the port.
1115  *
1116  * What symbols are output on the port after this point is
1117  * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
1118  * with the pipe being disabled, on older platforms it's HW specific if/how an
1119  * idle pattern is generated, as the pipe is already enabled here for those.
1120  *
1121  * This function must be called after intel_dp_start_link_train().
1122  */
intel_dp_stop_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1123 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
1124 			      const struct intel_crtc_state *crtc_state)
1125 {
1126 	intel_dp->link_trained = true;
1127 
1128 	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
1129 	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
1130 					       DP_TRAINING_PATTERN_DISABLE);
1131 
1132 	if (intel_dp_is_uhbr(crtc_state) &&
1133 	    wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1134 		lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
1135 	}
1136 }
1137 
1138 static bool
intel_dp_link_train_phy(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,enum drm_dp_phy dp_phy)1139 intel_dp_link_train_phy(struct intel_dp *intel_dp,
1140 			const struct intel_crtc_state *crtc_state,
1141 			enum drm_dp_phy dp_phy)
1142 {
1143 	bool ret = false;
1144 
1145 	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
1146 		goto out;
1147 
1148 	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
1149 		goto out;
1150 
1151 	ret = true;
1152 
1153 out:
1154 	lt_dbg(intel_dp, dp_phy,
1155 	       "Link Training %s at link rate = %d, lane count = %d\n",
1156 	       ret ? "passed" : "failed",
1157 	       crtc_state->port_clock, crtc_state->lane_count);
1158 
1159 	return ret;
1160 }
1161 
intel_dp_can_link_train_fallback_for_edp(struct intel_dp * intel_dp,int link_rate,u8 lane_count)1162 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
1163 						     int link_rate,
1164 						     u8 lane_count)
1165 {
1166 	/* FIXME figure out what we actually want here */
1167 	const struct drm_display_mode *fixed_mode =
1168 		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
1169 	int mode_rate, max_rate;
1170 
1171 	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
1172 	max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
1173 	if (mode_rate > max_rate)
1174 		return false;
1175 
1176 	return true;
1177 }
1178 
reduce_link_params_in_bw_order(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int * new_link_rate,int * new_lane_count)1179 static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,
1180 					   const struct intel_crtc_state *crtc_state,
1181 					   int *new_link_rate, int *new_lane_count)
1182 {
1183 	int link_rate;
1184 	int lane_count;
1185 	int i;
1186 
1187 	i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
1188 	for (i--; i >= 0; i--) {
1189 		intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count);
1190 
1191 		if ((intel_dp->link.force_rate &&
1192 		     intel_dp->link.force_rate != link_rate) ||
1193 		    (intel_dp->link.force_lane_count &&
1194 		     intel_dp->link.force_lane_count != lane_count))
1195 			continue;
1196 
1197 		break;
1198 	}
1199 
1200 	if (i < 0)
1201 		return false;
1202 
1203 	*new_link_rate = link_rate;
1204 	*new_lane_count = lane_count;
1205 
1206 	return true;
1207 }
1208 
reduce_link_rate(struct intel_dp * intel_dp,int current_rate)1209 static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)
1210 {
1211 	int rate_index;
1212 	int new_rate;
1213 
1214 	if (intel_dp->link.force_rate)
1215 		return -1;
1216 
1217 	rate_index = intel_dp_rate_index(intel_dp->common_rates,
1218 					 intel_dp->num_common_rates,
1219 					 current_rate);
1220 
1221 	if (rate_index <= 0)
1222 		return -1;
1223 
1224 	new_rate = intel_dp_common_rate(intel_dp, rate_index - 1);
1225 
1226 	/* TODO: Make switching from UHBR to non-UHBR rates work. */
1227 	if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate))
1228 		return -1;
1229 
1230 	return new_rate;
1231 }
1232 
reduce_lane_count(struct intel_dp * intel_dp,int current_lane_count)1233 static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)
1234 {
1235 	if (intel_dp->link.force_lane_count)
1236 		return -1;
1237 
1238 	if (current_lane_count == 1)
1239 		return -1;
1240 
1241 	return current_lane_count >> 1;
1242 }
1243 
reduce_link_params_in_rate_lane_order(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int * new_link_rate,int * new_lane_count)1244 static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,
1245 						  const struct intel_crtc_state *crtc_state,
1246 						  int *new_link_rate, int *new_lane_count)
1247 {
1248 	int link_rate;
1249 	int lane_count;
1250 
1251 	lane_count = crtc_state->lane_count;
1252 	link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
1253 	if (link_rate < 0) {
1254 		lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);
1255 		link_rate = intel_dp_max_common_rate(intel_dp);
1256 	}
1257 
1258 	if (lane_count < 0)
1259 		return false;
1260 
1261 	*new_link_rate = link_rate;
1262 	*new_lane_count = lane_count;
1263 
1264 	return true;
1265 }
1266 
reduce_link_params(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int * new_link_rate,int * new_lane_count)1267 static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
1268 			       int *new_link_rate, int *new_lane_count)
1269 {
1270 	/* TODO: Use the same fallback logic on SST as on MST. */
1271 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1272 		return reduce_link_params_in_bw_order(intel_dp, crtc_state,
1273 						      new_link_rate, new_lane_count);
1274 	else
1275 		return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,
1276 							     new_link_rate, new_lane_count);
1277 }
1278 
intel_dp_get_link_train_fallback_values(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1279 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1280 						   const struct intel_crtc_state *crtc_state)
1281 {
1282 	int new_link_rate;
1283 	int new_lane_count;
1284 
1285 	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
1286 		lt_dbg(intel_dp, DP_PHY_DPRX,
1287 		       "Retrying Link training for eDP with max parameters\n");
1288 		intel_dp->use_max_params = true;
1289 		return 0;
1290 	}
1291 
1292 	if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))
1293 		return -1;
1294 
1295 	if (intel_dp_is_edp(intel_dp) &&
1296 	    !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) {
1297 		lt_dbg(intel_dp, DP_PHY_DPRX,
1298 		       "Retrying Link training for eDP with same parameters\n");
1299 		return 0;
1300 	}
1301 
1302 	lt_dbg(intel_dp, DP_PHY_DPRX,
1303 	       "Reducing link parameters from %dx%d to %dx%d\n",
1304 	       crtc_state->lane_count, crtc_state->port_clock,
1305 	       new_lane_count, new_link_rate);
1306 
1307 	intel_dp->link.max_rate = new_link_rate;
1308 	intel_dp->link.max_lane_count = new_lane_count;
1309 
1310 	return 0;
1311 }
1312 
intel_dp_schedule_fallback_link_training(struct intel_atomic_state * state,struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1313 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state,
1314 						     struct intel_dp *intel_dp,
1315 						     const struct intel_crtc_state *crtc_state)
1316 {
1317 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1318 
1319 	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
1320 		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
1321 		return true;
1322 	}
1323 
1324 	if (intel_dp->hobl_active) {
1325 		lt_dbg(intel_dp, DP_PHY_DPRX,
1326 		       "Link Training failed with HOBL active, not enabling it from now on\n");
1327 		intel_dp->hobl_failed = true;
1328 	} else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {
1329 		return false;
1330 	}
1331 
1332 	/* Schedule a Hotplug Uevent to userspace to start modeset */
1333 	intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
1334 
1335 	return true;
1336 }
1337 
1338 /* Perform the link training on all LTTPRs and the DPRX on a link. */
1339 static bool
intel_dp_link_train_all_phys(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int lttpr_count)1340 intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
1341 			     const struct intel_crtc_state *crtc_state,
1342 			     int lttpr_count)
1343 {
1344 	bool ret = true;
1345 	int i;
1346 
1347 	for (i = lttpr_count - 1; i >= 0; i--) {
1348 		enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
1349 
1350 		ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
1351 		intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
1352 
1353 		if (!ret)
1354 			break;
1355 	}
1356 
1357 	if (ret)
1358 		ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
1359 
1360 	if (intel_dp->set_idle_link_train)
1361 		intel_dp->set_idle_link_train(intel_dp, crtc_state);
1362 
1363 	return ret;
1364 }
1365 
1366 /*
1367  * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1)
1368  */
1369 static bool
intel_dp_128b132b_lane_eq(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1370 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
1371 			  const struct intel_crtc_state *crtc_state)
1372 {
1373 	u8 link_status[DP_LINK_STATUS_SIZE];
1374 	int delay_us;
1375 	int try, max_tries = 20;
1376 	unsigned long deadline;
1377 	bool timeout = false;
1378 
1379 	/*
1380 	 * Reset signal levels. Start transmitting 128b/132b TPS1.
1381 	 *
1382 	 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1
1383 	 * in DP_TRAINING_PATTERN_SET.
1384 	 */
1385 	if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
1386 				       DP_TRAINING_PATTERN_1)) {
1387 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");
1388 		return false;
1389 	}
1390 
1391 	delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
1392 
1393 	/* Read the initial TX FFE settings. */
1394 	if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1395 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");
1396 		return false;
1397 	}
1398 
1399 	/* Update signal levels and training set as requested. */
1400 	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1401 	if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
1402 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");
1403 		return false;
1404 	}
1405 
1406 	/* Start transmitting 128b/132b TPS2. */
1407 	if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
1408 				     DP_TRAINING_PATTERN_2)) {
1409 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");
1410 		return false;
1411 	}
1412 
1413 	/* Time budget for the LANEx_EQ_DONE Sequence */
1414 	deadline = jiffies + msecs_to_jiffies_timeout(450);
1415 
1416 	for (try = 0; try < max_tries; try++) {
1417 		fsleep(delay_us);
1418 
1419 		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1420 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1421 			return false;
1422 		}
1423 
1424 		if (drm_dp_128b132b_link_training_failed(link_status)) {
1425 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1426 			lt_err(intel_dp, DP_PHY_DPRX,
1427 			       "Downstream link training failure\n");
1428 			return false;
1429 		}
1430 
1431 		if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
1432 			lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
1433 			break;
1434 		}
1435 
1436 		if (timeout) {
1437 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1438 			lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");
1439 			return false;
1440 		}
1441 
1442 		if (time_after(jiffies, deadline))
1443 			timeout = true; /* try one last time after deadline */
1444 
1445 		/*
1446 		 * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE
1447 		 * presets.
1448 		 */
1449 		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
1450 
1451 		intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1452 
1453 		/* Update signal levels and training set as requested. */
1454 		if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
1455 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
1456 			return false;
1457 		}
1458 	}
1459 
1460 	if (try == max_tries) {
1461 		intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1462 		lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");
1463 		return false;
1464 	}
1465 
1466 	for (;;) {
1467 		if (time_after(jiffies, deadline))
1468 			timeout = true; /* try one last time after deadline */
1469 
1470 		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1471 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1472 			return false;
1473 		}
1474 
1475 		if (drm_dp_128b132b_link_training_failed(link_status)) {
1476 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1477 			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
1478 			return false;
1479 		}
1480 
1481 		if (drm_dp_128b132b_eq_interlane_align_done(link_status)) {
1482 			lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");
1483 			break;
1484 		}
1485 
1486 		if (timeout) {
1487 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1488 			lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");
1489 			return false;
1490 		}
1491 
1492 		usleep_range(2000, 3000);
1493 	}
1494 
1495 	return true;
1496 }
1497 
1498 /*
1499  * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2)
1500  */
1501 static bool
intel_dp_128b132b_lane_cds(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int lttpr_count)1502 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
1503 			   const struct intel_crtc_state *crtc_state,
1504 			   int lttpr_count)
1505 {
1506 	u8 link_status[DP_LINK_STATUS_SIZE];
1507 	unsigned long deadline;
1508 
1509 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
1510 			       DP_TRAINING_PATTERN_2_CDS) != 1) {
1511 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");
1512 		return false;
1513 	}
1514 
1515 	/* Time budget for the LANEx_CDS_DONE Sequence */
1516 	deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20);
1517 
1518 	for (;;) {
1519 		bool timeout = false;
1520 
1521 		if (time_after(jiffies, deadline))
1522 			timeout = true; /* try one last time after deadline */
1523 
1524 		usleep_range(2000, 3000);
1525 
1526 		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1527 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1528 			return false;
1529 		}
1530 
1531 		if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
1532 		    drm_dp_128b132b_cds_interlane_align_done(link_status) &&
1533 		    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
1534 			lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
1535 			break;
1536 		}
1537 
1538 		if (drm_dp_128b132b_link_training_failed(link_status)) {
1539 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1540 			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
1541 			return false;
1542 		}
1543 
1544 		if (timeout) {
1545 			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1546 			lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");
1547 			return false;
1548 		}
1549 	}
1550 
1551 	return true;
1552 }
1553 
1554 /*
1555  * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.)
1556  */
1557 static bool
intel_dp_128b132b_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int lttpr_count)1558 intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
1559 			     const struct intel_crtc_state *crtc_state,
1560 			     int lttpr_count)
1561 {
1562 	bool passed = false;
1563 
1564 	if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1565 		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
1566 		goto out;
1567 	}
1568 
1569 	if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
1570 	    intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))
1571 		passed = true;
1572 
1573 	lt_dbg(intel_dp, DP_PHY_DPRX,
1574 	       "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
1575 	       passed ? "passed" : "failed",
1576 	       crtc_state->port_clock, crtc_state->lane_count);
1577 
1578 out:
1579 	/*
1580 	 * Ensure that the training pattern does get set to TPS2 even in case
1581 	 * of a failure, as is the case at the end of a passing link training
1582 	 * and what is expected by the transcoder. Leaving TPS1 set (and
1583 	 * disabling the link train mode in DP_TP_CTL later from TPS1 directly)
1584 	 * would result in a stuck transcoder HW state and flip-done timeouts
1585 	 * later in the modeset sequence.
1586 	 */
1587 	if (!passed)
1588 		intel_dp_program_link_training_pattern(intel_dp, crtc_state,
1589 						       DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
1590 
1591 	return passed;
1592 }
1593 
1594 /**
1595  * intel_dp_start_link_train - start link training
1596  * @state: Atomic state
1597  * @intel_dp: DP struct
1598  * @crtc_state: state for CRTC attached to the encoder
1599  *
1600  * Start the link training of the @intel_dp port, scheduling a fallback
1601  * retraining with reduced link rate/lane parameters if the link training
1602  * fails.
1603  * After calling this function intel_dp_stop_link_train() must be called.
1604  */
intel_dp_start_link_train(struct intel_atomic_state * state,struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1605 void intel_dp_start_link_train(struct intel_atomic_state *state,
1606 			       struct intel_dp *intel_dp,
1607 			       const struct intel_crtc_state *crtc_state)
1608 {
1609 	struct intel_display *display = to_intel_display(state);
1610 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1611 	struct intel_encoder *encoder = &dig_port->base;
1612 	bool passed;
1613 	/*
1614 	 * Reinit the LTTPRs here to ensure that they are switched to
1615 	 * non-transparent mode. During an earlier LTTPR detection this
1616 	 * could've been prevented by an active link.
1617 	 */
1618 	int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
1619 
1620 	if (lttpr_count < 0)
1621 		/* Still continue with enabling the port and link training. */
1622 		lttpr_count = 0;
1623 
1624 	intel_dp_prepare_link_train(intel_dp, crtc_state);
1625 
1626 	if (intel_dp_is_uhbr(crtc_state))
1627 		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
1628 	else
1629 		passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);
1630 
1631 	if (intel_dp->link.force_train_failure) {
1632 		intel_dp->link.force_train_failure--;
1633 		lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");
1634 	} else if (passed) {
1635 		intel_dp->link.seq_train_failures = 0;
1636 		intel_encoder_link_check_queue_work(encoder, 2000);
1637 		return;
1638 	}
1639 
1640 	intel_dp->link.seq_train_failures++;
1641 
1642 	/*
1643 	 * Ignore the link failure in CI
1644 	 *
1645 	 * In fixed enviroments like CI, sometimes unexpected long HPDs are
1646 	 * generated by the displays. If ignore_long_hpd flag is set, such long
1647 	 * HPDs are ignored. And probably as a consequence of these ignored
1648 	 * long HPDs, subsequent link trainings are failed resulting into CI
1649 	 * execution failures.
1650 	 *
1651 	 * For test cases which rely on the link training or processing of HPDs
1652 	 * ignore_long_hpd flag can unset from the testcase.
1653 	 */
1654 	if (display->hotplug.ignore_long_hpd) {
1655 		lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
1656 		return;
1657 	}
1658 
1659 	if (intel_dp->link.seq_train_failures < 2) {
1660 		intel_encoder_link_check_queue_work(encoder, 0);
1661 		return;
1662 	}
1663 
1664 	if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))
1665 		return;
1666 
1667 	intel_dp->link.retrain_disabled = true;
1668 
1669 	if (!passed)
1670 		lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n");
1671 	else
1672 		lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");
1673 }
1674 
intel_dp_128b132b_sdp_crc16(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)1675 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
1676 				 const struct intel_crtc_state *crtc_state)
1677 {
1678 	/*
1679 	 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
1680 	 * disable SDP CRC. This is applicable for Display version 13.
1681 	 * Default value of bit 31 is '0' hence discarding the write
1682 	 * TODO: Corrective actions on SDP corruption yet to be defined
1683 	 */
1684 	if (!intel_dp_is_uhbr(crtc_state))
1685 		return;
1686 
1687 	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
1688 	drm_dp_dpcd_writeb(&intel_dp->aux,
1689 			   DP_SDP_ERROR_DETECTION_CONFIGURATION,
1690 			   DP_SDP_CRC16_128B132B_EN);
1691 
1692 	lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
1693 }
1694 
i915_dp_force_link_rate_show(struct seq_file * m,void * data)1695 static int i915_dp_force_link_rate_show(struct seq_file *m, void *data)
1696 {
1697 	struct intel_connector *connector = to_intel_connector(m->private);
1698 	struct intel_display *display = to_intel_display(connector);
1699 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1700 	int current_rate = -1;
1701 	int force_rate;
1702 	int err;
1703 	int i;
1704 
1705 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1706 	if (err)
1707 		return err;
1708 
1709 	if (intel_dp->link_trained)
1710 		current_rate = intel_dp->link_rate;
1711 	force_rate = intel_dp->link.force_rate;
1712 
1713 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1714 
1715 	seq_printf(m, "%sauto%s",
1716 		   force_rate == 0 ? "[" : "",
1717 		   force_rate == 0 ? "]" : "");
1718 
1719 	for (i = 0; i < intel_dp->num_source_rates; i++)
1720 		seq_printf(m, " %s%d%s%s",
1721 			   intel_dp->source_rates[i] == force_rate ? "[" : "",
1722 			   intel_dp->source_rates[i],
1723 			   intel_dp->source_rates[i] == current_rate ? "*" : "",
1724 			   intel_dp->source_rates[i] == force_rate ? "]" : "");
1725 
1726 	seq_putc(m, '\n');
1727 
1728 	return 0;
1729 }
1730 
parse_link_rate(struct intel_dp * intel_dp,const char __user * ubuf,size_t len)1731 static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len)
1732 {
1733 	char *kbuf;
1734 	const char *p;
1735 	int rate;
1736 	int ret = 0;
1737 
1738 	kbuf = memdup_user_nul(ubuf, len);
1739 	if (IS_ERR(kbuf))
1740 		return PTR_ERR(kbuf);
1741 
1742 	p = strim(kbuf);
1743 
1744 	if (!strcmp(p, "auto")) {
1745 		rate = 0;
1746 	} else {
1747 		ret = kstrtoint(p, 0, &rate);
1748 		if (ret < 0)
1749 			goto out_free;
1750 
1751 		if (intel_dp_rate_index(intel_dp->source_rates,
1752 					intel_dp->num_source_rates,
1753 					rate) < 0)
1754 			ret = -EINVAL;
1755 	}
1756 
1757 out_free:
1758 	kfree(kbuf);
1759 
1760 	return ret < 0 ? ret : rate;
1761 }
1762 
i915_dp_force_link_rate_write(struct file * file,const char __user * ubuf,size_t len,loff_t * offp)1763 static ssize_t i915_dp_force_link_rate_write(struct file *file,
1764 					     const char __user *ubuf,
1765 					     size_t len, loff_t *offp)
1766 {
1767 	struct seq_file *m = file->private_data;
1768 	struct intel_connector *connector = to_intel_connector(m->private);
1769 	struct intel_display *display = to_intel_display(connector);
1770 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1771 	int rate;
1772 	int err;
1773 
1774 	rate = parse_link_rate(intel_dp, ubuf, len);
1775 	if (rate < 0)
1776 		return rate;
1777 
1778 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1779 	if (err)
1780 		return err;
1781 
1782 	intel_dp_reset_link_params(intel_dp);
1783 	intel_dp->link.force_rate = rate;
1784 
1785 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1786 
1787 	*offp += len;
1788 
1789 	return len;
1790 }
1791 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate);
1792 
i915_dp_force_lane_count_show(struct seq_file * m,void * data)1793 static int i915_dp_force_lane_count_show(struct seq_file *m, void *data)
1794 {
1795 	struct intel_connector *connector = to_intel_connector(m->private);
1796 	struct intel_display *display = to_intel_display(connector);
1797 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1798 	int current_lane_count = -1;
1799 	int force_lane_count;
1800 	int err;
1801 	int i;
1802 
1803 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1804 	if (err)
1805 		return err;
1806 
1807 	if (intel_dp->link_trained)
1808 		current_lane_count = intel_dp->lane_count;
1809 	force_lane_count = intel_dp->link.force_lane_count;
1810 
1811 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1812 
1813 	seq_printf(m, "%sauto%s",
1814 		   force_lane_count == 0 ? "[" : "",
1815 		   force_lane_count == 0 ? "]" : "");
1816 
1817 	for (i = 1; i <= 4; i <<= 1)
1818 		seq_printf(m, " %s%d%s%s",
1819 			   i == force_lane_count ? "[" : "",
1820 			   i,
1821 			   i == current_lane_count ? "*" : "",
1822 			   i == force_lane_count ? "]" : "");
1823 
1824 	seq_putc(m, '\n');
1825 
1826 	return 0;
1827 }
1828 
parse_lane_count(const char __user * ubuf,size_t len)1829 static int parse_lane_count(const char __user *ubuf, size_t len)
1830 {
1831 	char *kbuf;
1832 	const char *p;
1833 	int lane_count;
1834 	int ret = 0;
1835 
1836 	kbuf = memdup_user_nul(ubuf, len);
1837 	if (IS_ERR(kbuf))
1838 		return PTR_ERR(kbuf);
1839 
1840 	p = strim(kbuf);
1841 
1842 	if (!strcmp(p, "auto")) {
1843 		lane_count = 0;
1844 	} else {
1845 		ret = kstrtoint(p, 0, &lane_count);
1846 		if (ret < 0)
1847 			goto out_free;
1848 
1849 		switch (lane_count) {
1850 		case 1:
1851 		case 2:
1852 		case 4:
1853 			break;
1854 		default:
1855 			ret = -EINVAL;
1856 		}
1857 	}
1858 
1859 out_free:
1860 	kfree(kbuf);
1861 
1862 	return ret < 0 ? ret : lane_count;
1863 }
1864 
i915_dp_force_lane_count_write(struct file * file,const char __user * ubuf,size_t len,loff_t * offp)1865 static ssize_t i915_dp_force_lane_count_write(struct file *file,
1866 					      const char __user *ubuf,
1867 					      size_t len, loff_t *offp)
1868 {
1869 	struct seq_file *m = file->private_data;
1870 	struct intel_connector *connector = to_intel_connector(m->private);
1871 	struct intel_display *display = to_intel_display(connector);
1872 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1873 	int lane_count;
1874 	int err;
1875 
1876 	lane_count = parse_lane_count(ubuf, len);
1877 	if (lane_count < 0)
1878 		return lane_count;
1879 
1880 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1881 	if (err)
1882 		return err;
1883 
1884 	intel_dp_reset_link_params(intel_dp);
1885 	intel_dp->link.force_lane_count = lane_count;
1886 
1887 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1888 
1889 	*offp += len;
1890 
1891 	return len;
1892 }
1893 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count);
1894 
i915_dp_max_link_rate_show(void * data,u64 * val)1895 static int i915_dp_max_link_rate_show(void *data, u64 *val)
1896 {
1897 	struct intel_connector *connector = to_intel_connector(data);
1898 	struct intel_display *display = to_intel_display(connector);
1899 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1900 	int err;
1901 
1902 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1903 	if (err)
1904 		return err;
1905 
1906 	*val = intel_dp->link.max_rate;
1907 
1908 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1909 
1910 	return 0;
1911 }
1912 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n");
1913 
i915_dp_max_lane_count_show(void * data,u64 * val)1914 static int i915_dp_max_lane_count_show(void *data, u64 *val)
1915 {
1916 	struct intel_connector *connector = to_intel_connector(data);
1917 	struct intel_display *display = to_intel_display(connector);
1918 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1919 	int err;
1920 
1921 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1922 	if (err)
1923 		return err;
1924 
1925 	*val = intel_dp->link.max_lane_count;
1926 
1927 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1928 
1929 	return 0;
1930 }
1931 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n");
1932 
i915_dp_force_link_training_failure_show(void * data,u64 * val)1933 static int i915_dp_force_link_training_failure_show(void *data, u64 *val)
1934 {
1935 	struct intel_connector *connector = to_intel_connector(data);
1936 	struct intel_display *display = to_intel_display(connector);
1937 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1938 	int err;
1939 
1940 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1941 	if (err)
1942 		return err;
1943 
1944 	*val = intel_dp->link.force_train_failure;
1945 
1946 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1947 
1948 	return 0;
1949 }
1950 
i915_dp_force_link_training_failure_write(void * data,u64 val)1951 static int i915_dp_force_link_training_failure_write(void *data, u64 val)
1952 {
1953 	struct intel_connector *connector = to_intel_connector(data);
1954 	struct intel_display *display = to_intel_display(connector);
1955 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1956 	int err;
1957 
1958 	if (val > 2)
1959 		return -EINVAL;
1960 
1961 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1962 	if (err)
1963 		return err;
1964 
1965 	intel_dp->link.force_train_failure = val;
1966 
1967 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1968 
1969 	return 0;
1970 }
1971 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops,
1972 			 i915_dp_force_link_training_failure_show,
1973 			 i915_dp_force_link_training_failure_write, "%llu\n");
1974 
i915_dp_force_link_retrain_show(void * data,u64 * val)1975 static int i915_dp_force_link_retrain_show(void *data, u64 *val)
1976 {
1977 	struct intel_connector *connector = to_intel_connector(data);
1978 	struct intel_display *display = to_intel_display(connector);
1979 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1980 	int err;
1981 
1982 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1983 	if (err)
1984 		return err;
1985 
1986 	*val = intel_dp->link.force_retrain;
1987 
1988 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1989 
1990 	return 0;
1991 }
1992 
i915_dp_force_link_retrain_write(void * data,u64 val)1993 static int i915_dp_force_link_retrain_write(void *data, u64 val)
1994 {
1995 	struct intel_connector *connector = to_intel_connector(data);
1996 	struct intel_display *display = to_intel_display(connector);
1997 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1998 	int err;
1999 
2000 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
2001 	if (err)
2002 		return err;
2003 
2004 	intel_dp->link.force_retrain = val;
2005 
2006 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
2007 
2008 	intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
2009 
2010 	return 0;
2011 }
2012 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops,
2013 			 i915_dp_force_link_retrain_show,
2014 			 i915_dp_force_link_retrain_write, "%llu\n");
2015 
i915_dp_link_retrain_disabled_show(struct seq_file * m,void * data)2016 static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data)
2017 {
2018 	struct intel_connector *connector = to_intel_connector(m->private);
2019 	struct intel_display *display = to_intel_display(connector);
2020 	struct intel_dp *intel_dp = intel_attached_dp(connector);
2021 	int err;
2022 
2023 	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
2024 	if (err)
2025 		return err;
2026 
2027 	seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled));
2028 
2029 	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
2030 
2031 	return 0;
2032 }
2033 DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled);
2034 
intel_dp_link_training_debugfs_add(struct intel_connector * connector)2035 void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
2036 {
2037 	struct dentry *root = connector->base.debugfs_entry;
2038 
2039 	if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
2040 	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2041 		return;
2042 
2043 	debugfs_create_file("i915_dp_force_link_rate", 0644, root,
2044 			    connector, &i915_dp_force_link_rate_fops);
2045 
2046 	debugfs_create_file("i915_dp_force_lane_count", 0644, root,
2047 			    connector, &i915_dp_force_lane_count_fops);
2048 
2049 	debugfs_create_file("i915_dp_max_link_rate", 0444, root,
2050 			    connector, &i915_dp_max_link_rate_fops);
2051 
2052 	debugfs_create_file("i915_dp_max_lane_count", 0444, root,
2053 			    connector, &i915_dp_max_lane_count_fops);
2054 
2055 	debugfs_create_file("i915_dp_force_link_training_failure", 0644, root,
2056 			    connector, &i915_dp_force_link_training_failure_fops);
2057 
2058 	debugfs_create_file("i915_dp_force_link_retrain", 0644, root,
2059 			    connector, &i915_dp_force_link_retrain_fops);
2060 
2061 	debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root,
2062 			    connector, &i915_dp_link_retrain_disabled_fops);
2063 }
2064