1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dp_tunnel.h" 58 #include "intel_dpio_phy.h" 59 #include "intel_dsi.h" 60 #include "intel_encoder.h" 61 #include "intel_fdi.h" 62 #include "intel_fifo_underrun.h" 63 #include "intel_gmbus.h" 64 #include "intel_hdcp.h" 65 #include "intel_hdmi.h" 66 #include "intel_hotplug.h" 67 #include "intel_hti.h" 68 #include "intel_lspcon.h" 69 #include "intel_mg_phy_regs.h" 70 #include "intel_modeset_lock.h" 71 #include "intel_pps.h" 72 #include "intel_psr.h" 73 #include "intel_quirks.h" 74 #include "intel_snps_phy.h" 75 #include "intel_tc.h" 76 #include "intel_vdsc.h" 77 #include "intel_vdsc_regs.h" 78 #include "skl_scaler.h" 79 #include "skl_universal_plane.h" 80 81 static const u8 index_to_dp_signal_levels[] = { 82 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 83 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 84 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 85 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 86 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 87 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 88 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 89 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 90 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 91 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 92 }; 93 94 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 95 const struct intel_ddi_buf_trans *trans) 96 { 97 int level; 98 99 level = intel_bios_hdmi_level_shift(encoder->devdata); 100 if (level < 0) 101 level = trans->hdmi_default_entry; 102 103 return level; 104 } 105 106 static bool has_buf_trans_select(struct drm_i915_private *i915) 107 { 108 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 109 } 110 111 static bool has_iboost(struct drm_i915_private *i915) 112 { 113 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 114 } 115 116 /* 117 * Starting with Haswell, DDI port buffers must be programmed with correct 118 * values in advance. This function programs the correct values for 119 * DP/eDP/FDI use cases. 120 */ 121 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 122 const struct intel_crtc_state *crtc_state) 123 { 124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 125 u32 iboost_bit = 0; 126 int i, n_entries; 127 enum port port = encoder->port; 128 const struct intel_ddi_buf_trans *trans; 129 130 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 132 return; 133 134 /* If we're boosting the current, set bit 31 of trans1 */ 135 if (has_iboost(dev_priv) && 136 intel_bios_dp_boost_level(encoder->devdata)) 137 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 138 139 for (i = 0; i < n_entries; i++) { 140 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 141 trans->entries[i].hsw.trans1 | iboost_bit); 142 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 143 trans->entries[i].hsw.trans2); 144 } 145 } 146 147 /* 148 * Starting with Haswell, DDI port buffers must be programmed with correct 149 * values in advance. This function programs the correct values for 150 * HDMI/DVI use cases. 151 */ 152 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 153 const struct intel_crtc_state *crtc_state) 154 { 155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 156 int level = intel_ddi_level(encoder, crtc_state, 0); 157 u32 iboost_bit = 0; 158 int n_entries; 159 enum port port = encoder->port; 160 const struct intel_ddi_buf_trans *trans; 161 162 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 163 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 164 return; 165 166 /* If we're boosting the current, set bit 31 of trans1 */ 167 if (has_iboost(dev_priv) && 168 intel_bios_hdmi_boost_level(encoder->devdata)) 169 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 170 171 /* Entry 9 is for HDMI: */ 172 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 173 trans->entries[level].hsw.trans1 | iboost_bit); 174 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 175 trans->entries[level].hsw.trans2); 176 } 177 178 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 179 { 180 int ret; 181 182 /* FIXME: find out why Bspec's 100us timeout is too short */ 183 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 184 XELPDP_PORT_BUF_PHY_IDLE), 10000); 185 if (ret) 186 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 187 port_name(port)); 188 } 189 190 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 191 enum port port) 192 { 193 if (IS_BROXTON(dev_priv)) { 194 udelay(16); 195 return; 196 } 197 198 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 199 DDI_BUF_IS_IDLE), 8)) 200 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 201 port_name(port)); 202 } 203 204 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 205 { 206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 207 enum port port = encoder->port; 208 int timeout_us; 209 int ret; 210 211 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 212 if (DISPLAY_VER(dev_priv) < 10) { 213 usleep_range(518, 1000); 214 return; 215 } 216 217 if (DISPLAY_VER(dev_priv) >= 14) { 218 timeout_us = 10000; 219 } else if (IS_DG2(dev_priv)) { 220 timeout_us = 1200; 221 } else if (DISPLAY_VER(dev_priv) >= 12) { 222 if (intel_encoder_is_tc(encoder)) 223 timeout_us = 3000; 224 else 225 timeout_us = 1000; 226 } else { 227 timeout_us = 500; 228 } 229 230 if (DISPLAY_VER(dev_priv) >= 14) 231 ret = _wait_for(!(intel_de_read(dev_priv, 232 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 233 XELPDP_PORT_BUF_PHY_IDLE), 234 timeout_us, 10, 10); 235 else 236 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 237 timeout_us, 10, 10); 238 239 if (ret) 240 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 241 port_name(port)); 242 } 243 244 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 245 { 246 switch (pll->info->id) { 247 case DPLL_ID_WRPLL1: 248 return PORT_CLK_SEL_WRPLL1; 249 case DPLL_ID_WRPLL2: 250 return PORT_CLK_SEL_WRPLL2; 251 case DPLL_ID_SPLL: 252 return PORT_CLK_SEL_SPLL; 253 case DPLL_ID_LCPLL_810: 254 return PORT_CLK_SEL_LCPLL_810; 255 case DPLL_ID_LCPLL_1350: 256 return PORT_CLK_SEL_LCPLL_1350; 257 case DPLL_ID_LCPLL_2700: 258 return PORT_CLK_SEL_LCPLL_2700; 259 default: 260 MISSING_CASE(pll->info->id); 261 return PORT_CLK_SEL_NONE; 262 } 263 } 264 265 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 266 const struct intel_crtc_state *crtc_state) 267 { 268 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 269 int clock = crtc_state->port_clock; 270 const enum intel_dpll_id id = pll->info->id; 271 272 switch (id) { 273 default: 274 /* 275 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 276 * here, so do warn if this get passed in 277 */ 278 MISSING_CASE(id); 279 return DDI_CLK_SEL_NONE; 280 case DPLL_ID_ICL_TBTPLL: 281 switch (clock) { 282 case 162000: 283 return DDI_CLK_SEL_TBT_162; 284 case 270000: 285 return DDI_CLK_SEL_TBT_270; 286 case 540000: 287 return DDI_CLK_SEL_TBT_540; 288 case 810000: 289 return DDI_CLK_SEL_TBT_810; 290 default: 291 MISSING_CASE(clock); 292 return DDI_CLK_SEL_NONE; 293 } 294 case DPLL_ID_ICL_MGPLL1: 295 case DPLL_ID_ICL_MGPLL2: 296 case DPLL_ID_ICL_MGPLL3: 297 case DPLL_ID_ICL_MGPLL4: 298 case DPLL_ID_TGL_MGPLL5: 299 case DPLL_ID_TGL_MGPLL6: 300 return DDI_CLK_SEL_MG; 301 } 302 } 303 304 static u32 ddi_buf_phy_link_rate(int port_clock) 305 { 306 switch (port_clock) { 307 case 162000: 308 return DDI_BUF_PHY_LINK_RATE(0); 309 case 216000: 310 return DDI_BUF_PHY_LINK_RATE(4); 311 case 243000: 312 return DDI_BUF_PHY_LINK_RATE(5); 313 case 270000: 314 return DDI_BUF_PHY_LINK_RATE(1); 315 case 324000: 316 return DDI_BUF_PHY_LINK_RATE(6); 317 case 432000: 318 return DDI_BUF_PHY_LINK_RATE(7); 319 case 540000: 320 return DDI_BUF_PHY_LINK_RATE(2); 321 case 810000: 322 return DDI_BUF_PHY_LINK_RATE(3); 323 default: 324 MISSING_CASE(port_clock); 325 return DDI_BUF_PHY_LINK_RATE(0); 326 } 327 } 328 329 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 330 const struct intel_crtc_state *crtc_state) 331 { 332 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 333 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 334 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 335 336 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 337 intel_dp->DP = dig_port->saved_port_bits | 338 DDI_PORT_WIDTH(crtc_state->lane_count) | 339 DDI_BUF_TRANS_SELECT(0); 340 341 if (DISPLAY_VER(i915) >= 14) { 342 if (intel_dp_is_uhbr(crtc_state)) 343 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 344 else 345 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 346 } 347 348 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 349 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 350 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 351 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 352 } 353 } 354 355 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 356 enum port port) 357 { 358 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 359 360 switch (val) { 361 case DDI_CLK_SEL_NONE: 362 return 0; 363 case DDI_CLK_SEL_TBT_162: 364 return 162000; 365 case DDI_CLK_SEL_TBT_270: 366 return 270000; 367 case DDI_CLK_SEL_TBT_540: 368 return 540000; 369 case DDI_CLK_SEL_TBT_810: 370 return 810000; 371 default: 372 MISSING_CASE(val); 373 return 0; 374 } 375 } 376 377 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 378 { 379 /* CRT dotclock is determined via other means */ 380 if (pipe_config->has_pch_encoder) 381 return; 382 383 pipe_config->hw.adjusted_mode.crtc_clock = 384 intel_crtc_dotclock(pipe_config); 385 } 386 387 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 388 const struct drm_connector_state *conn_state) 389 { 390 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 392 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 393 u32 temp; 394 395 if (!intel_crtc_has_dp_encoder(crtc_state)) 396 return; 397 398 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 399 400 temp = DP_MSA_MISC_SYNC_CLOCK; 401 402 switch (crtc_state->pipe_bpp) { 403 case 18: 404 temp |= DP_MSA_MISC_6_BPC; 405 break; 406 case 24: 407 temp |= DP_MSA_MISC_8_BPC; 408 break; 409 case 30: 410 temp |= DP_MSA_MISC_10_BPC; 411 break; 412 case 36: 413 temp |= DP_MSA_MISC_12_BPC; 414 break; 415 default: 416 MISSING_CASE(crtc_state->pipe_bpp); 417 break; 418 } 419 420 /* nonsense combination */ 421 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 422 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 423 424 if (crtc_state->limited_color_range) 425 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 426 427 /* 428 * As per DP 1.2 spec section 2.3.4.3 while sending 429 * YCBCR 444 signals we should program MSA MISC1/0 fields with 430 * colorspace information. 431 */ 432 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 433 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 434 435 /* 436 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 437 * of Color Encoding Format and Content Color Gamut] while sending 438 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 439 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 440 */ 441 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 442 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 443 444 intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), 445 temp); 446 } 447 448 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 449 { 450 if (master_transcoder == TRANSCODER_EDP) 451 return 0; 452 else 453 return master_transcoder + 1; 454 } 455 456 static void 457 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 458 const struct intel_crtc_state *crtc_state) 459 { 460 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 461 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 462 u32 val = 0; 463 464 if (intel_dp_is_uhbr(crtc_state)) 465 val = TRANS_DP2_128B132B_CHANNEL_CODING; 466 467 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 468 } 469 470 /* 471 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 472 * 473 * Only intended to be used by intel_ddi_enable_transcoder_func() and 474 * intel_ddi_config_transcoder_func(). 475 */ 476 static u32 477 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 478 const struct intel_crtc_state *crtc_state) 479 { 480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 482 enum pipe pipe = crtc->pipe; 483 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 484 enum port port = encoder->port; 485 u32 temp; 486 487 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 488 temp = TRANS_DDI_FUNC_ENABLE; 489 if (DISPLAY_VER(dev_priv) >= 12) 490 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 491 else 492 temp |= TRANS_DDI_SELECT_PORT(port); 493 494 switch (crtc_state->pipe_bpp) { 495 default: 496 MISSING_CASE(crtc_state->pipe_bpp); 497 fallthrough; 498 case 18: 499 temp |= TRANS_DDI_BPC_6; 500 break; 501 case 24: 502 temp |= TRANS_DDI_BPC_8; 503 break; 504 case 30: 505 temp |= TRANS_DDI_BPC_10; 506 break; 507 case 36: 508 temp |= TRANS_DDI_BPC_12; 509 break; 510 } 511 512 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 513 temp |= TRANS_DDI_PVSYNC; 514 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 515 temp |= TRANS_DDI_PHSYNC; 516 517 if (cpu_transcoder == TRANSCODER_EDP) { 518 switch (pipe) { 519 default: 520 MISSING_CASE(pipe); 521 fallthrough; 522 case PIPE_A: 523 /* On Haswell, can only use the always-on power well for 524 * eDP when not using the panel fitter, and when not 525 * using motion blur mitigation (which we don't 526 * support). */ 527 if (crtc_state->pch_pfit.force_thru) 528 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 529 else 530 temp |= TRANS_DDI_EDP_INPUT_A_ON; 531 break; 532 case PIPE_B: 533 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 534 break; 535 case PIPE_C: 536 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 537 break; 538 } 539 } 540 541 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 542 if (crtc_state->has_hdmi_sink) 543 temp |= TRANS_DDI_MODE_SELECT_HDMI; 544 else 545 temp |= TRANS_DDI_MODE_SELECT_DVI; 546 547 if (crtc_state->hdmi_scrambling) 548 temp |= TRANS_DDI_HDMI_SCRAMBLING; 549 if (crtc_state->hdmi_high_tmds_clock_ratio) 550 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 551 if (DISPLAY_VER(dev_priv) >= 14) 552 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 553 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 554 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 555 temp |= (crtc_state->fdi_lanes - 1) << 1; 556 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 557 if (intel_dp_is_uhbr(crtc_state)) 558 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 559 else 560 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 561 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 562 563 if (DISPLAY_VER(dev_priv) >= 12) { 564 enum transcoder master; 565 566 master = crtc_state->mst_master_transcoder; 567 drm_WARN_ON(&dev_priv->drm, 568 master == INVALID_TRANSCODER); 569 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 570 } 571 } else { 572 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 573 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 574 } 575 576 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 577 crtc_state->master_transcoder != INVALID_TRANSCODER) { 578 u8 master_select = 579 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 580 581 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 582 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 583 } 584 585 return temp; 586 } 587 588 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 589 const struct intel_crtc_state *crtc_state) 590 { 591 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 592 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 593 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 594 595 if (DISPLAY_VER(dev_priv) >= 11) { 596 enum transcoder master_transcoder = crtc_state->master_transcoder; 597 u32 ctl2 = 0; 598 599 if (master_transcoder != INVALID_TRANSCODER) { 600 u8 master_select = 601 bdw_trans_port_sync_master_select(master_transcoder); 602 603 ctl2 |= PORT_SYNC_MODE_ENABLE | 604 PORT_SYNC_MODE_MASTER_SELECT(master_select); 605 } 606 607 intel_de_write(dev_priv, 608 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 609 ctl2); 610 } 611 612 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 613 intel_ddi_transcoder_func_reg_val_get(encoder, 614 crtc_state)); 615 } 616 617 /* 618 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 619 * bit. 620 */ 621 static void 622 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 623 const struct intel_crtc_state *crtc_state) 624 { 625 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 627 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 628 u32 ctl; 629 630 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 631 ctl &= ~TRANS_DDI_FUNC_ENABLE; 632 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 633 ctl); 634 } 635 636 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 637 { 638 struct intel_display *display = to_intel_display(crtc_state); 639 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 641 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 642 u32 ctl; 643 644 if (DISPLAY_VER(dev_priv) >= 11) 645 intel_de_write(dev_priv, 646 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), 647 0); 648 649 ctl = intel_de_read(dev_priv, 650 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 651 652 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 653 654 ctl &= ~TRANS_DDI_FUNC_ENABLE; 655 656 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 657 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 658 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 659 660 if (DISPLAY_VER(dev_priv) >= 12) { 661 if (!intel_dp_mst_is_master_trans(crtc_state)) { 662 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 663 TRANS_DDI_MODE_SELECT_MASK); 664 } 665 } else { 666 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 667 } 668 669 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 670 ctl); 671 672 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 673 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 674 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 675 /* Quirk time at 100ms for reliable operation */ 676 msleep(100); 677 } 678 } 679 680 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 681 enum transcoder cpu_transcoder, 682 bool enable, u32 hdcp_mask) 683 { 684 struct drm_device *dev = intel_encoder->base.dev; 685 struct drm_i915_private *dev_priv = to_i915(dev); 686 intel_wakeref_t wakeref; 687 int ret = 0; 688 689 wakeref = intel_display_power_get_if_enabled(dev_priv, 690 intel_encoder->power_domain); 691 if (drm_WARN_ON(dev, !wakeref)) 692 return -ENXIO; 693 694 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 695 hdcp_mask, enable ? hdcp_mask : 0); 696 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 697 return ret; 698 } 699 700 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 701 { 702 struct drm_device *dev = intel_connector->base.dev; 703 struct drm_i915_private *dev_priv = to_i915(dev); 704 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 705 int type = intel_connector->base.connector_type; 706 enum port port = encoder->port; 707 enum transcoder cpu_transcoder; 708 intel_wakeref_t wakeref; 709 enum pipe pipe = 0; 710 u32 tmp; 711 bool ret; 712 713 wakeref = intel_display_power_get_if_enabled(dev_priv, 714 encoder->power_domain); 715 if (!wakeref) 716 return false; 717 718 if (!encoder->get_hw_state(encoder, &pipe)) { 719 ret = false; 720 goto out; 721 } 722 723 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 724 cpu_transcoder = TRANSCODER_EDP; 725 else 726 cpu_transcoder = (enum transcoder) pipe; 727 728 tmp = intel_de_read(dev_priv, 729 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 730 731 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 732 case TRANS_DDI_MODE_SELECT_HDMI: 733 case TRANS_DDI_MODE_SELECT_DVI: 734 ret = type == DRM_MODE_CONNECTOR_HDMIA; 735 break; 736 737 case TRANS_DDI_MODE_SELECT_DP_SST: 738 ret = type == DRM_MODE_CONNECTOR_eDP || 739 type == DRM_MODE_CONNECTOR_DisplayPort; 740 break; 741 742 case TRANS_DDI_MODE_SELECT_DP_MST: 743 /* if the transcoder is in MST state then 744 * connector isn't connected */ 745 ret = false; 746 break; 747 748 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 749 if (HAS_DP20(dev_priv)) 750 /* 128b/132b */ 751 ret = false; 752 else 753 /* FDI */ 754 ret = type == DRM_MODE_CONNECTOR_VGA; 755 break; 756 757 default: 758 ret = false; 759 break; 760 } 761 762 out: 763 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 764 765 return ret; 766 } 767 768 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 769 u8 *pipe_mask, bool *is_dp_mst) 770 { 771 struct drm_device *dev = encoder->base.dev; 772 struct drm_i915_private *dev_priv = to_i915(dev); 773 enum port port = encoder->port; 774 intel_wakeref_t wakeref; 775 enum pipe p; 776 u32 tmp; 777 u8 mst_pipe_mask; 778 779 *pipe_mask = 0; 780 *is_dp_mst = false; 781 782 wakeref = intel_display_power_get_if_enabled(dev_priv, 783 encoder->power_domain); 784 if (!wakeref) 785 return; 786 787 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 788 if (!(tmp & DDI_BUF_CTL_ENABLE)) 789 goto out; 790 791 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 792 tmp = intel_de_read(dev_priv, 793 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); 794 795 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 796 default: 797 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 798 fallthrough; 799 case TRANS_DDI_EDP_INPUT_A_ON: 800 case TRANS_DDI_EDP_INPUT_A_ONOFF: 801 *pipe_mask = BIT(PIPE_A); 802 break; 803 case TRANS_DDI_EDP_INPUT_B_ONOFF: 804 *pipe_mask = BIT(PIPE_B); 805 break; 806 case TRANS_DDI_EDP_INPUT_C_ONOFF: 807 *pipe_mask = BIT(PIPE_C); 808 break; 809 } 810 811 goto out; 812 } 813 814 mst_pipe_mask = 0; 815 for_each_pipe(dev_priv, p) { 816 enum transcoder cpu_transcoder = (enum transcoder)p; 817 unsigned int port_mask, ddi_select; 818 intel_wakeref_t trans_wakeref; 819 820 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 821 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 822 if (!trans_wakeref) 823 continue; 824 825 if (DISPLAY_VER(dev_priv) >= 12) { 826 port_mask = TGL_TRANS_DDI_PORT_MASK; 827 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 828 } else { 829 port_mask = TRANS_DDI_PORT_MASK; 830 ddi_select = TRANS_DDI_SELECT_PORT(port); 831 } 832 833 tmp = intel_de_read(dev_priv, 834 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 835 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 836 trans_wakeref); 837 838 if ((tmp & port_mask) != ddi_select) 839 continue; 840 841 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 842 (HAS_DP20(dev_priv) && 843 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 844 mst_pipe_mask |= BIT(p); 845 846 *pipe_mask |= BIT(p); 847 } 848 849 if (!*pipe_mask) 850 drm_dbg_kms(&dev_priv->drm, 851 "No pipe for [ENCODER:%d:%s] found\n", 852 encoder->base.base.id, encoder->base.name); 853 854 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 855 drm_dbg_kms(&dev_priv->drm, 856 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 857 encoder->base.base.id, encoder->base.name, 858 *pipe_mask); 859 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 860 } 861 862 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 863 drm_dbg_kms(&dev_priv->drm, 864 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 865 encoder->base.base.id, encoder->base.name, 866 *pipe_mask, mst_pipe_mask); 867 else 868 *is_dp_mst = mst_pipe_mask; 869 870 out: 871 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 872 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 873 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 874 BXT_PHY_LANE_POWERDOWN_ACK | 875 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 876 drm_err(&dev_priv->drm, 877 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 878 encoder->base.base.id, encoder->base.name, tmp); 879 } 880 881 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 882 } 883 884 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 885 enum pipe *pipe) 886 { 887 u8 pipe_mask; 888 bool is_mst; 889 890 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 891 892 if (is_mst || !pipe_mask) 893 return false; 894 895 *pipe = ffs(pipe_mask) - 1; 896 897 return true; 898 } 899 900 static enum intel_display_power_domain 901 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 902 const struct intel_crtc_state *crtc_state) 903 { 904 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 905 906 /* 907 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 908 * DC states enabled at the same time, while for driver initiated AUX 909 * transfers we need the same AUX IOs to be powered but with DC states 910 * disabled. Accordingly use the AUX_IO_<port> power domain here which 911 * leaves DC states enabled. 912 * 913 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 914 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 915 * well, so we can acquire a wider AUX_<port> power domain reference 916 * instead of a specific AUX_IO_<port> reference without powering up any 917 * extra wells. 918 */ 919 if (intel_encoder_can_psr(&dig_port->base)) 920 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 921 else if (DISPLAY_VER(i915) < 14 && 922 (intel_crtc_has_dp_encoder(crtc_state) || 923 intel_encoder_is_tc(&dig_port->base))) 924 return intel_aux_power_domain(dig_port); 925 else 926 return POWER_DOMAIN_INVALID; 927 } 928 929 static void 930 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 931 const struct intel_crtc_state *crtc_state) 932 { 933 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 934 enum intel_display_power_domain domain = 935 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 936 937 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 938 939 if (domain == POWER_DOMAIN_INVALID) 940 return; 941 942 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 943 } 944 945 static void 946 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 947 const struct intel_crtc_state *crtc_state) 948 { 949 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 950 enum intel_display_power_domain domain = 951 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 952 intel_wakeref_t wf; 953 954 wf = fetch_and_zero(&dig_port->aux_wakeref); 955 if (!wf) 956 return; 957 958 intel_display_power_put(i915, domain, wf); 959 } 960 961 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 962 struct intel_crtc_state *crtc_state) 963 { 964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 965 struct intel_digital_port *dig_port; 966 967 /* 968 * TODO: Add support for MST encoders. Atm, the following should never 969 * happen since fake-MST encoders don't set their get_power_domains() 970 * hook. 971 */ 972 if (drm_WARN_ON(&dev_priv->drm, 973 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 974 return; 975 976 dig_port = enc_to_dig_port(encoder); 977 978 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 979 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 980 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 981 dig_port->ddi_io_power_domain); 982 } 983 984 main_link_aux_power_domain_get(dig_port, crtc_state); 985 } 986 987 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 988 const struct intel_crtc_state *crtc_state) 989 { 990 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 992 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 993 enum phy phy = intel_encoder_to_phy(encoder); 994 u32 val; 995 996 if (cpu_transcoder == TRANSCODER_EDP) 997 return; 998 999 if (DISPLAY_VER(dev_priv) >= 13) 1000 val = TGL_TRANS_CLK_SEL_PORT(phy); 1001 else if (DISPLAY_VER(dev_priv) >= 12) 1002 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1003 else 1004 val = TRANS_CLK_SEL_PORT(encoder->port); 1005 1006 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1007 } 1008 1009 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1010 { 1011 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1012 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1013 u32 val; 1014 1015 if (cpu_transcoder == TRANSCODER_EDP) 1016 return; 1017 1018 if (DISPLAY_VER(dev_priv) >= 12) 1019 val = TGL_TRANS_CLK_SEL_DISABLED; 1020 else 1021 val = TRANS_CLK_SEL_DISABLED; 1022 1023 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1024 } 1025 1026 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1027 enum port port, u8 iboost) 1028 { 1029 u32 tmp; 1030 1031 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1032 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1033 if (iboost) 1034 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1035 else 1036 tmp |= BALANCE_LEG_DISABLE(port); 1037 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1038 } 1039 1040 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1041 const struct intel_crtc_state *crtc_state, 1042 int level) 1043 { 1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1046 u8 iboost; 1047 1048 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1049 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1050 else 1051 iboost = intel_bios_dp_boost_level(encoder->devdata); 1052 1053 if (iboost == 0) { 1054 const struct intel_ddi_buf_trans *trans; 1055 int n_entries; 1056 1057 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1058 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1059 return; 1060 1061 iboost = trans->entries[level].hsw.i_boost; 1062 } 1063 1064 /* Make sure that the requested I_boost is valid */ 1065 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1066 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1067 return; 1068 } 1069 1070 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1071 1072 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1073 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1074 } 1075 1076 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1077 const struct intel_crtc_state *crtc_state) 1078 { 1079 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1081 int n_entries; 1082 1083 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1084 1085 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1086 n_entries = 1; 1087 if (drm_WARN_ON(&dev_priv->drm, 1088 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1089 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1090 1091 return index_to_dp_signal_levels[n_entries - 1] & 1092 DP_TRAIN_VOLTAGE_SWING_MASK; 1093 } 1094 1095 /* 1096 * We assume that the full set of pre-emphasis values can be 1097 * used on all DDI platforms. Should that change we need to 1098 * rethink this code. 1099 */ 1100 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1101 { 1102 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1103 } 1104 1105 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1106 int lane) 1107 { 1108 if (crtc_state->port_clock > 600000) 1109 return 0; 1110 1111 if (crtc_state->lane_count == 4) 1112 return lane >= 1 ? LOADGEN_SELECT : 0; 1113 else 1114 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1115 } 1116 1117 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1118 const struct intel_crtc_state *crtc_state) 1119 { 1120 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1121 const struct intel_ddi_buf_trans *trans; 1122 enum phy phy = intel_encoder_to_phy(encoder); 1123 int n_entries, ln; 1124 u32 val; 1125 1126 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1127 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1128 return; 1129 1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1131 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1132 1133 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1134 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1135 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1136 intel_dp->hobl_active ? val : 0); 1137 } 1138 1139 /* Set PORT_TX_DW5 */ 1140 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1141 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1142 TAP2_DISABLE | TAP3_DISABLE); 1143 val |= SCALING_MODE_SEL(0x2); 1144 val |= RTERM_SELECT(0x6); 1145 val |= TAP3_DISABLE; 1146 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1147 1148 /* Program PORT_TX_DW2 */ 1149 for (ln = 0; ln < 4; ln++) { 1150 int level = intel_ddi_level(encoder, crtc_state, ln); 1151 1152 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1153 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1154 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1155 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1156 RCOMP_SCALAR(0x98)); 1157 } 1158 1159 /* Program PORT_TX_DW4 */ 1160 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1161 for (ln = 0; ln < 4; ln++) { 1162 int level = intel_ddi_level(encoder, crtc_state, ln); 1163 1164 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1165 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1166 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1167 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1168 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1169 } 1170 1171 /* Program PORT_TX_DW7 */ 1172 for (ln = 0; ln < 4; ln++) { 1173 int level = intel_ddi_level(encoder, crtc_state, ln); 1174 1175 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1176 N_SCALAR_MASK, 1177 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1178 } 1179 } 1180 1181 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1182 const struct intel_crtc_state *crtc_state) 1183 { 1184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1185 enum phy phy = intel_encoder_to_phy(encoder); 1186 u32 val; 1187 int ln; 1188 1189 /* 1190 * 1. If port type is eDP or DP, 1191 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1192 * else clear to 0b. 1193 */ 1194 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1195 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1196 val &= ~COMMON_KEEPER_EN; 1197 else 1198 val |= COMMON_KEEPER_EN; 1199 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1200 1201 /* 2. Program loadgen select */ 1202 /* 1203 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1204 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1205 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1206 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1207 */ 1208 for (ln = 0; ln < 4; ln++) { 1209 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1210 LOADGEN_SELECT, 1211 icl_combo_phy_loadgen_select(crtc_state, ln)); 1212 } 1213 1214 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1215 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1216 0, SUS_CLOCK_CONFIG); 1217 1218 /* 4. Clear training enable to change swing values */ 1219 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1220 val &= ~TX_TRAINING_EN; 1221 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1222 1223 /* 5. Program swing and de-emphasis */ 1224 icl_ddi_combo_vswing_program(encoder, crtc_state); 1225 1226 /* 6. Set training enable to trigger update */ 1227 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1228 val |= TX_TRAINING_EN; 1229 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1230 } 1231 1232 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1233 const struct intel_crtc_state *crtc_state) 1234 { 1235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1236 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1237 const struct intel_ddi_buf_trans *trans; 1238 int n_entries, ln; 1239 1240 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1241 return; 1242 1243 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1244 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1245 return; 1246 1247 for (ln = 0; ln < 2; ln++) { 1248 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1249 CRI_USE_FS32, 0); 1250 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1251 CRI_USE_FS32, 0); 1252 } 1253 1254 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1255 for (ln = 0; ln < 2; ln++) { 1256 int level; 1257 1258 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1259 1260 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1261 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1262 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1263 1264 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1265 1266 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1267 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1268 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1269 } 1270 1271 /* Program MG_TX_DRVCTRL with values from vswing table */ 1272 for (ln = 0; ln < 2; ln++) { 1273 int level; 1274 1275 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1276 1277 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1278 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1279 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1280 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1281 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1282 CRI_TXDEEMPH_OVERRIDE_EN); 1283 1284 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1285 1286 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1287 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1288 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1289 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1290 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1291 CRI_TXDEEMPH_OVERRIDE_EN); 1292 1293 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1294 } 1295 1296 /* 1297 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1298 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1299 * values from table for which TX1 and TX2 enabled. 1300 */ 1301 for (ln = 0; ln < 2; ln++) { 1302 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1303 CFG_LOW_RATE_LKREN_EN, 1304 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1305 } 1306 1307 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1308 for (ln = 0; ln < 2; ln++) { 1309 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1310 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1311 CFG_AMI_CK_DIV_OVERRIDE_EN, 1312 crtc_state->port_clock > 500000 ? 1313 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1314 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1315 1316 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1317 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1318 CFG_AMI_CK_DIV_OVERRIDE_EN, 1319 crtc_state->port_clock > 500000 ? 1320 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1321 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1322 } 1323 1324 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1325 for (ln = 0; ln < 2; ln++) { 1326 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1327 0, CRI_CALCINIT); 1328 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1329 0, CRI_CALCINIT); 1330 } 1331 } 1332 1333 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1334 const struct intel_crtc_state *crtc_state) 1335 { 1336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1337 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1338 const struct intel_ddi_buf_trans *trans; 1339 int n_entries, ln; 1340 1341 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1342 return; 1343 1344 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1345 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1346 return; 1347 1348 for (ln = 0; ln < 2; ln++) { 1349 int level; 1350 1351 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1352 1353 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1354 1355 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1356 DKL_TX_PRESHOOT_COEFF_MASK | 1357 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1358 DKL_TX_VSWING_CONTROL_MASK, 1359 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1360 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1361 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1362 1363 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1364 1365 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1366 DKL_TX_PRESHOOT_COEFF_MASK | 1367 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1368 DKL_TX_VSWING_CONTROL_MASK, 1369 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1370 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1371 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1372 1373 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1374 DKL_TX_DP20BITMODE, 0); 1375 1376 if (IS_ALDERLAKE_P(dev_priv)) { 1377 u32 val; 1378 1379 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1380 if (ln == 0) { 1381 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1382 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1383 } else { 1384 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1385 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1386 } 1387 } else { 1388 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1389 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1390 } 1391 1392 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1393 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1394 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1395 val); 1396 } 1397 } 1398 } 1399 1400 static int translate_signal_level(struct intel_dp *intel_dp, 1401 u8 signal_levels) 1402 { 1403 struct intel_display *display = to_intel_display(intel_dp); 1404 int i; 1405 1406 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1407 if (index_to_dp_signal_levels[i] == signal_levels) 1408 return i; 1409 } 1410 1411 drm_WARN(display->drm, 1, 1412 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1413 signal_levels); 1414 1415 return 0; 1416 } 1417 1418 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1419 const struct intel_crtc_state *crtc_state, 1420 int lane) 1421 { 1422 u8 train_set = intel_dp->train_set[lane]; 1423 1424 if (intel_dp_is_uhbr(crtc_state)) { 1425 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1426 } else { 1427 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1428 DP_TRAIN_PRE_EMPHASIS_MASK); 1429 1430 return translate_signal_level(intel_dp, signal_levels); 1431 } 1432 } 1433 1434 int intel_ddi_level(struct intel_encoder *encoder, 1435 const struct intel_crtc_state *crtc_state, 1436 int lane) 1437 { 1438 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1439 const struct intel_ddi_buf_trans *trans; 1440 int level, n_entries; 1441 1442 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1443 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1444 return 0; 1445 1446 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1447 level = intel_ddi_hdmi_level(encoder, trans); 1448 else 1449 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1450 lane); 1451 1452 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1453 level = n_entries - 1; 1454 1455 return level; 1456 } 1457 1458 static void 1459 hsw_set_signal_levels(struct intel_encoder *encoder, 1460 const struct intel_crtc_state *crtc_state) 1461 { 1462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1463 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1464 int level = intel_ddi_level(encoder, crtc_state, 0); 1465 enum port port = encoder->port; 1466 u32 signal_levels; 1467 1468 if (has_iboost(dev_priv)) 1469 skl_ddi_set_iboost(encoder, crtc_state, level); 1470 1471 /* HDMI ignores the rest */ 1472 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1473 return; 1474 1475 signal_levels = DDI_BUF_TRANS_SELECT(level); 1476 1477 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1478 signal_levels); 1479 1480 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1481 intel_dp->DP |= signal_levels; 1482 1483 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1484 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1485 } 1486 1487 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1488 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1489 { 1490 mutex_lock(&i915->display.dpll.lock); 1491 1492 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1493 1494 /* 1495 * "This step and the step before must be 1496 * done with separate register writes." 1497 */ 1498 intel_de_rmw(i915, reg, clk_off, 0); 1499 1500 mutex_unlock(&i915->display.dpll.lock); 1501 } 1502 1503 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1504 u32 clk_off) 1505 { 1506 mutex_lock(&i915->display.dpll.lock); 1507 1508 intel_de_rmw(i915, reg, 0, clk_off); 1509 1510 mutex_unlock(&i915->display.dpll.lock); 1511 } 1512 1513 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1514 u32 clk_off) 1515 { 1516 return !(intel_de_read(i915, reg) & clk_off); 1517 } 1518 1519 static struct intel_shared_dpll * 1520 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1521 u32 clk_sel_mask, u32 clk_sel_shift) 1522 { 1523 enum intel_dpll_id id; 1524 1525 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1526 1527 return intel_get_shared_dpll_by_id(i915, id); 1528 } 1529 1530 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1531 const struct intel_crtc_state *crtc_state) 1532 { 1533 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1534 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1535 enum phy phy = intel_encoder_to_phy(encoder); 1536 1537 if (drm_WARN_ON(&i915->drm, !pll)) 1538 return; 1539 1540 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1541 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1542 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1543 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1544 } 1545 1546 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1547 { 1548 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1549 enum phy phy = intel_encoder_to_phy(encoder); 1550 1551 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1552 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1553 } 1554 1555 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1556 { 1557 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1558 enum phy phy = intel_encoder_to_phy(encoder); 1559 1560 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1561 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1562 } 1563 1564 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1565 { 1566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1567 enum phy phy = intel_encoder_to_phy(encoder); 1568 1569 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1570 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1571 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1572 } 1573 1574 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1575 const struct intel_crtc_state *crtc_state) 1576 { 1577 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1578 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1579 enum phy phy = intel_encoder_to_phy(encoder); 1580 1581 if (drm_WARN_ON(&i915->drm, !pll)) 1582 return; 1583 1584 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1585 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1586 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1587 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1588 } 1589 1590 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1591 { 1592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1593 enum phy phy = intel_encoder_to_phy(encoder); 1594 1595 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1596 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1597 } 1598 1599 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1600 { 1601 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1602 enum phy phy = intel_encoder_to_phy(encoder); 1603 1604 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1605 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1606 } 1607 1608 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1609 { 1610 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1611 enum phy phy = intel_encoder_to_phy(encoder); 1612 1613 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1614 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1615 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1616 } 1617 1618 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1619 const struct intel_crtc_state *crtc_state) 1620 { 1621 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1622 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1623 enum phy phy = intel_encoder_to_phy(encoder); 1624 1625 if (drm_WARN_ON(&i915->drm, !pll)) 1626 return; 1627 1628 /* 1629 * If we fail this, something went very wrong: first 2 PLLs should be 1630 * used by first 2 phys and last 2 PLLs by last phys 1631 */ 1632 if (drm_WARN_ON(&i915->drm, 1633 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1634 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1635 return; 1636 1637 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1638 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1639 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1640 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1641 } 1642 1643 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1644 { 1645 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1646 enum phy phy = intel_encoder_to_phy(encoder); 1647 1648 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1649 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1650 } 1651 1652 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1653 { 1654 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1655 enum phy phy = intel_encoder_to_phy(encoder); 1656 1657 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1658 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1659 } 1660 1661 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1662 { 1663 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1664 enum phy phy = intel_encoder_to_phy(encoder); 1665 enum intel_dpll_id id; 1666 u32 val; 1667 1668 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1669 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1670 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1671 id = val; 1672 1673 /* 1674 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1675 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1676 * bit for phy C and D. 1677 */ 1678 if (phy >= PHY_C) 1679 id += DPLL_ID_DG1_DPLL2; 1680 1681 return intel_get_shared_dpll_by_id(i915, id); 1682 } 1683 1684 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1685 const struct intel_crtc_state *crtc_state) 1686 { 1687 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1688 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1689 enum phy phy = intel_encoder_to_phy(encoder); 1690 1691 if (drm_WARN_ON(&i915->drm, !pll)) 1692 return; 1693 1694 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1695 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1696 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1697 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1698 } 1699 1700 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1701 { 1702 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1703 enum phy phy = intel_encoder_to_phy(encoder); 1704 1705 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1706 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1707 } 1708 1709 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1710 { 1711 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1712 enum phy phy = intel_encoder_to_phy(encoder); 1713 1714 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1715 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1716 } 1717 1718 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1719 { 1720 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1721 enum phy phy = intel_encoder_to_phy(encoder); 1722 1723 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1724 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1725 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1726 } 1727 1728 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1729 const struct intel_crtc_state *crtc_state) 1730 { 1731 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1732 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1733 enum port port = encoder->port; 1734 1735 if (drm_WARN_ON(&i915->drm, !pll)) 1736 return; 1737 1738 /* 1739 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1740 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1741 */ 1742 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1743 1744 icl_ddi_combo_enable_clock(encoder, crtc_state); 1745 } 1746 1747 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1748 { 1749 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1750 enum port port = encoder->port; 1751 1752 icl_ddi_combo_disable_clock(encoder); 1753 1754 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1755 } 1756 1757 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1758 { 1759 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1760 enum port port = encoder->port; 1761 u32 tmp; 1762 1763 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1764 1765 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1766 return false; 1767 1768 return icl_ddi_combo_is_clock_enabled(encoder); 1769 } 1770 1771 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1772 const struct intel_crtc_state *crtc_state) 1773 { 1774 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1775 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1776 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1777 enum port port = encoder->port; 1778 1779 if (drm_WARN_ON(&i915->drm, !pll)) 1780 return; 1781 1782 intel_de_write(i915, DDI_CLK_SEL(port), 1783 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1784 1785 mutex_lock(&i915->display.dpll.lock); 1786 1787 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1788 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1789 1790 mutex_unlock(&i915->display.dpll.lock); 1791 } 1792 1793 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1794 { 1795 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1796 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1797 enum port port = encoder->port; 1798 1799 mutex_lock(&i915->display.dpll.lock); 1800 1801 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1802 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1803 1804 mutex_unlock(&i915->display.dpll.lock); 1805 1806 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1807 } 1808 1809 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1810 { 1811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1812 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1813 enum port port = encoder->port; 1814 u32 tmp; 1815 1816 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1817 1818 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1819 return false; 1820 1821 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1822 1823 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1824 } 1825 1826 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1827 { 1828 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1829 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1830 enum port port = encoder->port; 1831 enum intel_dpll_id id; 1832 u32 tmp; 1833 1834 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1835 1836 switch (tmp & DDI_CLK_SEL_MASK) { 1837 case DDI_CLK_SEL_TBT_162: 1838 case DDI_CLK_SEL_TBT_270: 1839 case DDI_CLK_SEL_TBT_540: 1840 case DDI_CLK_SEL_TBT_810: 1841 id = DPLL_ID_ICL_TBTPLL; 1842 break; 1843 case DDI_CLK_SEL_MG: 1844 id = icl_tc_port_to_pll_id(tc_port); 1845 break; 1846 default: 1847 MISSING_CASE(tmp); 1848 fallthrough; 1849 case DDI_CLK_SEL_NONE: 1850 return NULL; 1851 } 1852 1853 return intel_get_shared_dpll_by_id(i915, id); 1854 } 1855 1856 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1857 { 1858 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1859 enum intel_dpll_id id; 1860 1861 switch (encoder->port) { 1862 case PORT_A: 1863 id = DPLL_ID_SKL_DPLL0; 1864 break; 1865 case PORT_B: 1866 id = DPLL_ID_SKL_DPLL1; 1867 break; 1868 case PORT_C: 1869 id = DPLL_ID_SKL_DPLL2; 1870 break; 1871 default: 1872 MISSING_CASE(encoder->port); 1873 return NULL; 1874 } 1875 1876 return intel_get_shared_dpll_by_id(i915, id); 1877 } 1878 1879 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1880 const struct intel_crtc_state *crtc_state) 1881 { 1882 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1883 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1884 enum port port = encoder->port; 1885 1886 if (drm_WARN_ON(&i915->drm, !pll)) 1887 return; 1888 1889 mutex_lock(&i915->display.dpll.lock); 1890 1891 intel_de_rmw(i915, DPLL_CTRL2, 1892 DPLL_CTRL2_DDI_CLK_OFF(port) | 1893 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1894 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1895 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1896 1897 mutex_unlock(&i915->display.dpll.lock); 1898 } 1899 1900 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1901 { 1902 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1903 enum port port = encoder->port; 1904 1905 mutex_lock(&i915->display.dpll.lock); 1906 1907 intel_de_rmw(i915, DPLL_CTRL2, 1908 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1909 1910 mutex_unlock(&i915->display.dpll.lock); 1911 } 1912 1913 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1914 { 1915 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1916 enum port port = encoder->port; 1917 1918 /* 1919 * FIXME Not sure if the override affects both 1920 * the PLL selection and the CLK_OFF bit. 1921 */ 1922 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1923 } 1924 1925 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1926 { 1927 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1928 enum port port = encoder->port; 1929 enum intel_dpll_id id; 1930 u32 tmp; 1931 1932 tmp = intel_de_read(i915, DPLL_CTRL2); 1933 1934 /* 1935 * FIXME Not sure if the override affects both 1936 * the PLL selection and the CLK_OFF bit. 1937 */ 1938 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1939 return NULL; 1940 1941 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1942 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1943 1944 return intel_get_shared_dpll_by_id(i915, id); 1945 } 1946 1947 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1948 const struct intel_crtc_state *crtc_state) 1949 { 1950 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1951 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1952 enum port port = encoder->port; 1953 1954 if (drm_WARN_ON(&i915->drm, !pll)) 1955 return; 1956 1957 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1958 } 1959 1960 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1961 { 1962 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1963 enum port port = encoder->port; 1964 1965 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1966 } 1967 1968 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1969 { 1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1971 enum port port = encoder->port; 1972 1973 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1974 } 1975 1976 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1977 { 1978 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1979 enum port port = encoder->port; 1980 enum intel_dpll_id id; 1981 u32 tmp; 1982 1983 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1984 1985 switch (tmp & PORT_CLK_SEL_MASK) { 1986 case PORT_CLK_SEL_WRPLL1: 1987 id = DPLL_ID_WRPLL1; 1988 break; 1989 case PORT_CLK_SEL_WRPLL2: 1990 id = DPLL_ID_WRPLL2; 1991 break; 1992 case PORT_CLK_SEL_SPLL: 1993 id = DPLL_ID_SPLL; 1994 break; 1995 case PORT_CLK_SEL_LCPLL_810: 1996 id = DPLL_ID_LCPLL_810; 1997 break; 1998 case PORT_CLK_SEL_LCPLL_1350: 1999 id = DPLL_ID_LCPLL_1350; 2000 break; 2001 case PORT_CLK_SEL_LCPLL_2700: 2002 id = DPLL_ID_LCPLL_2700; 2003 break; 2004 default: 2005 MISSING_CASE(tmp); 2006 fallthrough; 2007 case PORT_CLK_SEL_NONE: 2008 return NULL; 2009 } 2010 2011 return intel_get_shared_dpll_by_id(i915, id); 2012 } 2013 2014 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2015 const struct intel_crtc_state *crtc_state) 2016 { 2017 if (encoder->enable_clock) 2018 encoder->enable_clock(encoder, crtc_state); 2019 } 2020 2021 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2022 { 2023 if (encoder->disable_clock) 2024 encoder->disable_clock(encoder); 2025 } 2026 2027 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2028 { 2029 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2030 u32 port_mask; 2031 bool ddi_clk_needed; 2032 2033 /* 2034 * In case of DP MST, we sanitize the primary encoder only, not the 2035 * virtual ones. 2036 */ 2037 if (encoder->type == INTEL_OUTPUT_DP_MST) 2038 return; 2039 2040 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2041 u8 pipe_mask; 2042 bool is_mst; 2043 2044 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2045 /* 2046 * In the unlikely case that BIOS enables DP in MST mode, just 2047 * warn since our MST HW readout is incomplete. 2048 */ 2049 if (drm_WARN_ON(&i915->drm, is_mst)) 2050 return; 2051 } 2052 2053 port_mask = BIT(encoder->port); 2054 ddi_clk_needed = encoder->base.crtc; 2055 2056 if (encoder->type == INTEL_OUTPUT_DSI) { 2057 struct intel_encoder *other_encoder; 2058 2059 port_mask = intel_dsi_encoder_ports(encoder); 2060 /* 2061 * Sanity check that we haven't incorrectly registered another 2062 * encoder using any of the ports of this DSI encoder. 2063 */ 2064 for_each_intel_encoder(&i915->drm, other_encoder) { 2065 if (other_encoder == encoder) 2066 continue; 2067 2068 if (drm_WARN_ON(&i915->drm, 2069 port_mask & BIT(other_encoder->port))) 2070 return; 2071 } 2072 /* 2073 * For DSI we keep the ddi clocks gated 2074 * except during enable/disable sequence. 2075 */ 2076 ddi_clk_needed = false; 2077 } 2078 2079 if (ddi_clk_needed || !encoder->is_clock_enabled || 2080 !encoder->is_clock_enabled(encoder)) 2081 return; 2082 2083 drm_dbg_kms(&i915->drm, 2084 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2085 encoder->base.base.id, encoder->base.name); 2086 2087 encoder->disable_clock(encoder); 2088 } 2089 2090 static void 2091 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2092 const struct intel_crtc_state *crtc_state) 2093 { 2094 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2095 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2096 u32 ln0, ln1, pin_assignment; 2097 u8 width; 2098 2099 if (DISPLAY_VER(dev_priv) >= 14) 2100 return; 2101 2102 if (!intel_encoder_is_tc(&dig_port->base) || 2103 intel_tc_port_in_tbt_alt_mode(dig_port)) 2104 return; 2105 2106 if (DISPLAY_VER(dev_priv) >= 12) { 2107 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2108 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2109 } else { 2110 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2111 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2112 } 2113 2114 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2115 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2116 2117 /* DPPATC */ 2118 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2119 width = crtc_state->lane_count; 2120 2121 switch (pin_assignment) { 2122 case 0x0: 2123 drm_WARN_ON(&dev_priv->drm, 2124 !intel_tc_port_in_legacy_mode(dig_port)); 2125 if (width == 1) { 2126 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2127 } else { 2128 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2129 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2130 } 2131 break; 2132 case 0x1: 2133 if (width == 4) { 2134 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2135 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2136 } 2137 break; 2138 case 0x2: 2139 if (width == 2) { 2140 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2141 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2142 } 2143 break; 2144 case 0x3: 2145 case 0x5: 2146 if (width == 1) { 2147 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2148 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2149 } else { 2150 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2151 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2152 } 2153 break; 2154 case 0x4: 2155 case 0x6: 2156 if (width == 1) { 2157 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2158 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2159 } else { 2160 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2161 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2162 } 2163 break; 2164 default: 2165 MISSING_CASE(pin_assignment); 2166 } 2167 2168 if (DISPLAY_VER(dev_priv) >= 12) { 2169 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2170 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2171 } else { 2172 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2173 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2174 } 2175 } 2176 2177 static enum transcoder 2178 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2179 { 2180 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2181 return crtc_state->mst_master_transcoder; 2182 else 2183 return crtc_state->cpu_transcoder; 2184 } 2185 2186 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2187 const struct intel_crtc_state *crtc_state) 2188 { 2189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2190 2191 if (DISPLAY_VER(dev_priv) >= 12) 2192 return TGL_DP_TP_CTL(dev_priv, 2193 tgl_dp_tp_transcoder(crtc_state)); 2194 else 2195 return DP_TP_CTL(encoder->port); 2196 } 2197 2198 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2199 const struct intel_crtc_state *crtc_state) 2200 { 2201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2202 2203 if (DISPLAY_VER(dev_priv) >= 12) 2204 return TGL_DP_TP_STATUS(dev_priv, 2205 tgl_dp_tp_transcoder(crtc_state)); 2206 else 2207 return DP_TP_STATUS(encoder->port); 2208 } 2209 2210 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2211 const struct intel_crtc_state *crtc_state, 2212 bool enable) 2213 { 2214 struct intel_display *display = to_intel_display(intel_dp); 2215 2216 if (!crtc_state->vrr.enable) 2217 return; 2218 2219 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2220 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2221 drm_dbg_kms(display->drm, 2222 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2223 str_enable_disable(enable)); 2224 } 2225 2226 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2227 const struct intel_crtc_state *crtc_state, 2228 bool enable) 2229 { 2230 struct intel_display *display = to_intel_display(intel_dp); 2231 2232 if (!crtc_state->fec_enable) 2233 return; 2234 2235 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2236 enable ? DP_FEC_READY : 0) <= 0) 2237 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2238 enable ? "enabled" : "disabled"); 2239 2240 if (enable && 2241 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2242 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2243 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2244 } 2245 2246 static int read_fec_detected_status(struct drm_dp_aux *aux) 2247 { 2248 int ret; 2249 u8 status; 2250 2251 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2252 if (ret < 0) 2253 return ret; 2254 2255 return status; 2256 } 2257 2258 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2259 { 2260 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2261 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2262 int status; 2263 int err; 2264 2265 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2266 status & mask || status < 0, 2267 10000, 200000); 2268 2269 if (!err && status >= 0) 2270 return; 2271 2272 if (err == -ETIMEDOUT) 2273 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2274 str_enabled_disabled(enabled)); 2275 else 2276 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2277 } 2278 2279 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2280 const struct intel_crtc_state *crtc_state, 2281 bool enabled) 2282 { 2283 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2284 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2285 int ret; 2286 2287 if (!crtc_state->fec_enable) 2288 return; 2289 2290 if (enabled) 2291 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2292 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2293 else 2294 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2295 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2296 2297 if (ret) 2298 drm_err(&i915->drm, 2299 "Timeout waiting for FEC live state to get %s\n", 2300 str_enabled_disabled(enabled)); 2301 2302 /* 2303 * At least the Synoptics MST hub doesn't set the detected flag for 2304 * FEC decoding disabling so skip waiting for that. 2305 */ 2306 if (enabled) 2307 wait_for_fec_detected(&intel_dp->aux, enabled); 2308 } 2309 2310 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2311 const struct intel_crtc_state *crtc_state) 2312 { 2313 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2314 2315 if (!crtc_state->fec_enable) 2316 return; 2317 2318 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2319 0, DP_TP_CTL_FEC_ENABLE); 2320 } 2321 2322 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2323 const struct intel_crtc_state *crtc_state) 2324 { 2325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2326 2327 if (!crtc_state->fec_enable) 2328 return; 2329 2330 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2331 DP_TP_CTL_FEC_ENABLE, 0); 2332 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2333 } 2334 2335 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2336 const struct intel_crtc_state *crtc_state) 2337 { 2338 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2339 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2340 2341 if (intel_encoder_is_combo(encoder)) { 2342 enum phy phy = intel_encoder_to_phy(encoder); 2343 bool lane_reversal = 2344 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2345 2346 intel_combo_phy_power_up_lanes(i915, phy, false, 2347 crtc_state->lane_count, 2348 lane_reversal); 2349 } 2350 } 2351 2352 /* 2353 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2354 * platforms. 2355 */ 2356 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2357 { 2358 if (DISPLAY_VER(i915) > 20) 2359 return ~0; 2360 else if (IS_ALDERLAKE_P(i915)) 2361 return BIT(PIPE_A) | BIT(PIPE_B); 2362 else 2363 return BIT(PIPE_A); 2364 } 2365 2366 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2367 struct intel_crtc_state *pipe_config) 2368 { 2369 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2370 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2371 enum pipe pipe = crtc->pipe; 2372 u32 dss1; 2373 2374 if (!HAS_MSO(i915)) 2375 return; 2376 2377 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2378 2379 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2380 if (!pipe_config->splitter.enable) 2381 return; 2382 2383 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2384 pipe_config->splitter.enable = false; 2385 return; 2386 } 2387 2388 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2389 default: 2390 drm_WARN(&i915->drm, true, 2391 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2392 fallthrough; 2393 case SPLITTER_CONFIGURATION_2_SEGMENT: 2394 pipe_config->splitter.link_count = 2; 2395 break; 2396 case SPLITTER_CONFIGURATION_4_SEGMENT: 2397 pipe_config->splitter.link_count = 4; 2398 break; 2399 } 2400 2401 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2402 } 2403 2404 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2405 { 2406 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2407 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2408 enum pipe pipe = crtc->pipe; 2409 u32 dss1 = 0; 2410 2411 if (!HAS_MSO(i915)) 2412 return; 2413 2414 if (crtc_state->splitter.enable) { 2415 dss1 |= SPLITTER_ENABLE; 2416 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2417 if (crtc_state->splitter.link_count == 2) 2418 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2419 else 2420 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2421 } 2422 2423 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2424 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2425 OVERLAP_PIXELS_MASK, dss1); 2426 } 2427 2428 static u8 mtl_get_port_width(u8 lane_count) 2429 { 2430 switch (lane_count) { 2431 case 1: 2432 return 0; 2433 case 2: 2434 return 1; 2435 case 3: 2436 return 4; 2437 case 4: 2438 return 3; 2439 default: 2440 MISSING_CASE(lane_count); 2441 return 4; 2442 } 2443 } 2444 2445 static void 2446 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2447 { 2448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2449 enum port port = encoder->port; 2450 i915_reg_t reg; 2451 u32 set_bits, wait_bits; 2452 2453 if (DISPLAY_VER(dev_priv) >= 20) { 2454 reg = DDI_BUF_CTL(port); 2455 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2456 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2457 } else { 2458 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2459 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2460 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2461 } 2462 2463 intel_de_rmw(dev_priv, reg, 0, set_bits); 2464 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2465 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2466 port_name(port)); 2467 } 2468 } 2469 2470 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2471 const struct intel_crtc_state *crtc_state) 2472 { 2473 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2474 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2475 enum port port = encoder->port; 2476 u32 val; 2477 2478 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2479 val &= ~XELPDP_PORT_WIDTH_MASK; 2480 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2481 2482 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2483 if (intel_dp_is_uhbr(crtc_state)) 2484 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2485 else 2486 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2487 2488 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2489 val |= XELPDP_PORT_REVERSAL; 2490 2491 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2492 } 2493 2494 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2495 { 2496 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2497 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2498 u32 val; 2499 2500 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2501 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2502 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2503 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2504 } 2505 2506 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2507 struct intel_encoder *encoder, 2508 const struct intel_crtc_state *crtc_state, 2509 const struct drm_connector_state *conn_state) 2510 { 2511 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2512 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2513 2514 intel_dp_set_link_params(intel_dp, 2515 crtc_state->port_clock, 2516 crtc_state->lane_count); 2517 2518 /* 2519 * We only configure what the register value will be here. Actual 2520 * enabling happens during link training farther down. 2521 */ 2522 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2523 2524 /* 2525 * 1. Enable Power Wells 2526 * 2527 * This was handled at the beginning of intel_atomic_commit_tail(), 2528 * before we called down into this function. 2529 */ 2530 2531 /* 2. PMdemand was already set */ 2532 2533 /* 3. Select Thunderbolt */ 2534 mtl_port_buf_ctl_io_selection(encoder); 2535 2536 /* 4. Enable Panel Power if PPS is required */ 2537 intel_pps_on(intel_dp); 2538 2539 /* 5. Enable the port PLL */ 2540 intel_ddi_enable_clock(encoder, crtc_state); 2541 2542 /* 2543 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2544 * Transcoder. 2545 */ 2546 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2547 2548 /* 2549 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2550 */ 2551 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2552 2553 /* 2554 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2555 * Transport Select 2556 */ 2557 intel_ddi_config_transcoder_func(encoder, crtc_state); 2558 2559 /* 2560 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2561 */ 2562 intel_ddi_mso_configure(crtc_state); 2563 2564 if (!is_mst) 2565 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2566 2567 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2568 if (!is_mst) 2569 intel_dp_sink_enable_decompression(state, 2570 to_intel_connector(conn_state->connector), 2571 crtc_state); 2572 2573 /* 2574 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2575 * in the FEC_CONFIGURATION register to 1 before initiating link 2576 * training 2577 */ 2578 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2579 2580 intel_dp_check_frl_training(intel_dp); 2581 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2582 2583 /* 2584 * 6. The rest of the below are substeps under the bspec's "Enable and 2585 * Train Display Port" step. Note that steps that are specific to 2586 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2587 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2588 * us when active_mst_links==0, so any steps designated for "single 2589 * stream or multi-stream master transcoder" can just be performed 2590 * unconditionally here. 2591 * 2592 * mtl_ddi_prepare_link_retrain() that is called by 2593 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2594 * 6.i and 6.j 2595 * 2596 * 6.k Follow DisplayPort specification training sequence (see notes for 2597 * failure handling) 2598 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2599 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2600 * (timeout after 800 us) 2601 */ 2602 intel_dp_start_link_train(state, intel_dp, crtc_state); 2603 2604 /* 6.n Set DP_TP_CTL link training to Normal */ 2605 if (!is_trans_port_sync_mode(crtc_state)) 2606 intel_dp_stop_link_train(intel_dp, crtc_state); 2607 2608 /* 6.o Configure and enable FEC if needed */ 2609 intel_ddi_enable_fec(encoder, crtc_state); 2610 2611 if (!is_mst) 2612 intel_dsc_dp_pps_write(encoder, crtc_state); 2613 } 2614 2615 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2616 struct intel_encoder *encoder, 2617 const struct intel_crtc_state *crtc_state, 2618 const struct drm_connector_state *conn_state) 2619 { 2620 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2621 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2622 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2623 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2624 2625 intel_dp_set_link_params(intel_dp, 2626 crtc_state->port_clock, 2627 crtc_state->lane_count); 2628 2629 /* 2630 * We only configure what the register value will be here. Actual 2631 * enabling happens during link training farther down. 2632 */ 2633 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2634 2635 /* 2636 * 1. Enable Power Wells 2637 * 2638 * This was handled at the beginning of intel_atomic_commit_tail(), 2639 * before we called down into this function. 2640 */ 2641 2642 /* 2. Enable Panel Power if PPS is required */ 2643 intel_pps_on(intel_dp); 2644 2645 /* 2646 * 3. For non-TBT Type-C ports, set FIA lane count 2647 * (DFLEXDPSP.DPX4TXLATC) 2648 * 2649 * This was done before tgl_ddi_pre_enable_dp by 2650 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2651 */ 2652 2653 /* 2654 * 4. Enable the port PLL. 2655 * 2656 * The PLL enabling itself was already done before this function by 2657 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2658 * configure the PLL to port mapping here. 2659 */ 2660 intel_ddi_enable_clock(encoder, crtc_state); 2661 2662 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2663 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2664 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2665 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2666 dig_port->ddi_io_power_domain); 2667 } 2668 2669 /* 6. Program DP_MODE */ 2670 icl_program_mg_dp_mode(dig_port, crtc_state); 2671 2672 /* 2673 * 7. The rest of the below are substeps under the bspec's "Enable and 2674 * Train Display Port" step. Note that steps that are specific to 2675 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2676 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2677 * us when active_mst_links==0, so any steps designated for "single 2678 * stream or multi-stream master transcoder" can just be performed 2679 * unconditionally here. 2680 */ 2681 2682 /* 2683 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2684 * Transcoder. 2685 */ 2686 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2687 2688 if (HAS_DP20(dev_priv)) 2689 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2690 2691 /* 2692 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2693 * Transport Select 2694 */ 2695 intel_ddi_config_transcoder_func(encoder, crtc_state); 2696 2697 /* 2698 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2699 * selected 2700 * 2701 * This will be handled by the intel_dp_start_link_train() farther 2702 * down this function. 2703 */ 2704 2705 /* 7.e Configure voltage swing and related IO settings */ 2706 encoder->set_signal_levels(encoder, crtc_state); 2707 2708 /* 2709 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2710 * the used lanes of the DDI. 2711 */ 2712 intel_ddi_power_up_lanes(encoder, crtc_state); 2713 2714 /* 2715 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2716 */ 2717 intel_ddi_mso_configure(crtc_state); 2718 2719 if (!is_mst) 2720 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2721 2722 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2723 if (!is_mst) 2724 intel_dp_sink_enable_decompression(state, 2725 to_intel_connector(conn_state->connector), 2726 crtc_state); 2727 /* 2728 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2729 * in the FEC_CONFIGURATION register to 1 before initiating link 2730 * training 2731 */ 2732 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2733 2734 intel_dp_check_frl_training(intel_dp); 2735 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2736 2737 /* 2738 * 7.i Follow DisplayPort specification training sequence (see notes for 2739 * failure handling) 2740 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2741 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2742 * (timeout after 800 us) 2743 */ 2744 intel_dp_start_link_train(state, intel_dp, crtc_state); 2745 2746 /* 7.k Set DP_TP_CTL link training to Normal */ 2747 if (!is_trans_port_sync_mode(crtc_state)) 2748 intel_dp_stop_link_train(intel_dp, crtc_state); 2749 2750 /* 7.l Configure and enable FEC if needed */ 2751 intel_ddi_enable_fec(encoder, crtc_state); 2752 2753 if (!is_mst) 2754 intel_dsc_dp_pps_write(encoder, crtc_state); 2755 } 2756 2757 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2758 struct intel_encoder *encoder, 2759 const struct intel_crtc_state *crtc_state, 2760 const struct drm_connector_state *conn_state) 2761 { 2762 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2763 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2764 enum port port = encoder->port; 2765 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2766 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2767 2768 if (DISPLAY_VER(dev_priv) < 11) 2769 drm_WARN_ON(&dev_priv->drm, 2770 is_mst && (port == PORT_A || port == PORT_E)); 2771 else 2772 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2773 2774 intel_dp_set_link_params(intel_dp, 2775 crtc_state->port_clock, 2776 crtc_state->lane_count); 2777 2778 /* 2779 * We only configure what the register value will be here. Actual 2780 * enabling happens during link training farther down. 2781 */ 2782 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2783 2784 intel_pps_on(intel_dp); 2785 2786 intel_ddi_enable_clock(encoder, crtc_state); 2787 2788 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2789 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2790 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2791 dig_port->ddi_io_power_domain); 2792 } 2793 2794 icl_program_mg_dp_mode(dig_port, crtc_state); 2795 2796 if (has_buf_trans_select(dev_priv)) 2797 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2798 2799 encoder->set_signal_levels(encoder, crtc_state); 2800 2801 intel_ddi_power_up_lanes(encoder, crtc_state); 2802 2803 if (!is_mst) 2804 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2805 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2806 if (!is_mst) 2807 intel_dp_sink_enable_decompression(state, 2808 to_intel_connector(conn_state->connector), 2809 crtc_state); 2810 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2811 intel_dp_start_link_train(state, intel_dp, crtc_state); 2812 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2813 !is_trans_port_sync_mode(crtc_state)) 2814 intel_dp_stop_link_train(intel_dp, crtc_state); 2815 2816 intel_ddi_enable_fec(encoder, crtc_state); 2817 2818 if (!is_mst) { 2819 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2820 intel_dsc_dp_pps_write(encoder, crtc_state); 2821 } 2822 } 2823 2824 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2825 struct intel_encoder *encoder, 2826 const struct intel_crtc_state *crtc_state, 2827 const struct drm_connector_state *conn_state) 2828 { 2829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2830 2831 if (HAS_DP20(dev_priv)) 2832 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2833 crtc_state); 2834 2835 /* Panel replay has to be enabled in sink dpcd before link training. */ 2836 if (crtc_state->has_panel_replay) 2837 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2838 2839 if (DISPLAY_VER(dev_priv) >= 14) 2840 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2841 else if (DISPLAY_VER(dev_priv) >= 12) 2842 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2843 else 2844 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2845 2846 /* MST will call a setting of MSA after an allocating of Virtual Channel 2847 * from MST encoder pre_enable callback. 2848 */ 2849 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2850 intel_ddi_set_dp_msa(crtc_state, conn_state); 2851 } 2852 2853 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2854 struct intel_encoder *encoder, 2855 const struct intel_crtc_state *crtc_state, 2856 const struct drm_connector_state *conn_state) 2857 { 2858 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2859 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2861 2862 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2863 intel_ddi_enable_clock(encoder, crtc_state); 2864 2865 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2866 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2867 dig_port->ddi_io_power_domain); 2868 2869 icl_program_mg_dp_mode(dig_port, crtc_state); 2870 2871 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2872 2873 dig_port->set_infoframes(encoder, 2874 crtc_state->has_infoframe, 2875 crtc_state, conn_state); 2876 } 2877 2878 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2879 struct intel_encoder *encoder, 2880 const struct intel_crtc_state *crtc_state, 2881 const struct drm_connector_state *conn_state) 2882 { 2883 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2884 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2885 enum pipe pipe = crtc->pipe; 2886 2887 /* 2888 * When called from DP MST code: 2889 * - conn_state will be NULL 2890 * - encoder will be the main encoder (ie. mst->primary) 2891 * - the main connector associated with this port 2892 * won't be active or linked to a crtc 2893 * - crtc_state will be the state of the first stream to 2894 * be activated on this port, and it may not be the same 2895 * stream that will be deactivated last, but each stream 2896 * should have a state that is identical when it comes to 2897 * the DP link parameteres 2898 */ 2899 2900 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2901 2902 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2903 2904 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2905 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2906 conn_state); 2907 } else { 2908 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2909 2910 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2911 conn_state); 2912 2913 /* FIXME precompute everything properly */ 2914 /* FIXME how do we turn infoframes off again? */ 2915 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2916 dig_port->set_infoframes(encoder, 2917 crtc_state->has_infoframe, 2918 crtc_state, conn_state); 2919 } 2920 } 2921 2922 static void 2923 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2924 { 2925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2926 enum port port = encoder->port; 2927 i915_reg_t reg; 2928 u32 clr_bits, wait_bits; 2929 2930 if (DISPLAY_VER(dev_priv) >= 20) { 2931 reg = DDI_BUF_CTL(port); 2932 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2933 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2934 } else { 2935 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2936 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2937 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2938 } 2939 2940 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2941 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2942 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2943 port_name(port)); 2944 } 2945 2946 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2947 const struct intel_crtc_state *crtc_state) 2948 { 2949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2950 enum port port = encoder->port; 2951 u32 val; 2952 2953 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2954 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2955 if (val & DDI_BUF_CTL_ENABLE) { 2956 val &= ~DDI_BUF_CTL_ENABLE; 2957 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2958 2959 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2960 mtl_wait_ddi_buf_idle(dev_priv, port); 2961 } 2962 2963 /* 3.d Disable D2D Link */ 2964 mtl_ddi_disable_d2d_link(encoder); 2965 2966 /* 3.e Disable DP_TP_CTL */ 2967 if (intel_crtc_has_dp_encoder(crtc_state)) { 2968 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2969 DP_TP_CTL_ENABLE, 0); 2970 } 2971 } 2972 2973 static void disable_ddi_buf(struct intel_encoder *encoder, 2974 const struct intel_crtc_state *crtc_state) 2975 { 2976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2977 enum port port = encoder->port; 2978 bool wait = false; 2979 u32 val; 2980 2981 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2982 if (val & DDI_BUF_CTL_ENABLE) { 2983 val &= ~DDI_BUF_CTL_ENABLE; 2984 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2985 wait = true; 2986 } 2987 2988 if (intel_crtc_has_dp_encoder(crtc_state)) 2989 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2990 DP_TP_CTL_ENABLE, 0); 2991 2992 intel_ddi_disable_fec(encoder, crtc_state); 2993 2994 if (wait) 2995 intel_wait_ddi_buf_idle(dev_priv, port); 2996 } 2997 2998 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2999 const struct intel_crtc_state *crtc_state) 3000 { 3001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3002 3003 if (DISPLAY_VER(dev_priv) >= 14) { 3004 mtl_disable_ddi_buf(encoder, crtc_state); 3005 3006 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 3007 intel_ddi_disable_fec(encoder, crtc_state); 3008 } else { 3009 disable_ddi_buf(encoder, crtc_state); 3010 } 3011 3012 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3013 } 3014 3015 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3016 struct intel_encoder *encoder, 3017 const struct intel_crtc_state *old_crtc_state, 3018 const struct drm_connector_state *old_conn_state) 3019 { 3020 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3021 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3022 struct intel_dp *intel_dp = &dig_port->dp; 3023 intel_wakeref_t wakeref; 3024 bool is_mst = intel_crtc_has_type(old_crtc_state, 3025 INTEL_OUTPUT_DP_MST); 3026 3027 if (!is_mst) 3028 intel_dp_set_infoframes(encoder, false, 3029 old_crtc_state, old_conn_state); 3030 3031 /* 3032 * Power down sink before disabling the port, otherwise we end 3033 * up getting interrupts from the sink on detecting link loss. 3034 */ 3035 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3036 3037 if (DISPLAY_VER(dev_priv) >= 12) { 3038 if (is_mst) { 3039 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3040 3041 intel_de_rmw(dev_priv, 3042 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 3043 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3044 0); 3045 } 3046 } else { 3047 if (!is_mst) 3048 intel_ddi_disable_transcoder_clock(old_crtc_state); 3049 } 3050 3051 intel_disable_ddi_buf(encoder, old_crtc_state); 3052 3053 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3054 3055 /* 3056 * From TGL spec: "If single stream or multi-stream master transcoder: 3057 * Configure Transcoder Clock select to direct no clock to the 3058 * transcoder" 3059 */ 3060 if (DISPLAY_VER(dev_priv) >= 12) 3061 intel_ddi_disable_transcoder_clock(old_crtc_state); 3062 3063 intel_pps_vdd_on(intel_dp); 3064 intel_pps_off(intel_dp); 3065 3066 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3067 3068 if (wakeref) 3069 intel_display_power_put(dev_priv, 3070 dig_port->ddi_io_power_domain, 3071 wakeref); 3072 3073 intel_ddi_disable_clock(encoder); 3074 3075 /* De-select Thunderbolt */ 3076 if (DISPLAY_VER(dev_priv) >= 14) 3077 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3078 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3079 } 3080 3081 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3082 struct intel_encoder *encoder, 3083 const struct intel_crtc_state *old_crtc_state, 3084 const struct drm_connector_state *old_conn_state) 3085 { 3086 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3087 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3088 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3089 intel_wakeref_t wakeref; 3090 3091 dig_port->set_infoframes(encoder, false, 3092 old_crtc_state, old_conn_state); 3093 3094 if (DISPLAY_VER(dev_priv) < 12) 3095 intel_ddi_disable_transcoder_clock(old_crtc_state); 3096 3097 intel_disable_ddi_buf(encoder, old_crtc_state); 3098 3099 if (DISPLAY_VER(dev_priv) >= 12) 3100 intel_ddi_disable_transcoder_clock(old_crtc_state); 3101 3102 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3103 if (wakeref) 3104 intel_display_power_put(dev_priv, 3105 dig_port->ddi_io_power_domain, 3106 wakeref); 3107 3108 intel_ddi_disable_clock(encoder); 3109 3110 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3111 } 3112 3113 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3114 struct intel_encoder *encoder, 3115 const struct intel_crtc_state *old_crtc_state, 3116 const struct drm_connector_state *old_conn_state) 3117 { 3118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3119 struct intel_crtc *pipe_crtc; 3120 3121 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3122 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3123 const struct intel_crtc_state *old_pipe_crtc_state = 3124 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3125 3126 intel_crtc_vblank_off(old_pipe_crtc_state); 3127 } 3128 3129 intel_disable_transcoder(old_crtc_state); 3130 3131 intel_ddi_disable_transcoder_func(old_crtc_state); 3132 3133 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3134 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3135 const struct intel_crtc_state *old_pipe_crtc_state = 3136 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3137 3138 intel_dsc_disable(old_pipe_crtc_state); 3139 3140 if (DISPLAY_VER(dev_priv) >= 9) 3141 skl_scaler_disable(old_pipe_crtc_state); 3142 else 3143 ilk_pfit_disable(old_pipe_crtc_state); 3144 } 3145 } 3146 3147 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3148 struct intel_encoder *encoder, 3149 const struct intel_crtc_state *old_crtc_state, 3150 const struct drm_connector_state *old_conn_state) 3151 { 3152 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3153 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3154 old_conn_state); 3155 3156 /* 3157 * When called from DP MST code: 3158 * - old_conn_state will be NULL 3159 * - encoder will be the main encoder (ie. mst->primary) 3160 * - the main connector associated with this port 3161 * won't be active or linked to a crtc 3162 * - old_crtc_state will be the state of the last stream to 3163 * be deactivated on this port, and it may not be the same 3164 * stream that was activated last, but each stream 3165 * should have a state that is identical when it comes to 3166 * the DP link parameteres 3167 */ 3168 3169 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3170 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3171 old_conn_state); 3172 else 3173 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3174 old_conn_state); 3175 } 3176 3177 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3178 struct intel_encoder *encoder, 3179 const struct intel_crtc_state *old_crtc_state, 3180 const struct drm_connector_state *old_conn_state) 3181 { 3182 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3183 3184 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3185 3186 if (intel_encoder_is_tc(encoder)) 3187 intel_tc_port_put_link(dig_port); 3188 } 3189 3190 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3191 struct intel_encoder *encoder, 3192 const struct intel_crtc_state *crtc_state) 3193 { 3194 const struct drm_connector_state *conn_state; 3195 struct drm_connector *conn; 3196 int i; 3197 3198 if (!crtc_state->sync_mode_slaves_mask) 3199 return; 3200 3201 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3202 struct intel_encoder *slave_encoder = 3203 to_intel_encoder(conn_state->best_encoder); 3204 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3205 const struct intel_crtc_state *slave_crtc_state; 3206 3207 if (!slave_crtc) 3208 continue; 3209 3210 slave_crtc_state = 3211 intel_atomic_get_new_crtc_state(state, slave_crtc); 3212 3213 if (slave_crtc_state->master_transcoder != 3214 crtc_state->cpu_transcoder) 3215 continue; 3216 3217 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3218 slave_crtc_state); 3219 } 3220 3221 usleep_range(200, 400); 3222 3223 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3224 crtc_state); 3225 } 3226 3227 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3228 struct intel_encoder *encoder, 3229 const struct intel_crtc_state *crtc_state, 3230 const struct drm_connector_state *conn_state) 3231 { 3232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3233 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3234 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3235 enum port port = encoder->port; 3236 3237 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3238 intel_dp_stop_link_train(intel_dp, crtc_state); 3239 3240 drm_connector_update_privacy_screen(conn_state); 3241 intel_edp_backlight_on(crtc_state, conn_state); 3242 3243 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3244 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3245 3246 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3247 } 3248 3249 /* FIXME bad home for this function */ 3250 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3251 enum transcoder cpu_transcoder) 3252 { 3253 return DISPLAY_VER(i915) >= 14 ? 3254 MTL_CHICKEN_TRANS(cpu_transcoder) : 3255 CHICKEN_TRANS(cpu_transcoder); 3256 } 3257 3258 static i915_reg_t 3259 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3260 enum port port) 3261 { 3262 static const enum transcoder trans[] = { 3263 [PORT_A] = TRANSCODER_EDP, 3264 [PORT_B] = TRANSCODER_A, 3265 [PORT_C] = TRANSCODER_B, 3266 [PORT_D] = TRANSCODER_C, 3267 [PORT_E] = TRANSCODER_A, 3268 }; 3269 3270 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3271 3272 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3273 port = PORT_A; 3274 3275 return CHICKEN_TRANS(trans[port]); 3276 } 3277 3278 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3279 struct intel_encoder *encoder, 3280 const struct intel_crtc_state *crtc_state, 3281 const struct drm_connector_state *conn_state) 3282 { 3283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3284 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3285 struct drm_connector *connector = conn_state->connector; 3286 enum port port = encoder->port; 3287 u32 buf_ctl; 3288 3289 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3290 crtc_state->hdmi_high_tmds_clock_ratio, 3291 crtc_state->hdmi_scrambling)) 3292 drm_dbg_kms(&dev_priv->drm, 3293 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3294 connector->base.id, connector->name); 3295 3296 if (has_buf_trans_select(dev_priv)) 3297 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3298 3299 /* e. Enable D2D Link for C10/C20 Phy */ 3300 if (DISPLAY_VER(dev_priv) >= 14) 3301 mtl_ddi_enable_d2d(encoder); 3302 3303 encoder->set_signal_levels(encoder, crtc_state); 3304 3305 /* Display WA #1143: skl,kbl,cfl */ 3306 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3307 /* 3308 * For some reason these chicken bits have been 3309 * stuffed into a transcoder register, event though 3310 * the bits affect a specific DDI port rather than 3311 * a specific transcoder. 3312 */ 3313 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3314 u32 val; 3315 3316 val = intel_de_read(dev_priv, reg); 3317 3318 if (port == PORT_E) 3319 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3320 DDIE_TRAINING_OVERRIDE_VALUE; 3321 else 3322 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3323 DDI_TRAINING_OVERRIDE_VALUE; 3324 3325 intel_de_write(dev_priv, reg, val); 3326 intel_de_posting_read(dev_priv, reg); 3327 3328 udelay(1); 3329 3330 if (port == PORT_E) 3331 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3332 DDIE_TRAINING_OVERRIDE_VALUE); 3333 else 3334 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3335 DDI_TRAINING_OVERRIDE_VALUE); 3336 3337 intel_de_write(dev_priv, reg, val); 3338 } 3339 3340 intel_ddi_power_up_lanes(encoder, crtc_state); 3341 3342 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3343 * are ignored so nothing special needs to be done besides 3344 * enabling the port. 3345 * 3346 * On ADL_P the PHY link rate and lane count must be programmed but 3347 * these are both 0 for HDMI. 3348 * 3349 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3350 * is filled with lane count, already set in the crtc_state. 3351 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3352 */ 3353 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3354 if (DISPLAY_VER(dev_priv) >= 14) { 3355 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3356 u32 port_buf = 0; 3357 3358 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3359 3360 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3361 port_buf |= XELPDP_PORT_REVERSAL; 3362 3363 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3364 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3365 3366 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3367 3368 if (DISPLAY_VER(dev_priv) >= 20) 3369 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3370 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3371 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3372 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3373 } 3374 3375 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3376 3377 intel_wait_ddi_buf_active(encoder); 3378 } 3379 3380 static void intel_enable_ddi(struct intel_atomic_state *state, 3381 struct intel_encoder *encoder, 3382 const struct intel_crtc_state *crtc_state, 3383 const struct drm_connector_state *conn_state) 3384 { 3385 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3386 struct intel_crtc *pipe_crtc; 3387 3388 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3389 3390 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3391 intel_audio_sdp_split_update(crtc_state); 3392 3393 intel_enable_transcoder(crtc_state); 3394 3395 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3396 3397 for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, 3398 intel_crtc_joined_pipe_mask(crtc_state)) { 3399 const struct intel_crtc_state *pipe_crtc_state = 3400 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3401 3402 intel_crtc_vblank_on(pipe_crtc_state); 3403 } 3404 3405 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3406 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3407 else 3408 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3409 3410 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3411 3412 } 3413 3414 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3415 struct intel_encoder *encoder, 3416 const struct intel_crtc_state *old_crtc_state, 3417 const struct drm_connector_state *old_conn_state) 3418 { 3419 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3420 struct intel_connector *connector = 3421 to_intel_connector(old_conn_state->connector); 3422 3423 intel_dp->link_trained = false; 3424 3425 intel_psr_disable(intel_dp, old_crtc_state); 3426 intel_edp_backlight_off(old_conn_state); 3427 /* Disable the decompression in DP Sink */ 3428 intel_dp_sink_disable_decompression(state, 3429 connector, old_crtc_state); 3430 /* Disable Ignore_MSA bit in DP Sink */ 3431 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3432 false); 3433 } 3434 3435 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3436 struct intel_encoder *encoder, 3437 const struct intel_crtc_state *old_crtc_state, 3438 const struct drm_connector_state *old_conn_state) 3439 { 3440 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3441 struct drm_connector *connector = old_conn_state->connector; 3442 3443 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3444 false, false)) 3445 drm_dbg_kms(&i915->drm, 3446 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3447 connector->base.id, connector->name); 3448 } 3449 3450 static void intel_disable_ddi(struct intel_atomic_state *state, 3451 struct intel_encoder *encoder, 3452 const struct intel_crtc_state *old_crtc_state, 3453 const struct drm_connector_state *old_conn_state) 3454 { 3455 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3456 3457 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3458 3459 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3460 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3461 old_conn_state); 3462 else 3463 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3464 old_conn_state); 3465 } 3466 3467 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3468 struct intel_encoder *encoder, 3469 const struct intel_crtc_state *crtc_state, 3470 const struct drm_connector_state *conn_state) 3471 { 3472 intel_ddi_set_dp_msa(crtc_state, conn_state); 3473 3474 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3475 3476 intel_backlight_update(state, encoder, crtc_state, conn_state); 3477 drm_connector_update_privacy_screen(conn_state); 3478 } 3479 3480 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3481 struct intel_encoder *encoder, 3482 const struct intel_crtc_state *crtc_state, 3483 const struct drm_connector_state *conn_state) 3484 { 3485 3486 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3487 !intel_encoder_is_mst(encoder)) 3488 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3489 conn_state); 3490 3491 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3492 } 3493 3494 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3495 struct intel_encoder *encoder, 3496 struct intel_crtc *crtc) 3497 { 3498 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3499 const struct intel_crtc_state *crtc_state = 3500 intel_atomic_get_new_crtc_state(state, crtc); 3501 struct intel_crtc *pipe_crtc; 3502 3503 /* FIXME: Add MTL pll_mgr */ 3504 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3505 return; 3506 3507 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3508 intel_crtc_joined_pipe_mask(crtc_state)) 3509 intel_update_active_dpll(state, pipe_crtc, encoder); 3510 } 3511 3512 static void 3513 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3514 struct intel_encoder *encoder, 3515 const struct intel_crtc_state *crtc_state, 3516 const struct drm_connector_state *conn_state) 3517 { 3518 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3519 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3520 bool is_tc_port = intel_encoder_is_tc(encoder); 3521 3522 if (is_tc_port) { 3523 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3524 3525 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3526 intel_ddi_update_active_dpll(state, encoder, crtc); 3527 } 3528 3529 main_link_aux_power_domain_get(dig_port, crtc_state); 3530 3531 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3532 /* 3533 * Program the lane count for static/dynamic connections on 3534 * Type-C ports. Skip this step for TBT. 3535 */ 3536 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3537 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3538 bxt_dpio_phy_set_lane_optim_mask(encoder, 3539 crtc_state->lane_lat_optim_mask); 3540 } 3541 3542 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3543 { 3544 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3545 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3546 int ln; 3547 3548 for (ln = 0; ln < 2; ln++) 3549 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3550 } 3551 3552 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3553 const struct intel_crtc_state *crtc_state) 3554 { 3555 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3556 struct intel_encoder *encoder = &dig_port->base; 3557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3558 enum port port = encoder->port; 3559 u32 dp_tp_ctl; 3560 3561 /* 3562 * TODO: To train with only a different voltage swing entry is not 3563 * necessary disable and enable port 3564 */ 3565 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3566 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3567 mtl_disable_ddi_buf(encoder, crtc_state); 3568 3569 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3570 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3571 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3572 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3573 } else { 3574 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3575 if (crtc_state->enhanced_framing) 3576 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3577 } 3578 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3579 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3580 3581 /* 6.f Enable D2D Link */ 3582 mtl_ddi_enable_d2d(encoder); 3583 3584 /* 6.g Configure voltage swing and related IO settings */ 3585 encoder->set_signal_levels(encoder, crtc_state); 3586 3587 /* 6.h Configure PORT_BUF_CTL1 */ 3588 mtl_port_buf_ctl_program(encoder, crtc_state); 3589 3590 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3591 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3592 if (DISPLAY_VER(dev_priv) >= 20) 3593 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3594 3595 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3596 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3597 3598 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3599 intel_wait_ddi_buf_active(encoder); 3600 } 3601 3602 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3603 const struct intel_crtc_state *crtc_state) 3604 { 3605 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3606 struct intel_encoder *encoder = &dig_port->base; 3607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3608 enum port port = encoder->port; 3609 u32 dp_tp_ctl, ddi_buf_ctl; 3610 bool wait = false; 3611 3612 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3613 3614 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3615 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3616 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3617 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3618 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3619 wait = true; 3620 } 3621 3622 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3623 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3624 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3625 3626 if (wait) 3627 intel_wait_ddi_buf_idle(dev_priv, port); 3628 } 3629 3630 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3631 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3632 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3633 } else { 3634 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3635 if (crtc_state->enhanced_framing) 3636 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3637 } 3638 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3639 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3640 3641 if (IS_ALDERLAKE_P(dev_priv) && 3642 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3643 adlp_tbt_to_dp_alt_switch_wa(encoder); 3644 3645 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3646 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3647 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3648 3649 intel_wait_ddi_buf_active(encoder); 3650 } 3651 3652 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3653 const struct intel_crtc_state *crtc_state, 3654 u8 dp_train_pat) 3655 { 3656 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3657 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3658 u32 temp; 3659 3660 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3661 3662 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3663 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3664 case DP_TRAINING_PATTERN_DISABLE: 3665 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3666 break; 3667 case DP_TRAINING_PATTERN_1: 3668 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3669 break; 3670 case DP_TRAINING_PATTERN_2: 3671 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3672 break; 3673 case DP_TRAINING_PATTERN_3: 3674 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3675 break; 3676 case DP_TRAINING_PATTERN_4: 3677 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3678 break; 3679 } 3680 3681 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3682 } 3683 3684 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3685 const struct intel_crtc_state *crtc_state) 3686 { 3687 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3688 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3689 enum port port = encoder->port; 3690 3691 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3692 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3693 3694 /* 3695 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3696 * reason we need to set idle transmission mode is to work around a HW 3697 * issue where we enable the pipe while not in idle link-training mode. 3698 * In this case there is requirement to wait for a minimum number of 3699 * idle patterns to be sent. 3700 */ 3701 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3702 return; 3703 3704 if (intel_de_wait_for_set(dev_priv, 3705 dp_tp_status_reg(encoder, crtc_state), 3706 DP_TP_STATUS_IDLE_DONE, 2)) 3707 drm_err(&dev_priv->drm, 3708 "Timed out waiting for DP idle patterns\n"); 3709 } 3710 3711 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3712 enum transcoder cpu_transcoder) 3713 { 3714 if (cpu_transcoder == TRANSCODER_EDP) 3715 return false; 3716 3717 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3718 return false; 3719 3720 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3721 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3722 } 3723 3724 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3725 { 3726 if (crtc_state->port_clock > 594000) 3727 return 2; 3728 else 3729 return 0; 3730 } 3731 3732 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3733 { 3734 if (crtc_state->port_clock > 594000) 3735 return 3; 3736 else 3737 return 0; 3738 } 3739 3740 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3741 { 3742 if (crtc_state->port_clock > 594000) 3743 return 1; 3744 else 3745 return 0; 3746 } 3747 3748 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3749 { 3750 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3751 3752 if (DISPLAY_VER(dev_priv) >= 14) 3753 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3754 else if (DISPLAY_VER(dev_priv) >= 12) 3755 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3756 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3757 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3758 else if (DISPLAY_VER(dev_priv) >= 11) 3759 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3760 } 3761 3762 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3763 enum transcoder cpu_transcoder) 3764 { 3765 u32 master_select; 3766 3767 if (DISPLAY_VER(dev_priv) >= 11) { 3768 u32 ctl2 = intel_de_read(dev_priv, 3769 TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); 3770 3771 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3772 return INVALID_TRANSCODER; 3773 3774 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3775 } else { 3776 u32 ctl = intel_de_read(dev_priv, 3777 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3778 3779 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3780 return INVALID_TRANSCODER; 3781 3782 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3783 } 3784 3785 if (master_select == 0) 3786 return TRANSCODER_EDP; 3787 else 3788 return master_select - 1; 3789 } 3790 3791 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3792 { 3793 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3794 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3795 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3796 enum transcoder cpu_transcoder; 3797 3798 crtc_state->master_transcoder = 3799 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3800 3801 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3802 enum intel_display_power_domain power_domain; 3803 intel_wakeref_t trans_wakeref; 3804 3805 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3806 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3807 power_domain); 3808 3809 if (!trans_wakeref) 3810 continue; 3811 3812 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3813 crtc_state->cpu_transcoder) 3814 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3815 3816 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3817 } 3818 3819 drm_WARN_ON(&dev_priv->drm, 3820 crtc_state->master_transcoder != INVALID_TRANSCODER && 3821 crtc_state->sync_mode_slaves_mask); 3822 } 3823 3824 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3825 struct intel_crtc_state *pipe_config) 3826 { 3827 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3828 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3829 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3830 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3831 u32 temp, flags = 0; 3832 3833 temp = intel_de_read(dev_priv, 3834 TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3835 if (temp & TRANS_DDI_PHSYNC) 3836 flags |= DRM_MODE_FLAG_PHSYNC; 3837 else 3838 flags |= DRM_MODE_FLAG_NHSYNC; 3839 if (temp & TRANS_DDI_PVSYNC) 3840 flags |= DRM_MODE_FLAG_PVSYNC; 3841 else 3842 flags |= DRM_MODE_FLAG_NVSYNC; 3843 3844 pipe_config->hw.adjusted_mode.flags |= flags; 3845 3846 switch (temp & TRANS_DDI_BPC_MASK) { 3847 case TRANS_DDI_BPC_6: 3848 pipe_config->pipe_bpp = 18; 3849 break; 3850 case TRANS_DDI_BPC_8: 3851 pipe_config->pipe_bpp = 24; 3852 break; 3853 case TRANS_DDI_BPC_10: 3854 pipe_config->pipe_bpp = 30; 3855 break; 3856 case TRANS_DDI_BPC_12: 3857 pipe_config->pipe_bpp = 36; 3858 break; 3859 default: 3860 break; 3861 } 3862 3863 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3864 case TRANS_DDI_MODE_SELECT_HDMI: 3865 pipe_config->has_hdmi_sink = true; 3866 3867 pipe_config->infoframes.enable |= 3868 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3869 3870 if (pipe_config->infoframes.enable) 3871 pipe_config->has_infoframe = true; 3872 3873 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3874 pipe_config->hdmi_scrambling = true; 3875 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3876 pipe_config->hdmi_high_tmds_clock_ratio = true; 3877 fallthrough; 3878 case TRANS_DDI_MODE_SELECT_DVI: 3879 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3880 if (DISPLAY_VER(dev_priv) >= 14) 3881 pipe_config->lane_count = 3882 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3883 else 3884 pipe_config->lane_count = 4; 3885 break; 3886 case TRANS_DDI_MODE_SELECT_DP_SST: 3887 if (encoder->type == INTEL_OUTPUT_EDP) 3888 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3889 else 3890 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3891 pipe_config->lane_count = 3892 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3893 3894 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3895 &pipe_config->dp_m_n); 3896 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3897 &pipe_config->dp_m2_n2); 3898 3899 pipe_config->enhanced_framing = 3900 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3901 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3902 3903 if (DISPLAY_VER(dev_priv) >= 11) 3904 pipe_config->fec_enable = 3905 intel_de_read(dev_priv, 3906 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3907 3908 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3909 pipe_config->infoframes.enable |= 3910 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3911 else 3912 pipe_config->infoframes.enable |= 3913 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3914 break; 3915 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3916 if (!HAS_DP20(dev_priv)) { 3917 /* FDI */ 3918 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3919 pipe_config->enhanced_framing = 3920 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3921 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3922 break; 3923 } 3924 fallthrough; /* 128b/132b */ 3925 case TRANS_DDI_MODE_SELECT_DP_MST: 3926 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3927 pipe_config->lane_count = 3928 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3929 3930 if (DISPLAY_VER(dev_priv) >= 12) 3931 pipe_config->mst_master_transcoder = 3932 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3933 3934 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3935 &pipe_config->dp_m_n); 3936 3937 if (DISPLAY_VER(dev_priv) >= 11) 3938 pipe_config->fec_enable = 3939 intel_de_read(dev_priv, 3940 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3941 3942 pipe_config->infoframes.enable |= 3943 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3944 break; 3945 default: 3946 break; 3947 } 3948 } 3949 3950 static void intel_ddi_get_config(struct intel_encoder *encoder, 3951 struct intel_crtc_state *pipe_config) 3952 { 3953 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3954 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3955 3956 /* XXX: DSI transcoder paranoia */ 3957 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3958 return; 3959 3960 intel_ddi_read_func_ctl(encoder, pipe_config); 3961 3962 intel_ddi_mso_get_config(encoder, pipe_config); 3963 3964 pipe_config->has_audio = 3965 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3966 3967 if (encoder->type == INTEL_OUTPUT_EDP) 3968 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3969 3970 ddi_dotclock_get(pipe_config); 3971 3972 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3973 pipe_config->lane_lat_optim_mask = 3974 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 3975 3976 intel_ddi_compute_min_voltage_level(pipe_config); 3977 3978 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3979 3980 intel_read_infoframe(encoder, pipe_config, 3981 HDMI_INFOFRAME_TYPE_AVI, 3982 &pipe_config->infoframes.avi); 3983 intel_read_infoframe(encoder, pipe_config, 3984 HDMI_INFOFRAME_TYPE_SPD, 3985 &pipe_config->infoframes.spd); 3986 intel_read_infoframe(encoder, pipe_config, 3987 HDMI_INFOFRAME_TYPE_VENDOR, 3988 &pipe_config->infoframes.hdmi); 3989 intel_read_infoframe(encoder, pipe_config, 3990 HDMI_INFOFRAME_TYPE_DRM, 3991 &pipe_config->infoframes.drm); 3992 3993 if (DISPLAY_VER(dev_priv) >= 8) 3994 bdw_get_trans_port_sync_config(pipe_config); 3995 3996 intel_psr_get_config(encoder, pipe_config); 3997 3998 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3999 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4000 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4001 4002 intel_audio_codec_get_config(encoder, pipe_config); 4003 } 4004 4005 void intel_ddi_get_clock(struct intel_encoder *encoder, 4006 struct intel_crtc_state *crtc_state, 4007 struct intel_shared_dpll *pll) 4008 { 4009 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4010 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4011 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4012 bool pll_active; 4013 4014 if (drm_WARN_ON(&i915->drm, !pll)) 4015 return; 4016 4017 port_dpll->pll = pll; 4018 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4019 drm_WARN_ON(&i915->drm, !pll_active); 4020 4021 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4022 4023 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4024 &crtc_state->dpll_hw_state); 4025 } 4026 4027 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4028 struct intel_crtc_state *crtc_state) 4029 { 4030 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4031 4032 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4033 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4034 else 4035 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4036 4037 intel_ddi_get_config(encoder, crtc_state); 4038 } 4039 4040 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4041 struct intel_crtc_state *crtc_state) 4042 { 4043 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4044 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4045 4046 intel_ddi_get_config(encoder, crtc_state); 4047 } 4048 4049 static void adls_ddi_get_config(struct intel_encoder *encoder, 4050 struct intel_crtc_state *crtc_state) 4051 { 4052 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4053 intel_ddi_get_config(encoder, crtc_state); 4054 } 4055 4056 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4057 struct intel_crtc_state *crtc_state) 4058 { 4059 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4060 intel_ddi_get_config(encoder, crtc_state); 4061 } 4062 4063 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4064 struct intel_crtc_state *crtc_state) 4065 { 4066 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4067 intel_ddi_get_config(encoder, crtc_state); 4068 } 4069 4070 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4071 struct intel_crtc_state *crtc_state) 4072 { 4073 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4074 intel_ddi_get_config(encoder, crtc_state); 4075 } 4076 4077 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4078 { 4079 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4080 } 4081 4082 static enum icl_port_dpll_id 4083 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4084 const struct intel_crtc_state *crtc_state) 4085 { 4086 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4087 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4088 4089 if (drm_WARN_ON(&i915->drm, !pll)) 4090 return ICL_PORT_DPLL_DEFAULT; 4091 4092 if (icl_ddi_tc_pll_is_tbt(pll)) 4093 return ICL_PORT_DPLL_DEFAULT; 4094 else 4095 return ICL_PORT_DPLL_MG_PHY; 4096 } 4097 4098 enum icl_port_dpll_id 4099 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4100 const struct intel_crtc_state *crtc_state) 4101 { 4102 if (!encoder->port_pll_type) 4103 return ICL_PORT_DPLL_DEFAULT; 4104 4105 return encoder->port_pll_type(encoder, crtc_state); 4106 } 4107 4108 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4109 struct intel_crtc_state *crtc_state, 4110 struct intel_shared_dpll *pll) 4111 { 4112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4113 enum icl_port_dpll_id port_dpll_id; 4114 struct icl_port_dpll *port_dpll; 4115 bool pll_active; 4116 4117 if (drm_WARN_ON(&i915->drm, !pll)) 4118 return; 4119 4120 if (icl_ddi_tc_pll_is_tbt(pll)) 4121 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4122 else 4123 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4124 4125 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4126 4127 port_dpll->pll = pll; 4128 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4129 drm_WARN_ON(&i915->drm, !pll_active); 4130 4131 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4132 4133 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4134 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4135 else 4136 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4137 &crtc_state->dpll_hw_state); 4138 } 4139 4140 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4141 struct intel_crtc_state *crtc_state) 4142 { 4143 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4144 intel_ddi_get_config(encoder, crtc_state); 4145 } 4146 4147 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4148 struct intel_crtc_state *crtc_state) 4149 { 4150 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4151 intel_ddi_get_config(encoder, crtc_state); 4152 } 4153 4154 static void skl_ddi_get_config(struct intel_encoder *encoder, 4155 struct intel_crtc_state *crtc_state) 4156 { 4157 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4158 intel_ddi_get_config(encoder, crtc_state); 4159 } 4160 4161 void hsw_ddi_get_config(struct intel_encoder *encoder, 4162 struct intel_crtc_state *crtc_state) 4163 { 4164 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4165 intel_ddi_get_config(encoder, crtc_state); 4166 } 4167 4168 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4169 const struct intel_crtc_state *crtc_state) 4170 { 4171 if (intel_encoder_is_tc(encoder)) 4172 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4173 crtc_state); 4174 4175 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4176 (!crtc_state && intel_encoder_is_dp(encoder))) 4177 intel_dp_sync_state(encoder, crtc_state); 4178 } 4179 4180 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4181 struct intel_crtc_state *crtc_state) 4182 { 4183 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4184 bool fastset = true; 4185 4186 if (intel_encoder_is_tc(encoder)) { 4187 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4188 encoder->base.base.id, encoder->base.name); 4189 crtc_state->uapi.mode_changed = true; 4190 fastset = false; 4191 } 4192 4193 if (intel_crtc_has_dp_encoder(crtc_state) && 4194 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4195 fastset = false; 4196 4197 return fastset; 4198 } 4199 4200 static enum intel_output_type 4201 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4202 struct intel_crtc_state *crtc_state, 4203 struct drm_connector_state *conn_state) 4204 { 4205 switch (conn_state->connector->connector_type) { 4206 case DRM_MODE_CONNECTOR_HDMIA: 4207 return INTEL_OUTPUT_HDMI; 4208 case DRM_MODE_CONNECTOR_eDP: 4209 return INTEL_OUTPUT_EDP; 4210 case DRM_MODE_CONNECTOR_DisplayPort: 4211 return INTEL_OUTPUT_DP; 4212 default: 4213 MISSING_CASE(conn_state->connector->connector_type); 4214 return INTEL_OUTPUT_UNUSED; 4215 } 4216 } 4217 4218 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4219 struct intel_crtc_state *pipe_config, 4220 struct drm_connector_state *conn_state) 4221 { 4222 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4224 enum port port = encoder->port; 4225 int ret; 4226 4227 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4228 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4229 4230 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4231 pipe_config->has_hdmi_sink = 4232 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4233 4234 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4235 } else { 4236 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4237 } 4238 4239 if (ret) 4240 return ret; 4241 4242 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4243 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4244 pipe_config->pch_pfit.force_thru = 4245 pipe_config->pch_pfit.enabled || 4246 pipe_config->crc_enabled; 4247 4248 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4249 pipe_config->lane_lat_optim_mask = 4250 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4251 4252 intel_ddi_compute_min_voltage_level(pipe_config); 4253 4254 return 0; 4255 } 4256 4257 static bool mode_equal(const struct drm_display_mode *mode1, 4258 const struct drm_display_mode *mode2) 4259 { 4260 return drm_mode_match(mode1, mode2, 4261 DRM_MODE_MATCH_TIMINGS | 4262 DRM_MODE_MATCH_FLAGS | 4263 DRM_MODE_MATCH_3D_FLAGS) && 4264 mode1->clock == mode2->clock; /* we want an exact match */ 4265 } 4266 4267 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4268 const struct intel_link_m_n *m_n_2) 4269 { 4270 return m_n_1->tu == m_n_2->tu && 4271 m_n_1->data_m == m_n_2->data_m && 4272 m_n_1->data_n == m_n_2->data_n && 4273 m_n_1->link_m == m_n_2->link_m && 4274 m_n_1->link_n == m_n_2->link_n; 4275 } 4276 4277 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4278 const struct intel_crtc_state *crtc_state2) 4279 { 4280 /* 4281 * FIXME the modeset sequence is currently wrong and 4282 * can't deal with joiner + port sync at the same time. 4283 */ 4284 return crtc_state1->hw.active && crtc_state2->hw.active && 4285 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4286 crtc_state1->output_types == crtc_state2->output_types && 4287 crtc_state1->output_format == crtc_state2->output_format && 4288 crtc_state1->lane_count == crtc_state2->lane_count && 4289 crtc_state1->port_clock == crtc_state2->port_clock && 4290 mode_equal(&crtc_state1->hw.adjusted_mode, 4291 &crtc_state2->hw.adjusted_mode) && 4292 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4293 } 4294 4295 static u8 4296 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4297 int tile_group_id) 4298 { 4299 struct drm_connector *connector; 4300 const struct drm_connector_state *conn_state; 4301 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4302 struct intel_atomic_state *state = 4303 to_intel_atomic_state(ref_crtc_state->uapi.state); 4304 u8 transcoders = 0; 4305 int i; 4306 4307 /* 4308 * We don't enable port sync on BDW due to missing w/as and 4309 * due to not having adjusted the modeset sequence appropriately. 4310 */ 4311 if (DISPLAY_VER(dev_priv) < 9) 4312 return 0; 4313 4314 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4315 return 0; 4316 4317 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4318 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4319 const struct intel_crtc_state *crtc_state; 4320 4321 if (!crtc) 4322 continue; 4323 4324 if (!connector->has_tile || 4325 connector->tile_group->id != 4326 tile_group_id) 4327 continue; 4328 crtc_state = intel_atomic_get_new_crtc_state(state, 4329 crtc); 4330 if (!crtcs_port_sync_compatible(ref_crtc_state, 4331 crtc_state)) 4332 continue; 4333 transcoders |= BIT(crtc_state->cpu_transcoder); 4334 } 4335 4336 return transcoders; 4337 } 4338 4339 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4340 struct intel_crtc_state *crtc_state, 4341 struct drm_connector_state *conn_state) 4342 { 4343 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4344 struct drm_connector *connector = conn_state->connector; 4345 u8 port_sync_transcoders = 0; 4346 4347 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4348 encoder->base.base.id, encoder->base.name, 4349 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4350 4351 if (connector->has_tile) 4352 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4353 connector->tile_group->id); 4354 4355 /* 4356 * EDP Transcoders cannot be ensalved 4357 * make them a master always when present 4358 */ 4359 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4360 crtc_state->master_transcoder = TRANSCODER_EDP; 4361 else 4362 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4363 4364 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4365 crtc_state->master_transcoder = INVALID_TRANSCODER; 4366 crtc_state->sync_mode_slaves_mask = 4367 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4368 } 4369 4370 return 0; 4371 } 4372 4373 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4374 { 4375 struct drm_i915_private *i915 = to_i915(encoder->dev); 4376 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4377 4378 intel_dp_encoder_flush_work(encoder); 4379 if (intel_encoder_is_tc(&dig_port->base)) 4380 intel_tc_port_cleanup(dig_port); 4381 intel_display_power_flush_work(i915); 4382 4383 drm_encoder_cleanup(encoder); 4384 kfree(dig_port->hdcp_port_data.streams); 4385 kfree(dig_port); 4386 } 4387 4388 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4389 { 4390 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4391 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4392 4393 intel_dp->reset_link_params = true; 4394 4395 intel_pps_encoder_reset(intel_dp); 4396 4397 if (intel_encoder_is_tc(&dig_port->base)) 4398 intel_tc_port_init_mode(dig_port); 4399 } 4400 4401 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4402 { 4403 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4404 4405 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4406 4407 return 0; 4408 } 4409 4410 static const struct drm_encoder_funcs intel_ddi_funcs = { 4411 .reset = intel_ddi_encoder_reset, 4412 .destroy = intel_ddi_encoder_destroy, 4413 .late_register = intel_ddi_encoder_late_register, 4414 }; 4415 4416 static struct intel_connector * 4417 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4418 { 4419 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4420 struct intel_connector *connector; 4421 enum port port = dig_port->base.port; 4422 4423 connector = intel_connector_alloc(); 4424 if (!connector) 4425 return NULL; 4426 4427 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4428 if (DISPLAY_VER(i915) >= 14) 4429 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4430 else 4431 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4432 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4433 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4434 4435 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4436 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4437 4438 if (!intel_dp_init_connector(dig_port, connector)) { 4439 kfree(connector); 4440 return NULL; 4441 } 4442 4443 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4444 struct drm_device *dev = dig_port->base.base.dev; 4445 struct drm_privacy_screen *privacy_screen; 4446 4447 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4448 if (!IS_ERR(privacy_screen)) { 4449 drm_connector_attach_privacy_screen_provider(&connector->base, 4450 privacy_screen); 4451 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4452 drm_warn(dev, "Error getting privacy-screen\n"); 4453 } 4454 } 4455 4456 return connector; 4457 } 4458 4459 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4460 struct drm_modeset_acquire_ctx *ctx) 4461 { 4462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4463 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4464 struct intel_connector *connector = hdmi->attached_connector; 4465 struct i2c_adapter *ddc = connector->base.ddc; 4466 struct drm_connector_state *conn_state; 4467 struct intel_crtc_state *crtc_state; 4468 struct intel_crtc *crtc; 4469 u8 config; 4470 int ret; 4471 4472 if (connector->base.status != connector_status_connected) 4473 return 0; 4474 4475 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4476 ctx); 4477 if (ret) 4478 return ret; 4479 4480 conn_state = connector->base.state; 4481 4482 crtc = to_intel_crtc(conn_state->crtc); 4483 if (!crtc) 4484 return 0; 4485 4486 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4487 if (ret) 4488 return ret; 4489 4490 crtc_state = to_intel_crtc_state(crtc->base.state); 4491 4492 drm_WARN_ON(&dev_priv->drm, 4493 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4494 4495 if (!crtc_state->hw.active) 4496 return 0; 4497 4498 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4499 !crtc_state->hdmi_scrambling) 4500 return 0; 4501 4502 if (conn_state->commit && 4503 !try_wait_for_completion(&conn_state->commit->hw_done)) 4504 return 0; 4505 4506 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4507 if (ret < 0) { 4508 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4509 connector->base.base.id, connector->base.name, ret); 4510 return 0; 4511 } 4512 4513 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4514 crtc_state->hdmi_high_tmds_clock_ratio && 4515 !!(config & SCDC_SCRAMBLING_ENABLE) == 4516 crtc_state->hdmi_scrambling) 4517 return 0; 4518 4519 /* 4520 * HDMI 2.0 says that one should not send scrambled data 4521 * prior to configuring the sink scrambling, and that 4522 * TMDS clock/data transmission should be suspended when 4523 * changing the TMDS clock rate in the sink. So let's 4524 * just do a full modeset here, even though some sinks 4525 * would be perfectly happy if were to just reconfigure 4526 * the SCDC settings on the fly. 4527 */ 4528 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); 4529 } 4530 4531 static void intel_ddi_link_check(struct intel_encoder *encoder) 4532 { 4533 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4534 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4535 4536 /* TODO: Move checking the HDMI link state here as well. */ 4537 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); 4538 4539 intel_dp_link_check(encoder); 4540 } 4541 4542 static enum intel_hotplug_state 4543 intel_ddi_hotplug(struct intel_encoder *encoder, 4544 struct intel_connector *connector) 4545 { 4546 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4547 struct intel_dp *intel_dp = &dig_port->dp; 4548 bool is_tc = intel_encoder_is_tc(encoder); 4549 struct drm_modeset_acquire_ctx ctx; 4550 enum intel_hotplug_state state; 4551 int ret; 4552 4553 if (intel_dp->compliance.test_active && 4554 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4555 intel_dp_phy_test(encoder); 4556 /* just do the PHY test and nothing else */ 4557 return INTEL_HOTPLUG_UNCHANGED; 4558 } 4559 4560 state = intel_encoder_hotplug(encoder, connector); 4561 4562 if (!intel_tc_port_link_reset(dig_port)) { 4563 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4564 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4565 ret = intel_hdmi_reset_link(encoder, &ctx); 4566 drm_WARN_ON(encoder->base.dev, ret); 4567 } else { 4568 intel_dp_check_link_state(intel_dp); 4569 } 4570 } 4571 4572 /* 4573 * Unpowered type-c dongles can take some time to boot and be 4574 * responsible, so here giving some time to those dongles to power up 4575 * and then retrying the probe. 4576 * 4577 * On many platforms the HDMI live state signal is known to be 4578 * unreliable, so we can't use it to detect if a sink is connected or 4579 * not. Instead we detect if it's connected based on whether we can 4580 * read the EDID or not. That in turn has a problem during disconnect, 4581 * since the HPD interrupt may be raised before the DDC lines get 4582 * disconnected (due to how the required length of DDC vs. HPD 4583 * connector pins are specified) and so we'll still be able to get a 4584 * valid EDID. To solve this schedule another detection cycle if this 4585 * time around we didn't detect any change in the sink's connection 4586 * status. 4587 * 4588 * Type-c connectors which get their HPD signal deasserted then 4589 * reasserted, without unplugging/replugging the sink from the 4590 * connector, introduce a delay until the AUX channel communication 4591 * becomes functional. Retry the detection for 5 seconds on type-c 4592 * connectors to account for this delay. 4593 */ 4594 if (state == INTEL_HOTPLUG_UNCHANGED && 4595 connector->hotplug_retries < (is_tc ? 5 : 1) && 4596 !dig_port->dp.is_mst) 4597 state = INTEL_HOTPLUG_RETRY; 4598 4599 return state; 4600 } 4601 4602 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4603 { 4604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4605 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4606 4607 return intel_de_read(dev_priv, SDEISR) & bit; 4608 } 4609 4610 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4611 { 4612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4613 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4614 4615 return intel_de_read(dev_priv, DEISR) & bit; 4616 } 4617 4618 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4619 { 4620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4621 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4622 4623 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4624 } 4625 4626 static struct intel_connector * 4627 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4628 { 4629 struct intel_connector *connector; 4630 enum port port = dig_port->base.port; 4631 4632 connector = intel_connector_alloc(); 4633 if (!connector) 4634 return NULL; 4635 4636 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4637 intel_hdmi_init_connector(dig_port, connector); 4638 4639 return connector; 4640 } 4641 4642 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4643 { 4644 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4645 4646 if (dig_port->base.port != PORT_A) 4647 return false; 4648 4649 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4650 return false; 4651 4652 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4653 * supported configuration 4654 */ 4655 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4656 return true; 4657 4658 return false; 4659 } 4660 4661 static int 4662 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4663 { 4664 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4665 enum port port = dig_port->base.port; 4666 int max_lanes = 4; 4667 4668 if (DISPLAY_VER(dev_priv) >= 11) 4669 return max_lanes; 4670 4671 if (port == PORT_A || port == PORT_E) { 4672 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4673 max_lanes = port == PORT_A ? 4 : 0; 4674 else 4675 /* Both A and E share 2 lanes */ 4676 max_lanes = 2; 4677 } 4678 4679 /* 4680 * Some BIOS might fail to set this bit on port A if eDP 4681 * wasn't lit up at boot. Force this bit set when needed 4682 * so we use the proper lane count for our calculations. 4683 */ 4684 if (intel_ddi_a_force_4_lanes(dig_port)) { 4685 drm_dbg_kms(&dev_priv->drm, 4686 "Forcing DDI_A_4_LANES for port A\n"); 4687 dig_port->saved_port_bits |= DDI_A_4_LANES; 4688 max_lanes = 4; 4689 } 4690 4691 return max_lanes; 4692 } 4693 4694 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4695 enum port port) 4696 { 4697 if (port >= PORT_D_XELPD) 4698 return HPD_PORT_D + port - PORT_D_XELPD; 4699 else if (port >= PORT_TC1) 4700 return HPD_PORT_TC1 + port - PORT_TC1; 4701 else 4702 return HPD_PORT_A + port - PORT_A; 4703 } 4704 4705 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4706 enum port port) 4707 { 4708 if (port >= PORT_TC1) 4709 return HPD_PORT_C + port - PORT_TC1; 4710 else 4711 return HPD_PORT_A + port - PORT_A; 4712 } 4713 4714 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4715 enum port port) 4716 { 4717 if (port >= PORT_TC1) 4718 return HPD_PORT_TC1 + port - PORT_TC1; 4719 else 4720 return HPD_PORT_A + port - PORT_A; 4721 } 4722 4723 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4724 enum port port) 4725 { 4726 if (HAS_PCH_TGP(dev_priv)) 4727 return tgl_hpd_pin(dev_priv, port); 4728 4729 if (port >= PORT_TC1) 4730 return HPD_PORT_C + port - PORT_TC1; 4731 else 4732 return HPD_PORT_A + port - PORT_A; 4733 } 4734 4735 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4736 enum port port) 4737 { 4738 if (port >= PORT_C) 4739 return HPD_PORT_TC1 + port - PORT_C; 4740 else 4741 return HPD_PORT_A + port - PORT_A; 4742 } 4743 4744 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4745 enum port port) 4746 { 4747 if (port == PORT_D) 4748 return HPD_PORT_A; 4749 4750 if (HAS_PCH_TGP(dev_priv)) 4751 return icl_hpd_pin(dev_priv, port); 4752 4753 return HPD_PORT_A + port - PORT_A; 4754 } 4755 4756 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4757 { 4758 if (HAS_PCH_TGP(dev_priv)) 4759 return icl_hpd_pin(dev_priv, port); 4760 4761 return HPD_PORT_A + port - PORT_A; 4762 } 4763 4764 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4765 { 4766 if (DISPLAY_VER(i915) >= 12) 4767 return port >= PORT_TC1; 4768 else if (DISPLAY_VER(i915) >= 11) 4769 return port >= PORT_C; 4770 else 4771 return false; 4772 } 4773 4774 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4775 { 4776 intel_dp_encoder_suspend(encoder); 4777 } 4778 4779 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4780 { 4781 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4783 4784 /* 4785 * TODO: Move this to intel_dp_encoder_suspend(), 4786 * once modeset locking around that is removed. 4787 */ 4788 intel_encoder_link_check_flush_work(encoder); 4789 intel_tc_port_suspend(dig_port); 4790 } 4791 4792 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4793 { 4794 intel_dp_encoder_shutdown(encoder); 4795 intel_hdmi_encoder_shutdown(encoder); 4796 } 4797 4798 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4799 { 4800 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4801 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4802 4803 intel_tc_port_cleanup(dig_port); 4804 } 4805 4806 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4807 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4808 4809 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4810 { 4811 /* straps not used on skl+ */ 4812 if (DISPLAY_VER(i915) >= 9) 4813 return true; 4814 4815 switch (port) { 4816 case PORT_A: 4817 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4818 case PORT_B: 4819 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4820 case PORT_C: 4821 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4822 case PORT_D: 4823 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4824 case PORT_E: 4825 return true; /* no strap for DDI-E */ 4826 default: 4827 MISSING_CASE(port); 4828 return false; 4829 } 4830 } 4831 4832 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4833 { 4834 return init_dp || intel_encoder_is_tc(encoder); 4835 } 4836 4837 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4838 { 4839 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4840 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4841 "Platform does not support DSI\n"); 4842 } 4843 4844 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4845 { 4846 struct intel_encoder *encoder; 4847 4848 for_each_intel_encoder(&i915->drm, encoder) { 4849 /* FIXME what about second port for dual link DSI? */ 4850 if (encoder->port == port) 4851 return true; 4852 } 4853 4854 return false; 4855 } 4856 4857 void intel_ddi_init(struct intel_display *display, 4858 const struct intel_bios_encoder_data *devdata) 4859 { 4860 struct drm_i915_private *dev_priv = to_i915(display->drm); 4861 struct intel_digital_port *dig_port; 4862 struct intel_encoder *encoder; 4863 bool init_hdmi, init_dp; 4864 enum port port; 4865 enum phy phy; 4866 4867 port = intel_bios_encoder_port(devdata); 4868 if (port == PORT_NONE) 4869 return; 4870 4871 if (!port_strap_detected(dev_priv, port)) { 4872 drm_dbg_kms(&dev_priv->drm, 4873 "Port %c strap not detected\n", port_name(port)); 4874 return; 4875 } 4876 4877 if (!assert_port_valid(dev_priv, port)) 4878 return; 4879 4880 if (port_in_use(dev_priv, port)) { 4881 drm_dbg_kms(&dev_priv->drm, 4882 "Port %c already claimed\n", port_name(port)); 4883 return; 4884 } 4885 4886 if (intel_bios_encoder_supports_dsi(devdata)) { 4887 /* BXT/GLK handled elsewhere, for now at least */ 4888 if (!assert_has_icl_dsi(dev_priv)) 4889 return; 4890 4891 icl_dsi_init(dev_priv, devdata); 4892 return; 4893 } 4894 4895 phy = intel_port_to_phy(dev_priv, port); 4896 4897 /* 4898 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4899 * have taken over some of the PHYs and made them unavailable to the 4900 * driver. In that case we should skip initializing the corresponding 4901 * outputs. 4902 */ 4903 if (intel_hti_uses_phy(display, phy)) { 4904 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4905 port_name(port), phy_name(phy)); 4906 return; 4907 } 4908 4909 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4910 intel_bios_encoder_supports_hdmi(devdata); 4911 init_dp = intel_bios_encoder_supports_dp(devdata); 4912 4913 if (intel_bios_encoder_is_lspcon(devdata)) { 4914 /* 4915 * Lspcon device needs to be driven with DP connector 4916 * with special detection sequence. So make sure DP 4917 * is initialized before lspcon. 4918 */ 4919 init_dp = true; 4920 init_hdmi = false; 4921 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4922 port_name(port)); 4923 } 4924 4925 if (!init_dp && !init_hdmi) { 4926 drm_dbg_kms(&dev_priv->drm, 4927 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4928 port_name(port)); 4929 return; 4930 } 4931 4932 if (intel_phy_is_snps(dev_priv, phy) && 4933 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4934 drm_dbg_kms(&dev_priv->drm, 4935 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4936 phy_name(phy)); 4937 } 4938 4939 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4940 if (!dig_port) 4941 return; 4942 4943 dig_port->aux_ch = AUX_CH_NONE; 4944 4945 encoder = &dig_port->base; 4946 encoder->devdata = devdata; 4947 4948 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4949 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4950 DRM_MODE_ENCODER_TMDS, 4951 "DDI %c/PHY %c", 4952 port_name(port - PORT_D_XELPD + PORT_D), 4953 phy_name(phy)); 4954 } else if (DISPLAY_VER(dev_priv) >= 12) { 4955 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4956 4957 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4958 DRM_MODE_ENCODER_TMDS, 4959 "DDI %s%c/PHY %s%c", 4960 port >= PORT_TC1 ? "TC" : "", 4961 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4962 tc_port != TC_PORT_NONE ? "TC" : "", 4963 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4964 } else if (DISPLAY_VER(dev_priv) >= 11) { 4965 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4966 4967 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4968 DRM_MODE_ENCODER_TMDS, 4969 "DDI %c%s/PHY %s%c", 4970 port_name(port), 4971 port >= PORT_C ? " (TC)" : "", 4972 tc_port != TC_PORT_NONE ? "TC" : "", 4973 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4974 } else { 4975 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4976 DRM_MODE_ENCODER_TMDS, 4977 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4978 } 4979 4980 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 4981 4982 mutex_init(&dig_port->hdcp_mutex); 4983 dig_port->num_hdcp_streams = 0; 4984 4985 encoder->hotplug = intel_ddi_hotplug; 4986 encoder->compute_output_type = intel_ddi_compute_output_type; 4987 encoder->compute_config = intel_ddi_compute_config; 4988 encoder->compute_config_late = intel_ddi_compute_config_late; 4989 encoder->enable = intel_enable_ddi; 4990 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4991 encoder->pre_enable = intel_ddi_pre_enable; 4992 encoder->disable = intel_disable_ddi; 4993 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4994 encoder->post_disable = intel_ddi_post_disable; 4995 encoder->update_pipe = intel_ddi_update_pipe; 4996 encoder->audio_enable = intel_audio_codec_enable; 4997 encoder->audio_disable = intel_audio_codec_disable; 4998 encoder->get_hw_state = intel_ddi_get_hw_state; 4999 encoder->sync_state = intel_ddi_sync_state; 5000 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5001 encoder->suspend = intel_ddi_encoder_suspend; 5002 encoder->shutdown = intel_ddi_encoder_shutdown; 5003 encoder->get_power_domains = intel_ddi_get_power_domains; 5004 5005 encoder->type = INTEL_OUTPUT_DDI; 5006 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5007 encoder->port = port; 5008 encoder->cloneable = 0; 5009 encoder->pipe_mask = ~0; 5010 5011 if (DISPLAY_VER(dev_priv) >= 14) { 5012 encoder->enable_clock = intel_mtl_pll_enable; 5013 encoder->disable_clock = intel_mtl_pll_disable; 5014 encoder->port_pll_type = intel_mtl_port_pll_type; 5015 encoder->get_config = mtl_ddi_get_config; 5016 } else if (IS_DG2(dev_priv)) { 5017 encoder->enable_clock = intel_mpllb_enable; 5018 encoder->disable_clock = intel_mpllb_disable; 5019 encoder->get_config = dg2_ddi_get_config; 5020 } else if (IS_ALDERLAKE_S(dev_priv)) { 5021 encoder->enable_clock = adls_ddi_enable_clock; 5022 encoder->disable_clock = adls_ddi_disable_clock; 5023 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5024 encoder->get_config = adls_ddi_get_config; 5025 } else if (IS_ROCKETLAKE(dev_priv)) { 5026 encoder->enable_clock = rkl_ddi_enable_clock; 5027 encoder->disable_clock = rkl_ddi_disable_clock; 5028 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5029 encoder->get_config = rkl_ddi_get_config; 5030 } else if (IS_DG1(dev_priv)) { 5031 encoder->enable_clock = dg1_ddi_enable_clock; 5032 encoder->disable_clock = dg1_ddi_disable_clock; 5033 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5034 encoder->get_config = dg1_ddi_get_config; 5035 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5036 if (intel_ddi_is_tc(dev_priv, port)) { 5037 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5038 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5039 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5040 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5041 encoder->get_config = icl_ddi_combo_get_config; 5042 } else { 5043 encoder->enable_clock = icl_ddi_combo_enable_clock; 5044 encoder->disable_clock = icl_ddi_combo_disable_clock; 5045 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5046 encoder->get_config = icl_ddi_combo_get_config; 5047 } 5048 } else if (DISPLAY_VER(dev_priv) >= 11) { 5049 if (intel_ddi_is_tc(dev_priv, port)) { 5050 encoder->enable_clock = icl_ddi_tc_enable_clock; 5051 encoder->disable_clock = icl_ddi_tc_disable_clock; 5052 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5053 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5054 encoder->get_config = icl_ddi_tc_get_config; 5055 } else { 5056 encoder->enable_clock = icl_ddi_combo_enable_clock; 5057 encoder->disable_clock = icl_ddi_combo_disable_clock; 5058 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5059 encoder->get_config = icl_ddi_combo_get_config; 5060 } 5061 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5062 /* BXT/GLK have fixed PLL->port mapping */ 5063 encoder->get_config = bxt_ddi_get_config; 5064 } else if (DISPLAY_VER(dev_priv) == 9) { 5065 encoder->enable_clock = skl_ddi_enable_clock; 5066 encoder->disable_clock = skl_ddi_disable_clock; 5067 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5068 encoder->get_config = skl_ddi_get_config; 5069 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5070 encoder->enable_clock = hsw_ddi_enable_clock; 5071 encoder->disable_clock = hsw_ddi_disable_clock; 5072 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5073 encoder->get_config = hsw_ddi_get_config; 5074 } 5075 5076 if (DISPLAY_VER(dev_priv) >= 14) { 5077 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5078 } else if (IS_DG2(dev_priv)) { 5079 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5080 } else if (DISPLAY_VER(dev_priv) >= 12) { 5081 if (intel_encoder_is_combo(encoder)) 5082 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5083 else 5084 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5085 } else if (DISPLAY_VER(dev_priv) >= 11) { 5086 if (intel_encoder_is_combo(encoder)) 5087 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5088 else 5089 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5090 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5091 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5092 } else { 5093 encoder->set_signal_levels = hsw_set_signal_levels; 5094 } 5095 5096 intel_ddi_buf_trans_init(encoder); 5097 5098 if (DISPLAY_VER(dev_priv) >= 13) 5099 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5100 else if (IS_DG1(dev_priv)) 5101 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5102 else if (IS_ROCKETLAKE(dev_priv)) 5103 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5104 else if (DISPLAY_VER(dev_priv) >= 12) 5105 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5106 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5107 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5108 else if (DISPLAY_VER(dev_priv) == 11) 5109 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5110 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5111 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5112 else 5113 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5114 5115 if (DISPLAY_VER(dev_priv) >= 11) 5116 dig_port->saved_port_bits = 5117 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5118 & DDI_BUF_PORT_REVERSAL; 5119 else 5120 dig_port->saved_port_bits = 5121 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5122 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5123 5124 if (intel_bios_encoder_lane_reversal(devdata)) 5125 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5126 5127 dig_port->dp.output_reg = INVALID_MMIO_REG; 5128 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5129 5130 if (need_aux_ch(encoder, init_dp)) { 5131 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5132 if (dig_port->aux_ch == AUX_CH_NONE) 5133 goto err; 5134 } 5135 5136 if (intel_encoder_is_tc(encoder)) { 5137 bool is_legacy = 5138 !intel_bios_encoder_supports_typec_usb(devdata) && 5139 !intel_bios_encoder_supports_tbt(devdata); 5140 5141 if (!is_legacy && init_hdmi) { 5142 is_legacy = !init_dp; 5143 5144 drm_dbg_kms(&dev_priv->drm, 5145 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5146 port_name(port), 5147 str_yes_no(init_dp), 5148 is_legacy ? "legacy" : "non-legacy"); 5149 } 5150 5151 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5152 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5153 5154 dig_port->lock = intel_tc_port_lock; 5155 dig_port->unlock = intel_tc_port_unlock; 5156 5157 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5158 goto err; 5159 } 5160 5161 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5162 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5163 5164 if (DISPLAY_VER(dev_priv) >= 11) { 5165 if (intel_encoder_is_tc(encoder)) 5166 dig_port->connected = intel_tc_port_connected; 5167 else 5168 dig_port->connected = lpt_digital_port_connected; 5169 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5170 dig_port->connected = bdw_digital_port_connected; 5171 } else if (DISPLAY_VER(dev_priv) == 9) { 5172 dig_port->connected = lpt_digital_port_connected; 5173 } else if (IS_BROADWELL(dev_priv)) { 5174 if (port == PORT_A) 5175 dig_port->connected = bdw_digital_port_connected; 5176 else 5177 dig_port->connected = lpt_digital_port_connected; 5178 } else if (IS_HASWELL(dev_priv)) { 5179 if (port == PORT_A) 5180 dig_port->connected = hsw_digital_port_connected; 5181 else 5182 dig_port->connected = lpt_digital_port_connected; 5183 } 5184 5185 intel_infoframe_init(dig_port); 5186 5187 if (init_dp) { 5188 if (!intel_ddi_init_dp_connector(dig_port)) 5189 goto err; 5190 5191 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5192 5193 if (dig_port->dp.mso_link_count) 5194 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5195 } 5196 5197 /* 5198 * In theory we don't need the encoder->type check, 5199 * but leave it just in case we have some really bad VBTs... 5200 */ 5201 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5202 if (!intel_ddi_init_hdmi_connector(dig_port)) 5203 goto err; 5204 } 5205 5206 return; 5207 5208 err: 5209 drm_encoder_cleanup(&encoder->base); 5210 kfree(dig_port); 5211 } 5212