1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_TOP_DISPLAY_CFG_TYPES_H__ 6 #define __DML_TOP_DISPLAY_CFG_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 10 #define DML2_MAX_PLANES 8 11 #define DML2_MAX_DCN_PIPES 8 12 #define DML2_MAX_MCACHES 8 // assume plane is going to be supported by a max of 8 mcaches 13 #define DML2_MAX_WRITEBACK 3 14 15 enum dml2_swizzle_mode { 16 dml2_sw_linear, // SW_LINEAR accepts 256 byte aligned pitch and also 128 byte aligned pitch if DCC is not enabled 17 dml2_sw_256b_2d, 18 dml2_sw_4kb_2d, 19 dml2_sw_64kb_2d, 20 dml2_sw_256kb_2d, 21 22 dml2_gfx11_sw_linear, 23 dml2_gfx11_sw_64kb_d, 24 dml2_gfx11_sw_64kb_d_t, 25 dml2_gfx11_sw_64kb_d_x, 26 dml2_gfx11_sw_64kb_r_x, 27 dml2_gfx11_sw_256kb_d_x, 28 dml2_gfx11_sw_256kb_r_x, 29 30 }; 31 32 enum dml2_source_format_class { 33 dml2_444_8 = 0, 34 dml2_444_16 = 1, 35 dml2_444_32 = 2, 36 dml2_444_64 = 3, 37 dml2_420_8 = 4, 38 dml2_420_10 = 5, 39 dml2_420_12 = 6, 40 dml2_rgbe_alpha = 9, 41 dml2_rgbe = 10, 42 dml2_mono_8 = 11, 43 dml2_mono_16 = 12, 44 dml2_422_planar_8 = 13, 45 dml2_422_planar_10 = 14, 46 dml2_422_planar_12 = 15, 47 dml2_422_packed_8 = 16, 48 dml2_422_packed_10 = 17, 49 dml2_422_packed_12 = 18 50 }; 51 52 enum dml2_rotation_angle { 53 dml2_rotation_0 = 0, 54 dml2_rotation_90 = 1, 55 dml2_rotation_180 = 2, 56 dml2_rotation_270 = 3 57 }; 58 59 enum dml2_output_format_class { 60 dml2_444 = 0, 61 dml2_s422 = 1, 62 dml2_n422 = 2, 63 dml2_420 = 3 64 }; 65 66 enum dml2_output_encoder_class { 67 dml2_dp = 0, 68 dml2_edp = 1, 69 dml2_dp2p0 = 2, 70 dml2_hdmi = 3, 71 dml2_hdmifrl = 4, 72 dml2_none = 5 73 }; 74 75 enum dml2_output_link_dp_rate { 76 dml2_dp_rate_na = 0, 77 dml2_dp_rate_hbr = 1, 78 dml2_dp_rate_hbr2 = 2, 79 dml2_dp_rate_hbr3 = 3, 80 dml2_dp_rate_uhbr10 = 4, 81 dml2_dp_rate_uhbr13p5 = 5, 82 dml2_dp_rate_uhbr20 = 6 83 }; 84 85 enum dml2_uclk_pstate_change_strategy { 86 dml2_uclk_pstate_change_strategy_auto = 0, 87 dml2_uclk_pstate_change_strategy_force_vactive = 1, 88 dml2_uclk_pstate_change_strategy_force_vblank = 2, 89 dml2_uclk_pstate_change_strategy_force_drr = 3, 90 dml2_uclk_pstate_change_strategy_force_mall_svp = 4, 91 dml2_uclk_pstate_change_strategy_force_mall_full_frame = 5, 92 }; 93 94 enum dml2_svp_mode_override { 95 dml2_svp_mode_override_auto = 0, 96 dml2_svp_mode_override_main_pipe = 1, 97 dml2_svp_mode_override_phantom_pipe = 2, //does not need to be defined explicitly, main overrides result in implicit phantom additions 98 dml2_svp_mode_override_phantom_pipe_no_data_return = 3, 99 dml2_svp_mode_override_imall = 4 100 }; 101 102 enum dml2_refresh_from_mall_mode_override { 103 dml2_refresh_from_mall_mode_override_auto = 0, 104 dml2_refresh_from_mall_mode_override_force_disable = 1, 105 dml2_refresh_from_mall_mode_override_force_enable = 2 106 }; 107 108 enum dml2_odm_mode { 109 dml2_odm_mode_auto = 0, 110 dml2_odm_mode_bypass, 111 dml2_odm_mode_combine_2to1, 112 dml2_odm_mode_combine_3to1, 113 dml2_odm_mode_combine_4to1, 114 dml2_odm_mode_split_1to2, 115 dml2_odm_mode_mso_1to2, 116 dml2_odm_mode_mso_1to4 117 }; 118 119 enum dml2_scaling_transform { 120 dml2_scaling_transform_explicit = 0, 121 dml2_scaling_transform_fullscreen, 122 dml2_scaling_transform_aspect_ratio, 123 dml2_scaling_transform_centered 124 }; 125 126 enum dml2_dsc_enable_option { 127 dml2_dsc_disable = 0, 128 dml2_dsc_enable = 1, 129 dml2_dsc_enable_if_necessary = 2 130 }; 131 132 enum dml2_tdlut_addressing_mode { 133 dml2_tdlut_sw_linear = 0, 134 dml2_tdlut_simple_linear = 1 135 }; 136 137 enum dml2_tdlut_width_mode { 138 dml2_tdlut_width_17_cube = 0, 139 dml2_tdlut_width_33_cube = 1 140 }; 141 142 enum dml2_twait_budgeting_setting { 143 dml2_twait_budgeting_setting_ignore = 0,// Ignore this budget in twait 144 145 dml2_twait_budgeting_setting_if_needed, // Budget for it only if needed 146 //(i.e. UCLK/FCLK DPM cannot be supported in active) 147 148 dml2_twait_budgeting_setting_try, // Budget for it as long as there is an SoC state that 149 // can support it 150 }; 151 152 struct dml2_get_cursor_dlg_reg{ 153 unsigned int cursor_x_position; 154 unsigned int cursor_hotspot_x; 155 unsigned int cursor_primary_offset; 156 unsigned int cursor_secondary_offset; 157 bool cursor_stereo_en; 158 bool cursor_2x_magnify; 159 double hratio; 160 double pixel_rate_mhz; 161 double dlg_refclk_mhz; 162 }; 163 164 /// @brief Surface Parameters 165 struct dml2_surface_cfg { 166 enum dml2_swizzle_mode tiling; 167 168 struct { 169 unsigned long pitch; 170 unsigned long width; 171 unsigned long height; 172 } plane0; 173 174 175 struct { 176 unsigned long pitch; 177 unsigned long width; 178 unsigned long height; 179 } plane1; 180 181 struct { 182 bool enable; 183 struct { 184 unsigned long pitch; 185 } plane0; 186 struct { 187 unsigned long pitch; 188 } plane1; 189 190 struct { 191 double dcc_rate_plane0; 192 double dcc_rate_plane1; 193 double fraction_of_zero_size_request_plane0; 194 double fraction_of_zero_size_request_plane1; 195 } informative; 196 } dcc; 197 }; 198 199 200 struct dml2_composition_cfg { 201 enum dml2_rotation_angle rotation_angle; 202 bool mirrored; 203 enum dml2_scaling_transform scaling_transform; 204 bool rect_out_height_spans_vactive; 205 206 struct { 207 bool stationary; 208 struct { 209 unsigned long width; 210 unsigned long height; 211 unsigned long x_start; 212 unsigned long y_start; 213 } plane0; 214 215 struct { 216 unsigned long width; 217 unsigned long height; 218 unsigned long x_start; 219 unsigned long y_start; 220 } plane1; 221 } viewport; 222 223 struct { 224 bool enabled; 225 struct { 226 double h_ratio; 227 double v_ratio; 228 unsigned int h_taps; 229 unsigned int v_taps; 230 } plane0; 231 232 struct { 233 double h_ratio; 234 double v_ratio; 235 unsigned int h_taps; 236 unsigned int v_taps; 237 } plane1; 238 239 unsigned long rect_out_width; 240 } scaler_info; 241 }; 242 243 struct dml2_timing_cfg { 244 unsigned long h_total; 245 unsigned long v_total; 246 unsigned long h_blank_end; 247 unsigned long v_blank_end; 248 unsigned long h_front_porch; 249 unsigned long v_front_porch; 250 unsigned long h_sync_width; 251 unsigned long pixel_clock_khz; 252 unsigned long h_active; 253 unsigned long v_active; 254 unsigned int bpc; //FIXME: review with Jun 255 struct { 256 enum dml2_dsc_enable_option enable; 257 unsigned int dsc_compressed_bpp_x16; 258 struct { 259 // for dv to specify num dsc slices to use 260 unsigned int num_slices; 261 } overrides; 262 } dsc; 263 bool interlaced; 264 struct { 265 /* static */ 266 bool enabled; 267 unsigned long min_refresh_uhz; 268 unsigned int max_instant_vtotal_delta; 269 /* dynamic */ 270 bool disallowed; 271 bool drr_active_variable; 272 bool drr_active_fixed; 273 } drr_config; 274 unsigned long vblank_nom; 275 }; 276 277 struct dml2_link_output_cfg { 278 enum dml2_output_format_class output_format; 279 enum dml2_output_encoder_class output_encoder; 280 unsigned int output_dp_lane_count; 281 enum dml2_output_link_dp_rate output_dp_link_rate; 282 unsigned long audio_sample_rate; 283 unsigned long audio_sample_layout; 284 bool output_disabled; // The stream does not go to a backend for output to a physical 285 //connector (e.g. writeback only, phantom pipe) goes to writeback 286 bool validate_output; // Do not validate the link configuration for this display stream. 287 }; 288 289 struct dml2_writeback_info { 290 enum dml2_source_format_class pixel_format; 291 unsigned long input_width; 292 unsigned long input_height; 293 unsigned long output_width; 294 unsigned long output_height; 295 unsigned long v_taps; 296 unsigned long h_taps; 297 unsigned long v_taps_chroma; 298 unsigned long h_taps_chroma; 299 double h_ratio; 300 double v_ratio; 301 }; 302 303 struct dml2_writeback_cfg { 304 unsigned int active_writebacks_per_stream; 305 struct dml2_writeback_info writeback_stream[DML2_MAX_WRITEBACK]; 306 }; 307 308 struct dml2_plane_parameters { 309 unsigned int stream_index; // Identifies which plane will be composed 310 311 enum dml2_source_format_class pixel_format; 312 /* 313 * The surface and composition structures use 314 * the terms plane0 and plane1. These planes 315 * are expected to hold the following data based 316 * on the pixel format. 317 * 318 * RGB or YUV Non-Planar Types: 319 * dml2_444_8 320 * dml2_444_16 321 * dml2_444_32 322 * dml2_444_64 323 * dml2_rgbe 324 * 325 * plane0 = argb or rgbe 326 * plane1 = not used 327 * 328 * YUV Planar-Types: 329 * dml2_420_8 330 * dml2_420_10 331 * dml2_420_12 332 * 333 * plane0 = luma 334 * plane1 = chroma 335 * 336 * RGB Planar Types: 337 * dml2_rgbe_alpha 338 * 339 * plane0 = rgbe 340 * plane1 = alpha 341 * 342 * Mono Non-Planar Types: 343 * dml2_mono_8 344 * dml2_mono_16 345 * 346 * plane0 = luma 347 * plane1 = not used 348 */ 349 350 struct dml2_surface_cfg surface; 351 struct dml2_composition_cfg composition; 352 353 struct { 354 bool enable; 355 unsigned long lines_before_active_required; 356 unsigned long transmitted_bytes; 357 } dynamic_meta_data; 358 359 struct { 360 unsigned int num_cursors; 361 unsigned long cursor_width; 362 unsigned long cursor_bpp; 363 } cursor; 364 365 // For TDLUT, SW would assume TDLUT is setup and enable all the time and 366 // budget for worst case addressing/width mode 367 struct { 368 bool setup_for_tdlut; 369 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 370 enum dml2_tdlut_width_mode tdlut_width_mode; 371 bool tdlut_mpc_width_flag; 372 } tdlut; 373 374 bool immediate_flip; 375 376 struct { 377 // Logical overrides to power management policies (usually) 378 enum dml2_uclk_pstate_change_strategy uclk_pstate_change_strategy; 379 enum dml2_refresh_from_mall_mode_override refresh_from_mall; 380 unsigned int det_size_override_kb; 381 unsigned int mpcc_combine_factor; 382 383 // reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait 384 // The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override. 385 long reserved_vblank_time_ns; 386 unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay 387 unsigned int gpuvm_min_page_size_kbytes; 388 389 enum dml2_svp_mode_override legacy_svp_config; //TODO remove in favor of svp_config 390 391 struct { 392 // HW specific overrides, there's almost no reason to mess with these 393 // generally used for debugging or simulation 394 bool force_one_row_for_frame; 395 struct { 396 bool enable; 397 bool value; 398 } force_pte_buffer_mode; 399 double dppclk_mhz; 400 } hw; 401 } overrides; 402 }; 403 404 struct dml2_stream_parameters { 405 struct dml2_timing_cfg timing; 406 struct dml2_link_output_cfg output; 407 struct dml2_writeback_cfg writeback; 408 409 struct { 410 enum dml2_odm_mode odm_mode; 411 bool disable_dynamic_odm; 412 bool disable_subvp; 413 int minimum_vblank_idle_requirement_us; 414 bool minimize_active_latency_hiding; 415 416 struct { 417 struct { 418 enum dml2_twait_budgeting_setting uclk_pstate; 419 enum dml2_twait_budgeting_setting fclk_pstate; 420 enum dml2_twait_budgeting_setting stutter_enter_exit; 421 } twait_budgeting; 422 } hw; 423 } overrides; 424 }; 425 426 struct dml2_display_cfg { 427 bool gpuvm_enable; 428 bool hostvm_enable; 429 430 // Allocate DET proportionally between streams based on pixel rate 431 // and then allocate proportionally between planes. 432 bool minimize_det_reallocation; 433 434 unsigned int gpuvm_max_page_table_levels; 435 unsigned int hostvm_max_non_cached_page_table_levels; 436 437 struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES]; 438 struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES]; 439 440 unsigned int num_planes; 441 unsigned int num_streams; 442 443 struct { 444 struct { 445 // HW specific overrides, there's almost no reason to mess with these 446 // generally used for debugging or simulation 447 struct { 448 bool enable; 449 bool value; 450 } force_unbounded_requesting; 451 452 struct { 453 bool enable; 454 bool value; 455 } force_nom_det_size_kbytes; 456 bool mode_support_check_disable; 457 bool mcache_admissibility_check_disable; 458 bool surface_viewport_size_check_disable; 459 double dlg_ref_clk_mhz; 460 double dispclk_mhz; 461 double dcfclk_mhz; 462 bool optimize_tdlut_scheduling; // TBD: for DV, will set this to 1, to ensure tdlut schedule is calculated based on address/width mode 463 } hw; 464 465 struct { 466 bool uclk_pstate_change_disable; 467 bool fclk_pstate_change_disable; 468 bool g6_temp_read_pstate_disable; 469 bool g7_ppt_pstate_disable; 470 } power_management; 471 472 bool enhanced_prefetch_schedule_acceleration; 473 bool dcc_programming_assumes_scan_direction_unknown; 474 bool synchronize_timings; 475 bool synchronize_ddr_displays_for_uclk_pstate_change; 476 bool max_outstanding_when_urgent_expected_disable; 477 bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming 478 unsigned int best_effort_min_active_latency_hiding_us; 479 bool all_streams_blanked; 480 } overrides; 481 }; 482 483 struct dml2_pipe_configuration_descriptor { 484 struct { 485 unsigned int viewport_x_start; 486 unsigned int viewport_width; 487 } plane0; 488 489 struct { 490 unsigned int viewport_x_start; 491 unsigned int viewport_width; 492 } plane1; 493 494 bool plane1_enabled; 495 bool imall_enabled; 496 }; 497 498 struct dml2_plane_mcache_configuration_descriptor { 499 const struct dml2_plane_parameters *plane_descriptor; 500 const struct dml2_mcache_surface_allocation *mcache_allocation; 501 502 struct dml2_pipe_configuration_descriptor pipe_configurations[DML2_MAX_DCN_PIPES]; 503 char num_pipes; 504 }; 505 506 #endif 507