1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate)
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * TI Common Platform Ethernet Switch (CPSW) Driver
32 * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs.
33 *
34 * This controller is documented in the AM335x Technical Reference
35 * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM
36 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM.
37 *
38 * It is basically a single Ethernet port (port 0) wired internally to
39 * a 3-port store-and-forward switch connected to two independent
40 * "sliver" controllers (port 1 and port 2). You can operate the
41 * controller in a variety of different ways by suitably configuring
42 * the slivers and the Address Lookup Engine (ALE) that routes packets
43 * between the ports.
44 *
45 * This code was developed and tested on a BeagleBone with
46 * an AM335x SoC.
47 */
48
49 #include <sys/cdefs.h>
50 #include "opt_cpsw.h"
51
52 #include <sys/param.h>
53 #include <sys/bus.h>
54 #include <sys/kernel.h>
55 #include <sys/lock.h>
56 #include <sys/mbuf.h>
57 #include <sys/module.h>
58 #include <sys/mutex.h>
59 #include <sys/rman.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/sysctl.h>
63
64 #include <machine/bus.h>
65 #include <machine/resource.h>
66 #include <machine/stdarg.h>
67
68 #include <net/ethernet.h>
69 #include <net/bpf.h>
70 #include <net/if.h>
71 #include <net/if_dl.h>
72 #include <net/if_media.h>
73 #include <net/if_types.h>
74
75 #include <dev/syscon/syscon.h>
76 #include "syscon_if.h"
77 #include <arm/ti/am335x/am335x_scm.h>
78
79 #include <dev/mii/mii.h>
80 #include <dev/mii/miivar.h>
81
82 #include <dev/ofw/ofw_bus.h>
83 #include <dev/ofw/ofw_bus_subr.h>
84
85 #include <dev/fdt/fdt_common.h>
86
87 #ifdef CPSW_ETHERSWITCH
88 #include <dev/etherswitch/etherswitch.h>
89 #include "etherswitch_if.h"
90 #endif
91
92 #include "if_cpswreg.h"
93 #include "if_cpswvar.h"
94
95 #include "miibus_if.h"
96
97 /* Device probe/attach/detach. */
98 static int cpsw_probe(device_t);
99 static int cpsw_attach(device_t);
100 static int cpsw_detach(device_t);
101 static int cpswp_probe(device_t);
102 static int cpswp_attach(device_t);
103 static int cpswp_detach(device_t);
104
105 static phandle_t cpsw_get_node(device_t, device_t);
106
107 /* Device Init/shutdown. */
108 static int cpsw_shutdown(device_t);
109 static void cpswp_init(void *);
110 static void cpswp_init_locked(void *);
111 static void cpswp_stop_locked(struct cpswp_softc *);
112
113 /* Device Suspend/Resume. */
114 static int cpsw_suspend(device_t);
115 static int cpsw_resume(device_t);
116
117 /* Ioctl. */
118 static int cpswp_ioctl(if_t, u_long command, caddr_t data);
119
120 static int cpswp_miibus_readreg(device_t, int phy, int reg);
121 static int cpswp_miibus_writereg(device_t, int phy, int reg, int value);
122 static void cpswp_miibus_statchg(device_t);
123
124 /* Send/Receive packets. */
125 static void cpsw_intr_rx(void *arg);
126 static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *);
127 static void cpsw_rx_enqueue(struct cpsw_softc *);
128 static void cpswp_start(if_t);
129 static void cpsw_intr_tx(void *);
130 static void cpswp_tx_enqueue(struct cpswp_softc *);
131 static int cpsw_tx_dequeue(struct cpsw_softc *);
132
133 /* Misc interrupts and watchdog. */
134 static void cpsw_intr_rx_thresh(void *);
135 static void cpsw_intr_misc(void *);
136 static void cpswp_tick(void *);
137 static void cpswp_ifmedia_sts(if_t, struct ifmediareq *);
138 static int cpswp_ifmedia_upd(if_t);
139 static void cpsw_tx_watchdog(void *);
140
141 /* ALE support */
142 static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *);
143 static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *);
144 static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *);
145 static void cpsw_ale_dump_table(struct cpsw_softc *);
146 static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int,
147 int);
148 static int cpswp_ale_update_addresses(struct cpswp_softc *, int);
149
150 /* Statistics and sysctls. */
151 static void cpsw_add_sysctls(struct cpsw_softc *);
152 static void cpsw_stats_collect(struct cpsw_softc *);
153 static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS);
154
155 #ifdef CPSW_ETHERSWITCH
156 static etherswitch_info_t *cpsw_getinfo(device_t);
157 static int cpsw_getport(device_t, etherswitch_port_t *);
158 static int cpsw_setport(device_t, etherswitch_port_t *);
159 static int cpsw_getconf(device_t, etherswitch_conf_t *);
160 static int cpsw_getvgroup(device_t, etherswitch_vlangroup_t *);
161 static int cpsw_setvgroup(device_t, etherswitch_vlangroup_t *);
162 static int cpsw_readreg(device_t, int);
163 static int cpsw_writereg(device_t, int, int);
164 static int cpsw_readphy(device_t, int, int);
165 static int cpsw_writephy(device_t, int, int, int);
166 #endif
167
168 /*
169 * Arbitrary limit on number of segments in an mbuf to be transmitted.
170 * Packets with more segments than this will be defragmented before
171 * they are queued.
172 */
173 #define CPSW_TXFRAGS 16
174
175 /* Shared resources. */
176 static device_method_t cpsw_methods[] = {
177 /* Device interface */
178 DEVMETHOD(device_probe, cpsw_probe),
179 DEVMETHOD(device_attach, cpsw_attach),
180 DEVMETHOD(device_detach, cpsw_detach),
181 DEVMETHOD(device_shutdown, cpsw_shutdown),
182 DEVMETHOD(device_suspend, cpsw_suspend),
183 DEVMETHOD(device_resume, cpsw_resume),
184 /* Bus interface */
185 DEVMETHOD(bus_add_child, device_add_child_ordered),
186 /* OFW methods */
187 DEVMETHOD(ofw_bus_get_node, cpsw_get_node),
188 #ifdef CPSW_ETHERSWITCH
189 /* etherswitch interface */
190 DEVMETHOD(etherswitch_getinfo, cpsw_getinfo),
191 DEVMETHOD(etherswitch_readreg, cpsw_readreg),
192 DEVMETHOD(etherswitch_writereg, cpsw_writereg),
193 DEVMETHOD(etherswitch_readphyreg, cpsw_readphy),
194 DEVMETHOD(etherswitch_writephyreg, cpsw_writephy),
195 DEVMETHOD(etherswitch_getport, cpsw_getport),
196 DEVMETHOD(etherswitch_setport, cpsw_setport),
197 DEVMETHOD(etherswitch_getvgroup, cpsw_getvgroup),
198 DEVMETHOD(etherswitch_setvgroup, cpsw_setvgroup),
199 DEVMETHOD(etherswitch_getconf, cpsw_getconf),
200 #endif
201 DEVMETHOD_END
202 };
203
204 static driver_t cpsw_driver = {
205 "cpswss",
206 cpsw_methods,
207 sizeof(struct cpsw_softc),
208 };
209
210 DRIVER_MODULE(cpswss, simplebus, cpsw_driver, 0, 0);
211
212 /* Port/Slave resources. */
213 static device_method_t cpswp_methods[] = {
214 /* Device interface */
215 DEVMETHOD(device_probe, cpswp_probe),
216 DEVMETHOD(device_attach, cpswp_attach),
217 DEVMETHOD(device_detach, cpswp_detach),
218 /* MII interface */
219 DEVMETHOD(miibus_readreg, cpswp_miibus_readreg),
220 DEVMETHOD(miibus_writereg, cpswp_miibus_writereg),
221 DEVMETHOD(miibus_statchg, cpswp_miibus_statchg),
222 DEVMETHOD_END
223 };
224
225 static driver_t cpswp_driver = {
226 "cpsw",
227 cpswp_methods,
228 sizeof(struct cpswp_softc),
229 };
230
231 #ifdef CPSW_ETHERSWITCH
232 DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, 0, 0);
233 MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1);
234 #endif
235
236 DRIVER_MODULE(cpsw, cpswss, cpswp_driver, 0, 0);
237 DRIVER_MODULE(miibus, cpsw, miibus_driver, 0, 0);
238 MODULE_DEPEND(cpsw, ether, 1, 1, 1);
239 MODULE_DEPEND(cpsw, miibus, 1, 1, 1);
240
241 #ifdef CPSW_ETHERSWITCH
242 static struct cpsw_vlangroups cpsw_vgroups[CPSW_VLANS];
243 #endif
244
245 static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 };
246
247 static struct resource_spec irq_res_spec[] = {
248 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
249 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE },
250 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE },
251 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE },
252 { -1, 0 }
253 };
254
255 static struct {
256 void (*cb)(void *);
257 } cpsw_intr_cb[] = {
258 { cpsw_intr_rx_thresh },
259 { cpsw_intr_rx },
260 { cpsw_intr_tx },
261 { cpsw_intr_misc },
262 };
263
264 /* Number of entries here must match size of stats
265 * array in struct cpswp_softc. */
266 static struct cpsw_stat {
267 int reg;
268 char *oid;
269 } cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = {
270 {0x00, "GoodRxFrames"},
271 {0x04, "BroadcastRxFrames"},
272 {0x08, "MulticastRxFrames"},
273 {0x0C, "PauseRxFrames"},
274 {0x10, "RxCrcErrors"},
275 {0x14, "RxAlignErrors"},
276 {0x18, "OversizeRxFrames"},
277 {0x1c, "RxJabbers"},
278 {0x20, "ShortRxFrames"},
279 {0x24, "RxFragments"},
280 {0x30, "RxOctets"},
281 {0x34, "GoodTxFrames"},
282 {0x38, "BroadcastTxFrames"},
283 {0x3c, "MulticastTxFrames"},
284 {0x40, "PauseTxFrames"},
285 {0x44, "DeferredTxFrames"},
286 {0x48, "CollisionsTxFrames"},
287 {0x4c, "SingleCollisionTxFrames"},
288 {0x50, "MultipleCollisionTxFrames"},
289 {0x54, "ExcessiveCollisions"},
290 {0x58, "LateCollisions"},
291 {0x5c, "TxUnderrun"},
292 {0x60, "CarrierSenseErrors"},
293 {0x64, "TxOctets"},
294 {0x68, "RxTx64OctetFrames"},
295 {0x6c, "RxTx65to127OctetFrames"},
296 {0x70, "RxTx128to255OctetFrames"},
297 {0x74, "RxTx256to511OctetFrames"},
298 {0x78, "RxTx512to1024OctetFrames"},
299 {0x7c, "RxTx1024upOctetFrames"},
300 {0x80, "NetOctets"},
301 {0x84, "RxStartOfFrameOverruns"},
302 {0x88, "RxMiddleOfFrameOverruns"},
303 {0x8c, "RxDmaOverruns"}
304 };
305
306 /*
307 * Basic debug support.
308 */
309
310 static void
cpsw_debugf_head(const char * funcname)311 cpsw_debugf_head(const char *funcname)
312 {
313 int t = (int)(time_second % (24 * 60 * 60));
314
315 printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname);
316 }
317
318 static void
cpsw_debugf(const char * fmt,...)319 cpsw_debugf(const char *fmt, ...)
320 {
321 va_list ap;
322
323 va_start(ap, fmt);
324 vprintf(fmt, ap);
325 va_end(ap);
326 printf("\n");
327
328 }
329
330 #define CPSW_DEBUGF(_sc, a) do { \
331 if ((_sc)->debug) { \
332 cpsw_debugf_head(__func__); \
333 cpsw_debugf a; \
334 } \
335 } while (0)
336
337 /*
338 * Locking macros
339 */
340 #define CPSW_TX_LOCK(sc) do { \
341 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
342 mtx_lock(&(sc)->tx.lock); \
343 } while (0)
344
345 #define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
346 #define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
347
348 #define CPSW_RX_LOCK(sc) do { \
349 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \
350 mtx_lock(&(sc)->rx.lock); \
351 } while (0)
352
353 #define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock)
354 #define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED)
355
356 #define CPSW_PORT_LOCK(_sc) do { \
357 mtx_assert(&(_sc)->lock, MA_NOTOWNED); \
358 mtx_lock(&(_sc)->lock); \
359 } while (0)
360
361 #define CPSW_PORT_UNLOCK(_sc) mtx_unlock(&(_sc)->lock)
362 #define CPSW_PORT_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->lock, MA_OWNED)
363
364 /*
365 * Read/Write macros
366 */
367 #define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg))
368 #define cpsw_write_4(_sc, _reg, _val) \
369 bus_write_4((_sc)->mem_res, (_reg), (_val))
370
371 #define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16))
372
373 #define cpsw_cpdma_bd_paddr(sc, slot) \
374 BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset)
375 #define cpsw_cpdma_read_bd(sc, slot, val) \
376 bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
377 #define cpsw_cpdma_write_bd(sc, slot, val) \
378 bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
379 #define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \
380 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
381 #define cpsw_cpdma_write_bd_flags(sc, slot, val) \
382 bus_write_2(sc->mem_res, slot->bd_offset + 14, val)
383 #define cpsw_cpdma_read_bd_flags(sc, slot) \
384 bus_read_2(sc->mem_res, slot->bd_offset + 14)
385 #define cpsw_write_hdp_slot(sc, queue, slot) \
386 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
387 #define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0))
388 #define cpsw_read_cp(sc, queue) \
389 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET)
390 #define cpsw_write_cp(sc, queue, val) \
391 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
392 #define cpsw_write_cp_slot(sc, queue, slot) \
393 cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot))
394
395 #if 0
396 /* XXX temporary function versions for debugging. */
397 static void
398 cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
399 {
400 uint32_t reg = queue->hdp_offset;
401 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
402 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg)));
403 cpsw_write_4(sc, reg, v);
404 }
405
406 static void
407 cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
408 {
409 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
410 CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue)));
411 cpsw_write_cp(sc, queue, v);
412 }
413 #endif
414
415 /*
416 * Expanded dump routines for verbose debugging.
417 */
418 static void
cpsw_dump_slot(struct cpsw_softc * sc,struct cpsw_slot * slot)419 cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
420 {
421 static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ",
422 "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun",
423 "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1",
424 "Port0"};
425 struct cpsw_cpdma_bd bd;
426 const char *sep;
427 int i;
428
429 cpsw_cpdma_read_bd(sc, slot, &bd);
430 printf("BD Addr : 0x%08x Next : 0x%08x\n",
431 cpsw_cpdma_bd_paddr(sc, slot), bd.next);
432 printf(" BufPtr: 0x%08x BufLen: 0x%08x\n", bd.bufptr, bd.buflen);
433 printf(" BufOff: 0x%08x PktLen: 0x%08x\n", bd.bufoff, bd.pktlen);
434 printf(" Flags: ");
435 sep = "";
436 for (i = 0; i < 16; ++i) {
437 if (bd.flags & (1 << (15 - i))) {
438 printf("%s%s", sep, flags[i]);
439 sep = ",";
440 }
441 }
442 printf("\n");
443 if (slot->mbuf) {
444 printf(" Ether: %14D\n",
445 (char *)(slot->mbuf->m_data), " ");
446 printf(" Packet: %16D\n",
447 (char *)(slot->mbuf->m_data) + 14, " ");
448 }
449 }
450
451 #define CPSW_DUMP_SLOT(cs, slot) do { \
452 IF_DEBUG(sc) { \
453 cpsw_dump_slot(sc, slot); \
454 } \
455 } while (0)
456
457 static void
cpsw_dump_queue(struct cpsw_softc * sc,struct cpsw_slots * q)458 cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q)
459 {
460 struct cpsw_slot *slot;
461 int i = 0;
462 int others = 0;
463
464 STAILQ_FOREACH(slot, q, next) {
465 if (i > CPSW_TXFRAGS)
466 ++others;
467 else
468 cpsw_dump_slot(sc, slot);
469 ++i;
470 }
471 if (others)
472 printf(" ... and %d more.\n", others);
473 printf("\n");
474 }
475
476 #define CPSW_DUMP_QUEUE(sc, q) do { \
477 IF_DEBUG(sc) { \
478 cpsw_dump_queue(sc, q); \
479 } \
480 } while (0)
481
482 static void
cpsw_init_slots(struct cpsw_softc * sc)483 cpsw_init_slots(struct cpsw_softc *sc)
484 {
485 struct cpsw_slot *slot;
486 int i;
487
488 STAILQ_INIT(&sc->avail);
489
490 /* Put the slot descriptors onto the global avail list. */
491 for (i = 0; i < nitems(sc->_slots); i++) {
492 slot = &sc->_slots[i];
493 slot->bd_offset = cpsw_cpdma_bd_offset(i);
494 STAILQ_INSERT_TAIL(&sc->avail, slot, next);
495 }
496 }
497
498 static int
cpsw_add_slots(struct cpsw_softc * sc,struct cpsw_queue * queue,int requested)499 cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested)
500 {
501 const int max_slots = nitems(sc->_slots);
502 struct cpsw_slot *slot;
503 int i;
504
505 if (requested < 0)
506 requested = max_slots;
507
508 for (i = 0; i < requested; ++i) {
509 slot = STAILQ_FIRST(&sc->avail);
510 if (slot == NULL)
511 return (0);
512 if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) {
513 device_printf(sc->dev, "failed to create dmamap\n");
514 return (ENOMEM);
515 }
516 STAILQ_REMOVE_HEAD(&sc->avail, next);
517 STAILQ_INSERT_TAIL(&queue->avail, slot, next);
518 ++queue->avail_queue_len;
519 ++queue->queue_slots;
520 }
521 return (0);
522 }
523
524 static void
cpsw_free_slot(struct cpsw_softc * sc,struct cpsw_slot * slot)525 cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
526 {
527 int error __diagused;
528
529 if (slot->dmamap) {
530 if (slot->mbuf)
531 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
532 error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap);
533 KASSERT(error == 0, ("Mapping still active"));
534 slot->dmamap = NULL;
535 }
536 if (slot->mbuf) {
537 m_freem(slot->mbuf);
538 slot->mbuf = NULL;
539 }
540 }
541
542 static void
cpsw_reset(struct cpsw_softc * sc)543 cpsw_reset(struct cpsw_softc *sc)
544 {
545 int i;
546
547 callout_stop(&sc->watchdog.callout);
548
549 /* Reset RMII/RGMII wrapper. */
550 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
551 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
552 ;
553
554 /* Disable TX and RX interrupts for all cores. */
555 for (i = 0; i < 3; ++i) {
556 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00);
557 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00);
558 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00);
559 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00);
560 }
561
562 /* Reset CPSW subsystem. */
563 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
564 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
565 ;
566
567 /* Reset Sliver port 1 and 2 */
568 for (i = 0; i < 2; i++) {
569 /* Reset */
570 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
571 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
572 ;
573 }
574
575 /* Reset DMA controller. */
576 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
577 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
578 ;
579
580 /* Disable TX & RX DMA */
581 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0);
582 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0);
583
584 /* Clear all queues. */
585 for (i = 0; i < 8; i++) {
586 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
587 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
588 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
589 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
590 }
591
592 /* Clear all interrupt Masks */
593 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
594 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
595 }
596
597 static void
cpsw_init(struct cpsw_softc * sc)598 cpsw_init(struct cpsw_softc *sc)
599 {
600 struct cpsw_slot *slot;
601 uint32_t reg;
602
603 /* Disable the interrupt pacing. */
604 reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
605 reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK);
606 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg);
607
608 /* Clear ALE */
609 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL);
610
611 /* Enable ALE */
612 reg = CPSW_ALE_CTL_ENABLE;
613 if (sc->dualemac)
614 reg |= CPSW_ALE_CTL_VLAN_AWARE;
615 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg);
616
617 /* Set Host Port Mapping. */
618 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
619 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
620
621 /* Initialize ALE: set host port to forwarding(3). */
622 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0),
623 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD);
624
625 cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
626
627 /* Enable statistics for ports 0, 1 and 2 */
628 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
629
630 /* Turn off flow control. */
631 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
632
633 /* Make IP hdr aligned with 4 */
634 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2);
635
636 /* Initialize RX Buffer Descriptors */
637 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0);
638 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
639
640 /* Enable TX & RX DMA */
641 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
642 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
643
644 /* Enable Interrupts for core 0 */
645 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF);
646 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF);
647 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF);
648 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F);
649
650 /* Enable host Error Interrupt */
651 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3);
652
653 /* Enable interrupts for RX and TX on Channel 0 */
654 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET,
655 CPSW_CPDMA_RX_INT(0) | CPSW_CPDMA_RX_INT_THRESH(0));
656 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1);
657
658 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */
659 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */
660 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff);
661
662 /* Select MII in GMII_SEL, Internal Delay mode */
663 //ti_scm_reg_write_4(0x650, 0);
664
665 /* Initialize active queues. */
666 slot = STAILQ_FIRST(&sc->tx.active);
667 if (slot != NULL)
668 cpsw_write_hdp_slot(sc, &sc->tx, slot);
669 slot = STAILQ_FIRST(&sc->rx.active);
670 if (slot != NULL)
671 cpsw_write_hdp_slot(sc, &sc->rx, slot);
672 cpsw_rx_enqueue(sc);
673 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len);
674 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS);
675
676 /* Activate network interface. */
677 sc->rx.running = 1;
678 sc->tx.running = 1;
679 sc->watchdog.timer = 0;
680 callout_init(&sc->watchdog.callout, 0);
681 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc);
682 }
683
684 /*
685 *
686 * Device Probe, Attach, Detach.
687 *
688 */
689
690 static int
cpsw_probe(device_t dev)691 cpsw_probe(device_t dev)
692 {
693
694 if (!ofw_bus_status_okay(dev))
695 return (ENXIO);
696
697 if (!ofw_bus_is_compatible(dev, "ti,cpsw"))
698 return (ENXIO);
699
700 device_set_desc(dev, "3-port Switch Ethernet Subsystem");
701 return (BUS_PROBE_DEFAULT);
702 }
703
704 static int
cpsw_intr_attach(struct cpsw_softc * sc)705 cpsw_intr_attach(struct cpsw_softc *sc)
706 {
707 int i;
708
709 for (i = 0; i < CPSW_INTR_COUNT; i++) {
710 if (bus_setup_intr(sc->dev, sc->irq_res[i],
711 INTR_TYPE_NET | INTR_MPSAFE, NULL,
712 cpsw_intr_cb[i].cb, sc, &sc->ih_cookie[i]) != 0) {
713 return (-1);
714 }
715 }
716
717 return (0);
718 }
719
720 static void
cpsw_intr_detach(struct cpsw_softc * sc)721 cpsw_intr_detach(struct cpsw_softc *sc)
722 {
723 int i;
724
725 for (i = 0; i < CPSW_INTR_COUNT; i++) {
726 if (sc->ih_cookie[i]) {
727 bus_teardown_intr(sc->dev, sc->irq_res[i],
728 sc->ih_cookie[i]);
729 }
730 }
731 }
732
733 static int
cpsw_get_fdt_data(struct cpsw_softc * sc,int port)734 cpsw_get_fdt_data(struct cpsw_softc *sc, int port)
735 {
736 char *name;
737 int len, phy, vlan;
738 pcell_t phy_id[3], vlan_id;
739 phandle_t child;
740 unsigned long mdio_child_addr;
741
742 /* Find any slave with phy-handle/phy_id */
743 phy = -1;
744 vlan = -1;
745 for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) {
746 if (OF_getprop_alloc(child, "name", (void **)&name) < 0)
747 continue;
748 if (sscanf(name, "slave@%lx", &mdio_child_addr) != 1) {
749 OF_prop_free(name);
750 continue;
751 }
752 OF_prop_free(name);
753
754 if (mdio_child_addr != slave_mdio_addr[port] &&
755 mdio_child_addr != (slave_mdio_addr[port] & 0xFFF))
756 continue;
757
758 if (fdt_get_phyaddr(child, NULL, &phy, NULL) != 0){
759 /* Users with old DTB will have phy_id instead */
760 phy = -1;
761 len = OF_getproplen(child, "phy_id");
762 if (len / sizeof(pcell_t) == 2) {
763 /* Get phy address from fdt */
764 if (OF_getencprop(child, "phy_id", phy_id, len) > 0)
765 phy = phy_id[1];
766 }
767 }
768
769 len = OF_getproplen(child, "dual_emac_res_vlan");
770 if (len / sizeof(pcell_t) == 1) {
771 /* Get phy address from fdt */
772 if (OF_getencprop(child, "dual_emac_res_vlan",
773 &vlan_id, len) > 0) {
774 vlan = vlan_id;
775 }
776 }
777
778 break;
779 }
780 if (phy == -1)
781 return (ENXIO);
782 sc->port[port].phy = phy;
783 sc->port[port].vlan = vlan;
784
785 return (0);
786 }
787
788 static int
cpsw_attach(device_t dev)789 cpsw_attach(device_t dev)
790 {
791 int error, i;
792 struct cpsw_softc *sc;
793 uint32_t reg;
794
795 sc = device_get_softc(dev);
796 sc->dev = dev;
797 sc->node = ofw_bus_get_node(dev);
798 getbinuptime(&sc->attach_uptime);
799
800 if (OF_getencprop(sc->node, "active_slave", &sc->active_slave,
801 sizeof(sc->active_slave)) <= 0) {
802 sc->active_slave = 0;
803 }
804 if (sc->active_slave > 1)
805 sc->active_slave = 1;
806
807 if (OF_hasprop(sc->node, "dual_emac"))
808 sc->dualemac = 1;
809
810 for (i = 0; i < CPSW_PORTS; i++) {
811 if (!sc->dualemac && i != sc->active_slave)
812 continue;
813 if (cpsw_get_fdt_data(sc, i) != 0) {
814 device_printf(dev,
815 "failed to get PHY address from FDT\n");
816 return (ENXIO);
817 }
818 }
819
820 /* Initialize mutexes */
821 mtx_init(&sc->tx.lock, device_get_nameunit(dev),
822 "cpsw TX lock", MTX_DEF);
823 mtx_init(&sc->rx.lock, device_get_nameunit(dev),
824 "cpsw RX lock", MTX_DEF);
825
826 /* Allocate IRQ resources */
827 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res);
828 if (error) {
829 device_printf(dev, "could not allocate IRQ resources\n");
830 cpsw_detach(dev);
831 return (ENXIO);
832 }
833
834 sc->mem_rid = 0;
835 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
836 &sc->mem_rid, RF_ACTIVE);
837 if (sc->mem_res == NULL) {
838 device_printf(sc->dev, "failed to allocate memory resource\n");
839 cpsw_detach(dev);
840 return (ENXIO);
841 }
842
843 reg = cpsw_read_4(sc, CPSW_SS_IDVER);
844 device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7),
845 reg & 0xFF, (reg >> 11) & 0x1F);
846
847 cpsw_add_sysctls(sc);
848
849 /* Allocate a busdma tag and DMA safe memory for mbufs. */
850 error = bus_dma_tag_create(
851 bus_get_dma_tag(sc->dev), /* parent */
852 1, 0, /* alignment, boundary */
853 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
854 BUS_SPACE_MAXADDR, /* highaddr */
855 NULL, NULL, /* filtfunc, filtfuncarg */
856 MCLBYTES, CPSW_TXFRAGS, /* maxsize, nsegments */
857 MCLBYTES, 0, /* maxsegsz, flags */
858 NULL, NULL, /* lockfunc, lockfuncarg */
859 &sc->mbuf_dtag); /* dmatag */
860 if (error) {
861 device_printf(dev, "bus_dma_tag_create failed\n");
862 cpsw_detach(dev);
863 return (error);
864 }
865
866 /* Allocate a NULL buffer for padding. */
867 sc->nullpad = malloc(ETHER_MIN_LEN, M_DEVBUF, M_WAITOK | M_ZERO);
868
869 cpsw_init_slots(sc);
870
871 /* Allocate slots to TX and RX queues. */
872 STAILQ_INIT(&sc->rx.avail);
873 STAILQ_INIT(&sc->rx.active);
874 STAILQ_INIT(&sc->tx.avail);
875 STAILQ_INIT(&sc->tx.active);
876 // For now: 128 slots to TX, rest to RX.
877 // XXX TODO: start with 32/64 and grow dynamically based on demand.
878 if (cpsw_add_slots(sc, &sc->tx, 128) ||
879 cpsw_add_slots(sc, &sc->rx, -1)) {
880 device_printf(dev, "failed to allocate dmamaps\n");
881 cpsw_detach(dev);
882 return (ENOMEM);
883 }
884 device_printf(dev, "Initial queue size TX=%d RX=%d\n",
885 sc->tx.queue_slots, sc->rx.queue_slots);
886
887 sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0);
888 sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0);
889
890 if (cpsw_intr_attach(sc) == -1) {
891 device_printf(dev, "failed to setup interrupts\n");
892 cpsw_detach(dev);
893 return (ENXIO);
894 }
895
896 #ifdef CPSW_ETHERSWITCH
897 for (i = 0; i < CPSW_VLANS; i++)
898 cpsw_vgroups[i].vid = -1;
899 #endif
900
901 /* Reset the controller. */
902 cpsw_reset(sc);
903 cpsw_init(sc);
904
905 for (i = 0; i < CPSW_PORTS; i++) {
906 if (!sc->dualemac && i != sc->active_slave)
907 continue;
908 sc->port[i].dev = device_add_child(dev, "cpsw", i);
909 if (sc->port[i].dev == NULL) {
910 cpsw_detach(dev);
911 return (ENXIO);
912 }
913 }
914 bus_generic_probe(dev);
915 bus_generic_attach(dev);
916
917 return (0);
918 }
919
920 static int
cpsw_detach(device_t dev)921 cpsw_detach(device_t dev)
922 {
923 struct cpsw_softc *sc;
924 int error, i;
925
926 bus_generic_detach(dev);
927 sc = device_get_softc(dev);
928
929 for (i = 0; i < CPSW_PORTS; i++) {
930 if (sc->port[i].dev)
931 device_delete_child(dev, sc->port[i].dev);
932 }
933
934 if (device_is_attached(dev)) {
935 callout_stop(&sc->watchdog.callout);
936 callout_drain(&sc->watchdog.callout);
937 }
938
939 /* Stop and release all interrupts */
940 cpsw_intr_detach(sc);
941
942 /* Free dmamaps and mbufs */
943 for (i = 0; i < nitems(sc->_slots); ++i)
944 cpsw_free_slot(sc, &sc->_slots[i]);
945
946 /* Free null padding buffer. */
947 if (sc->nullpad)
948 free(sc->nullpad, M_DEVBUF);
949
950 /* Free DMA tag */
951 if (sc->mbuf_dtag) {
952 error = bus_dma_tag_destroy(sc->mbuf_dtag);
953 KASSERT(error == 0, ("Unable to destroy DMA tag"));
954 }
955
956 /* Free IO memory handler */
957 if (sc->mem_res != NULL)
958 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
959 bus_release_resources(dev, irq_res_spec, sc->irq_res);
960
961 /* Destroy mutexes */
962 mtx_destroy(&sc->rx.lock);
963 mtx_destroy(&sc->tx.lock);
964
965 /* Detach the switch device, if present. */
966 error = bus_generic_detach(dev);
967 if (error != 0)
968 return (error);
969
970 return (device_delete_children(dev));
971 }
972
973 static phandle_t
cpsw_get_node(device_t bus,device_t dev)974 cpsw_get_node(device_t bus, device_t dev)
975 {
976
977 /* Share controller node with port device. */
978 return (ofw_bus_get_node(bus));
979 }
980
981 static int
cpswp_probe(device_t dev)982 cpswp_probe(device_t dev)
983 {
984
985 if (device_get_unit(dev) > 1) {
986 device_printf(dev, "Only two ports are supported.\n");
987 return (ENXIO);
988 }
989 device_set_desc(dev, "Ethernet Switch Port");
990
991 return (BUS_PROBE_DEFAULT);
992 }
993
994 static int
cpswp_attach(device_t dev)995 cpswp_attach(device_t dev)
996 {
997 int error;
998 if_t ifp;
999 struct cpswp_softc *sc;
1000 uint32_t reg;
1001 uint8_t mac_addr[ETHER_ADDR_LEN];
1002 phandle_t opp_table;
1003 struct syscon *syscon;
1004
1005 sc = device_get_softc(dev);
1006 sc->dev = dev;
1007 sc->pdev = device_get_parent(dev);
1008 sc->swsc = device_get_softc(sc->pdev);
1009 sc->unit = device_get_unit(dev);
1010 sc->phy = sc->swsc->port[sc->unit].phy;
1011 sc->vlan = sc->swsc->port[sc->unit].vlan;
1012 if (sc->swsc->dualemac && sc->vlan == -1)
1013 sc->vlan = sc->unit + 1;
1014
1015 if (sc->unit == 0) {
1016 sc->physel = MDIOUSERPHYSEL0;
1017 sc->phyaccess = MDIOUSERACCESS0;
1018 } else {
1019 sc->physel = MDIOUSERPHYSEL1;
1020 sc->phyaccess = MDIOUSERACCESS1;
1021 }
1022
1023 mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock",
1024 MTX_DEF);
1025
1026 /* Allocate network interface */
1027 ifp = sc->ifp = if_alloc(IFT_ETHER);
1028 if_initname(ifp, device_get_name(sc->dev), sc->unit);
1029 if_setsoftc(ifp, sc);
1030 if_setflags(ifp, IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST);
1031
1032 if_setcapenable(ifp, if_getcapabilities(ifp));
1033
1034 if_setinitfn(ifp, cpswp_init);
1035 if_setstartfn(ifp, cpswp_start);
1036 if_setioctlfn(ifp, cpswp_ioctl);
1037
1038 if_setsendqlen(ifp, sc->swsc->tx.queue_slots);
1039 if_setsendqready(ifp);
1040
1041 /* FIXME: For now; Go and kidnap syscon from opp-table */
1042 /* ti,cpsw actually have an optional syscon reference but only for am33xx?? */
1043 opp_table = OF_finddevice("/opp-table");
1044 if (opp_table == -1) {
1045 device_printf(dev, "Cant find /opp-table\n");
1046 cpswp_detach(dev);
1047 return (ENXIO);
1048 }
1049 if (!OF_hasprop(opp_table, "syscon")) {
1050 device_printf(dev, "/opp-table doesnt have required syscon property\n");
1051 cpswp_detach(dev);
1052 return (ENXIO);
1053 }
1054 if (syscon_get_by_ofw_property(dev, opp_table, "syscon", &syscon) != 0) {
1055 device_printf(dev, "Failed to get syscon\n");
1056 cpswp_detach(dev);
1057 return (ENXIO);
1058 }
1059
1060 /* Get high part of MAC address from control module (mac_id[0|1]_hi) */
1061 reg = SYSCON_READ_4(syscon, SCM_MAC_ID0_HI + sc->unit * 8);
1062 mac_addr[0] = reg & 0xFF;
1063 mac_addr[1] = (reg >> 8) & 0xFF;
1064 mac_addr[2] = (reg >> 16) & 0xFF;
1065 mac_addr[3] = (reg >> 24) & 0xFF;
1066
1067 /* Get low part of MAC address from control module (mac_id[0|1]_lo) */
1068 reg = SYSCON_READ_4(syscon, SCM_MAC_ID0_LO + sc->unit * 8);
1069 mac_addr[4] = reg & 0xFF;
1070 mac_addr[5] = (reg >> 8) & 0xFF;
1071
1072 error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd,
1073 cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0);
1074 if (error) {
1075 device_printf(dev, "attaching PHYs failed\n");
1076 cpswp_detach(dev);
1077 return (error);
1078 }
1079 sc->mii = device_get_softc(sc->miibus);
1080
1081 /* Select PHY and enable interrupts */
1082 cpsw_write_4(sc->swsc, sc->physel,
1083 MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F));
1084
1085 ether_ifattach(sc->ifp, mac_addr);
1086 callout_init(&sc->mii_callout, 0);
1087
1088 return (0);
1089 }
1090
1091 static int
cpswp_detach(device_t dev)1092 cpswp_detach(device_t dev)
1093 {
1094 struct cpswp_softc *sc;
1095
1096 sc = device_get_softc(dev);
1097 CPSW_DEBUGF(sc->swsc, (""));
1098 if (device_is_attached(dev)) {
1099 ether_ifdetach(sc->ifp);
1100 CPSW_PORT_LOCK(sc);
1101 cpswp_stop_locked(sc);
1102 CPSW_PORT_UNLOCK(sc);
1103 callout_drain(&sc->mii_callout);
1104 }
1105
1106 bus_generic_detach(dev);
1107
1108 if_free(sc->ifp);
1109 mtx_destroy(&sc->lock);
1110
1111 return (0);
1112 }
1113
1114 /*
1115 *
1116 * Init/Shutdown.
1117 *
1118 */
1119
1120 static int
cpsw_ports_down(struct cpsw_softc * sc)1121 cpsw_ports_down(struct cpsw_softc *sc)
1122 {
1123 struct cpswp_softc *psc;
1124 if_t ifp1, ifp2;
1125
1126 if (!sc->dualemac)
1127 return (1);
1128 psc = device_get_softc(sc->port[0].dev);
1129 ifp1 = psc->ifp;
1130 psc = device_get_softc(sc->port[1].dev);
1131 ifp2 = psc->ifp;
1132 if ((if_getflags(ifp1) & IFF_UP) == 0 && (if_getflags(ifp2) & IFF_UP) == 0)
1133 return (1);
1134
1135 return (0);
1136 }
1137
1138 static void
cpswp_init(void * arg)1139 cpswp_init(void *arg)
1140 {
1141 struct cpswp_softc *sc = arg;
1142
1143 CPSW_DEBUGF(sc->swsc, (""));
1144 CPSW_PORT_LOCK(sc);
1145 cpswp_init_locked(arg);
1146 CPSW_PORT_UNLOCK(sc);
1147 }
1148
1149 static void
cpswp_init_locked(void * arg)1150 cpswp_init_locked(void *arg)
1151 {
1152 #ifdef CPSW_ETHERSWITCH
1153 int i;
1154 #endif
1155 struct cpswp_softc *sc = arg;
1156 if_t ifp;
1157 uint32_t reg;
1158
1159 CPSW_DEBUGF(sc->swsc, (""));
1160 CPSW_PORT_LOCK_ASSERT(sc);
1161 ifp = sc->ifp;
1162 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1163 return;
1164
1165 getbinuptime(&sc->init_uptime);
1166
1167 if (!sc->swsc->rx.running && !sc->swsc->tx.running) {
1168 /* Reset the controller. */
1169 cpsw_reset(sc->swsc);
1170 cpsw_init(sc->swsc);
1171 }
1172
1173 /* Set Slave Mapping. */
1174 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210);
1175 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1),
1176 0x33221100);
1177 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2);
1178 /* Enable MAC RX/TX modules. */
1179 /* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */
1180 /* Huh? Docs call bit 0 "Loopback" some places, "FullDuplex" others. */
1181 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
1182 reg |= CPSW_SL_MACTL_GMII_ENABLE;
1183 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
1184
1185 /* Initialize ALE: set port to forwarding, initialize addrs */
1186 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1),
1187 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD);
1188 cpswp_ale_update_addresses(sc, 1);
1189
1190 if (sc->swsc->dualemac) {
1191 /* Set Port VID. */
1192 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1),
1193 sc->vlan & 0xfff);
1194 cpsw_ale_update_vlan_table(sc->swsc, sc->vlan,
1195 (1 << (sc->unit + 1)) | (1 << 0), /* Member list */
1196 (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */
1197 (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */
1198 #ifdef CPSW_ETHERSWITCH
1199 for (i = 0; i < CPSW_VLANS; i++) {
1200 if (cpsw_vgroups[i].vid != -1)
1201 continue;
1202 cpsw_vgroups[i].vid = sc->vlan;
1203 break;
1204 }
1205 #endif
1206 }
1207
1208 mii_mediachg(sc->mii);
1209 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc);
1210 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1211 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1212 }
1213
1214 static int
cpsw_shutdown(device_t dev)1215 cpsw_shutdown(device_t dev)
1216 {
1217 struct cpsw_softc *sc;
1218 struct cpswp_softc *psc;
1219 int i;
1220
1221 sc = device_get_softc(dev);
1222 CPSW_DEBUGF(sc, (""));
1223 for (i = 0; i < CPSW_PORTS; i++) {
1224 if (!sc->dualemac && i != sc->active_slave)
1225 continue;
1226 psc = device_get_softc(sc->port[i].dev);
1227 CPSW_PORT_LOCK(psc);
1228 cpswp_stop_locked(psc);
1229 CPSW_PORT_UNLOCK(psc);
1230 }
1231
1232 return (0);
1233 }
1234
1235 static void
cpsw_rx_teardown(struct cpsw_softc * sc)1236 cpsw_rx_teardown(struct cpsw_softc *sc)
1237 {
1238 int i = 0;
1239
1240 CPSW_RX_LOCK(sc);
1241 CPSW_DEBUGF(sc, ("starting RX teardown"));
1242 sc->rx.teardown = 1;
1243 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0);
1244 CPSW_RX_UNLOCK(sc);
1245 while (sc->rx.running) {
1246 if (++i > 10) {
1247 device_printf(sc->dev,
1248 "Unable to cleanly shutdown receiver\n");
1249 return;
1250 }
1251 DELAY(200);
1252 }
1253 if (!sc->rx.running)
1254 CPSW_DEBUGF(sc, ("finished RX teardown (%d retries)", i));
1255 }
1256
1257 static void
cpsw_tx_teardown(struct cpsw_softc * sc)1258 cpsw_tx_teardown(struct cpsw_softc *sc)
1259 {
1260 int i = 0;
1261
1262 CPSW_TX_LOCK(sc);
1263 CPSW_DEBUGF(sc, ("starting TX teardown"));
1264 /* Start the TX queue teardown if queue is not empty. */
1265 if (STAILQ_FIRST(&sc->tx.active) != NULL)
1266 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0);
1267 else
1268 sc->tx.teardown = 1;
1269 cpsw_tx_dequeue(sc);
1270 while (sc->tx.running && ++i < 10) {
1271 DELAY(200);
1272 cpsw_tx_dequeue(sc);
1273 }
1274 if (sc->tx.running) {
1275 device_printf(sc->dev,
1276 "Unable to cleanly shutdown transmitter\n");
1277 }
1278 CPSW_DEBUGF(sc,
1279 ("finished TX teardown (%d retries, %d idle buffers)", i,
1280 sc->tx.active_queue_len));
1281 CPSW_TX_UNLOCK(sc);
1282 }
1283
1284 static void
cpswp_stop_locked(struct cpswp_softc * sc)1285 cpswp_stop_locked(struct cpswp_softc *sc)
1286 {
1287 if_t ifp;
1288 uint32_t reg;
1289
1290 ifp = sc->ifp;
1291 CPSW_DEBUGF(sc->swsc, (""));
1292 CPSW_PORT_LOCK_ASSERT(sc);
1293
1294 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1295 return;
1296
1297 /* Disable interface */
1298 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1299 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1300
1301 /* Stop ticker */
1302 callout_stop(&sc->mii_callout);
1303
1304 /* Tear down the RX/TX queues. */
1305 if (cpsw_ports_down(sc->swsc)) {
1306 cpsw_rx_teardown(sc->swsc);
1307 cpsw_tx_teardown(sc->swsc);
1308 }
1309
1310 /* Stop MAC RX/TX modules. */
1311 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
1312 reg &= ~CPSW_SL_MACTL_GMII_ENABLE;
1313 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
1314
1315 if (cpsw_ports_down(sc->swsc)) {
1316 /* Capture stats before we reset controller. */
1317 cpsw_stats_collect(sc->swsc);
1318
1319 cpsw_reset(sc->swsc);
1320 cpsw_init(sc->swsc);
1321 }
1322 }
1323
1324 /*
1325 * Suspend/Resume.
1326 */
1327
1328 static int
cpsw_suspend(device_t dev)1329 cpsw_suspend(device_t dev)
1330 {
1331 struct cpsw_softc *sc;
1332 struct cpswp_softc *psc;
1333 int i;
1334
1335 sc = device_get_softc(dev);
1336 CPSW_DEBUGF(sc, (""));
1337 for (i = 0; i < CPSW_PORTS; i++) {
1338 if (!sc->dualemac && i != sc->active_slave)
1339 continue;
1340 psc = device_get_softc(sc->port[i].dev);
1341 CPSW_PORT_LOCK(psc);
1342 cpswp_stop_locked(psc);
1343 CPSW_PORT_UNLOCK(psc);
1344 }
1345
1346 return (0);
1347 }
1348
1349 static int
cpsw_resume(device_t dev)1350 cpsw_resume(device_t dev)
1351 {
1352 struct cpsw_softc *sc;
1353
1354 sc = device_get_softc(dev);
1355 CPSW_DEBUGF(sc, ("UNIMPLEMENTED"));
1356
1357 return (0);
1358 }
1359
1360 /*
1361 *
1362 * IOCTL
1363 *
1364 */
1365
1366 static void
cpsw_set_promisc(struct cpswp_softc * sc,int set)1367 cpsw_set_promisc(struct cpswp_softc *sc, int set)
1368 {
1369 uint32_t reg;
1370
1371 /*
1372 * Enabling promiscuous mode requires ALE_BYPASS to be enabled.
1373 * That disables the ALE forwarding logic and causes every
1374 * packet to be sent only to the host port. In bypass mode,
1375 * the ALE processes host port transmit packets the same as in
1376 * normal mode.
1377 */
1378 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL);
1379 reg &= ~CPSW_ALE_CTL_BYPASS;
1380 if (set)
1381 reg |= CPSW_ALE_CTL_BYPASS;
1382 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg);
1383 }
1384
1385 static void
cpsw_set_allmulti(struct cpswp_softc * sc,int set)1386 cpsw_set_allmulti(struct cpswp_softc *sc, int set)
1387 {
1388 if (set) {
1389 printf("All-multicast mode unimplemented\n");
1390 }
1391 }
1392
1393 static int
cpswp_ioctl(if_t ifp,u_long command,caddr_t data)1394 cpswp_ioctl(if_t ifp, u_long command, caddr_t data)
1395 {
1396 struct cpswp_softc *sc;
1397 struct ifreq *ifr;
1398 int error;
1399 uint32_t changed;
1400
1401 error = 0;
1402 sc = if_getsoftc(ifp);
1403 ifr = (struct ifreq *)data;
1404
1405 switch (command) {
1406 case SIOCSIFCAP:
1407 changed = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
1408 if (changed & IFCAP_HWCSUM) {
1409 if ((ifr->ifr_reqcap & changed) & IFCAP_HWCSUM)
1410 if_setcapenablebit(ifp, IFCAP_HWCSUM, 0);
1411 else
1412 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
1413 }
1414 error = 0;
1415 break;
1416 case SIOCSIFFLAGS:
1417 CPSW_PORT_LOCK(sc);
1418 if (if_getflags(ifp) & IFF_UP) {
1419 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1420 changed = if_getflags(ifp) ^ sc->if_flags;
1421 CPSW_DEBUGF(sc->swsc,
1422 ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)",
1423 changed));
1424 if (changed & IFF_PROMISC)
1425 cpsw_set_promisc(sc,
1426 if_getflags(ifp) & IFF_PROMISC);
1427 if (changed & IFF_ALLMULTI)
1428 cpsw_set_allmulti(sc,
1429 if_getflags(ifp) & IFF_ALLMULTI);
1430 } else {
1431 CPSW_DEBUGF(sc->swsc,
1432 ("SIOCSIFFLAGS: starting up"));
1433 cpswp_init_locked(sc);
1434 }
1435 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1436 CPSW_DEBUGF(sc->swsc, ("SIOCSIFFLAGS: shutting down"));
1437 cpswp_stop_locked(sc);
1438 }
1439
1440 sc->if_flags = if_getflags(ifp);
1441 CPSW_PORT_UNLOCK(sc);
1442 break;
1443 case SIOCADDMULTI:
1444 cpswp_ale_update_addresses(sc, 0);
1445 break;
1446 case SIOCDELMULTI:
1447 /* Ugh. DELMULTI doesn't provide the specific address
1448 being removed, so the best we can do is remove
1449 everything and rebuild it all. */
1450 cpswp_ale_update_addresses(sc, 1);
1451 break;
1452 case SIOCGIFMEDIA:
1453 case SIOCSIFMEDIA:
1454 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command);
1455 break;
1456 default:
1457 error = ether_ioctl(ifp, command, data);
1458 }
1459 return (error);
1460 }
1461
1462 /*
1463 *
1464 * MIIBUS
1465 *
1466 */
1467 static int
cpswp_miibus_ready(struct cpsw_softc * sc,uint32_t reg)1468 cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg)
1469 {
1470 uint32_t r, retries = CPSW_MIIBUS_RETRIES;
1471
1472 while (--retries) {
1473 r = cpsw_read_4(sc, reg);
1474 if ((r & MDIO_PHYACCESS_GO) == 0)
1475 return (1);
1476 DELAY(CPSW_MIIBUS_DELAY);
1477 }
1478
1479 return (0);
1480 }
1481
1482 static int
cpswp_miibus_readreg(device_t dev,int phy,int reg)1483 cpswp_miibus_readreg(device_t dev, int phy, int reg)
1484 {
1485 struct cpswp_softc *sc;
1486 uint32_t cmd, r;
1487
1488 sc = device_get_softc(dev);
1489 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1490 device_printf(dev, "MDIO not ready to read\n");
1491 return (0);
1492 }
1493
1494 /* Set GO, reg, phy */
1495 cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16;
1496 cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
1497
1498 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1499 device_printf(dev, "MDIO timed out during read\n");
1500 return (0);
1501 }
1502
1503 r = cpsw_read_4(sc->swsc, sc->phyaccess);
1504 if ((r & MDIO_PHYACCESS_ACK) == 0) {
1505 device_printf(dev, "Failed to read from PHY.\n");
1506 r = 0;
1507 }
1508 return (r & 0xFFFF);
1509 }
1510
1511 static int
cpswp_miibus_writereg(device_t dev,int phy,int reg,int value)1512 cpswp_miibus_writereg(device_t dev, int phy, int reg, int value)
1513 {
1514 struct cpswp_softc *sc;
1515 uint32_t cmd;
1516
1517 sc = device_get_softc(dev);
1518 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1519 device_printf(dev, "MDIO not ready to write\n");
1520 return (0);
1521 }
1522
1523 /* Set GO, WRITE, reg, phy, and value */
1524 cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE |
1525 (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF);
1526 cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
1527
1528 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1529 device_printf(dev, "MDIO timed out during write\n");
1530 return (0);
1531 }
1532
1533 return (0);
1534 }
1535
1536 static void
cpswp_miibus_statchg(device_t dev)1537 cpswp_miibus_statchg(device_t dev)
1538 {
1539 struct cpswp_softc *sc;
1540 uint32_t mac_control, reg;
1541
1542 sc = device_get_softc(dev);
1543 CPSW_DEBUGF(sc->swsc, (""));
1544
1545 reg = CPSW_SL_MACCONTROL(sc->unit);
1546 mac_control = cpsw_read_4(sc->swsc, reg);
1547 mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A |
1548 CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX);
1549
1550 switch(IFM_SUBTYPE(sc->mii->mii_media_active)) {
1551 case IFM_1000_SX:
1552 case IFM_1000_LX:
1553 case IFM_1000_CX:
1554 case IFM_1000_T:
1555 mac_control |= CPSW_SL_MACTL_GIG;
1556 break;
1557
1558 case IFM_100_TX:
1559 mac_control |= CPSW_SL_MACTL_IFCTL_A;
1560 break;
1561 }
1562 if (sc->mii->mii_media_active & IFM_FDX)
1563 mac_control |= CPSW_SL_MACTL_FULLDUPLEX;
1564
1565 cpsw_write_4(sc->swsc, reg, mac_control);
1566 }
1567
1568 /*
1569 *
1570 * Transmit/Receive Packets.
1571 *
1572 */
1573 static void
cpsw_intr_rx(void * arg)1574 cpsw_intr_rx(void *arg)
1575 {
1576 struct cpsw_softc *sc;
1577 if_t ifp;
1578 struct mbuf *received, *next;
1579
1580 sc = (struct cpsw_softc *)arg;
1581 CPSW_RX_LOCK(sc);
1582 if (sc->rx.teardown) {
1583 sc->rx.running = 0;
1584 sc->rx.teardown = 0;
1585 cpsw_write_cp(sc, &sc->rx, 0xfffffffc);
1586 }
1587 received = cpsw_rx_dequeue(sc);
1588 cpsw_rx_enqueue(sc);
1589 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1);
1590 CPSW_RX_UNLOCK(sc);
1591
1592 while (received != NULL) {
1593 next = received->m_nextpkt;
1594 received->m_nextpkt = NULL;
1595 ifp = received->m_pkthdr.rcvif;
1596 if_input(ifp, received);
1597 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1598 received = next;
1599 }
1600 }
1601
1602 static struct mbuf *
cpsw_rx_dequeue(struct cpsw_softc * sc)1603 cpsw_rx_dequeue(struct cpsw_softc *sc)
1604 {
1605 int nsegs, port, removed;
1606 struct cpsw_cpdma_bd bd;
1607 struct cpsw_slot *last, *slot;
1608 struct cpswp_softc *psc;
1609 struct mbuf *m, *m0, *mb_head, *mb_tail;
1610 uint16_t m0_flags;
1611
1612 nsegs = 0;
1613 m0 = NULL;
1614 last = NULL;
1615 mb_head = NULL;
1616 mb_tail = NULL;
1617 removed = 0;
1618
1619 /* Pull completed packets off hardware RX queue. */
1620 while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) {
1621 cpsw_cpdma_read_bd(sc, slot, &bd);
1622
1623 /*
1624 * Stop on packets still in use by hardware, but do not stop
1625 * on packets with the teardown complete flag, they will be
1626 * discarded later.
1627 */
1628 if ((bd.flags & (CPDMA_BD_OWNER | CPDMA_BD_TDOWNCMPLT)) ==
1629 CPDMA_BD_OWNER)
1630 break;
1631
1632 last = slot;
1633 ++removed;
1634 STAILQ_REMOVE_HEAD(&sc->rx.active, next);
1635 STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next);
1636
1637 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD);
1638 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
1639
1640 m = slot->mbuf;
1641 slot->mbuf = NULL;
1642
1643 if (bd.flags & CPDMA_BD_TDOWNCMPLT) {
1644 CPSW_DEBUGF(sc, ("RX teardown is complete"));
1645 m_freem(m);
1646 sc->rx.running = 0;
1647 sc->rx.teardown = 0;
1648 break;
1649 }
1650
1651 port = (bd.flags & CPDMA_BD_PORT_MASK) - 1;
1652 KASSERT(port >= 0 && port <= 1,
1653 ("patcket received with invalid port: %d", port));
1654 psc = device_get_softc(sc->port[port].dev);
1655
1656 /* Set up mbuf */
1657 m->m_data += bd.bufoff;
1658 m->m_len = bd.buflen;
1659 if (bd.flags & CPDMA_BD_SOP) {
1660 m->m_pkthdr.len = bd.pktlen;
1661 m->m_pkthdr.rcvif = psc->ifp;
1662 m->m_flags |= M_PKTHDR;
1663 m0_flags = bd.flags;
1664 m0 = m;
1665 }
1666 nsegs++;
1667 m->m_next = NULL;
1668 m->m_nextpkt = NULL;
1669 if (bd.flags & CPDMA_BD_EOP && m0 != NULL) {
1670 if (m0_flags & CPDMA_BD_PASS_CRC)
1671 m_adj(m0, -ETHER_CRC_LEN);
1672 m0_flags = 0;
1673 m0 = NULL;
1674 if (nsegs > sc->rx.longest_chain)
1675 sc->rx.longest_chain = nsegs;
1676 nsegs = 0;
1677 }
1678
1679 if ((if_getcapenable(psc->ifp) & IFCAP_RXCSUM) != 0) {
1680 /* check for valid CRC by looking into pkt_err[5:4] */
1681 if ((bd.flags &
1682 (CPDMA_BD_SOP | CPDMA_BD_PKT_ERR_MASK)) ==
1683 CPDMA_BD_SOP) {
1684 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1685 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1686 m->m_pkthdr.csum_data = 0xffff;
1687 }
1688 }
1689
1690 if (STAILQ_FIRST(&sc->rx.active) != NULL &&
1691 (bd.flags & (CPDMA_BD_EOP | CPDMA_BD_EOQ)) ==
1692 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) {
1693 cpsw_write_hdp_slot(sc, &sc->rx,
1694 STAILQ_FIRST(&sc->rx.active));
1695 sc->rx.queue_restart++;
1696 }
1697
1698 /* Add mbuf to packet list to be returned. */
1699 if (mb_tail != NULL && (bd.flags & CPDMA_BD_SOP)) {
1700 mb_tail->m_nextpkt = m;
1701 } else if (mb_tail != NULL) {
1702 mb_tail->m_next = m;
1703 } else if (mb_tail == NULL && (bd.flags & CPDMA_BD_SOP) == 0) {
1704 if (bootverbose)
1705 printf(
1706 "%s: %s: discanding fragment packet w/o header\n",
1707 __func__, if_name(psc->ifp));
1708 m_freem(m);
1709 continue;
1710 } else {
1711 mb_head = m;
1712 }
1713 mb_tail = m;
1714 }
1715
1716 if (removed != 0) {
1717 cpsw_write_cp_slot(sc, &sc->rx, last);
1718 sc->rx.queue_removes += removed;
1719 sc->rx.avail_queue_len += removed;
1720 sc->rx.active_queue_len -= removed;
1721 if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len)
1722 sc->rx.max_avail_queue_len = sc->rx.avail_queue_len;
1723 CPSW_DEBUGF(sc, ("Removed %d received packet(s) from RX queue", removed));
1724 }
1725
1726 return (mb_head);
1727 }
1728
1729 static void
cpsw_rx_enqueue(struct cpsw_softc * sc)1730 cpsw_rx_enqueue(struct cpsw_softc *sc)
1731 {
1732 bus_dma_segment_t seg[1];
1733 struct cpsw_cpdma_bd bd;
1734 struct cpsw_slot *first_new_slot, *last_old_slot, *next, *slot;
1735 int error, nsegs, added = 0;
1736
1737 /* Register new mbufs with hardware. */
1738 first_new_slot = NULL;
1739 last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next);
1740 while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) {
1741 if (first_new_slot == NULL)
1742 first_new_slot = slot;
1743 if (slot->mbuf == NULL) {
1744 slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1745 if (slot->mbuf == NULL) {
1746 device_printf(sc->dev,
1747 "Unable to fill RX queue\n");
1748 break;
1749 }
1750 slot->mbuf->m_len =
1751 slot->mbuf->m_pkthdr.len =
1752 slot->mbuf->m_ext.ext_size;
1753 }
1754
1755 error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap,
1756 slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT);
1757
1758 KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs));
1759 KASSERT(error == 0, ("DMA error (error=%d)", error));
1760 if (error != 0 || nsegs != 1) {
1761 device_printf(sc->dev,
1762 "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n",
1763 __func__, nsegs, error);
1764 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
1765 m_freem(slot->mbuf);
1766 slot->mbuf = NULL;
1767 break;
1768 }
1769
1770 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD);
1771
1772 /* Create and submit new rx descriptor. */
1773 if ((next = STAILQ_NEXT(slot, next)) != NULL)
1774 bd.next = cpsw_cpdma_bd_paddr(sc, next);
1775 else
1776 bd.next = 0;
1777 bd.bufptr = seg->ds_addr;
1778 bd.bufoff = 0;
1779 bd.buflen = MCLBYTES - 1;
1780 bd.pktlen = bd.buflen;
1781 bd.flags = CPDMA_BD_OWNER;
1782 cpsw_cpdma_write_bd(sc, slot, &bd);
1783 ++added;
1784
1785 STAILQ_REMOVE_HEAD(&sc->rx.avail, next);
1786 STAILQ_INSERT_TAIL(&sc->rx.active, slot, next);
1787 }
1788
1789 if (added == 0 || first_new_slot == NULL)
1790 return;
1791
1792 CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added));
1793
1794 /* Link new entries to hardware RX queue. */
1795 if (last_old_slot == NULL) {
1796 /* Start a fresh queue. */
1797 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot);
1798 } else {
1799 /* Add buffers to end of current queue. */
1800 cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot);
1801 }
1802 sc->rx.queue_adds += added;
1803 sc->rx.avail_queue_len -= added;
1804 sc->rx.active_queue_len += added;
1805 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added);
1806 if (sc->rx.active_queue_len > sc->rx.max_active_queue_len)
1807 sc->rx.max_active_queue_len = sc->rx.active_queue_len;
1808 }
1809
1810 static void
cpswp_start(if_t ifp)1811 cpswp_start(if_t ifp)
1812 {
1813 struct cpswp_softc *sc;
1814
1815 sc = if_getsoftc(ifp);
1816 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
1817 sc->swsc->tx.running == 0) {
1818 return;
1819 }
1820 CPSW_TX_LOCK(sc->swsc);
1821 cpswp_tx_enqueue(sc);
1822 cpsw_tx_dequeue(sc->swsc);
1823 CPSW_TX_UNLOCK(sc->swsc);
1824 }
1825
1826 static void
cpsw_intr_tx(void * arg)1827 cpsw_intr_tx(void *arg)
1828 {
1829 struct cpsw_softc *sc;
1830
1831 sc = (struct cpsw_softc *)arg;
1832 CPSW_TX_LOCK(sc);
1833 if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc)
1834 cpsw_write_cp(sc, &sc->tx, 0xfffffffc);
1835 cpsw_tx_dequeue(sc);
1836 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2);
1837 CPSW_TX_UNLOCK(sc);
1838 }
1839
1840 static void
cpswp_tx_enqueue(struct cpswp_softc * sc)1841 cpswp_tx_enqueue(struct cpswp_softc *sc)
1842 {
1843 bus_dma_segment_t segs[CPSW_TXFRAGS];
1844 struct cpsw_cpdma_bd bd;
1845 struct cpsw_slot *first_new_slot, *last, *last_old_slot, *next, *slot;
1846 struct mbuf *m0;
1847 int error, nsegs, seg, added = 0, padlen;
1848
1849 /* Pull pending packets from IF queue and prep them for DMA. */
1850 last = NULL;
1851 first_new_slot = NULL;
1852 last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next);
1853 while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) {
1854 m0 = if_dequeue(sc->ifp);
1855 if (m0 == NULL)
1856 break;
1857
1858 slot->mbuf = m0;
1859 padlen = ETHER_MIN_LEN - ETHER_CRC_LEN - m0->m_pkthdr.len;
1860 if (padlen < 0)
1861 padlen = 0;
1862 else if (padlen > 0)
1863 m_append(slot->mbuf, padlen, sc->swsc->nullpad);
1864
1865 /* Create mapping in DMA memory */
1866 error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag,
1867 slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT);
1868 /* If the packet is too fragmented, try to simplify. */
1869 if (error == EFBIG ||
1870 (error == 0 && nsegs > sc->swsc->tx.avail_queue_len)) {
1871 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap);
1872 m0 = m_defrag(slot->mbuf, M_NOWAIT);
1873 if (m0 == NULL) {
1874 device_printf(sc->dev,
1875 "Can't defragment packet; dropping\n");
1876 m_freem(slot->mbuf);
1877 } else {
1878 CPSW_DEBUGF(sc->swsc,
1879 ("Requeueing defragmented packet"));
1880 if_sendq_prepend(sc->ifp, m0);
1881 }
1882 slot->mbuf = NULL;
1883 continue;
1884 }
1885 if (error != 0) {
1886 device_printf(sc->dev,
1887 "%s: Can't setup DMA (error=%d), dropping packet\n",
1888 __func__, error);
1889 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap);
1890 m_freem(slot->mbuf);
1891 slot->mbuf = NULL;
1892 break;
1893 }
1894
1895 bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap,
1896 BUS_DMASYNC_PREWRITE);
1897
1898 CPSW_DEBUGF(sc->swsc,
1899 ("Queueing TX packet: %d segments + %d pad bytes",
1900 nsegs, padlen));
1901
1902 if (first_new_slot == NULL)
1903 first_new_slot = slot;
1904
1905 /* Link from the previous descriptor. */
1906 if (last != NULL)
1907 cpsw_cpdma_write_bd_next(sc->swsc, last, slot);
1908
1909 slot->ifp = sc->ifp;
1910
1911 /* If there is only one segment, the for() loop
1912 * gets skipped and the single buffer gets set up
1913 * as both SOP and EOP. */
1914 if (nsegs > 1) {
1915 next = STAILQ_NEXT(slot, next);
1916 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next);
1917 } else
1918 bd.next = 0;
1919 /* Start by setting up the first buffer. */
1920 bd.bufptr = segs[0].ds_addr;
1921 bd.bufoff = 0;
1922 bd.buflen = segs[0].ds_len;
1923 bd.pktlen = m_length(slot->mbuf, NULL);
1924 bd.flags = CPDMA_BD_SOP | CPDMA_BD_OWNER;
1925 if (sc->swsc->dualemac) {
1926 bd.flags |= CPDMA_BD_TO_PORT;
1927 bd.flags |= ((sc->unit + 1) & CPDMA_BD_PORT_MASK);
1928 }
1929 for (seg = 1; seg < nsegs; ++seg) {
1930 /* Save the previous buffer (which isn't EOP) */
1931 cpsw_cpdma_write_bd(sc->swsc, slot, &bd);
1932 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next);
1933 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next);
1934 slot = STAILQ_FIRST(&sc->swsc->tx.avail);
1935
1936 /* Setup next buffer (which isn't SOP) */
1937 if (nsegs > seg + 1) {
1938 next = STAILQ_NEXT(slot, next);
1939 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next);
1940 } else
1941 bd.next = 0;
1942 bd.bufptr = segs[seg].ds_addr;
1943 bd.bufoff = 0;
1944 bd.buflen = segs[seg].ds_len;
1945 bd.pktlen = 0;
1946 bd.flags = CPDMA_BD_OWNER;
1947 }
1948
1949 /* Save the final buffer. */
1950 bd.flags |= CPDMA_BD_EOP;
1951 cpsw_cpdma_write_bd(sc->swsc, slot, &bd);
1952 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next);
1953 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next);
1954
1955 last = slot;
1956 added += nsegs;
1957 if (nsegs > sc->swsc->tx.longest_chain)
1958 sc->swsc->tx.longest_chain = nsegs;
1959
1960 BPF_MTAP(sc->ifp, m0);
1961 }
1962
1963 if (first_new_slot == NULL)
1964 return;
1965
1966 /* Attach the list of new buffers to the hardware TX queue. */
1967 if (last_old_slot != NULL &&
1968 (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) &
1969 CPDMA_BD_EOQ) == 0) {
1970 /* Add buffers to end of current queue. */
1971 cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot,
1972 first_new_slot);
1973 } else {
1974 /* Start a fresh queue. */
1975 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot);
1976 }
1977 sc->swsc->tx.queue_adds += added;
1978 sc->swsc->tx.avail_queue_len -= added;
1979 sc->swsc->tx.active_queue_len += added;
1980 if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) {
1981 sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len;
1982 }
1983 CPSW_DEBUGF(sc->swsc, ("Queued %d TX packet(s)", added));
1984 }
1985
1986 static int
cpsw_tx_dequeue(struct cpsw_softc * sc)1987 cpsw_tx_dequeue(struct cpsw_softc *sc)
1988 {
1989 struct cpsw_slot *slot, *last_removed_slot = NULL;
1990 struct cpsw_cpdma_bd bd;
1991 uint32_t flags, removed = 0;
1992
1993 /* Pull completed buffers off the hardware TX queue. */
1994 slot = STAILQ_FIRST(&sc->tx.active);
1995 while (slot != NULL) {
1996 flags = cpsw_cpdma_read_bd_flags(sc, slot);
1997
1998 /* TearDown complete is only marked on the SOP for the packet. */
1999 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) ==
2000 (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) {
2001 sc->tx.teardown = 1;
2002 }
2003
2004 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_OWNER)) ==
2005 (CPDMA_BD_SOP | CPDMA_BD_OWNER) && sc->tx.teardown == 0)
2006 break; /* Hardware is still using this packet. */
2007
2008 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE);
2009 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
2010 m_freem(slot->mbuf);
2011 slot->mbuf = NULL;
2012
2013 if (slot->ifp) {
2014 if (sc->tx.teardown == 0)
2015 if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1);
2016 else
2017 if_inc_counter(slot->ifp, IFCOUNTER_OQDROPS, 1);
2018 }
2019
2020 /* Dequeue any additional buffers used by this packet. */
2021 while (slot != NULL && slot->mbuf == NULL) {
2022 STAILQ_REMOVE_HEAD(&sc->tx.active, next);
2023 STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next);
2024 ++removed;
2025 last_removed_slot = slot;
2026 slot = STAILQ_FIRST(&sc->tx.active);
2027 }
2028
2029 cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot);
2030
2031 /* Restart the TX queue if necessary. */
2032 cpsw_cpdma_read_bd(sc, last_removed_slot, &bd);
2033 if (slot != NULL && bd.next != 0 && (bd.flags &
2034 (CPDMA_BD_EOP | CPDMA_BD_OWNER | CPDMA_BD_EOQ)) ==
2035 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) {
2036 cpsw_write_hdp_slot(sc, &sc->tx, slot);
2037 sc->tx.queue_restart++;
2038 break;
2039 }
2040 }
2041
2042 if (removed != 0) {
2043 sc->tx.queue_removes += removed;
2044 sc->tx.active_queue_len -= removed;
2045 sc->tx.avail_queue_len += removed;
2046 if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len)
2047 sc->tx.max_avail_queue_len = sc->tx.avail_queue_len;
2048 CPSW_DEBUGF(sc, ("TX removed %d completed packet(s)", removed));
2049 }
2050
2051 if (sc->tx.teardown && STAILQ_EMPTY(&sc->tx.active)) {
2052 CPSW_DEBUGF(sc, ("TX teardown is complete"));
2053 sc->tx.teardown = 0;
2054 sc->tx.running = 0;
2055 }
2056
2057 return (removed);
2058 }
2059
2060 /*
2061 *
2062 * Miscellaneous interrupts.
2063 *
2064 */
2065
2066 static void
cpsw_intr_rx_thresh(void * arg)2067 cpsw_intr_rx_thresh(void *arg)
2068 {
2069 struct cpsw_softc *sc;
2070 if_t ifp;
2071 struct mbuf *received, *next;
2072
2073 sc = (struct cpsw_softc *)arg;
2074 CPSW_RX_LOCK(sc);
2075 received = cpsw_rx_dequeue(sc);
2076 cpsw_rx_enqueue(sc);
2077 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0);
2078 CPSW_RX_UNLOCK(sc);
2079
2080 while (received != NULL) {
2081 next = received->m_nextpkt;
2082 received->m_nextpkt = NULL;
2083 ifp = received->m_pkthdr.rcvif;
2084 if_input(ifp, received);
2085 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2086 received = next;
2087 }
2088 }
2089
2090 static void
cpsw_intr_misc_host_error(struct cpsw_softc * sc)2091 cpsw_intr_misc_host_error(struct cpsw_softc *sc)
2092 {
2093 uint32_t intstat;
2094 uint32_t dmastat;
2095 int txerr, rxerr, txchan, rxchan;
2096
2097 printf("\n\n");
2098 device_printf(sc->dev,
2099 "HOST ERROR: PROGRAMMING ERROR DETECTED BY HARDWARE\n");
2100 printf("\n\n");
2101 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED);
2102 device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat);
2103 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS);
2104 device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat);
2105
2106 txerr = (dmastat >> 20) & 15;
2107 txchan = (dmastat >> 16) & 7;
2108 rxerr = (dmastat >> 12) & 15;
2109 rxchan = (dmastat >> 8) & 7;
2110
2111 switch (txerr) {
2112 case 0: break;
2113 case 1: printf("SOP error on TX channel %d\n", txchan);
2114 break;
2115 case 2: printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan);
2116 break;
2117 case 3: printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan);
2118 break;
2119 case 4: printf("Zero Buffer Pointer on TX channel %d\n", txchan);
2120 break;
2121 case 5: printf("Zero Buffer Length on TX channel %d\n", txchan);
2122 break;
2123 case 6: printf("Packet length error on TX channel %d\n", txchan);
2124 break;
2125 default: printf("Unknown error on TX channel %d\n", txchan);
2126 break;
2127 }
2128
2129 if (txerr != 0) {
2130 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n",
2131 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan)));
2132 printf("CPSW_CPDMA_TX%d_CP=0x%x\n",
2133 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan)));
2134 cpsw_dump_queue(sc, &sc->tx.active);
2135 }
2136
2137 switch (rxerr) {
2138 case 0: break;
2139 case 2: printf("Ownership bit not set on RX channel %d\n", rxchan);
2140 break;
2141 case 4: printf("Zero Buffer Pointer on RX channel %d\n", rxchan);
2142 break;
2143 case 5: printf("Zero Buffer Length on RX channel %d\n", rxchan);
2144 break;
2145 case 6: printf("Buffer offset too big on RX channel %d\n", rxchan);
2146 break;
2147 default: printf("Unknown RX error on RX channel %d\n", rxchan);
2148 break;
2149 }
2150
2151 if (rxerr != 0) {
2152 printf("CPSW_CPDMA_RX%d_HDP=0x%x\n",
2153 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan)));
2154 printf("CPSW_CPDMA_RX%d_CP=0x%x\n",
2155 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan)));
2156 cpsw_dump_queue(sc, &sc->rx.active);
2157 }
2158
2159 printf("\nALE Table\n");
2160 cpsw_ale_dump_table(sc);
2161
2162 // XXX do something useful here??
2163 panic("CPSW HOST ERROR INTERRUPT");
2164
2165 // Suppress this interrupt in the future.
2166 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat);
2167 printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n");
2168 // The watchdog will probably reset the controller
2169 // in a little while. It will probably fail again.
2170 }
2171
2172 static void
cpsw_intr_misc(void * arg)2173 cpsw_intr_misc(void *arg)
2174 {
2175 struct cpsw_softc *sc = arg;
2176 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0));
2177
2178 if (stat & CPSW_WR_C_MISC_EVNT_PEND)
2179 CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented"));
2180 if (stat & CPSW_WR_C_MISC_STAT_PEND)
2181 cpsw_stats_collect(sc);
2182 if (stat & CPSW_WR_C_MISC_HOST_PEND)
2183 cpsw_intr_misc_host_error(sc);
2184 if (stat & CPSW_WR_C_MISC_MDIOLINK) {
2185 cpsw_write_4(sc, MDIOLINKINTMASKED,
2186 cpsw_read_4(sc, MDIOLINKINTMASKED));
2187 }
2188 if (stat & CPSW_WR_C_MISC_MDIOUSER) {
2189 CPSW_DEBUGF(sc,
2190 ("MDIO operation completed interrupt unimplemented"));
2191 }
2192 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3);
2193 }
2194
2195 /*
2196 *
2197 * Periodic Checks and Watchdog.
2198 *
2199 */
2200
2201 static void
cpswp_tick(void * msc)2202 cpswp_tick(void *msc)
2203 {
2204 struct cpswp_softc *sc = msc;
2205
2206 /* Check for media type change */
2207 mii_tick(sc->mii);
2208 if (sc->media_status != sc->mii->mii_media.ifm_media) {
2209 printf("%s: media type changed (ifm_media=%x)\n", __func__,
2210 sc->mii->mii_media.ifm_media);
2211 cpswp_ifmedia_upd(sc->ifp);
2212 }
2213
2214 /* Schedule another timeout one second from now */
2215 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc);
2216 }
2217
2218 static void
cpswp_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2219 cpswp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2220 {
2221 struct cpswp_softc *sc;
2222 struct mii_data *mii;
2223
2224 sc = if_getsoftc(ifp);
2225 CPSW_DEBUGF(sc->swsc, (""));
2226 CPSW_PORT_LOCK(sc);
2227
2228 mii = sc->mii;
2229 mii_pollstat(mii);
2230
2231 ifmr->ifm_active = mii->mii_media_active;
2232 ifmr->ifm_status = mii->mii_media_status;
2233 CPSW_PORT_UNLOCK(sc);
2234 }
2235
2236 static int
cpswp_ifmedia_upd(if_t ifp)2237 cpswp_ifmedia_upd(if_t ifp)
2238 {
2239 struct cpswp_softc *sc;
2240
2241 sc = if_getsoftc(ifp);
2242 CPSW_DEBUGF(sc->swsc, (""));
2243 CPSW_PORT_LOCK(sc);
2244 mii_mediachg(sc->mii);
2245 sc->media_status = sc->mii->mii_media.ifm_media;
2246 CPSW_PORT_UNLOCK(sc);
2247
2248 return (0);
2249 }
2250
2251 static void
cpsw_tx_watchdog_full_reset(struct cpsw_softc * sc)2252 cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc)
2253 {
2254 struct cpswp_softc *psc;
2255 int i;
2256
2257 cpsw_debugf_head("CPSW watchdog");
2258 device_printf(sc->dev, "watchdog timeout\n");
2259 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 0,
2260 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)));
2261 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 0,
2262 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)));
2263 cpsw_dump_queue(sc, &sc->tx.active);
2264 for (i = 0; i < CPSW_PORTS; i++) {
2265 if (!sc->dualemac && i != sc->active_slave)
2266 continue;
2267 psc = device_get_softc(sc->port[i].dev);
2268 CPSW_PORT_LOCK(psc);
2269 cpswp_stop_locked(psc);
2270 CPSW_PORT_UNLOCK(psc);
2271 }
2272 }
2273
2274 static void
cpsw_tx_watchdog(void * msc)2275 cpsw_tx_watchdog(void *msc)
2276 {
2277 struct cpsw_softc *sc;
2278
2279 sc = msc;
2280 CPSW_TX_LOCK(sc);
2281 if (sc->tx.active_queue_len == 0 || !sc->tx.running) {
2282 sc->watchdog.timer = 0; /* Nothing to do. */
2283 } else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) {
2284 sc->watchdog.timer = 0; /* Stuff done while we weren't looking. */
2285 } else if (cpsw_tx_dequeue(sc) > 0) {
2286 sc->watchdog.timer = 0; /* We just did something. */
2287 } else {
2288 /* There was something to do but it didn't get done. */
2289 ++sc->watchdog.timer;
2290 if (sc->watchdog.timer > 5) {
2291 sc->watchdog.timer = 0;
2292 ++sc->watchdog.resets;
2293 cpsw_tx_watchdog_full_reset(sc);
2294 }
2295 }
2296 sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes;
2297 CPSW_TX_UNLOCK(sc);
2298
2299 /* Schedule another timeout one second from now */
2300 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc);
2301 }
2302
2303 /*
2304 *
2305 * ALE support routines.
2306 *
2307 */
2308
2309 static void
cpsw_ale_read_entry(struct cpsw_softc * sc,uint16_t idx,uint32_t * ale_entry)2310 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry)
2311 {
2312 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023);
2313 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0);
2314 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1);
2315 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2);
2316 }
2317
2318 static void
cpsw_ale_write_entry(struct cpsw_softc * sc,uint16_t idx,uint32_t * ale_entry)2319 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry)
2320 {
2321 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]);
2322 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]);
2323 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]);
2324 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023));
2325 }
2326
2327 static void
cpsw_ale_remove_all_mc_entries(struct cpsw_softc * sc)2328 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc)
2329 {
2330 int i;
2331 uint32_t ale_entry[3];
2332
2333 /* First four entries are link address and broadcast. */
2334 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) {
2335 cpsw_ale_read_entry(sc, i, ale_entry);
2336 if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR ||
2337 ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) &&
2338 ALE_MCAST(ale_entry) == 1) { /* MCast link addr */
2339 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0;
2340 cpsw_ale_write_entry(sc, i, ale_entry);
2341 }
2342 }
2343 }
2344
2345 static int
cpsw_ale_mc_entry_set(struct cpsw_softc * sc,uint8_t portmap,int vlan,uint8_t * mac)2346 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan,
2347 uint8_t *mac)
2348 {
2349 int free_index = -1, matching_index = -1, i;
2350 uint32_t ale_entry[3], ale_type;
2351
2352 /* Find a matching entry or a free entry. */
2353 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) {
2354 cpsw_ale_read_entry(sc, i, ale_entry);
2355
2356 /* Entry Type[61:60] is 0 for free entry */
2357 if (free_index < 0 && ALE_TYPE(ale_entry) == 0)
2358 free_index = i;
2359
2360 if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) &&
2361 (((ale_entry[1] >> 0) & 0xFF) == mac[1]) &&
2362 (((ale_entry[0] >>24) & 0xFF) == mac[2]) &&
2363 (((ale_entry[0] >>16) & 0xFF) == mac[3]) &&
2364 (((ale_entry[0] >> 8) & 0xFF) == mac[4]) &&
2365 (((ale_entry[0] >> 0) & 0xFF) == mac[5])) {
2366 matching_index = i;
2367 break;
2368 }
2369 }
2370
2371 if (matching_index < 0) {
2372 if (free_index < 0)
2373 return (ENOMEM);
2374 i = free_index;
2375 }
2376
2377 if (vlan != -1)
2378 ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16;
2379 else
2380 ale_type = ALE_TYPE_ADDR << 28;
2381
2382 /* Set MAC address */
2383 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
2384 ale_entry[1] = mac[0] << 8 | mac[1];
2385
2386 /* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */
2387 ale_entry[1] |= ALE_MCAST_FWD | ale_type;
2388
2389 /* Set portmask [68:66] */
2390 ale_entry[2] = (portmap & 7) << 2;
2391
2392 cpsw_ale_write_entry(sc, i, ale_entry);
2393
2394 return 0;
2395 }
2396
2397 static void
cpsw_ale_dump_table(struct cpsw_softc * sc)2398 cpsw_ale_dump_table(struct cpsw_softc *sc) {
2399 int i;
2400 uint32_t ale_entry[3];
2401 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
2402 cpsw_ale_read_entry(sc, i, ale_entry);
2403 switch (ALE_TYPE(ale_entry)) {
2404 case ALE_TYPE_VLAN:
2405 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2],
2406 ale_entry[1], ale_entry[0]);
2407 printf("type: %u ", ALE_TYPE(ale_entry));
2408 printf("vlan: %u ", ALE_VLAN(ale_entry));
2409 printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry));
2410 printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry));
2411 printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry));
2412 printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry));
2413 printf("\n");
2414 break;
2415 case ALE_TYPE_ADDR:
2416 case ALE_TYPE_VLAN_ADDR:
2417 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2],
2418 ale_entry[1], ale_entry[0]);
2419 printf("type: %u ", ALE_TYPE(ale_entry));
2420 printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ",
2421 (ale_entry[1] >> 8) & 0xFF,
2422 (ale_entry[1] >> 0) & 0xFF,
2423 (ale_entry[0] >>24) & 0xFF,
2424 (ale_entry[0] >>16) & 0xFF,
2425 (ale_entry[0] >> 8) & 0xFF,
2426 (ale_entry[0] >> 0) & 0xFF);
2427 printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast ");
2428 if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR)
2429 printf("vlan: %u ", ALE_VLAN(ale_entry));
2430 printf("port: %u ", ALE_PORTS(ale_entry));
2431 printf("\n");
2432 break;
2433 }
2434 }
2435 printf("\n");
2436 }
2437
2438 static u_int
cpswp_set_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2439 cpswp_set_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2440 {
2441 struct cpswp_softc *sc = arg;
2442 uint32_t portmask;
2443
2444 if (sc->swsc->dualemac)
2445 portmask = 1 << (sc->unit + 1) | 1 << 0;
2446 else
2447 portmask = 7;
2448
2449 cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan, LLADDR(sdl));
2450
2451 return (1);
2452 }
2453
2454 static int
cpswp_ale_update_addresses(struct cpswp_softc * sc,int purge)2455 cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge)
2456 {
2457 uint8_t *mac;
2458 uint32_t ale_entry[3], ale_type, portmask;
2459
2460 if (sc->swsc->dualemac) {
2461 ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16;
2462 portmask = 1 << (sc->unit + 1) | 1 << 0;
2463 } else {
2464 ale_type = ALE_TYPE_ADDR << 28;
2465 portmask = 7;
2466 }
2467
2468 /*
2469 * Route incoming packets for our MAC address to Port 0 (host).
2470 * For simplicity, keep this entry at table index 0 for port 1 and
2471 * at index 2 for port 2 in the ALE.
2472 */
2473 mac = LLADDR((struct sockaddr_dl *)if_getifaddr(sc->ifp)->ifa_addr);
2474 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
2475 ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */
2476 ale_entry[2] = 0; /* port = 0 */
2477 cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry);
2478
2479 /* Set outgoing MAC Address for slave port. */
2480 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1),
2481 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]);
2482 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1),
2483 mac[5] << 8 | mac[4]);
2484
2485 /* Keep the broadcast address at table entry 1 (or 3). */
2486 ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */
2487 /* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */
2488 ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff;
2489 ale_entry[2] = portmask << 2;
2490 cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry);
2491
2492 /* SIOCDELMULTI doesn't specify the particular address
2493 being removed, so we have to remove all and rebuild. */
2494 if (purge)
2495 cpsw_ale_remove_all_mc_entries(sc->swsc);
2496
2497 /* Set other multicast addrs desired. */
2498 if_foreach_llmaddr(sc->ifp, cpswp_set_maddr, sc);
2499
2500 return (0);
2501 }
2502
2503 static int
cpsw_ale_update_vlan_table(struct cpsw_softc * sc,int vlan,int ports,int untag,int mcregflood,int mcunregflood)2504 cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports,
2505 int untag, int mcregflood, int mcunregflood)
2506 {
2507 int free_index, i, matching_index;
2508 uint32_t ale_entry[3];
2509
2510 free_index = matching_index = -1;
2511 /* Find a matching entry or a free entry. */
2512 for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) {
2513 cpsw_ale_read_entry(sc, i, ale_entry);
2514
2515 /* Entry Type[61:60] is 0 for free entry */
2516 if (free_index < 0 && ALE_TYPE(ale_entry) == 0)
2517 free_index = i;
2518
2519 if (ALE_VLAN(ale_entry) == vlan) {
2520 matching_index = i;
2521 break;
2522 }
2523 }
2524
2525 if (matching_index < 0) {
2526 if (free_index < 0)
2527 return (-1);
2528 i = free_index;
2529 }
2530
2531 ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 |
2532 (mcunregflood & 7) << 8 | (ports & 7);
2533 ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16;
2534 ale_entry[2] = 0;
2535 cpsw_ale_write_entry(sc, i, ale_entry);
2536
2537 return (0);
2538 }
2539
2540 /*
2541 *
2542 * Statistics and Sysctls.
2543 *
2544 */
2545
2546 #if 0
2547 static void
2548 cpsw_stats_dump(struct cpsw_softc *sc)
2549 {
2550 int i;
2551 uint32_t r;
2552
2553 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) {
2554 r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
2555 cpsw_stat_sysctls[i].reg);
2556 CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid,
2557 (intmax_t)sc->shadow_stats[i], r,
2558 (intmax_t)sc->shadow_stats[i] + r));
2559 }
2560 }
2561 #endif
2562
2563 static void
cpsw_stats_collect(struct cpsw_softc * sc)2564 cpsw_stats_collect(struct cpsw_softc *sc)
2565 {
2566 int i;
2567 uint32_t r;
2568
2569 CPSW_DEBUGF(sc, ("Controller shadow statistics updated."));
2570
2571 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) {
2572 r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
2573 cpsw_stat_sysctls[i].reg);
2574 sc->shadow_stats[i] += r;
2575 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg,
2576 r);
2577 }
2578 }
2579
2580 static int
cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS)2581 cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS)
2582 {
2583 struct cpsw_softc *sc;
2584 struct cpsw_stat *stat;
2585 uint64_t result;
2586
2587 sc = (struct cpsw_softc *)arg1;
2588 stat = &cpsw_stat_sysctls[oidp->oid_number];
2589 result = sc->shadow_stats[oidp->oid_number];
2590 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg);
2591 return (sysctl_handle_64(oidp, &result, 0, req));
2592 }
2593
2594 static int
cpsw_stat_attached(SYSCTL_HANDLER_ARGS)2595 cpsw_stat_attached(SYSCTL_HANDLER_ARGS)
2596 {
2597 struct cpsw_softc *sc;
2598 struct bintime t;
2599 unsigned result;
2600
2601 sc = (struct cpsw_softc *)arg1;
2602 getbinuptime(&t);
2603 bintime_sub(&t, &sc->attach_uptime);
2604 result = t.sec;
2605 return (sysctl_handle_int(oidp, &result, 0, req));
2606 }
2607
2608 static int
cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS)2609 cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS)
2610 {
2611 int error;
2612 struct cpsw_softc *sc;
2613 uint32_t ctrl, intr_per_ms;
2614
2615 sc = (struct cpsw_softc *)arg1;
2616 error = sysctl_handle_int(oidp, &sc->coal_us, 0, req);
2617 if (error != 0 || req->newptr == NULL)
2618 return (error);
2619
2620 ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
2621 ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK);
2622 if (sc->coal_us == 0) {
2623 /* Disable the interrupt pace hardware. */
2624 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
2625 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0);
2626 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0);
2627 return (0);
2628 }
2629
2630 if (sc->coal_us > CPSW_WR_C_IMAX_US_MAX)
2631 sc->coal_us = CPSW_WR_C_IMAX_US_MAX;
2632 if (sc->coal_us < CPSW_WR_C_IMAX_US_MIN)
2633 sc->coal_us = CPSW_WR_C_IMAX_US_MIN;
2634 intr_per_ms = 1000 / sc->coal_us;
2635 /* Just to make sure... */
2636 if (intr_per_ms > CPSW_WR_C_IMAX_MAX)
2637 intr_per_ms = CPSW_WR_C_IMAX_MAX;
2638 if (intr_per_ms < CPSW_WR_C_IMAX_MIN)
2639 intr_per_ms = CPSW_WR_C_IMAX_MIN;
2640
2641 /* Set the prescale to produce 4us pulses from the 125 Mhz clock. */
2642 ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK;
2643
2644 /* Enable the interrupt pace hardware. */
2645 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms);
2646 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms);
2647 ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE;
2648 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
2649
2650 return (0);
2651 }
2652
2653 static int
cpsw_stat_uptime(SYSCTL_HANDLER_ARGS)2654 cpsw_stat_uptime(SYSCTL_HANDLER_ARGS)
2655 {
2656 struct cpsw_softc *swsc;
2657 struct cpswp_softc *sc;
2658 struct bintime t;
2659 unsigned result;
2660
2661 swsc = arg1;
2662 sc = device_get_softc(swsc->port[arg2].dev);
2663 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
2664 getbinuptime(&t);
2665 bintime_sub(&t, &sc->init_uptime);
2666 result = t.sec;
2667 } else
2668 result = 0;
2669 return (sysctl_handle_int(oidp, &result, 0, req));
2670 }
2671
2672 static void
cpsw_add_queue_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * node,struct cpsw_queue * queue)2673 cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node,
2674 struct cpsw_queue *queue)
2675 {
2676 struct sysctl_oid_list *parent;
2677
2678 parent = SYSCTL_CHILDREN(node);
2679 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers",
2680 CTLFLAG_RD, &queue->queue_slots, 0,
2681 "Total buffers currently assigned to this queue");
2682 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers",
2683 CTLFLAG_RD, &queue->active_queue_len, 0,
2684 "Buffers currently registered with hardware controller");
2685 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers",
2686 CTLFLAG_RD, &queue->max_active_queue_len, 0,
2687 "Max value of activeBuffers since last driver reset");
2688 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers",
2689 CTLFLAG_RD, &queue->avail_queue_len, 0,
2690 "Buffers allocated to this queue but not currently "
2691 "registered with hardware controller");
2692 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers",
2693 CTLFLAG_RD, &queue->max_avail_queue_len, 0,
2694 "Max value of availBuffers since last driver reset");
2695 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued",
2696 CTLFLAG_RD, &queue->queue_adds, 0,
2697 "Total buffers added to queue");
2698 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued",
2699 CTLFLAG_RD, &queue->queue_removes, 0,
2700 "Total buffers removed from queue");
2701 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "queueRestart",
2702 CTLFLAG_RD, &queue->queue_restart, 0,
2703 "Total times the queue has been restarted");
2704 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain",
2705 CTLFLAG_RD, &queue->longest_chain, 0,
2706 "Max buffers used for a single packet");
2707 }
2708
2709 static void
cpsw_add_watchdog_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * node,struct cpsw_softc * sc)2710 cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node,
2711 struct cpsw_softc *sc)
2712 {
2713 struct sysctl_oid_list *parent;
2714
2715 parent = SYSCTL_CHILDREN(node);
2716 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets",
2717 CTLFLAG_RD, &sc->watchdog.resets, 0,
2718 "Total number of watchdog resets");
2719 }
2720
2721 static void
cpsw_add_sysctls(struct cpsw_softc * sc)2722 cpsw_add_sysctls(struct cpsw_softc *sc)
2723 {
2724 struct sysctl_ctx_list *ctx;
2725 struct sysctl_oid *stats_node, *queue_node, *node;
2726 struct sysctl_oid_list *parent, *stats_parent, *queue_parent;
2727 struct sysctl_oid_list *ports_parent, *port_parent;
2728 char port[16];
2729 int i;
2730
2731 ctx = device_get_sysctl_ctx(sc->dev);
2732 parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
2733
2734 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug",
2735 CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages");
2736
2737 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs",
2738 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
2739 sc, 0, cpsw_stat_attached, "IU",
2740 "Time since driver attach");
2741
2742 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "intr_coalesce_us",
2743 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
2744 sc, 0, cpsw_intr_coalesce, "IU",
2745 "minimum time between interrupts");
2746
2747 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports",
2748 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CPSW Ports Statistics");
2749 ports_parent = SYSCTL_CHILDREN(node);
2750 for (i = 0; i < CPSW_PORTS; i++) {
2751 if (!sc->dualemac && i != sc->active_slave)
2752 continue;
2753 port[0] = '0' + i;
2754 port[1] = '\0';
2755 node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO,
2756 port, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
2757 "CPSW Port Statistics");
2758 port_parent = SYSCTL_CHILDREN(node);
2759 SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime",
2760 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, i,
2761 cpsw_stat_uptime, "IU", "Seconds since driver init");
2762 }
2763
2764 stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
2765 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CPSW Statistics");
2766 stats_parent = SYSCTL_CHILDREN(stats_node);
2767 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) {
2768 SYSCTL_ADD_PROC(ctx, stats_parent, i,
2769 cpsw_stat_sysctls[i].oid,
2770 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
2771 sc, 0, cpsw_stats_sysctl, "IU",
2772 cpsw_stat_sysctls[i].oid);
2773 }
2774
2775 queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue",
2776 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CPSW Queue Statistics");
2777 queue_parent = SYSCTL_CHILDREN(queue_node);
2778
2779 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx",
2780 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Statistics");
2781 cpsw_add_queue_sysctls(ctx, node, &sc->tx);
2782
2783 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx",
2784 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Statistics");
2785 cpsw_add_queue_sysctls(ctx, node, &sc->rx);
2786
2787 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog",
2788 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Watchdog Statistics");
2789 cpsw_add_watchdog_sysctls(ctx, node, sc);
2790 }
2791
2792 #ifdef CPSW_ETHERSWITCH
2793 static etherswitch_info_t etherswitch_info = {
2794 .es_nports = CPSW_PORTS + 1,
2795 .es_nvlangroups = CPSW_VLANS,
2796 .es_name = "TI Common Platform Ethernet Switch (CPSW)",
2797 .es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q,
2798 };
2799
2800 static etherswitch_info_t *
cpsw_getinfo(device_t dev)2801 cpsw_getinfo(device_t dev)
2802 {
2803 return (ðerswitch_info);
2804 }
2805
2806 static int
cpsw_getport(device_t dev,etherswitch_port_t * p)2807 cpsw_getport(device_t dev, etherswitch_port_t *p)
2808 {
2809 int err;
2810 struct cpsw_softc *sc;
2811 struct cpswp_softc *psc;
2812 struct ifmediareq *ifmr;
2813 uint32_t reg;
2814
2815 if (p->es_port < 0 || p->es_port > CPSW_PORTS)
2816 return (ENXIO);
2817
2818 err = 0;
2819 sc = device_get_softc(dev);
2820 if (p->es_port == CPSW_CPU_PORT) {
2821 p->es_flags |= ETHERSWITCH_PORT_CPU;
2822 ifmr = &p->es_ifmr;
2823 ifmr->ifm_current = ifmr->ifm_active =
2824 IFM_ETHER | IFM_1000_T | IFM_FDX;
2825 ifmr->ifm_mask = 0;
2826 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID;
2827 ifmr->ifm_count = 0;
2828 } else {
2829 psc = device_get_softc(sc->port[p->es_port - 1].dev);
2830 err = ifmedia_ioctl(psc->ifp, &p->es_ifr,
2831 &psc->mii->mii_media, SIOCGIFMEDIA);
2832 }
2833 reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port));
2834 p->es_pvid = reg & ETHERSWITCH_VID_MASK;
2835
2836 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));
2837 if (reg & ALE_PORTCTL_DROP_UNTAGGED)
2838 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED;
2839 if (reg & ALE_PORTCTL_INGRESS)
2840 p->es_flags |= ETHERSWITCH_PORT_INGRESS;
2841
2842 return (err);
2843 }
2844
2845 static int
cpsw_setport(device_t dev,etherswitch_port_t * p)2846 cpsw_setport(device_t dev, etherswitch_port_t *p)
2847 {
2848 struct cpsw_softc *sc;
2849 struct cpswp_softc *psc;
2850 struct ifmedia *ifm;
2851 uint32_t reg;
2852
2853 if (p->es_port < 0 || p->es_port > CPSW_PORTS)
2854 return (ENXIO);
2855
2856 sc = device_get_softc(dev);
2857 if (p->es_pvid != 0) {
2858 cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port),
2859 p->es_pvid & ETHERSWITCH_VID_MASK);
2860 }
2861
2862 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));
2863 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED)
2864 reg |= ALE_PORTCTL_DROP_UNTAGGED;
2865 else
2866 reg &= ~ALE_PORTCTL_DROP_UNTAGGED;
2867 if (p->es_flags & ETHERSWITCH_PORT_INGRESS)
2868 reg |= ALE_PORTCTL_INGRESS;
2869 else
2870 reg &= ~ALE_PORTCTL_INGRESS;
2871 cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg);
2872
2873 /* CPU port does not allow media settings. */
2874 if (p->es_port == CPSW_CPU_PORT)
2875 return (0);
2876
2877 psc = device_get_softc(sc->port[p->es_port - 1].dev);
2878 ifm = &psc->mii->mii_media;
2879
2880 return (ifmedia_ioctl(psc->ifp, &p->es_ifr, ifm, SIOCSIFMEDIA));
2881 }
2882
2883 static int
cpsw_getconf(device_t dev,etherswitch_conf_t * conf)2884 cpsw_getconf(device_t dev, etherswitch_conf_t *conf)
2885 {
2886
2887 /* Return the VLAN mode. */
2888 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE;
2889 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q;
2890
2891 return (0);
2892 }
2893
2894 static int
cpsw_getvgroup(device_t dev,etherswitch_vlangroup_t * vg)2895 cpsw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
2896 {
2897 int i, vid;
2898 uint32_t ale_entry[3];
2899 struct cpsw_softc *sc;
2900
2901 sc = device_get_softc(dev);
2902
2903 if (vg->es_vlangroup >= CPSW_VLANS)
2904 return (EINVAL);
2905
2906 vg->es_vid = 0;
2907 vid = cpsw_vgroups[vg->es_vlangroup].vid;
2908 if (vid == -1)
2909 return (0);
2910
2911 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
2912 cpsw_ale_read_entry(sc, i, ale_entry);
2913 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN)
2914 continue;
2915 if (vid != ALE_VLAN(ale_entry))
2916 continue;
2917
2918 vg->es_fid = 0;
2919 vg->es_vid = ALE_VLAN(ale_entry) | ETHERSWITCH_VID_VALID;
2920 vg->es_member_ports = ALE_VLAN_MEMBERS(ale_entry);
2921 vg->es_untagged_ports = ALE_VLAN_UNTAG(ale_entry);
2922 }
2923
2924 return (0);
2925 }
2926
2927 static void
cpsw_remove_vlan(struct cpsw_softc * sc,int vlan)2928 cpsw_remove_vlan(struct cpsw_softc *sc, int vlan)
2929 {
2930 int i;
2931 uint32_t ale_entry[3];
2932
2933 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
2934 cpsw_ale_read_entry(sc, i, ale_entry);
2935 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN)
2936 continue;
2937 if (vlan != ALE_VLAN(ale_entry))
2938 continue;
2939 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0;
2940 cpsw_ale_write_entry(sc, i, ale_entry);
2941 break;
2942 }
2943 }
2944
2945 static int
cpsw_setvgroup(device_t dev,etherswitch_vlangroup_t * vg)2946 cpsw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
2947 {
2948 int i;
2949 struct cpsw_softc *sc;
2950
2951 sc = device_get_softc(dev);
2952
2953 for (i = 0; i < CPSW_VLANS; i++) {
2954 /* Is this Vlan ID in use by another vlangroup ? */
2955 if (vg->es_vlangroup != i && cpsw_vgroups[i].vid == vg->es_vid)
2956 return (EINVAL);
2957 }
2958
2959 if (vg->es_vid == 0) {
2960 if (cpsw_vgroups[vg->es_vlangroup].vid == -1)
2961 return (0);
2962 cpsw_remove_vlan(sc, cpsw_vgroups[vg->es_vlangroup].vid);
2963 cpsw_vgroups[vg->es_vlangroup].vid = -1;
2964 vg->es_untagged_ports = 0;
2965 vg->es_member_ports = 0;
2966 vg->es_vid = 0;
2967 return (0);
2968 }
2969
2970 vg->es_vid &= ETHERSWITCH_VID_MASK;
2971 vg->es_member_ports &= CPSW_PORTS_MASK;
2972 vg->es_untagged_ports &= CPSW_PORTS_MASK;
2973
2974 if (cpsw_vgroups[vg->es_vlangroup].vid != -1 &&
2975 cpsw_vgroups[vg->es_vlangroup].vid != vg->es_vid)
2976 return (EINVAL);
2977
2978 cpsw_vgroups[vg->es_vlangroup].vid = vg->es_vid;
2979 cpsw_ale_update_vlan_table(sc, vg->es_vid, vg->es_member_ports,
2980 vg->es_untagged_ports, vg->es_member_ports, 0);
2981
2982 return (0);
2983 }
2984
2985 static int
cpsw_readreg(device_t dev,int addr)2986 cpsw_readreg(device_t dev, int addr)
2987 {
2988
2989 /* Not supported. */
2990 return (0);
2991 }
2992
2993 static int
cpsw_writereg(device_t dev,int addr,int value)2994 cpsw_writereg(device_t dev, int addr, int value)
2995 {
2996
2997 /* Not supported. */
2998 return (0);
2999 }
3000
3001 static int
cpsw_readphy(device_t dev,int phy,int reg)3002 cpsw_readphy(device_t dev, int phy, int reg)
3003 {
3004
3005 /* Not supported. */
3006 return (0);
3007 }
3008
3009 static int
cpsw_writephy(device_t dev,int phy,int reg,int data)3010 cpsw_writephy(device_t dev, int phy, int reg, int data)
3011 {
3012
3013 /* Not supported. */
3014 return (0);
3015 }
3016 #endif
3017