1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
5 *
6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
7 * under sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include "opt_acpi.h"
32 #if defined(__amd64__)
33 #define DEV_APIC
34 #else
35 #include "opt_apic.h"
36 #endif
37 #include "opt_ddb.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/domainset.h>
42 #include <sys/kernel.h>
43 #include <sys/lock.h>
44 #include <sys/malloc.h>
45 #include <sys/memdesc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/rman.h>
49 #include <sys/rwlock.h>
50 #include <sys/smp.h>
51 #include <sys/taskqueue.h>
52 #include <sys/tree.h>
53 #include <sys/vmem.h>
54 #include <vm/vm.h>
55 #include <vm/vm_extern.h>
56 #include <vm/vm_kern.h>
57 #include <vm/vm_object.h>
58 #include <vm/vm_page.h>
59 #include <vm/vm_pager.h>
60 #include <vm/vm_map.h>
61 #include <contrib/dev/acpica/include/acpi.h>
62 #include <contrib/dev/acpica/include/accommon.h>
63 #include <dev/acpica/acpivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66 #include <machine/bus.h>
67 #include <machine/pci_cfgreg.h>
68 #include <machine/md_var.h>
69 #include <machine/cputypes.h>
70 #include <x86/include/busdma_impl.h>
71 #include <dev/iommu/busdma_iommu.h>
72 #include <x86/iommu/intel_reg.h>
73 #include <x86/iommu/x86_iommu.h>
74 #include <x86/iommu/intel_dmar.h>
75
76 #ifdef DEV_APIC
77 #include "pcib_if.h"
78 #include <machine/intr_machdep.h>
79 #include <x86/apicreg.h>
80 #include <x86/apicvar.h>
81 #endif
82
83 #define DMAR_FAULT_IRQ_RID 0
84 #define DMAR_QI_IRQ_RID 1
85 #define DMAR_REG_RID 2
86
87 static device_t *dmar_devs;
88 static int dmar_devcnt;
89
90 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
91
92 static void
dmar_iterate_tbl(dmar_iter_t iter,void * arg)93 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
94 {
95 ACPI_TABLE_DMAR *dmartbl;
96 ACPI_DMAR_HEADER *dmarh;
97 char *ptr, *ptrend;
98 ACPI_STATUS status;
99
100 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
101 if (ACPI_FAILURE(status))
102 return;
103 ptr = (char *)dmartbl + sizeof(*dmartbl);
104 ptrend = (char *)dmartbl + dmartbl->Header.Length;
105 for (;;) {
106 if (ptr >= ptrend)
107 break;
108 dmarh = (ACPI_DMAR_HEADER *)ptr;
109 if (dmarh->Length <= 0) {
110 printf("dmar_identify: corrupted DMAR table, l %d\n",
111 dmarh->Length);
112 break;
113 }
114 ptr += dmarh->Length;
115 if (!iter(dmarh, arg))
116 break;
117 }
118 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
119 }
120
121 struct find_iter_args {
122 int i;
123 ACPI_DMAR_HARDWARE_UNIT *res;
124 };
125
126 static int
dmar_find_iter(ACPI_DMAR_HEADER * dmarh,void * arg)127 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
128 {
129 struct find_iter_args *fia;
130
131 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
132 return (1);
133
134 fia = arg;
135 if (fia->i == 0) {
136 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
137 return (0);
138 }
139 fia->i--;
140 return (1);
141 }
142
143 static ACPI_DMAR_HARDWARE_UNIT *
dmar_find_by_index(int idx)144 dmar_find_by_index(int idx)
145 {
146 struct find_iter_args fia;
147
148 fia.i = idx;
149 fia.res = NULL;
150 dmar_iterate_tbl(dmar_find_iter, &fia);
151 return (fia.res);
152 }
153
154 static int
dmar_count_iter(ACPI_DMAR_HEADER * dmarh,void * arg)155 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
156 {
157
158 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
159 dmar_devcnt++;
160 return (1);
161 }
162
163 int dmar_rmrr_enable = 1;
164
165 static int dmar_enable = 0;
166 static void
dmar_identify(driver_t * driver,device_t parent)167 dmar_identify(driver_t *driver, device_t parent)
168 {
169 ACPI_TABLE_DMAR *dmartbl;
170 ACPI_DMAR_HARDWARE_UNIT *dmarh;
171 ACPI_STATUS status;
172 int i, error;
173
174 if (acpi_disabled("dmar"))
175 return;
176 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
177 if (!dmar_enable)
178 return;
179 TUNABLE_INT_FETCH("hw.dmar.rmrr_enable", &dmar_rmrr_enable);
180
181 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
182 if (ACPI_FAILURE(status))
183 return;
184 haw = dmartbl->Width + 1;
185 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
186 iommu_high = BUS_SPACE_MAXADDR;
187 else
188 iommu_high = 1ULL << (haw + 1);
189 if (bootverbose) {
190 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
191 (unsigned)dmartbl->Flags,
192 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
193 }
194 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
195
196 dmar_iterate_tbl(dmar_count_iter, NULL);
197 if (dmar_devcnt == 0)
198 return;
199 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
200 M_WAITOK | M_ZERO);
201 for (i = 0; i < dmar_devcnt; i++) {
202 dmarh = dmar_find_by_index(i);
203 if (dmarh == NULL) {
204 printf("dmar_identify: cannot find HWUNIT %d\n", i);
205 continue;
206 }
207 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
208 if (dmar_devs[i] == NULL) {
209 printf("dmar_identify: cannot create instance %d\n", i);
210 continue;
211 }
212 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
213 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
214 if (error != 0) {
215 printf(
216 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
217 i, (uintmax_t)dmarh->Address, error);
218 device_delete_child(parent, dmar_devs[i]);
219 dmar_devs[i] = NULL;
220 }
221 }
222 }
223
224 static int
dmar_probe(device_t dev)225 dmar_probe(device_t dev)
226 {
227
228 if (acpi_get_handle(dev) != NULL)
229 return (ENXIO);
230 device_set_desc(dev, "DMA remap");
231 return (BUS_PROBE_NOWILDCARD);
232 }
233
234 static void
dmar_release_resources(device_t dev,struct dmar_unit * unit)235 dmar_release_resources(device_t dev, struct dmar_unit *unit)
236 {
237 int i;
238
239 iommu_fini_busdma(&unit->iommu);
240 dmar_fini_irt(unit);
241 dmar_fini_qi(unit);
242 dmar_fini_fault_log(unit);
243 for (i = 0; i < DMAR_INTR_TOTAL; i++)
244 iommu_release_intr(DMAR2IOMMU(unit), i);
245 if (unit->regs != NULL) {
246 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
247 unit->regs);
248 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
249 unit->regs);
250 unit->regs = NULL;
251 }
252 if (unit->domids != NULL) {
253 delete_unrhdr(unit->domids);
254 unit->domids = NULL;
255 }
256 if (unit->ctx_obj != NULL) {
257 vm_object_deallocate(unit->ctx_obj);
258 unit->ctx_obj = NULL;
259 }
260 sysctl_ctx_free(&unit->iommu.sysctl_ctx);
261 }
262
263 #ifdef DEV_APIC
264 static int
dmar_remap_intr(device_t dev,device_t child,u_int irq)265 dmar_remap_intr(device_t dev, device_t child, u_int irq)
266 {
267 struct dmar_unit *unit;
268 struct iommu_msi_data *dmd;
269 uint64_t msi_addr;
270 uint32_t msi_data;
271 int i, error;
272
273 unit = device_get_softc(dev);
274 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
275 dmd = &unit->x86c.intrs[i];
276 if (irq == dmd->irq) {
277 error = PCIB_MAP_MSI(device_get_parent(
278 device_get_parent(dev)),
279 dev, irq, &msi_addr, &msi_data);
280 if (error != 0)
281 return (error);
282 DMAR_LOCK(unit);
283 dmd->msi_data = msi_data;
284 dmd->msi_addr = msi_addr;
285 (dmd->disable_intr)(DMAR2IOMMU(unit));
286 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
287 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
288 dmar_write4(unit, dmd->msi_uaddr_reg,
289 dmd->msi_addr >> 32);
290 (dmd->enable_intr)(DMAR2IOMMU(unit));
291 DMAR_UNLOCK(unit);
292 return (0);
293 }
294 }
295 return (ENOENT);
296 }
297 #endif
298
299 static void
dmar_print_caps(device_t dev,struct dmar_unit * unit,ACPI_DMAR_HARDWARE_UNIT * dmaru)300 dmar_print_caps(device_t dev, struct dmar_unit *unit,
301 ACPI_DMAR_HARDWARE_UNIT *dmaru)
302 {
303 uint32_t caphi, ecaphi;
304
305 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
306 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
307 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
308 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
309 caphi = unit->hw_cap >> 32;
310 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
311 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
312 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
313 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
314 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
315 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
316 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
317 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
318 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
319 printf("\n");
320 ecaphi = unit->hw_ecap >> 32;
321 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
322 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
323 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
324 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
325 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
326 DMAR_ECAP_IRO(unit->hw_ecap));
327 }
328
329 /* Remapping Hardware Static Affinity Structure lookup */
330 struct rhsa_iter_arg {
331 uint64_t base;
332 u_int proxim_dom;
333 };
334
335 static int
dmar_rhsa_iter(ACPI_DMAR_HEADER * dmarh,void * arg)336 dmar_rhsa_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
337 {
338 struct rhsa_iter_arg *ria;
339 ACPI_DMAR_RHSA *adr;
340
341 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_AFFINITY) {
342 ria = arg;
343 adr = (ACPI_DMAR_RHSA *)dmarh;
344 if (adr->BaseAddress == ria->base)
345 ria->proxim_dom = adr->ProximityDomain;
346 }
347 return (1);
348 }
349
350 static int
dmar_attach(device_t dev)351 dmar_attach(device_t dev)
352 {
353 struct dmar_unit *unit;
354 ACPI_DMAR_HARDWARE_UNIT *dmaru;
355 struct iommu_msi_data *dmd;
356 struct rhsa_iter_arg ria;
357 uint64_t timeout;
358 int disable_pmr;
359 int i, error;
360
361 unit = device_get_softc(dev);
362 unit->iommu.unit = device_get_unit(dev);
363 unit->iommu.dev = dev;
364 sysctl_ctx_init(&unit->iommu.sysctl_ctx);
365 dmaru = dmar_find_by_index(unit->iommu.unit);
366 if (dmaru == NULL)
367 return (EINVAL);
368 unit->segment = dmaru->Segment;
369 unit->base = dmaru->Address;
370 unit->reg_rid = DMAR_REG_RID;
371 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
372 &unit->reg_rid, RF_ACTIVE);
373 if (unit->regs == NULL) {
374 device_printf(dev, "cannot allocate register window\n");
375 dmar_devs[unit->iommu.unit] = NULL;
376 return (ENOMEM);
377 }
378 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
379 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
380 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
381 if (bootverbose)
382 dmar_print_caps(dev, unit, dmaru);
383 dmar_quirks_post_ident(unit);
384 unit->memdomain = -1;
385 ria.base = unit->base;
386 ria.proxim_dom = -1;
387 dmar_iterate_tbl(dmar_rhsa_iter, &ria);
388 if (ria.proxim_dom != -1)
389 unit->memdomain = acpi_map_pxm_to_vm_domainid(ria.proxim_dom);
390
391 timeout = dmar_get_timeout();
392 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout);
393 dmar_update_timeout(timeout);
394
395 for (i = 0; i < DMAR_INTR_TOTAL; i++)
396 unit->x86c.intrs[i].irq = -1;
397
398 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT];
399 dmd->name = "fault";
400 dmd->irq_rid = DMAR_FAULT_IRQ_RID;
401 dmd->handler = dmar_fault_intr;
402 dmd->msi_data_reg = DMAR_FEDATA_REG;
403 dmd->msi_addr_reg = DMAR_FEADDR_REG;
404 dmd->msi_uaddr_reg = DMAR_FEUADDR_REG;
405 dmd->enable_intr = dmar_enable_fault_intr;
406 dmd->disable_intr = dmar_disable_fault_intr;
407 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_FAULT);
408 if (error != 0) {
409 dmar_release_resources(dev, unit);
410 dmar_devs[unit->iommu.unit] = NULL;
411 return (error);
412 }
413 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
414 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
415 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32);
416
417 if (DMAR_HAS_QI(unit)) {
418 dmd = &unit->x86c.intrs[DMAR_INTR_QI];
419 dmd->name = "qi";
420 dmd->irq_rid = DMAR_QI_IRQ_RID;
421 dmd->handler = dmar_qi_intr;
422 dmd->msi_data_reg = DMAR_IEDATA_REG;
423 dmd->msi_addr_reg = DMAR_IEADDR_REG;
424 dmd->msi_uaddr_reg = DMAR_IEUADDR_REG;
425 dmd->enable_intr = dmar_enable_qi_intr;
426 dmd->disable_intr = dmar_disable_qi_intr;
427 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_QI);
428 if (error != 0) {
429 dmar_release_resources(dev, unit);
430 dmar_devs[unit->iommu.unit] = NULL;
431 return (error);
432 }
433
434 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
435 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
436 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32);
437 }
438
439 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF);
440 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
441 &unit->iommu.lock);
442 LIST_INIT(&unit->domains);
443
444 /*
445 * 9.2 "Context Entry":
446 * When Caching Mode (CM) field is reported as Set, the
447 * domain-id value of zero is architecturally reserved.
448 * Software must not use domain-id value of zero
449 * when CM is Set.
450 */
451 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
452 alloc_unr_specific(unit->domids, 0);
453
454 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
455 DMAR_CTX_CNT), 0, 0, NULL);
456 if (unit->memdomain != -1) {
457 unit->ctx_obj->domain.dr_policy = DOMAINSET_PREF(
458 unit->memdomain);
459 }
460
461 /*
462 * Allocate and load the root entry table pointer. Enable the
463 * address translation after the required invalidations are
464 * done.
465 */
466 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO);
467 DMAR_LOCK(unit);
468 error = dmar_load_root_entry_ptr(unit);
469 if (error != 0) {
470 DMAR_UNLOCK(unit);
471 dmar_release_resources(dev, unit);
472 dmar_devs[unit->iommu.unit] = NULL;
473 return (error);
474 }
475 error = dmar_inv_ctx_glob(unit);
476 if (error != 0) {
477 DMAR_UNLOCK(unit);
478 dmar_release_resources(dev, unit);
479 dmar_devs[unit->iommu.unit] = NULL;
480 return (error);
481 }
482 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
483 error = dmar_inv_iotlb_glob(unit);
484 if (error != 0) {
485 DMAR_UNLOCK(unit);
486 dmar_release_resources(dev, unit);
487 dmar_devs[unit->iommu.unit] = NULL;
488 return (error);
489 }
490 }
491
492 DMAR_UNLOCK(unit);
493 error = dmar_init_fault_log(unit);
494 if (error != 0) {
495 dmar_release_resources(dev, unit);
496 dmar_devs[unit->iommu.unit] = NULL;
497 return (error);
498 }
499 error = dmar_init_qi(unit);
500 if (error != 0) {
501 dmar_release_resources(dev, unit);
502 dmar_devs[unit->iommu.unit] = NULL;
503 return (error);
504 }
505 error = dmar_init_irt(unit);
506 if (error != 0) {
507 dmar_release_resources(dev, unit);
508 dmar_devs[unit->iommu.unit] = NULL;
509 return (error);
510 }
511
512 disable_pmr = 0;
513 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr);
514 if (disable_pmr) {
515 error = dmar_disable_protected_regions(unit);
516 if (error != 0)
517 device_printf(dev,
518 "Failed to disable protected regions\n");
519 }
520
521 error = iommu_init_busdma(&unit->iommu);
522 if (error != 0) {
523 dmar_release_resources(dev, unit);
524 dmar_devs[unit->iommu.unit] = NULL;
525 return (error);
526 }
527
528 #ifdef NOTYET
529 DMAR_LOCK(unit);
530 error = dmar_enable_translation(unit);
531 if (error != 0) {
532 DMAR_UNLOCK(unit);
533 dmar_release_resources(dev, unit);
534 dmar_devs[unit->iommu.unit] = NULL;
535 return (error);
536 }
537 DMAR_UNLOCK(unit);
538 #endif
539
540 return (0);
541 }
542
543 static int
dmar_detach(device_t dev)544 dmar_detach(device_t dev)
545 {
546
547 return (EBUSY);
548 }
549
550 static int
dmar_suspend(device_t dev)551 dmar_suspend(device_t dev)
552 {
553
554 return (0);
555 }
556
557 static int
dmar_resume(device_t dev)558 dmar_resume(device_t dev)
559 {
560
561 /* XXXKIB */
562 return (0);
563 }
564
565 static device_method_t dmar_methods[] = {
566 DEVMETHOD(device_identify, dmar_identify),
567 DEVMETHOD(device_probe, dmar_probe),
568 DEVMETHOD(device_attach, dmar_attach),
569 DEVMETHOD(device_detach, dmar_detach),
570 DEVMETHOD(device_suspend, dmar_suspend),
571 DEVMETHOD(device_resume, dmar_resume),
572 #ifdef DEV_APIC
573 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
574 #endif
575 DEVMETHOD_END
576 };
577
578 static driver_t dmar_driver = {
579 "dmar",
580 dmar_methods,
581 sizeof(struct dmar_unit),
582 };
583
584 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0);
585 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
586
587 static void
dmar_print_path(int busno,int depth,const ACPI_DMAR_PCI_PATH * path)588 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
589 {
590 int i;
591
592 printf("[%d, ", busno);
593 for (i = 0; i < depth; i++) {
594 if (i != 0)
595 printf(", ");
596 printf("(%d, %d)", path[i].Device, path[i].Function);
597 }
598 printf("]");
599 }
600
601 int
dmar_dev_depth(device_t child)602 dmar_dev_depth(device_t child)
603 {
604 devclass_t pci_class;
605 device_t bus, pcib;
606 int depth;
607
608 pci_class = devclass_find("pci");
609 for (depth = 1; ; depth++) {
610 bus = device_get_parent(child);
611 pcib = device_get_parent(bus);
612 if (device_get_devclass(device_get_parent(pcib)) !=
613 pci_class)
614 return (depth);
615 child = pcib;
616 }
617 }
618
619 void
dmar_dev_path(device_t child,int * busno,void * path1,int depth)620 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
621 {
622 devclass_t pci_class;
623 device_t bus, pcib;
624 ACPI_DMAR_PCI_PATH *path;
625
626 pci_class = devclass_find("pci");
627 path = path1;
628 for (depth--; depth != -1; depth--) {
629 path[depth].Device = pci_get_slot(child);
630 path[depth].Function = pci_get_function(child);
631 bus = device_get_parent(child);
632 pcib = device_get_parent(bus);
633 if (device_get_devclass(device_get_parent(pcib)) !=
634 pci_class) {
635 /* reached a host bridge */
636 *busno = pcib_get_bus(bus);
637 return;
638 }
639 child = pcib;
640 }
641 panic("wrong depth");
642 }
643
644 static int
dmar_match_pathes(int busno1,const ACPI_DMAR_PCI_PATH * path1,int depth1,int busno2,const ACPI_DMAR_PCI_PATH * path2,int depth2,enum AcpiDmarScopeType scope_type)645 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
646 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
647 enum AcpiDmarScopeType scope_type)
648 {
649 int i, depth;
650
651 if (busno1 != busno2)
652 return (0);
653 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
654 return (0);
655 depth = depth1;
656 if (depth2 < depth)
657 depth = depth2;
658 for (i = 0; i < depth; i++) {
659 if (path1[i].Device != path2[i].Device ||
660 path1[i].Function != path2[i].Function)
661 return (0);
662 }
663 return (1);
664 }
665
666 static int
dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE * devscope,int dev_busno,const ACPI_DMAR_PCI_PATH * dev_path,int dev_path_len)667 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
668 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
669 {
670 ACPI_DMAR_PCI_PATH *path;
671 int path_len;
672
673 if (devscope->Length < sizeof(*devscope)) {
674 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
675 devscope->Length);
676 return (-1);
677 }
678 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
679 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
680 return (0);
681 path_len = devscope->Length - sizeof(*devscope);
682 if (path_len % 2 != 0) {
683 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
684 devscope->Length);
685 return (-1);
686 }
687 path_len /= 2;
688 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
689 if (path_len == 0) {
690 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
691 devscope->Length);
692 return (-1);
693 }
694
695 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
696 dev_path, dev_path_len, devscope->EntryType));
697 }
698
699 static bool
dmar_match_by_path(struct dmar_unit * unit,int dev_domain,int dev_busno,const ACPI_DMAR_PCI_PATH * dev_path,int dev_path_len,const char ** banner)700 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
701 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
702 {
703 ACPI_DMAR_HARDWARE_UNIT *dmarh;
704 ACPI_DMAR_DEVICE_SCOPE *devscope;
705 char *ptr, *ptrend;
706 int match;
707
708 dmarh = dmar_find_by_index(unit->iommu.unit);
709 if (dmarh == NULL)
710 return (false);
711 if (dmarh->Segment != dev_domain)
712 return (false);
713 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
714 if (banner != NULL)
715 *banner = "INCLUDE_ALL";
716 return (true);
717 }
718 ptr = (char *)dmarh + sizeof(*dmarh);
719 ptrend = (char *)dmarh + dmarh->Header.Length;
720 while (ptr < ptrend) {
721 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
722 ptr += devscope->Length;
723 match = dmar_match_devscope(devscope, dev_busno, dev_path,
724 dev_path_len);
725 if (match == -1)
726 return (false);
727 if (match == 1) {
728 if (banner != NULL)
729 *banner = "specific match";
730 return (true);
731 }
732 }
733 return (false);
734 }
735
736 static struct dmar_unit *
dmar_find_by_scope(int dev_domain,int dev_busno,const ACPI_DMAR_PCI_PATH * dev_path,int dev_path_len)737 dmar_find_by_scope(int dev_domain, int dev_busno,
738 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
739 {
740 struct dmar_unit *unit;
741 int i;
742
743 for (i = 0; i < dmar_devcnt; i++) {
744 if (dmar_devs[i] == NULL)
745 continue;
746 unit = device_get_softc(dmar_devs[i]);
747 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
748 dev_path_len, NULL))
749 return (unit);
750 }
751 return (NULL);
752 }
753
754 struct dmar_unit *
dmar_find(device_t dev,bool verbose)755 dmar_find(device_t dev, bool verbose)
756 {
757 struct dmar_unit *unit;
758 const char *banner;
759 int i, dev_domain, dev_busno, dev_path_len;
760
761 /*
762 * This function can only handle PCI(e) devices.
763 */
764 if (device_get_devclass(device_get_parent(dev)) !=
765 devclass_find("pci"))
766 return (NULL);
767
768 dev_domain = pci_get_domain(dev);
769 dev_path_len = dmar_dev_depth(dev);
770 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
771 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
772 banner = "";
773
774 for (i = 0; i < dmar_devcnt; i++) {
775 if (dmar_devs[i] == NULL)
776 continue;
777 unit = device_get_softc(dmar_devs[i]);
778 if (dmar_match_by_path(unit, dev_domain, dev_busno,
779 dev_path, dev_path_len, &banner))
780 break;
781 }
782 if (i == dmar_devcnt)
783 return (NULL);
784
785 if (verbose) {
786 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
787 dev_domain, pci_get_bus(dev), pci_get_slot(dev),
788 pci_get_function(dev), unit->iommu.unit, banner);
789 printf(" scope path ");
790 dmar_print_path(dev_busno, dev_path_len, dev_path);
791 printf("\n");
792 }
793 iommu_device_set_iommu_prop(dev, unit->iommu.dev);
794 return (unit);
795 }
796
797 static struct dmar_unit *
dmar_find_nonpci(u_int id,u_int entry_type,uint16_t * rid)798 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
799 {
800 device_t dmar_dev;
801 struct dmar_unit *unit;
802 ACPI_DMAR_HARDWARE_UNIT *dmarh;
803 ACPI_DMAR_DEVICE_SCOPE *devscope;
804 ACPI_DMAR_PCI_PATH *path;
805 char *ptr, *ptrend;
806 #ifdef DEV_APIC
807 int error;
808 #endif
809 int i;
810
811 for (i = 0; i < dmar_devcnt; i++) {
812 dmar_dev = dmar_devs[i];
813 if (dmar_dev == NULL)
814 continue;
815 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
816 dmarh = dmar_find_by_index(i);
817 if (dmarh == NULL)
818 continue;
819 ptr = (char *)dmarh + sizeof(*dmarh);
820 ptrend = (char *)dmarh + dmarh->Header.Length;
821 for (;;) {
822 if (ptr >= ptrend)
823 break;
824 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
825 ptr += devscope->Length;
826 if (devscope->EntryType != entry_type)
827 continue;
828 if (devscope->EnumerationId != id)
829 continue;
830 #ifdef DEV_APIC
831 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
832 error = ioapic_get_rid(id, rid);
833 /*
834 * If our IOAPIC has PCI bindings then
835 * use the PCI device rid.
836 */
837 if (error == 0)
838 return (unit);
839 }
840 #endif
841 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
842 == 2) {
843 if (rid != NULL) {
844 path = (ACPI_DMAR_PCI_PATH *)
845 (devscope + 1);
846 *rid = PCI_RID(devscope->Bus,
847 path->Device, path->Function);
848 }
849 return (unit);
850 }
851 printf(
852 "dmar_find_nonpci: id %d type %d path length != 2\n",
853 id, entry_type);
854 break;
855 }
856 }
857 return (NULL);
858 }
859
860 struct dmar_unit *
dmar_find_hpet(device_t dev,uint16_t * rid)861 dmar_find_hpet(device_t dev, uint16_t *rid)
862 {
863 struct dmar_unit *unit;
864
865 unit = dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
866 rid);
867 if (unit != NULL)
868 iommu_device_set_iommu_prop(dev, unit->iommu.dev);
869 return (unit);
870 }
871
872 struct dmar_unit *
dmar_find_ioapic(u_int apic_id,uint16_t * rid)873 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
874 {
875 struct dmar_unit *unit;
876 device_t apic_dev;
877
878 unit = dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid);
879 if (unit != NULL) {
880 apic_dev = ioapic_get_dev(apic_id);
881 if (apic_dev != NULL)
882 iommu_device_set_iommu_prop(apic_dev, unit->iommu.dev);
883 }
884 return (unit);
885 }
886
887 struct rmrr_iter_args {
888 struct dmar_domain *domain;
889 int dev_domain;
890 int dev_busno;
891 const ACPI_DMAR_PCI_PATH *dev_path;
892 int dev_path_len;
893 struct iommu_map_entries_tailq *rmrr_entries;
894 };
895
896 static int
dmar_rmrr_iter(ACPI_DMAR_HEADER * dmarh,void * arg)897 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
898 {
899 struct rmrr_iter_args *ria;
900 ACPI_DMAR_RESERVED_MEMORY *resmem;
901 ACPI_DMAR_DEVICE_SCOPE *devscope;
902 struct iommu_map_entry *entry;
903 char *ptr, *ptrend;
904 int match;
905
906 if (!dmar_rmrr_enable)
907 return (1);
908
909 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
910 return (1);
911
912 ria = arg;
913 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
914 if (resmem->Segment != ria->dev_domain)
915 return (1);
916
917 ptr = (char *)resmem + sizeof(*resmem);
918 ptrend = (char *)resmem + resmem->Header.Length;
919 for (;;) {
920 if (ptr >= ptrend)
921 break;
922 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
923 ptr += devscope->Length;
924 match = dmar_match_devscope(devscope, ria->dev_busno,
925 ria->dev_path, ria->dev_path_len);
926 if (match == 1) {
927 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain),
928 IOMMU_PGF_WAITOK);
929 entry->start = resmem->BaseAddress;
930 /* The RMRR entry end address is inclusive. */
931 entry->end = resmem->EndAddress;
932 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
933 dmamap_link);
934 }
935 }
936
937 return (1);
938 }
939
940 void
dmar_dev_parse_rmrr(struct dmar_domain * domain,int dev_domain,int dev_busno,const void * dev_path,int dev_path_len,struct iommu_map_entries_tailq * rmrr_entries)941 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
942 const void *dev_path, int dev_path_len,
943 struct iommu_map_entries_tailq *rmrr_entries)
944 {
945 struct rmrr_iter_args ria;
946
947 ria.domain = domain;
948 ria.dev_domain = dev_domain;
949 ria.dev_busno = dev_busno;
950 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
951 ria.dev_path_len = dev_path_len;
952 ria.rmrr_entries = rmrr_entries;
953 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
954 }
955
956 struct inst_rmrr_iter_args {
957 struct dmar_unit *dmar;
958 };
959
960 static device_t
dmar_path_dev(int segment,int path_len,int busno,const ACPI_DMAR_PCI_PATH * path,uint16_t * rid)961 dmar_path_dev(int segment, int path_len, int busno,
962 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
963 {
964 device_t dev;
965 int i;
966
967 dev = NULL;
968 for (i = 0; i < path_len; i++) {
969 dev = pci_find_dbsf(segment, busno, path->Device,
970 path->Function);
971 if (i != path_len - 1) {
972 busno = pci_cfgregread(segment, busno, path->Device,
973 path->Function, PCIR_SECBUS_1, 1);
974 path++;
975 }
976 }
977 *rid = PCI_RID(busno, path->Device, path->Function);
978 return (dev);
979 }
980
981 static int
dmar_inst_rmrr_iter(ACPI_DMAR_HEADER * dmarh,void * arg)982 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
983 {
984 const ACPI_DMAR_RESERVED_MEMORY *resmem;
985 const ACPI_DMAR_DEVICE_SCOPE *devscope;
986 struct inst_rmrr_iter_args *iria;
987 const char *ptr, *ptrend;
988 device_t dev;
989 struct dmar_unit *unit;
990 int dev_path_len;
991 uint16_t rid;
992
993 iria = arg;
994
995 if (!dmar_rmrr_enable)
996 return (1);
997
998 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
999 return (1);
1000
1001 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
1002 if (resmem->Segment != iria->dmar->segment)
1003 return (1);
1004
1005 ptr = (const char *)resmem + sizeof(*resmem);
1006 ptrend = (const char *)resmem + resmem->Header.Length;
1007 for (;;) {
1008 if (ptr >= ptrend)
1009 break;
1010 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
1011 ptr += devscope->Length;
1012 /* XXXKIB bridge */
1013 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
1014 continue;
1015 rid = 0;
1016 dev_path_len = (devscope->Length -
1017 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
1018 dev = dmar_path_dev(resmem->Segment, dev_path_len,
1019 devscope->Bus,
1020 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
1021 if (dev == NULL) {
1022 if (bootverbose) {
1023 printf("dmar%d no dev found for RMRR "
1024 "[%#jx, %#jx] rid %#x scope path ",
1025 iria->dmar->iommu.unit,
1026 (uintmax_t)resmem->BaseAddress,
1027 (uintmax_t)resmem->EndAddress,
1028 rid);
1029 dmar_print_path(devscope->Bus, dev_path_len,
1030 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1031 printf("\n");
1032 }
1033 unit = dmar_find_by_scope(resmem->Segment,
1034 devscope->Bus,
1035 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1036 dev_path_len);
1037 if (iria->dmar != unit)
1038 continue;
1039 dmar_get_ctx_for_devpath(iria->dmar, rid,
1040 resmem->Segment, devscope->Bus,
1041 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1042 dev_path_len, false, true);
1043 } else {
1044 unit = dmar_find(dev, false);
1045 if (iria->dmar != unit)
1046 continue;
1047 iommu_instantiate_ctx(&(iria)->dmar->iommu,
1048 dev, true);
1049 }
1050 }
1051
1052 return (1);
1053
1054 }
1055
1056 /*
1057 * Pre-create all contexts for the DMAR which have RMRR entries.
1058 */
1059 int
dmar_instantiate_rmrr_ctxs(struct iommu_unit * unit)1060 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit)
1061 {
1062 struct dmar_unit *dmar;
1063 struct inst_rmrr_iter_args iria;
1064 int error;
1065
1066 dmar = IOMMU2DMAR(unit);
1067
1068 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1069 return (0);
1070
1071 error = 0;
1072 iria.dmar = dmar;
1073 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1074 DMAR_LOCK(dmar);
1075 if (!LIST_EMPTY(&dmar->domains)) {
1076 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1077 ("dmar%d: RMRR not handled but translation is already enabled",
1078 dmar->iommu.unit));
1079 error = dmar_disable_protected_regions(dmar);
1080 if (error != 0)
1081 printf("dmar%d: Failed to disable protected regions\n",
1082 dmar->iommu.unit);
1083 error = dmar_enable_translation(dmar);
1084 if (bootverbose) {
1085 if (error == 0) {
1086 printf("dmar%d: enabled translation\n",
1087 dmar->iommu.unit);
1088 } else {
1089 printf("dmar%d: enabling translation failed, "
1090 "error %d\n", dmar->iommu.unit, error);
1091 }
1092 }
1093 }
1094 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1095 return (error);
1096 }
1097
1098 #ifdef DDB
1099 #include <ddb/ddb.h>
1100 #include <ddb/db_lex.h>
1101
1102 static void
dmar_print_domain(struct dmar_domain * domain,bool show_mappings)1103 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1104 {
1105 struct iommu_domain *iodom;
1106
1107 iodom = DOM2IODOM(domain);
1108
1109 db_printf(
1110 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1111 " ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1112 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1113 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt,
1114 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt);
1115
1116 iommu_db_domain_print_contexts(iodom);
1117
1118 if (show_mappings)
1119 iommu_db_domain_print_mappings(iodom);
1120 }
1121
DB_SHOW_COMMAND_FLAGS(dmar_domain,db_dmar_print_domain,CS_OWN)1122 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN)
1123 {
1124 struct dmar_unit *unit;
1125 struct dmar_domain *domain;
1126 struct iommu_ctx *ctx;
1127 bool show_mappings, valid;
1128 int pci_domain, bus, device, function, i, t;
1129 db_expr_t radix;
1130
1131 valid = false;
1132 radix = db_radix;
1133 db_radix = 10;
1134 t = db_read_token();
1135 if (t == tSLASH) {
1136 t = db_read_token();
1137 if (t != tIDENT) {
1138 db_printf("Bad modifier\n");
1139 db_radix = radix;
1140 db_skip_to_eol();
1141 return;
1142 }
1143 show_mappings = strchr(db_tok_string, 'm') != NULL;
1144 t = db_read_token();
1145 } else {
1146 show_mappings = false;
1147 }
1148 if (t == tNUMBER) {
1149 pci_domain = db_tok_number;
1150 t = db_read_token();
1151 if (t == tNUMBER) {
1152 bus = db_tok_number;
1153 t = db_read_token();
1154 if (t == tNUMBER) {
1155 device = db_tok_number;
1156 t = db_read_token();
1157 if (t == tNUMBER) {
1158 function = db_tok_number;
1159 valid = true;
1160 }
1161 }
1162 }
1163 }
1164 db_radix = radix;
1165 db_skip_to_eol();
1166 if (!valid) {
1167 db_printf("usage: show dmar_domain [/m] "
1168 "<domain> <bus> <device> <func>\n");
1169 return;
1170 }
1171 for (i = 0; i < dmar_devcnt; i++) {
1172 unit = device_get_softc(dmar_devs[i]);
1173 LIST_FOREACH(domain, &unit->domains, link) {
1174 LIST_FOREACH(ctx, &domain->iodom.contexts, link) {
1175 if (pci_domain == unit->segment &&
1176 bus == pci_get_bus(ctx->tag->owner) &&
1177 device == pci_get_slot(ctx->tag->owner) &&
1178 function == pci_get_function(ctx->tag->
1179 owner)) {
1180 dmar_print_domain(domain,
1181 show_mappings);
1182 goto out;
1183 }
1184 }
1185 }
1186 }
1187 out:;
1188 }
1189
1190 static void
dmar_print_one(int idx,bool show_domains,bool show_mappings)1191 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1192 {
1193 struct dmar_unit *unit;
1194 struct dmar_domain *domain;
1195 int i, frir;
1196
1197 unit = device_get_softc(dmar_devs[idx]);
1198 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit,
1199 unit, dmar_read8(unit, DMAR_RTADDR_REG),
1200 dmar_read4(unit, DMAR_VER_REG));
1201 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1202 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1203 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1204 dmar_read4(unit, DMAR_GSTS_REG),
1205 dmar_read4(unit, DMAR_FSTS_REG),
1206 dmar_read4(unit, DMAR_FECTL_REG));
1207 if (unit->ir_enabled) {
1208 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1209 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1210 }
1211 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1212 dmar_read4(unit, DMAR_FEDATA_REG),
1213 dmar_read4(unit, DMAR_FEADDR_REG),
1214 dmar_read4(unit, DMAR_FEUADDR_REG));
1215 db_printf("primary fault log:\n");
1216 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1217 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1218 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1219 (uintmax_t)dmar_read8(unit, frir),
1220 (uintmax_t)dmar_read8(unit, frir + 8));
1221 }
1222 if (DMAR_HAS_QI(unit)) {
1223 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1224 dmar_read4(unit, DMAR_IEDATA_REG),
1225 dmar_read4(unit, DMAR_IEADDR_REG),
1226 dmar_read4(unit, DMAR_IEUADDR_REG));
1227 if (unit->qi_enabled) {
1228 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1229 "size 0x%jx\n"
1230 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1231 " hw compl 0x%jx@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1232 (uintmax_t)unit->x86c.inv_queue,
1233 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1234 (uintmax_t)unit->x86c.inv_queue_size,
1235 dmar_read4(unit, DMAR_IQH_REG),
1236 dmar_read4(unit, DMAR_IQT_REG),
1237 unit->x86c.inv_queue_avail,
1238 dmar_read4(unit, DMAR_ICS_REG),
1239 dmar_read4(unit, DMAR_IECTL_REG),
1240 (uintmax_t)unit->x86c.inv_waitd_seq_hw,
1241 &unit->x86c.inv_waitd_seq_hw,
1242 (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys,
1243 unit->x86c.inv_waitd_seq,
1244 unit->x86c.inv_waitd_gen);
1245 } else {
1246 db_printf("qi is disabled\n");
1247 }
1248 }
1249 if (show_domains) {
1250 db_printf("domains:\n");
1251 LIST_FOREACH(domain, &unit->domains, link) {
1252 dmar_print_domain(domain, show_mappings);
1253 if (db_pager_quit)
1254 break;
1255 }
1256 }
1257 }
1258
DB_SHOW_COMMAND(dmar,db_dmar_print)1259 DB_SHOW_COMMAND(dmar, db_dmar_print)
1260 {
1261 bool show_domains, show_mappings;
1262
1263 show_domains = strchr(modif, 'd') != NULL;
1264 show_mappings = strchr(modif, 'm') != NULL;
1265 if (!have_addr) {
1266 db_printf("usage: show dmar [/d] [/m] index\n");
1267 return;
1268 }
1269 dmar_print_one((int)addr, show_domains, show_mappings);
1270 }
1271
DB_SHOW_ALL_COMMAND(dmars,db_show_all_dmars)1272 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1273 {
1274 int i;
1275 bool show_domains, show_mappings;
1276
1277 show_domains = strchr(modif, 'd') != NULL;
1278 show_mappings = strchr(modif, 'm') != NULL;
1279
1280 for (i = 0; i < dmar_devcnt; i++) {
1281 dmar_print_one(i, show_domains, show_mappings);
1282 if (db_pager_quit)
1283 break;
1284 }
1285 }
1286 #endif
1287
1288 static struct iommu_unit *
dmar_find_method(device_t dev,bool verbose)1289 dmar_find_method(device_t dev, bool verbose)
1290 {
1291 struct dmar_unit *dmar;
1292
1293 dmar = dmar_find(dev, verbose);
1294 return (&dmar->iommu);
1295 }
1296
1297 static struct x86_unit_common *
dmar_get_x86_common(struct iommu_unit * unit)1298 dmar_get_x86_common(struct iommu_unit *unit)
1299 {
1300 struct dmar_unit *dmar;
1301
1302 dmar = IOMMU2DMAR(unit);
1303 return (&dmar->x86c);
1304 }
1305
1306 static void
dmar_unit_pre_instantiate_ctx(struct iommu_unit * unit)1307 dmar_unit_pre_instantiate_ctx(struct iommu_unit *unit)
1308 {
1309 dmar_quirks_pre_use(unit);
1310 dmar_instantiate_rmrr_ctxs(unit);
1311 }
1312
1313 static struct x86_iommu dmar_x86_iommu = {
1314 .get_x86_common = dmar_get_x86_common,
1315 .unit_pre_instantiate_ctx = dmar_unit_pre_instantiate_ctx,
1316 .domain_unload_entry = dmar_domain_unload_entry,
1317 .domain_unload = dmar_domain_unload,
1318 .get_ctx = dmar_get_ctx,
1319 .free_ctx_locked = dmar_free_ctx_locked_method,
1320 .find = dmar_find_method,
1321 .alloc_msi_intr = dmar_alloc_msi_intr,
1322 .map_msi_intr = dmar_map_msi_intr,
1323 .unmap_msi_intr = dmar_unmap_msi_intr,
1324 .map_ioapic_intr = dmar_map_ioapic_intr,
1325 .unmap_ioapic_intr = dmar_unmap_ioapic_intr,
1326 };
1327
1328 static void
x86_iommu_set_intel(void * arg __unused)1329 x86_iommu_set_intel(void *arg __unused)
1330 {
1331 if (cpu_vendor_id == CPU_VENDOR_INTEL)
1332 set_x86_iommu(&dmar_x86_iommu);
1333 }
1334
1335 SYSINIT(x86_iommu, SI_SUB_TUNABLES, SI_ORDER_ANY, x86_iommu_set_intel, NULL);
1336