1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_acpi.h" 32 #if defined(__amd64__) 33 #define DEV_APIC 34 #else 35 #include "opt_apic.h" 36 #endif 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/domainset.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/memdesc.h> 46 #include <sys/module.h> 47 #include <sys/mutex.h> 48 #include <sys/rman.h> 49 #include <sys/rwlock.h> 50 #include <sys/smp.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 #include <sys/vmem.h> 54 #include <vm/vm.h> 55 #include <vm/vm_extern.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_object.h> 58 #include <vm/vm_page.h> 59 #include <vm/vm_pager.h> 60 #include <vm/vm_map.h> 61 #include <contrib/dev/acpica/include/acpi.h> 62 #include <contrib/dev/acpica/include/accommon.h> 63 #include <dev/acpica/acpivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <machine/bus.h> 67 #include <machine/pci_cfgreg.h> 68 #include <machine/md_var.h> 69 #include <machine/cputypes.h> 70 #include <x86/include/busdma_impl.h> 71 #include <dev/iommu/busdma_iommu.h> 72 #include <x86/iommu/intel_reg.h> 73 #include <x86/iommu/x86_iommu.h> 74 #include <x86/iommu/intel_dmar.h> 75 76 #ifdef DEV_APIC 77 #include "pcib_if.h" 78 #include <machine/intr_machdep.h> 79 #include <x86/apicreg.h> 80 #include <x86/apicvar.h> 81 #endif 82 83 #define DMAR_FAULT_IRQ_RID 0 84 #define DMAR_QI_IRQ_RID 1 85 #define DMAR_REG_RID 2 86 87 static device_t *dmar_devs; 88 static int dmar_devcnt; 89 static bool dmar_running = false; 90 91 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 92 93 static void 94 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 95 { 96 ACPI_TABLE_DMAR *dmartbl; 97 ACPI_DMAR_HEADER *dmarh; 98 char *ptr, *ptrend; 99 ACPI_STATUS status; 100 101 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 102 if (ACPI_FAILURE(status)) 103 return; 104 ptr = (char *)dmartbl + sizeof(*dmartbl); 105 ptrend = (char *)dmartbl + dmartbl->Header.Length; 106 for (;;) { 107 if (ptr >= ptrend) 108 break; 109 dmarh = (ACPI_DMAR_HEADER *)ptr; 110 if (dmarh->Length <= 0) { 111 printf("dmar_identify: corrupted DMAR table, l %d\n", 112 dmarh->Length); 113 break; 114 } 115 ptr += dmarh->Length; 116 if (!iter(dmarh, arg)) 117 break; 118 } 119 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 120 } 121 122 struct find_iter_args { 123 int i; 124 ACPI_DMAR_HARDWARE_UNIT *res; 125 }; 126 127 static int 128 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 129 { 130 struct find_iter_args *fia; 131 132 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 133 return (1); 134 135 fia = arg; 136 if (fia->i == 0) { 137 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 138 return (0); 139 } 140 fia->i--; 141 return (1); 142 } 143 144 static ACPI_DMAR_HARDWARE_UNIT * 145 dmar_find_by_index(int idx) 146 { 147 struct find_iter_args fia; 148 149 fia.i = idx; 150 fia.res = NULL; 151 dmar_iterate_tbl(dmar_find_iter, &fia); 152 return (fia.res); 153 } 154 155 static int 156 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 157 { 158 159 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 160 dmar_devcnt++; 161 return (1); 162 } 163 164 /* Remapping Hardware Static Affinity Structure lookup */ 165 struct rhsa_iter_arg { 166 uint64_t base; 167 u_int proxim_dom; 168 }; 169 170 static int 171 dmar_rhsa_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 172 { 173 struct rhsa_iter_arg *ria; 174 ACPI_DMAR_RHSA *adr; 175 176 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_AFFINITY) { 177 ria = arg; 178 adr = (ACPI_DMAR_RHSA *)dmarh; 179 if (adr->BaseAddress == ria->base) 180 ria->proxim_dom = adr->ProximityDomain; 181 } 182 return (1); 183 } 184 185 int dmar_rmrr_enable = 1; 186 187 static int dmar_enable = 0; 188 static void 189 dmar_identify(driver_t *driver, device_t parent) 190 { 191 ACPI_TABLE_DMAR *dmartbl; 192 ACPI_DMAR_HARDWARE_UNIT *dmarh; 193 struct rhsa_iter_arg ria; 194 ACPI_STATUS status; 195 int i, error; 196 197 if (acpi_disabled("dmar")) 198 return; 199 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 200 if (!dmar_enable) 201 return; 202 TUNABLE_INT_FETCH("hw.dmar.rmrr_enable", &dmar_rmrr_enable); 203 204 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 205 if (ACPI_FAILURE(status)) 206 return; 207 haw = dmartbl->Width + 1; 208 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 209 iommu_high = BUS_SPACE_MAXADDR; 210 else 211 iommu_high = 1ULL << (haw + 1); 212 if (bootverbose) { 213 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 214 (unsigned)dmartbl->Flags, 215 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 216 } 217 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 218 219 dmar_iterate_tbl(dmar_count_iter, NULL); 220 if (dmar_devcnt == 0) 221 return; 222 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 223 M_WAITOK | M_ZERO); 224 for (i = 0; i < dmar_devcnt; i++) { 225 dmarh = dmar_find_by_index(i); 226 if (dmarh == NULL) { 227 printf("dmar_identify: cannot find HWUNIT %d\n", i); 228 continue; 229 } 230 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 231 if (dmar_devs[i] == NULL) { 232 printf("dmar_identify: cannot create instance %d\n", i); 233 continue; 234 } 235 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 236 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 237 if (error != 0) { 238 printf( 239 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 240 i, (uintmax_t)dmarh->Address, error); 241 device_delete_child(parent, dmar_devs[i]); 242 dmar_devs[i] = NULL; 243 continue; 244 } 245 246 ria.base = dmarh->Address; 247 ria.proxim_dom = -1; 248 dmar_iterate_tbl(dmar_rhsa_iter, &ria); 249 acpi_set_domain(dmar_devs[i], ria.proxim_dom == -1 ? 250 ACPI_DEV_DOMAIN_UNKNOWN : 251 acpi_map_pxm_to_vm_domainid(ria.proxim_dom)); 252 } 253 } 254 255 static int 256 dmar_probe(device_t dev) 257 { 258 259 if (acpi_get_handle(dev) != NULL) 260 return (ENXIO); 261 device_set_desc(dev, "DMA remap"); 262 return (BUS_PROBE_NOWILDCARD); 263 } 264 265 static void 266 dmar_release_resources(device_t dev, struct dmar_unit *unit) 267 { 268 int i; 269 270 iommu_fini_busdma(&unit->iommu); 271 dmar_fini_irt(unit); 272 dmar_fini_qi(unit); 273 dmar_fini_fault_log(unit); 274 for (i = 0; i < DMAR_INTR_TOTAL; i++) 275 iommu_release_intr(DMAR2IOMMU(unit), i); 276 if (unit->regs != NULL) { 277 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 278 unit->regs); 279 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 280 unit->regs); 281 unit->regs = NULL; 282 } 283 if (unit->domids != NULL) { 284 delete_unrhdr(unit->domids); 285 unit->domids = NULL; 286 } 287 if (unit->ctx_obj != NULL) { 288 vm_object_deallocate(unit->ctx_obj); 289 unit->ctx_obj = NULL; 290 } 291 sysctl_ctx_free(&unit->iommu.sysctl_ctx); 292 } 293 294 #ifdef DEV_APIC 295 static int 296 dmar_remap_intr(device_t dev, device_t child, u_int irq) 297 { 298 struct dmar_unit *unit; 299 struct iommu_msi_data *dmd; 300 uint64_t msi_addr; 301 uint32_t msi_data; 302 int i, error; 303 304 unit = device_get_softc(dev); 305 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 306 dmd = &unit->x86c.intrs[i]; 307 if (irq == dmd->irq) { 308 error = PCIB_MAP_MSI(device_get_parent( 309 device_get_parent(dev)), 310 dev, irq, &msi_addr, &msi_data); 311 if (error != 0) 312 return (error); 313 DMAR_LOCK(unit); 314 dmd->msi_data = msi_data; 315 dmd->msi_addr = msi_addr; 316 (dmd->disable_intr)(DMAR2IOMMU(unit)); 317 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 318 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 319 dmar_write4(unit, dmd->msi_uaddr_reg, 320 dmd->msi_addr >> 32); 321 (dmd->enable_intr)(DMAR2IOMMU(unit)); 322 DMAR_UNLOCK(unit); 323 return (0); 324 } 325 } 326 return (ENOENT); 327 } 328 #endif 329 330 static void 331 dmar_print_caps(device_t dev, struct dmar_unit *unit, 332 ACPI_DMAR_HARDWARE_UNIT *dmaru) 333 { 334 uint32_t caphi, ecaphi; 335 336 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 337 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 338 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 339 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 340 caphi = unit->hw_cap >> 32; 341 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 342 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 343 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 344 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 345 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 346 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 347 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 348 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 349 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 350 printf("\n"); 351 ecaphi = unit->hw_ecap >> 32; 352 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 353 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 354 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 355 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 356 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 357 DMAR_ECAP_IRO(unit->hw_ecap)); 358 } 359 360 static int 361 dmar_attach(device_t dev) 362 { 363 struct dmar_unit *unit; 364 ACPI_DMAR_HARDWARE_UNIT *dmaru; 365 struct iommu_msi_data *dmd; 366 uint64_t timeout; 367 int disable_pmr; 368 int i, error; 369 370 unit = device_get_softc(dev); 371 unit->iommu.unit = device_get_unit(dev); 372 unit->iommu.dev = dev; 373 sysctl_ctx_init(&unit->iommu.sysctl_ctx); 374 dmaru = dmar_find_by_index(unit->iommu.unit); 375 if (dmaru == NULL) 376 return (EINVAL); 377 unit->segment = dmaru->Segment; 378 unit->base = dmaru->Address; 379 unit->reg_rid = DMAR_REG_RID; 380 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 381 &unit->reg_rid, RF_ACTIVE); 382 if (unit->regs == NULL) { 383 device_printf(dev, "cannot allocate register window\n"); 384 dmar_devs[unit->iommu.unit] = NULL; 385 return (ENOMEM); 386 } 387 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 388 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 389 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 390 if (bootverbose) 391 dmar_print_caps(dev, unit, dmaru); 392 dmar_quirks_post_ident(unit); 393 unit->memdomain = acpi_get_domain(dev); 394 timeout = dmar_get_timeout(); 395 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout); 396 dmar_update_timeout(timeout); 397 398 for (i = 0; i < DMAR_INTR_TOTAL; i++) 399 unit->x86c.intrs[i].irq = -1; 400 401 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT]; 402 dmd->name = "fault"; 403 dmd->irq_rid = DMAR_FAULT_IRQ_RID; 404 dmd->handler = dmar_fault_intr; 405 dmd->msi_data_reg = DMAR_FEDATA_REG; 406 dmd->msi_addr_reg = DMAR_FEADDR_REG; 407 dmd->msi_uaddr_reg = DMAR_FEUADDR_REG; 408 dmd->enable_intr = dmar_enable_fault_intr; 409 dmd->disable_intr = dmar_disable_fault_intr; 410 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_FAULT); 411 if (error != 0) { 412 dmar_release_resources(dev, unit); 413 dmar_devs[unit->iommu.unit] = NULL; 414 return (error); 415 } 416 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 417 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 418 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); 419 420 if (DMAR_HAS_QI(unit)) { 421 dmd = &unit->x86c.intrs[DMAR_INTR_QI]; 422 dmd->name = "qi"; 423 dmd->irq_rid = DMAR_QI_IRQ_RID; 424 dmd->handler = dmar_qi_intr; 425 dmd->msi_data_reg = DMAR_IEDATA_REG; 426 dmd->msi_addr_reg = DMAR_IEADDR_REG; 427 dmd->msi_uaddr_reg = DMAR_IEUADDR_REG; 428 dmd->enable_intr = dmar_enable_qi_intr; 429 dmd->disable_intr = dmar_disable_qi_intr; 430 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_QI); 431 if (error != 0) { 432 dmar_release_resources(dev, unit); 433 dmar_devs[unit->iommu.unit] = NULL; 434 return (error); 435 } 436 437 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 438 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 439 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); 440 } 441 442 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 443 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 444 &unit->iommu.lock); 445 LIST_INIT(&unit->domains); 446 447 /* 448 * 9.2 "Context Entry": 449 * When Caching Mode (CM) field is reported as Set, the 450 * domain-id value of zero is architecturally reserved. 451 * Software must not use domain-id value of zero 452 * when CM is Set. 453 */ 454 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 455 alloc_unr_specific(unit->domids, 0); 456 457 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 458 DMAR_CTX_CNT), 0, 0, NULL); 459 if (unit->memdomain != -1) { 460 unit->ctx_obj->domain.dr_policy = DOMAINSET_PREF( 461 unit->memdomain); 462 } 463 464 /* 465 * Allocate and load the root entry table pointer. Enable the 466 * address translation after the required invalidations are 467 * done. 468 */ 469 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 470 DMAR_LOCK(unit); 471 error = dmar_load_root_entry_ptr(unit); 472 if (error != 0) { 473 DMAR_UNLOCK(unit); 474 dmar_release_resources(dev, unit); 475 dmar_devs[unit->iommu.unit] = NULL; 476 return (error); 477 } 478 error = dmar_inv_ctx_glob(unit); 479 if (error != 0) { 480 DMAR_UNLOCK(unit); 481 dmar_release_resources(dev, unit); 482 dmar_devs[unit->iommu.unit] = NULL; 483 return (error); 484 } 485 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 486 error = dmar_inv_iotlb_glob(unit); 487 if (error != 0) { 488 DMAR_UNLOCK(unit); 489 dmar_release_resources(dev, unit); 490 dmar_devs[unit->iommu.unit] = NULL; 491 return (error); 492 } 493 } 494 495 DMAR_UNLOCK(unit); 496 error = dmar_init_fault_log(unit); 497 if (error != 0) { 498 dmar_release_resources(dev, unit); 499 dmar_devs[unit->iommu.unit] = NULL; 500 return (error); 501 } 502 error = dmar_init_qi(unit); 503 if (error != 0) { 504 dmar_release_resources(dev, unit); 505 dmar_devs[unit->iommu.unit] = NULL; 506 return (error); 507 } 508 error = dmar_init_irt(unit); 509 if (error != 0) { 510 dmar_release_resources(dev, unit); 511 dmar_devs[unit->iommu.unit] = NULL; 512 return (error); 513 } 514 515 disable_pmr = 0; 516 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr); 517 if (disable_pmr) { 518 error = dmar_disable_protected_regions(unit); 519 if (error != 0) 520 device_printf(dev, 521 "Failed to disable protected regions\n"); 522 } 523 524 error = iommu_init_busdma(&unit->iommu); 525 if (error != 0) { 526 dmar_release_resources(dev, unit); 527 dmar_devs[unit->iommu.unit] = NULL; 528 return (error); 529 } 530 531 #ifdef NOTYET 532 DMAR_LOCK(unit); 533 error = dmar_enable_translation(unit); 534 if (error != 0) { 535 DMAR_UNLOCK(unit); 536 dmar_release_resources(dev, unit); 537 dmar_devs[unit->iommu.unit] = NULL; 538 return (error); 539 } 540 DMAR_UNLOCK(unit); 541 #endif 542 543 dmar_running = true; 544 return (0); 545 } 546 547 static int 548 dmar_detach(device_t dev) 549 { 550 551 return (EBUSY); 552 } 553 554 static int 555 dmar_suspend(device_t dev) 556 { 557 558 return (0); 559 } 560 561 static int 562 dmar_resume(device_t dev) 563 { 564 565 /* XXXKIB */ 566 return (0); 567 } 568 569 static device_method_t dmar_methods[] = { 570 DEVMETHOD(device_identify, dmar_identify), 571 DEVMETHOD(device_probe, dmar_probe), 572 DEVMETHOD(device_attach, dmar_attach), 573 DEVMETHOD(device_detach, dmar_detach), 574 DEVMETHOD(device_suspend, dmar_suspend), 575 DEVMETHOD(device_resume, dmar_resume), 576 #ifdef DEV_APIC 577 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 578 #endif 579 DEVMETHOD_END 580 }; 581 582 static driver_t dmar_driver = { 583 "dmar", 584 dmar_methods, 585 sizeof(struct dmar_unit), 586 }; 587 588 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0); 589 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 590 591 static void 592 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 593 { 594 int i; 595 596 printf("[%d, ", busno); 597 for (i = 0; i < depth; i++) { 598 if (i != 0) 599 printf(", "); 600 printf("(%d, %d)", path[i].Device, path[i].Function); 601 } 602 printf("]"); 603 } 604 605 int 606 dmar_dev_depth(device_t child) 607 { 608 device_t bus, pcib; 609 int depth; 610 611 for (depth = 1; ; depth++) { 612 bus = device_get_parent(child); 613 pcib = device_get_parent(bus); 614 if (!is_pci_device(pcib)) 615 return (depth); 616 child = pcib; 617 } 618 } 619 620 void 621 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 622 { 623 device_t bus, pcib; 624 ACPI_DMAR_PCI_PATH *path; 625 626 path = path1; 627 for (depth--; depth != -1; depth--) { 628 path[depth].Device = pci_get_slot(child); 629 path[depth].Function = pci_get_function(child); 630 bus = device_get_parent(child); 631 pcib = device_get_parent(bus); 632 if (!is_pci_device(pcib)) { 633 /* reached a host bridge */ 634 *busno = pcib_get_bus(bus); 635 return; 636 } 637 child = pcib; 638 } 639 panic("wrong depth"); 640 } 641 642 static int 643 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 644 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 645 enum AcpiDmarScopeType scope_type) 646 { 647 int i, depth; 648 649 if (busno1 != busno2) 650 return (0); 651 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 652 return (0); 653 depth = depth1; 654 if (depth2 < depth) 655 depth = depth2; 656 for (i = 0; i < depth; i++) { 657 if (path1[i].Device != path2[i].Device || 658 path1[i].Function != path2[i].Function) 659 return (0); 660 } 661 return (1); 662 } 663 664 static int 665 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 666 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 667 { 668 ACPI_DMAR_PCI_PATH *path; 669 int path_len; 670 671 if (devscope->Length < sizeof(*devscope)) { 672 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 673 devscope->Length); 674 return (-1); 675 } 676 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 677 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 678 return (0); 679 path_len = devscope->Length - sizeof(*devscope); 680 if (path_len % 2 != 0) { 681 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 682 devscope->Length); 683 return (-1); 684 } 685 path_len /= 2; 686 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 687 if (path_len == 0) { 688 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 689 devscope->Length); 690 return (-1); 691 } 692 693 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 694 dev_path, dev_path_len, devscope->EntryType)); 695 } 696 697 static bool 698 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 699 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 700 { 701 ACPI_DMAR_HARDWARE_UNIT *dmarh; 702 ACPI_DMAR_DEVICE_SCOPE *devscope; 703 char *ptr, *ptrend; 704 int match; 705 706 dmarh = dmar_find_by_index(unit->iommu.unit); 707 if (dmarh == NULL) 708 return (false); 709 if (dmarh->Segment != dev_domain) 710 return (false); 711 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 712 if (banner != NULL) 713 *banner = "INCLUDE_ALL"; 714 return (true); 715 } 716 ptr = (char *)dmarh + sizeof(*dmarh); 717 ptrend = (char *)dmarh + dmarh->Header.Length; 718 while (ptr < ptrend) { 719 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 720 ptr += devscope->Length; 721 match = dmar_match_devscope(devscope, dev_busno, dev_path, 722 dev_path_len); 723 if (match == -1) 724 return (false); 725 if (match == 1) { 726 if (banner != NULL) 727 *banner = "specific match"; 728 return (true); 729 } 730 } 731 return (false); 732 } 733 734 static struct dmar_unit * 735 dmar_find_by_scope(int dev_domain, int dev_busno, 736 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 737 { 738 struct dmar_unit *unit; 739 int i; 740 741 for (i = 0; i < dmar_devcnt; i++) { 742 if (dmar_devs[i] == NULL) 743 continue; 744 unit = device_get_softc(dmar_devs[i]); 745 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 746 dev_path_len, NULL)) 747 return (unit); 748 } 749 return (NULL); 750 } 751 752 struct dmar_unit * 753 dmar_find(device_t dev, bool verbose) 754 { 755 struct dmar_unit *unit; 756 const char *banner; 757 int i, dev_domain, dev_busno, dev_path_len; 758 759 /* 760 * This function can only handle PCI(e) devices. 761 */ 762 if (!is_pci_device(dev)) 763 return (NULL); 764 765 dev_domain = pci_get_domain(dev); 766 dev_path_len = dmar_dev_depth(dev); 767 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 768 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 769 banner = ""; 770 771 for (i = 0; i < dmar_devcnt; i++) { 772 if (dmar_devs[i] == NULL) 773 continue; 774 unit = device_get_softc(dmar_devs[i]); 775 if (dmar_match_by_path(unit, dev_domain, dev_busno, 776 dev_path, dev_path_len, &banner)) 777 break; 778 } 779 if (i == dmar_devcnt) 780 return (NULL); 781 782 if (verbose) { 783 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 784 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 785 pci_get_function(dev), unit->iommu.unit, banner); 786 printf(" scope path "); 787 dmar_print_path(dev_busno, dev_path_len, dev_path); 788 printf("\n"); 789 } 790 iommu_device_set_iommu_prop(dev, unit->iommu.dev); 791 return (unit); 792 } 793 794 static struct dmar_unit * 795 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 796 { 797 device_t dmar_dev; 798 struct dmar_unit *unit; 799 ACPI_DMAR_HARDWARE_UNIT *dmarh; 800 ACPI_DMAR_DEVICE_SCOPE *devscope; 801 ACPI_DMAR_PCI_PATH *path; 802 char *ptr, *ptrend; 803 #ifdef DEV_APIC 804 int error; 805 #endif 806 int i; 807 808 for (i = 0; i < dmar_devcnt; i++) { 809 dmar_dev = dmar_devs[i]; 810 if (dmar_dev == NULL) 811 continue; 812 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 813 dmarh = dmar_find_by_index(i); 814 if (dmarh == NULL) 815 continue; 816 ptr = (char *)dmarh + sizeof(*dmarh); 817 ptrend = (char *)dmarh + dmarh->Header.Length; 818 for (;;) { 819 if (ptr >= ptrend) 820 break; 821 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 822 ptr += devscope->Length; 823 if (devscope->EntryType != entry_type) 824 continue; 825 if (devscope->EnumerationId != id) 826 continue; 827 #ifdef DEV_APIC 828 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 829 error = ioapic_get_rid(id, rid); 830 /* 831 * If our IOAPIC has PCI bindings then 832 * use the PCI device rid. 833 */ 834 if (error == 0) 835 return (unit); 836 } 837 #endif 838 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 839 == 2) { 840 if (rid != NULL) { 841 path = (ACPI_DMAR_PCI_PATH *) 842 (devscope + 1); 843 *rid = PCI_RID(devscope->Bus, 844 path->Device, path->Function); 845 } 846 return (unit); 847 } 848 printf( 849 "dmar_find_nonpci: id %d type %d path length != 2\n", 850 id, entry_type); 851 break; 852 } 853 } 854 return (NULL); 855 } 856 857 struct dmar_unit * 858 dmar_find_hpet(device_t dev, uint16_t *rid) 859 { 860 struct dmar_unit *unit; 861 862 unit = dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 863 rid); 864 if (unit != NULL) 865 iommu_device_set_iommu_prop(dev, unit->iommu.dev); 866 return (unit); 867 } 868 869 struct dmar_unit * 870 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 871 { 872 struct dmar_unit *unit; 873 device_t apic_dev; 874 875 unit = dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid); 876 if (unit != NULL) { 877 apic_dev = ioapic_get_dev(apic_id); 878 if (apic_dev != NULL) 879 iommu_device_set_iommu_prop(apic_dev, unit->iommu.dev); 880 } 881 return (unit); 882 } 883 884 struct rmrr_iter_args { 885 struct dmar_domain *domain; 886 int dev_domain; 887 int dev_busno; 888 const ACPI_DMAR_PCI_PATH *dev_path; 889 int dev_path_len; 890 struct iommu_map_entries_tailq *rmrr_entries; 891 }; 892 893 static int 894 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 895 { 896 struct rmrr_iter_args *ria; 897 ACPI_DMAR_RESERVED_MEMORY *resmem; 898 ACPI_DMAR_DEVICE_SCOPE *devscope; 899 struct iommu_map_entry *entry; 900 char *ptr, *ptrend; 901 int match; 902 903 if (!dmar_rmrr_enable) 904 return (1); 905 906 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 907 return (1); 908 909 ria = arg; 910 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 911 if (resmem->Segment != ria->dev_domain) 912 return (1); 913 914 ptr = (char *)resmem + sizeof(*resmem); 915 ptrend = (char *)resmem + resmem->Header.Length; 916 for (;;) { 917 if (ptr >= ptrend) 918 break; 919 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 920 ptr += devscope->Length; 921 match = dmar_match_devscope(devscope, ria->dev_busno, 922 ria->dev_path, ria->dev_path_len); 923 if (match == 1) { 924 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 925 IOMMU_PGF_WAITOK); 926 entry->start = resmem->BaseAddress; 927 /* The RMRR entry end address is inclusive. */ 928 entry->end = resmem->EndAddress; 929 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 930 dmamap_link); 931 } 932 } 933 934 return (1); 935 } 936 937 void 938 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 939 const void *dev_path, int dev_path_len, 940 struct iommu_map_entries_tailq *rmrr_entries) 941 { 942 struct rmrr_iter_args ria; 943 944 ria.domain = domain; 945 ria.dev_domain = dev_domain; 946 ria.dev_busno = dev_busno; 947 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 948 ria.dev_path_len = dev_path_len; 949 ria.rmrr_entries = rmrr_entries; 950 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 951 } 952 953 struct inst_rmrr_iter_args { 954 struct dmar_unit *dmar; 955 }; 956 957 static device_t 958 dmar_path_dev(int segment, int path_len, int busno, 959 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 960 { 961 device_t dev; 962 int i; 963 964 dev = NULL; 965 for (i = 0; i < path_len; i++) { 966 dev = pci_find_dbsf(segment, busno, path->Device, 967 path->Function); 968 if (i != path_len - 1) { 969 busno = pci_cfgregread(segment, busno, path->Device, 970 path->Function, PCIR_SECBUS_1, 1); 971 path++; 972 } 973 } 974 *rid = PCI_RID(busno, path->Device, path->Function); 975 return (dev); 976 } 977 978 static int 979 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 980 { 981 const ACPI_DMAR_RESERVED_MEMORY *resmem; 982 const ACPI_DMAR_DEVICE_SCOPE *devscope; 983 struct inst_rmrr_iter_args *iria; 984 const char *ptr, *ptrend; 985 device_t dev; 986 struct dmar_unit *unit; 987 int dev_path_len; 988 uint16_t rid; 989 990 iria = arg; 991 992 if (!dmar_rmrr_enable) 993 return (1); 994 995 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 996 return (1); 997 998 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 999 if (resmem->Segment != iria->dmar->segment) 1000 return (1); 1001 1002 ptr = (const char *)resmem + sizeof(*resmem); 1003 ptrend = (const char *)resmem + resmem->Header.Length; 1004 for (;;) { 1005 if (ptr >= ptrend) 1006 break; 1007 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1008 ptr += devscope->Length; 1009 /* XXXKIB bridge */ 1010 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1011 continue; 1012 rid = 0; 1013 dev_path_len = (devscope->Length - 1014 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1015 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1016 devscope->Bus, 1017 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1018 if (dev == NULL) { 1019 if (bootverbose) { 1020 printf("dmar%d no dev found for RMRR " 1021 "[%#jx, %#jx] rid %#x scope path ", 1022 iria->dmar->iommu.unit, 1023 (uintmax_t)resmem->BaseAddress, 1024 (uintmax_t)resmem->EndAddress, 1025 rid); 1026 dmar_print_path(devscope->Bus, dev_path_len, 1027 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1028 printf("\n"); 1029 } 1030 unit = dmar_find_by_scope(resmem->Segment, 1031 devscope->Bus, 1032 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1033 dev_path_len); 1034 if (iria->dmar != unit) 1035 continue; 1036 dmar_get_ctx_for_devpath(iria->dmar, rid, 1037 resmem->Segment, devscope->Bus, 1038 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1039 dev_path_len, false, true); 1040 } else { 1041 unit = dmar_find(dev, false); 1042 if (iria->dmar != unit) 1043 continue; 1044 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1045 dev, true); 1046 } 1047 } 1048 1049 return (1); 1050 1051 } 1052 1053 int 1054 dmar_is_running(void) 1055 { 1056 1057 return (dmar_running ? 0 : ENXIO); 1058 } 1059 1060 /* 1061 * Pre-create all contexts for the DMAR which have RMRR entries. 1062 */ 1063 int 1064 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1065 { 1066 struct dmar_unit *dmar; 1067 struct inst_rmrr_iter_args iria; 1068 int error; 1069 1070 dmar = IOMMU2DMAR(unit); 1071 1072 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1073 return (0); 1074 1075 error = 0; 1076 iria.dmar = dmar; 1077 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1078 DMAR_LOCK(dmar); 1079 if (!LIST_EMPTY(&dmar->domains)) { 1080 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1081 ("dmar%d: RMRR not handled but translation is already enabled", 1082 dmar->iommu.unit)); 1083 error = dmar_disable_protected_regions(dmar); 1084 if (error != 0) 1085 printf("dmar%d: Failed to disable protected regions\n", 1086 dmar->iommu.unit); 1087 error = dmar_enable_translation(dmar); 1088 if (bootverbose) { 1089 if (error == 0) { 1090 printf("dmar%d: enabled translation\n", 1091 dmar->iommu.unit); 1092 } else { 1093 printf("dmar%d: enabling translation failed, " 1094 "error %d\n", dmar->iommu.unit, error); 1095 } 1096 } 1097 } 1098 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1099 return (error); 1100 } 1101 1102 #ifdef DDB 1103 #include <ddb/ddb.h> 1104 #include <ddb/db_lex.h> 1105 1106 static void 1107 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1108 { 1109 struct iommu_domain *iodom; 1110 1111 iodom = DOM2IODOM(domain); 1112 1113 db_printf( 1114 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1115 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1116 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1117 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1118 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1119 1120 iommu_db_domain_print_contexts(iodom); 1121 1122 if (show_mappings) 1123 iommu_db_domain_print_mappings(iodom); 1124 } 1125 1126 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN) 1127 { 1128 struct dmar_unit *unit; 1129 struct dmar_domain *domain; 1130 struct iommu_ctx *ctx; 1131 bool show_mappings, valid; 1132 int pci_domain, bus, device, function, i, t; 1133 db_expr_t radix; 1134 1135 valid = false; 1136 radix = db_radix; 1137 db_radix = 10; 1138 t = db_read_token(); 1139 if (t == tSLASH) { 1140 t = db_read_token(); 1141 if (t != tIDENT) { 1142 db_printf("Bad modifier\n"); 1143 db_radix = radix; 1144 db_skip_to_eol(); 1145 return; 1146 } 1147 show_mappings = strchr(db_tok_string, 'm') != NULL; 1148 t = db_read_token(); 1149 } else { 1150 show_mappings = false; 1151 } 1152 if (t == tNUMBER) { 1153 pci_domain = db_tok_number; 1154 t = db_read_token(); 1155 if (t == tNUMBER) { 1156 bus = db_tok_number; 1157 t = db_read_token(); 1158 if (t == tNUMBER) { 1159 device = db_tok_number; 1160 t = db_read_token(); 1161 if (t == tNUMBER) { 1162 function = db_tok_number; 1163 valid = true; 1164 } 1165 } 1166 } 1167 } 1168 db_radix = radix; 1169 db_skip_to_eol(); 1170 if (!valid) { 1171 db_printf("usage: show dmar_domain [/m] " 1172 "<domain> <bus> <device> <func>\n"); 1173 return; 1174 } 1175 for (i = 0; i < dmar_devcnt; i++) { 1176 unit = device_get_softc(dmar_devs[i]); 1177 LIST_FOREACH(domain, &unit->domains, link) { 1178 LIST_FOREACH(ctx, &domain->iodom.contexts, link) { 1179 if (pci_domain == unit->segment && 1180 bus == pci_get_bus(ctx->tag->owner) && 1181 device == pci_get_slot(ctx->tag->owner) && 1182 function == pci_get_function(ctx->tag-> 1183 owner)) { 1184 dmar_print_domain(domain, 1185 show_mappings); 1186 goto out; 1187 } 1188 } 1189 } 1190 } 1191 out:; 1192 } 1193 1194 static void 1195 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1196 { 1197 struct dmar_unit *unit; 1198 struct dmar_domain *domain; 1199 int i, frir; 1200 1201 unit = device_get_softc(dmar_devs[idx]); 1202 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1203 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1204 dmar_read4(unit, DMAR_VER_REG)); 1205 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1206 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1207 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1208 dmar_read4(unit, DMAR_GSTS_REG), 1209 dmar_read4(unit, DMAR_FSTS_REG), 1210 dmar_read4(unit, DMAR_FECTL_REG)); 1211 if (unit->ir_enabled) { 1212 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1213 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1214 } 1215 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1216 dmar_read4(unit, DMAR_FEDATA_REG), 1217 dmar_read4(unit, DMAR_FEADDR_REG), 1218 dmar_read4(unit, DMAR_FEUADDR_REG)); 1219 db_printf("primary fault log:\n"); 1220 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1221 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1222 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1223 (uintmax_t)dmar_read8(unit, frir), 1224 (uintmax_t)dmar_read8(unit, frir + 8)); 1225 } 1226 if (DMAR_HAS_QI(unit)) { 1227 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1228 dmar_read4(unit, DMAR_IEDATA_REG), 1229 dmar_read4(unit, DMAR_IEADDR_REG), 1230 dmar_read4(unit, DMAR_IEUADDR_REG)); 1231 if (unit->qi_enabled) { 1232 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1233 "size 0x%jx\n" 1234 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1235 " hw compl 0x%jx@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1236 (uintmax_t)unit->x86c.inv_queue, 1237 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1238 (uintmax_t)unit->x86c.inv_queue_size, 1239 dmar_read4(unit, DMAR_IQH_REG), 1240 dmar_read4(unit, DMAR_IQT_REG), 1241 unit->x86c.inv_queue_avail, 1242 dmar_read4(unit, DMAR_ICS_REG), 1243 dmar_read4(unit, DMAR_IECTL_REG), 1244 (uintmax_t)unit->x86c.inv_waitd_seq_hw, 1245 &unit->x86c.inv_waitd_seq_hw, 1246 (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys, 1247 unit->x86c.inv_waitd_seq, 1248 unit->x86c.inv_waitd_gen); 1249 } else { 1250 db_printf("qi is disabled\n"); 1251 } 1252 } 1253 if (show_domains) { 1254 db_printf("domains:\n"); 1255 LIST_FOREACH(domain, &unit->domains, link) { 1256 dmar_print_domain(domain, show_mappings); 1257 if (db_pager_quit) 1258 break; 1259 } 1260 } 1261 } 1262 1263 DB_SHOW_COMMAND(dmar, db_dmar_print) 1264 { 1265 bool show_domains, show_mappings; 1266 1267 show_domains = strchr(modif, 'd') != NULL; 1268 show_mappings = strchr(modif, 'm') != NULL; 1269 if (!have_addr) { 1270 db_printf("usage: show dmar [/d] [/m] index\n"); 1271 return; 1272 } 1273 dmar_print_one((int)addr, show_domains, show_mappings); 1274 } 1275 1276 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1277 { 1278 int i; 1279 bool show_domains, show_mappings; 1280 1281 show_domains = strchr(modif, 'd') != NULL; 1282 show_mappings = strchr(modif, 'm') != NULL; 1283 1284 for (i = 0; i < dmar_devcnt; i++) { 1285 dmar_print_one(i, show_domains, show_mappings); 1286 if (db_pager_quit) 1287 break; 1288 } 1289 } 1290 #endif 1291 1292 static struct iommu_unit * 1293 dmar_find_method(device_t dev, bool verbose) 1294 { 1295 struct dmar_unit *dmar; 1296 1297 dmar = dmar_find(dev, verbose); 1298 return (&dmar->iommu); 1299 } 1300 1301 static struct x86_unit_common * 1302 dmar_get_x86_common(struct iommu_unit *unit) 1303 { 1304 struct dmar_unit *dmar; 1305 1306 dmar = IOMMU2DMAR(unit); 1307 return (&dmar->x86c); 1308 } 1309 1310 static void 1311 dmar_unit_pre_instantiate_ctx(struct iommu_unit *unit) 1312 { 1313 dmar_quirks_pre_use(unit); 1314 dmar_instantiate_rmrr_ctxs(unit); 1315 } 1316 1317 static struct x86_iommu dmar_x86_iommu = { 1318 .get_x86_common = dmar_get_x86_common, 1319 .unit_pre_instantiate_ctx = dmar_unit_pre_instantiate_ctx, 1320 .domain_unload_entry = dmar_domain_unload_entry, 1321 .domain_unload = dmar_domain_unload, 1322 .get_ctx = dmar_get_ctx, 1323 .free_ctx_locked = dmar_free_ctx_locked_method, 1324 .find = dmar_find_method, 1325 .alloc_msi_intr = dmar_alloc_msi_intr, 1326 .map_msi_intr = dmar_map_msi_intr, 1327 .unmap_msi_intr = dmar_unmap_msi_intr, 1328 .map_ioapic_intr = dmar_map_ioapic_intr, 1329 .unmap_ioapic_intr = dmar_unmap_ioapic_intr, 1330 }; 1331 1332 static void 1333 x86_iommu_set_intel(void *arg __unused) 1334 { 1335 if (cpu_vendor_id == CPU_VENDOR_INTEL) 1336 set_x86_iommu(&dmar_x86_iommu); 1337 } 1338 1339 SYSINIT(x86_iommu, SI_SUB_TUNABLES, SI_ORDER_ANY, x86_iommu_set_intel, NULL); 1340