xref: /linux/drivers/clk/qcom/dispcc-sm8550.c (revision 9f3a2ba62c7226a6604b8aaeb92b5ff906fa4e6b)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2023, Linaro Ltd.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/err.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/pm_runtime.h>
16 
17 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
18 
19 #include "common.h"
20 #include "clk-alpha-pll.h"
21 #include "clk-branch.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-regmap.h"
25 #include "clk-regmap-divider.h"
26 #include "clk-regmap-mux.h"
27 #include "reset.h"
28 #include "gdsc.h"
29 
30 /* Need to match the order of clocks in DT binding */
31 enum {
32 	DT_BI_TCXO,
33 	DT_BI_TCXO_AO,
34 	DT_AHB_CLK,
35 	DT_SLEEP_CLK,
36 
37 	DT_DSI0_PHY_PLL_OUT_BYTECLK,
38 	DT_DSI0_PHY_PLL_OUT_DSICLK,
39 	DT_DSI1_PHY_PLL_OUT_BYTECLK,
40 	DT_DSI1_PHY_PLL_OUT_DSICLK,
41 
42 	DT_DP0_PHY_PLL_LINK_CLK,
43 	DT_DP0_PHY_PLL_VCO_DIV_CLK,
44 	DT_DP1_PHY_PLL_LINK_CLK,
45 	DT_DP1_PHY_PLL_VCO_DIV_CLK,
46 	DT_DP2_PHY_PLL_LINK_CLK,
47 	DT_DP2_PHY_PLL_VCO_DIV_CLK,
48 	DT_DP3_PHY_PLL_LINK_CLK,
49 	DT_DP3_PHY_PLL_VCO_DIV_CLK,
50 };
51 
52 #define DISP_CC_MISC_CMD	0xF000
53 
54 enum {
55 	P_BI_TCXO,
56 	P_DISP_CC_PLL0_OUT_MAIN,
57 	P_DISP_CC_PLL1_OUT_EVEN,
58 	P_DISP_CC_PLL1_OUT_MAIN,
59 	P_DP0_PHY_PLL_LINK_CLK,
60 	P_DP0_PHY_PLL_VCO_DIV_CLK,
61 	P_DP1_PHY_PLL_LINK_CLK,
62 	P_DP1_PHY_PLL_VCO_DIV_CLK,
63 	P_DP2_PHY_PLL_LINK_CLK,
64 	P_DP2_PHY_PLL_VCO_DIV_CLK,
65 	P_DP3_PHY_PLL_LINK_CLK,
66 	P_DP3_PHY_PLL_VCO_DIV_CLK,
67 	P_DSI0_PHY_PLL_OUT_BYTECLK,
68 	P_DSI0_PHY_PLL_OUT_DSICLK,
69 	P_DSI1_PHY_PLL_OUT_BYTECLK,
70 	P_DSI1_PHY_PLL_OUT_DSICLK,
71 	P_SLEEP_CLK,
72 };
73 
74 static struct pll_vco lucid_ole_vco[] = {
75 	{ 249600000, 2000000000, 0 },
76 };
77 
78 static struct alpha_pll_config disp_cc_pll0_config = {
79 	.l = 0xd,
80 	.alpha = 0x6492,
81 	.config_ctl_val = 0x20485699,
82 	.config_ctl_hi_val = 0x00182261,
83 	.config_ctl_hi1_val = 0x82aa299c,
84 	.test_ctl_val = 0x00000000,
85 	.test_ctl_hi_val = 0x00000003,
86 	.test_ctl_hi1_val = 0x00009000,
87 	.test_ctl_hi2_val = 0x00000034,
88 	.user_ctl_val = 0x00000000,
89 	.user_ctl_hi_val = 0x00000005,
90 };
91 
92 static struct clk_alpha_pll disp_cc_pll0 = {
93 	.offset = 0x0,
94 	.vco_table = lucid_ole_vco,
95 	.num_vco = ARRAY_SIZE(lucid_ole_vco),
96 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
97 	.clkr = {
98 		.hw.init = &(const struct clk_init_data) {
99 			.name = "disp_cc_pll0",
100 			.parent_data = &(const struct clk_parent_data) {
101 				.index = DT_BI_TCXO,
102 			},
103 			.num_parents = 1,
104 			.ops = &clk_alpha_pll_reset_lucid_ole_ops,
105 		},
106 	},
107 };
108 
109 static struct alpha_pll_config disp_cc_pll1_config = {
110 	.l = 0x1f,
111 	.alpha = 0x4000,
112 	.config_ctl_val = 0x20485699,
113 	.config_ctl_hi_val = 0x00182261,
114 	.config_ctl_hi1_val = 0x82aa299c,
115 	.test_ctl_val = 0x00000000,
116 	.test_ctl_hi_val = 0x00000003,
117 	.test_ctl_hi1_val = 0x00009000,
118 	.test_ctl_hi2_val = 0x00000034,
119 	.user_ctl_val = 0x00000000,
120 	.user_ctl_hi_val = 0x00000005,
121 };
122 
123 static struct clk_alpha_pll disp_cc_pll1 = {
124 	.offset = 0x1000,
125 	.vco_table = lucid_ole_vco,
126 	.num_vco = ARRAY_SIZE(lucid_ole_vco),
127 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
128 	.clkr = {
129 		.hw.init = &(const struct clk_init_data) {
130 			.name = "disp_cc_pll1",
131 			.parent_data = &(const struct clk_parent_data) {
132 				.index = DT_BI_TCXO,
133 			},
134 			.num_parents = 1,
135 			.ops = &clk_alpha_pll_reset_lucid_ole_ops,
136 		},
137 	},
138 };
139 
140 static const struct parent_map disp_cc_parent_map_0[] = {
141 	{ P_BI_TCXO, 0 },
142 };
143 
144 static const struct clk_parent_data disp_cc_parent_data_0[] = {
145 	{ .index = DT_BI_TCXO },
146 };
147 
148 static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
149 	{ .index = DT_BI_TCXO_AO },
150 };
151 
152 static const struct parent_map disp_cc_parent_map_1[] = {
153 	{ P_BI_TCXO, 0 },
154 	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
155 	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
156 	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
157 };
158 
159 static const struct clk_parent_data disp_cc_parent_data_1[] = {
160 	{ .index = DT_BI_TCXO },
161 	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
162 	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
163 	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
164 };
165 
166 static const struct parent_map disp_cc_parent_map_2[] = {
167 	{ P_BI_TCXO, 0 },
168 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
169 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
170 	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
171 	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
172 };
173 
174 static const struct clk_parent_data disp_cc_parent_data_2[] = {
175 	{ .index = DT_BI_TCXO },
176 	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
177 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
178 	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
179 	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
180 };
181 
182 static const struct parent_map disp_cc_parent_map_3[] = {
183 	{ P_BI_TCXO, 0 },
184 	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
185 	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
186 	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
187 };
188 
189 static const struct clk_parent_data disp_cc_parent_data_3[] = {
190 	{ .index = DT_BI_TCXO },
191 	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
192 	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
193 	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
194 };
195 
196 static const struct parent_map disp_cc_parent_map_4[] = {
197 	{ P_BI_TCXO, 0 },
198 	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
199 	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
200 	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
201 	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
202 	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
203 };
204 
205 static const struct clk_parent_data disp_cc_parent_data_4[] = {
206 	{ .index = DT_BI_TCXO },
207 	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
208 	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
209 	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
210 	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
211 	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
212 };
213 
214 static const struct parent_map disp_cc_parent_map_5[] = {
215 	{ P_BI_TCXO, 0 },
216 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
217 	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
218 };
219 
220 static const struct clk_parent_data disp_cc_parent_data_5[] = {
221 	{ .index = DT_BI_TCXO },
222 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
223 	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
224 };
225 
226 static const struct parent_map disp_cc_parent_map_6[] = {
227 	{ P_BI_TCXO, 0 },
228 	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
229 	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
230 };
231 
232 static const struct clk_parent_data disp_cc_parent_data_6[] = {
233 	{ .index = DT_BI_TCXO },
234 	{ .hw = &disp_cc_pll1.clkr.hw },
235 	{ .hw = &disp_cc_pll1.clkr.hw },
236 };
237 
238 static const struct parent_map disp_cc_parent_map_7[] = {
239 	{ P_BI_TCXO, 0 },
240 	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
241 	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
242 	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
243 	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
244 };
245 
246 static const struct clk_parent_data disp_cc_parent_data_7[] = {
247 	{ .index = DT_BI_TCXO },
248 	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
249 	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
250 	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
251 	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
252 };
253 
254 static const struct parent_map disp_cc_parent_map_8[] = {
255 	{ P_BI_TCXO, 0 },
256 	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
257 	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
258 	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
259 };
260 
261 static const struct clk_parent_data disp_cc_parent_data_8[] = {
262 	{ .index = DT_BI_TCXO },
263 	{ .hw = &disp_cc_pll0.clkr.hw },
264 	{ .hw = &disp_cc_pll1.clkr.hw },
265 	{ .hw = &disp_cc_pll1.clkr.hw },
266 };
267 
268 static const struct parent_map disp_cc_parent_map_9[] = {
269 	{ P_SLEEP_CLK, 0 },
270 };
271 
272 static const struct clk_parent_data disp_cc_parent_data_9[] = {
273 	{ .index = DT_SLEEP_CLK },
274 };
275 
276 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
277 	F(19200000, P_BI_TCXO, 1, 0, 0),
278 	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
279 	F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
280 	{ }
281 };
282 
283 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
284 	.cmd_rcgr = 0x82e8,
285 	.mnd_width = 0,
286 	.hid_width = 5,
287 	.parent_map = disp_cc_parent_map_6,
288 	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
289 	.clkr.hw.init = &(const struct clk_init_data) {
290 		.name = "disp_cc_mdss_ahb_clk_src",
291 		.parent_data = disp_cc_parent_data_6,
292 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
293 		.flags = CLK_SET_RATE_PARENT,
294 		.ops = &clk_rcg2_shared_ops,
295 	},
296 };
297 
298 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
299 	F(19200000, P_BI_TCXO, 1, 0, 0),
300 	{ }
301 };
302 
303 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
304 	.cmd_rcgr = 0x8108,
305 	.mnd_width = 0,
306 	.hid_width = 5,
307 	.parent_map = disp_cc_parent_map_2,
308 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
309 	.clkr.hw.init = &(const struct clk_init_data) {
310 		.name = "disp_cc_mdss_byte0_clk_src",
311 		.parent_data = disp_cc_parent_data_2,
312 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
313 		.flags = CLK_SET_RATE_PARENT,
314 		.ops = &clk_byte2_ops,
315 	},
316 };
317 
318 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
319 	.cmd_rcgr = 0x8124,
320 	.mnd_width = 0,
321 	.hid_width = 5,
322 	.parent_map = disp_cc_parent_map_2,
323 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
324 	.clkr.hw.init = &(const struct clk_init_data) {
325 		.name = "disp_cc_mdss_byte1_clk_src",
326 		.parent_data = disp_cc_parent_data_2,
327 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
328 		.flags = CLK_SET_RATE_PARENT,
329 		.ops = &clk_byte2_ops,
330 	},
331 };
332 
333 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
334 	.cmd_rcgr = 0x81bc,
335 	.mnd_width = 0,
336 	.hid_width = 5,
337 	.parent_map = disp_cc_parent_map_0,
338 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
339 	.clkr.hw.init = &(const struct clk_init_data) {
340 		.name = "disp_cc_mdss_dptx0_aux_clk_src",
341 		.parent_data = disp_cc_parent_data_0,
342 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
343 		.flags = CLK_SET_RATE_PARENT,
344 		.ops = &clk_rcg2_ops,
345 	},
346 };
347 
348 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
349 	.cmd_rcgr = 0x8170,
350 	.mnd_width = 0,
351 	.hid_width = 5,
352 	.parent_map = disp_cc_parent_map_7,
353 	.clkr.hw.init = &(const struct clk_init_data) {
354 		.name = "disp_cc_mdss_dptx0_link_clk_src",
355 		.parent_data = disp_cc_parent_data_7,
356 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
357 		.flags = CLK_SET_RATE_PARENT,
358 		.ops = &clk_byte2_ops,
359 	},
360 };
361 
362 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
363 	.cmd_rcgr = 0x818c,
364 	.mnd_width = 16,
365 	.hid_width = 5,
366 	.parent_map = disp_cc_parent_map_4,
367 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
368 	.clkr.hw.init = &(const struct clk_init_data) {
369 		.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
370 		.parent_data = disp_cc_parent_data_4,
371 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
372 		.flags = CLK_SET_RATE_PARENT,
373 		.ops = &clk_dp_ops,
374 	},
375 };
376 
377 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
378 	.cmd_rcgr = 0x81a4,
379 	.mnd_width = 16,
380 	.hid_width = 5,
381 	.parent_map = disp_cc_parent_map_4,
382 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
383 	.clkr.hw.init = &(const struct clk_init_data) {
384 		.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
385 		.parent_data = disp_cc_parent_data_4,
386 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
387 		.flags = CLK_SET_RATE_PARENT,
388 		.ops = &clk_dp_ops,
389 	},
390 };
391 
392 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
393 	.cmd_rcgr = 0x8220,
394 	.mnd_width = 0,
395 	.hid_width = 5,
396 	.parent_map = disp_cc_parent_map_0,
397 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
398 	.clkr.hw.init = &(const struct clk_init_data) {
399 		.name = "disp_cc_mdss_dptx1_aux_clk_src",
400 		.parent_data = disp_cc_parent_data_0,
401 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
402 		.flags = CLK_SET_RATE_PARENT,
403 		.ops = &clk_rcg2_ops,
404 	},
405 };
406 
407 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
408 	.cmd_rcgr = 0x8204,
409 	.mnd_width = 0,
410 	.hid_width = 5,
411 	.parent_map = disp_cc_parent_map_3,
412 	.clkr.hw.init = &(const struct clk_init_data) {
413 		.name = "disp_cc_mdss_dptx1_link_clk_src",
414 		.parent_data = disp_cc_parent_data_3,
415 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
416 		.flags = CLK_SET_RATE_PARENT,
417 		.ops = &clk_byte2_ops,
418 	},
419 };
420 
421 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
422 	.cmd_rcgr = 0x81d4,
423 	.mnd_width = 16,
424 	.hid_width = 5,
425 	.parent_map = disp_cc_parent_map_1,
426 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
427 	.clkr.hw.init = &(const struct clk_init_data) {
428 		.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
429 		.parent_data = disp_cc_parent_data_1,
430 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
431 		.flags = CLK_SET_RATE_PARENT,
432 		.ops = &clk_dp_ops,
433 	},
434 };
435 
436 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
437 	.cmd_rcgr = 0x81ec,
438 	.mnd_width = 16,
439 	.hid_width = 5,
440 	.parent_map = disp_cc_parent_map_1,
441 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
442 	.clkr.hw.init = &(const struct clk_init_data) {
443 		.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
444 		.parent_data = disp_cc_parent_data_1,
445 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
446 		.flags = CLK_SET_RATE_PARENT,
447 		.ops = &clk_dp_ops,
448 	},
449 };
450 
451 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
452 	.cmd_rcgr = 0x8284,
453 	.mnd_width = 0,
454 	.hid_width = 5,
455 	.parent_map = disp_cc_parent_map_0,
456 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
457 	.clkr.hw.init = &(const struct clk_init_data) {
458 		.name = "disp_cc_mdss_dptx2_aux_clk_src",
459 		.parent_data = disp_cc_parent_data_0,
460 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
461 		.flags = CLK_SET_RATE_PARENT,
462 		.ops = &clk_rcg2_ops,
463 	},
464 };
465 
466 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
467 	.cmd_rcgr = 0x8238,
468 	.mnd_width = 0,
469 	.hid_width = 5,
470 	.parent_map = disp_cc_parent_map_3,
471 	.clkr.hw.init = &(const struct clk_init_data) {
472 		.name = "disp_cc_mdss_dptx2_link_clk_src",
473 		.parent_data = disp_cc_parent_data_3,
474 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
475 		.flags = CLK_SET_RATE_PARENT,
476 		.ops = &clk_byte2_ops,
477 	},
478 };
479 
480 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
481 	.cmd_rcgr = 0x8254,
482 	.mnd_width = 16,
483 	.hid_width = 5,
484 	.parent_map = disp_cc_parent_map_1,
485 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
486 	.clkr.hw.init = &(const struct clk_init_data) {
487 		.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
488 		.parent_data = disp_cc_parent_data_1,
489 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
490 		.flags = CLK_SET_RATE_PARENT,
491 		.ops = &clk_dp_ops,
492 	},
493 };
494 
495 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
496 	.cmd_rcgr = 0x826c,
497 	.mnd_width = 16,
498 	.hid_width = 5,
499 	.parent_map = disp_cc_parent_map_1,
500 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
501 	.clkr.hw.init = &(const struct clk_init_data) {
502 		.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
503 		.parent_data = disp_cc_parent_data_1,
504 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
505 		.flags = CLK_SET_RATE_PARENT,
506 		.ops = &clk_dp_ops,
507 	},
508 };
509 
510 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
511 	.cmd_rcgr = 0x82d0,
512 	.mnd_width = 0,
513 	.hid_width = 5,
514 	.parent_map = disp_cc_parent_map_0,
515 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
516 	.clkr.hw.init = &(const struct clk_init_data) {
517 		.name = "disp_cc_mdss_dptx3_aux_clk_src",
518 		.parent_data = disp_cc_parent_data_0,
519 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
520 		.flags = CLK_SET_RATE_PARENT,
521 		.ops = &clk_rcg2_ops,
522 	},
523 };
524 
525 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
526 	.cmd_rcgr = 0x82b4,
527 	.mnd_width = 0,
528 	.hid_width = 5,
529 	.parent_map = disp_cc_parent_map_3,
530 	.clkr.hw.init = &(const struct clk_init_data) {
531 		.name = "disp_cc_mdss_dptx3_link_clk_src",
532 		.parent_data = disp_cc_parent_data_3,
533 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
534 		.flags = CLK_SET_RATE_PARENT,
535 		.ops = &clk_byte2_ops,
536 	},
537 };
538 
539 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
540 	.cmd_rcgr = 0x829c,
541 	.mnd_width = 16,
542 	.hid_width = 5,
543 	.parent_map = disp_cc_parent_map_1,
544 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
545 	.clkr.hw.init = &(const struct clk_init_data) {
546 		.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
547 		.parent_data = disp_cc_parent_data_1,
548 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
549 		.flags = CLK_SET_RATE_PARENT,
550 		.ops = &clk_dp_ops,
551 	},
552 };
553 
554 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
555 	.cmd_rcgr = 0x8140,
556 	.mnd_width = 0,
557 	.hid_width = 5,
558 	.parent_map = disp_cc_parent_map_5,
559 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
560 	.clkr.hw.init = &(const struct clk_init_data) {
561 		.name = "disp_cc_mdss_esc0_clk_src",
562 		.parent_data = disp_cc_parent_data_5,
563 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
564 		.flags = CLK_SET_RATE_PARENT,
565 		.ops = &clk_rcg2_shared_ops,
566 	},
567 };
568 
569 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
570 	.cmd_rcgr = 0x8158,
571 	.mnd_width = 0,
572 	.hid_width = 5,
573 	.parent_map = disp_cc_parent_map_5,
574 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
575 	.clkr.hw.init = &(const struct clk_init_data) {
576 		.name = "disp_cc_mdss_esc1_clk_src",
577 		.parent_data = disp_cc_parent_data_5,
578 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
579 		.flags = CLK_SET_RATE_PARENT,
580 		.ops = &clk_rcg2_shared_ops,
581 	},
582 };
583 
584 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
585 	F(19200000, P_BI_TCXO, 1, 0, 0),
586 	F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
587 	F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
588 	F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
589 	F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
590 	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
591 	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
592 	F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
593 	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
594 	{ }
595 };
596 
597 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] = {
598 	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
599 	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
600 	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
601 	{ }
602 };
603 
604 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = {
605 	F(19200000, P_BI_TCXO, 1, 0, 0),
606 	F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
607 	F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
608 	F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
609 	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
610 	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
611 	F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
612 	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
613 	{ }
614 };
615 
616 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
617 	.cmd_rcgr = 0x80d8,
618 	.mnd_width = 0,
619 	.hid_width = 5,
620 	.parent_map = disp_cc_parent_map_8,
621 	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
622 	.clkr.hw.init = &(const struct clk_init_data) {
623 		.name = "disp_cc_mdss_mdp_clk_src",
624 		.parent_data = disp_cc_parent_data_8,
625 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
626 		.flags = CLK_SET_RATE_PARENT,
627 		.ops = &clk_rcg2_shared_ops,
628 	},
629 };
630 
631 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
632 	.cmd_rcgr = 0x80a8,
633 	.mnd_width = 8,
634 	.hid_width = 5,
635 	.parent_map = disp_cc_parent_map_2,
636 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
637 	.clkr.hw.init = &(const struct clk_init_data) {
638 		.name = "disp_cc_mdss_pclk0_clk_src",
639 		.parent_data = disp_cc_parent_data_2,
640 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
641 		.flags = CLK_SET_RATE_PARENT,
642 		.ops = &clk_pixel_ops,
643 	},
644 };
645 
646 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
647 	.cmd_rcgr = 0x80c0,
648 	.mnd_width = 8,
649 	.hid_width = 5,
650 	.parent_map = disp_cc_parent_map_2,
651 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
652 	.clkr.hw.init = &(const struct clk_init_data) {
653 		.name = "disp_cc_mdss_pclk1_clk_src",
654 		.parent_data = disp_cc_parent_data_2,
655 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
656 		.flags = CLK_SET_RATE_PARENT,
657 		.ops = &clk_pixel_ops,
658 	},
659 };
660 
661 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
662 	.cmd_rcgr = 0x80f0,
663 	.mnd_width = 0,
664 	.hid_width = 5,
665 	.parent_map = disp_cc_parent_map_0,
666 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
667 	.clkr.hw.init = &(const struct clk_init_data) {
668 		.name = "disp_cc_mdss_vsync_clk_src",
669 		.parent_data = disp_cc_parent_data_0,
670 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
671 		.flags = CLK_SET_RATE_PARENT,
672 		.ops = &clk_rcg2_ops,
673 	},
674 };
675 
676 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
677 	F(32000, P_SLEEP_CLK, 1, 0, 0),
678 	{ }
679 };
680 
681 static struct clk_rcg2 disp_cc_sleep_clk_src = {
682 	.cmd_rcgr = 0xe05c,
683 	.mnd_width = 0,
684 	.hid_width = 5,
685 	.parent_map = disp_cc_parent_map_9,
686 	.freq_tbl = ftbl_disp_cc_sleep_clk_src,
687 	.clkr.hw.init = &(const struct clk_init_data) {
688 		.name = "disp_cc_sleep_clk_src",
689 		.parent_data = disp_cc_parent_data_9,
690 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
691 		.flags = CLK_SET_RATE_PARENT,
692 		.ops = &clk_rcg2_ops,
693 	},
694 };
695 
696 static struct clk_rcg2 disp_cc_xo_clk_src = {
697 	.cmd_rcgr = 0xe03c,
698 	.mnd_width = 0,
699 	.hid_width = 5,
700 	.parent_map = disp_cc_parent_map_0,
701 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
702 	.clkr.hw.init = &(const struct clk_init_data) {
703 		.name = "disp_cc_xo_clk_src",
704 		.parent_data = disp_cc_parent_data_0_ao,
705 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
706 		.flags = CLK_SET_RATE_PARENT,
707 		.ops = &clk_rcg2_ops,
708 	},
709 };
710 
711 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
712 	.reg = 0x8120,
713 	.shift = 0,
714 	.width = 4,
715 	.clkr.hw.init = &(const struct clk_init_data) {
716 		.name = "disp_cc_mdss_byte0_div_clk_src",
717 		.parent_hws = (const struct clk_hw*[]) {
718 			&disp_cc_mdss_byte0_clk_src.clkr.hw,
719 		},
720 		.num_parents = 1,
721 		.ops = &clk_regmap_div_ops,
722 	},
723 };
724 
725 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
726 	.reg = 0x813c,
727 	.shift = 0,
728 	.width = 4,
729 	.clkr.hw.init = &(const struct clk_init_data) {
730 		.name = "disp_cc_mdss_byte1_div_clk_src",
731 		.parent_hws = (const struct clk_hw*[]) {
732 			&disp_cc_mdss_byte1_clk_src.clkr.hw,
733 		},
734 		.num_parents = 1,
735 		.ops = &clk_regmap_div_ops,
736 	},
737 };
738 
739 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
740 	.reg = 0x8188,
741 	.shift = 0,
742 	.width = 4,
743 	.clkr.hw.init = &(const struct clk_init_data) {
744 		.name = "disp_cc_mdss_dptx0_link_div_clk_src",
745 		.parent_hws = (const struct clk_hw*[]) {
746 			&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
747 		},
748 		.num_parents = 1,
749 		.flags = CLK_SET_RATE_PARENT,
750 		.ops = &clk_regmap_div_ro_ops,
751 	},
752 };
753 
754 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
755 	.reg = 0x821c,
756 	.shift = 0,
757 	.width = 4,
758 	.clkr.hw.init = &(const struct clk_init_data) {
759 		.name = "disp_cc_mdss_dptx1_link_div_clk_src",
760 		.parent_hws = (const struct clk_hw*[]) {
761 			&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
762 		},
763 		.num_parents = 1,
764 		.flags = CLK_SET_RATE_PARENT,
765 		.ops = &clk_regmap_div_ro_ops,
766 	},
767 };
768 
769 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
770 	.reg = 0x8250,
771 	.shift = 0,
772 	.width = 4,
773 	.clkr.hw.init = &(const struct clk_init_data) {
774 		.name = "disp_cc_mdss_dptx2_link_div_clk_src",
775 		.parent_hws = (const struct clk_hw*[]) {
776 			&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
777 		},
778 		.num_parents = 1,
779 		.flags = CLK_SET_RATE_PARENT,
780 		.ops = &clk_regmap_div_ro_ops,
781 	},
782 };
783 
784 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
785 	.reg = 0x82cc,
786 	.shift = 0,
787 	.width = 4,
788 	.clkr.hw.init = &(const struct clk_init_data) {
789 		.name = "disp_cc_mdss_dptx3_link_div_clk_src",
790 		.parent_hws = (const struct clk_hw*[]) {
791 			&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
792 		},
793 		.num_parents = 1,
794 		.flags = CLK_SET_RATE_PARENT,
795 		.ops = &clk_regmap_div_ro_ops,
796 	},
797 };
798 
799 static struct clk_branch disp_cc_mdss_accu_clk = {
800 	.halt_reg = 0xe058,
801 	.halt_check = BRANCH_HALT_VOTED,
802 	.clkr = {
803 		.enable_reg = 0xe058,
804 		.enable_mask = BIT(0),
805 		.hw.init = &(const struct clk_init_data) {
806 			.name = "disp_cc_mdss_accu_clk",
807 			.parent_hws = (const struct clk_hw*[]) {
808 				&disp_cc_xo_clk_src.clkr.hw,
809 			},
810 			.num_parents = 1,
811 			.flags = CLK_SET_RATE_PARENT,
812 			.ops = &clk_branch2_ops,
813 		},
814 	},
815 };
816 
817 static struct clk_branch disp_cc_mdss_ahb1_clk = {
818 	.halt_reg = 0xa020,
819 	.halt_check = BRANCH_HALT,
820 	.clkr = {
821 		.enable_reg = 0xa020,
822 		.enable_mask = BIT(0),
823 		.hw.init = &(const struct clk_init_data) {
824 			.name = "disp_cc_mdss_ahb1_clk",
825 			.parent_hws = (const struct clk_hw*[]) {
826 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
827 			},
828 			.num_parents = 1,
829 			.flags = CLK_SET_RATE_PARENT,
830 			.ops = &clk_branch2_ops,
831 		},
832 	},
833 };
834 
835 static struct clk_branch disp_cc_mdss_ahb_clk = {
836 	.halt_reg = 0x80a4,
837 	.halt_check = BRANCH_HALT,
838 	.clkr = {
839 		.enable_reg = 0x80a4,
840 		.enable_mask = BIT(0),
841 		.hw.init = &(const struct clk_init_data) {
842 			.name = "disp_cc_mdss_ahb_clk",
843 			.parent_hws = (const struct clk_hw*[]) {
844 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
845 			},
846 			.num_parents = 1,
847 			.flags = CLK_SET_RATE_PARENT,
848 			.ops = &clk_branch2_ops,
849 		},
850 	},
851 };
852 
853 static struct clk_branch disp_cc_mdss_byte0_clk = {
854 	.halt_reg = 0x8028,
855 	.halt_check = BRANCH_HALT,
856 	.clkr = {
857 		.enable_reg = 0x8028,
858 		.enable_mask = BIT(0),
859 		.hw.init = &(const struct clk_init_data) {
860 			.name = "disp_cc_mdss_byte0_clk",
861 			.parent_hws = (const struct clk_hw*[]) {
862 				&disp_cc_mdss_byte0_clk_src.clkr.hw,
863 			},
864 			.num_parents = 1,
865 			.flags = CLK_SET_RATE_PARENT,
866 			.ops = &clk_branch2_ops,
867 		},
868 	},
869 };
870 
871 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
872 	.halt_reg = 0x802c,
873 	.halt_check = BRANCH_HALT,
874 	.clkr = {
875 		.enable_reg = 0x802c,
876 		.enable_mask = BIT(0),
877 		.hw.init = &(const struct clk_init_data) {
878 			.name = "disp_cc_mdss_byte0_intf_clk",
879 			.parent_hws = (const struct clk_hw*[]) {
880 				&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
881 			},
882 			.num_parents = 1,
883 			.flags = CLK_SET_RATE_PARENT,
884 			.ops = &clk_branch2_ops,
885 		},
886 	},
887 };
888 
889 static struct clk_branch disp_cc_mdss_byte1_clk = {
890 	.halt_reg = 0x8030,
891 	.halt_check = BRANCH_HALT,
892 	.clkr = {
893 		.enable_reg = 0x8030,
894 		.enable_mask = BIT(0),
895 		.hw.init = &(const struct clk_init_data) {
896 			.name = "disp_cc_mdss_byte1_clk",
897 			.parent_hws = (const struct clk_hw*[]) {
898 				&disp_cc_mdss_byte1_clk_src.clkr.hw,
899 			},
900 			.num_parents = 1,
901 			.flags = CLK_SET_RATE_PARENT,
902 			.ops = &clk_branch2_ops,
903 		},
904 	},
905 };
906 
907 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
908 	.halt_reg = 0x8034,
909 	.halt_check = BRANCH_HALT,
910 	.clkr = {
911 		.enable_reg = 0x8034,
912 		.enable_mask = BIT(0),
913 		.hw.init = &(const struct clk_init_data) {
914 			.name = "disp_cc_mdss_byte1_intf_clk",
915 			.parent_hws = (const struct clk_hw*[]) {
916 				&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
917 			},
918 			.num_parents = 1,
919 			.flags = CLK_SET_RATE_PARENT,
920 			.ops = &clk_branch2_ops,
921 		},
922 	},
923 };
924 
925 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
926 	.halt_reg = 0x8058,
927 	.halt_check = BRANCH_HALT,
928 	.clkr = {
929 		.enable_reg = 0x8058,
930 		.enable_mask = BIT(0),
931 		.hw.init = &(const struct clk_init_data) {
932 			.name = "disp_cc_mdss_dptx0_aux_clk",
933 			.parent_hws = (const struct clk_hw*[]) {
934 				&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
935 			},
936 			.num_parents = 1,
937 			.flags = CLK_SET_RATE_PARENT,
938 			.ops = &clk_branch2_ops,
939 		},
940 	},
941 };
942 
943 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
944 	.halt_reg = 0x804c,
945 	.halt_check = BRANCH_HALT,
946 	.clkr = {
947 		.enable_reg = 0x804c,
948 		.enable_mask = BIT(0),
949 		.hw.init = &(const struct clk_init_data) {
950 			.name = "disp_cc_mdss_dptx0_crypto_clk",
951 			.parent_hws = (const struct clk_hw*[]) {
952 				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
953 			},
954 			.num_parents = 1,
955 			.flags = CLK_SET_RATE_PARENT,
956 			.ops = &clk_branch2_ops,
957 		},
958 	},
959 };
960 
961 static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
962 	.halt_reg = 0x8040,
963 	.halt_check = BRANCH_HALT,
964 	.clkr = {
965 		.enable_reg = 0x8040,
966 		.enable_mask = BIT(0),
967 		.hw.init = &(const struct clk_init_data) {
968 			.name = "disp_cc_mdss_dptx0_link_clk",
969 			.parent_hws = (const struct clk_hw*[]) {
970 				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
971 			},
972 			.num_parents = 1,
973 			.flags = CLK_SET_RATE_PARENT,
974 			.ops = &clk_branch2_ops,
975 		},
976 	},
977 };
978 
979 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
980 	.halt_reg = 0x8048,
981 	.halt_check = BRANCH_HALT,
982 	.clkr = {
983 		.enable_reg = 0x8048,
984 		.enable_mask = BIT(0),
985 		.hw.init = &(const struct clk_init_data) {
986 			.name = "disp_cc_mdss_dptx0_link_intf_clk",
987 			.parent_hws = (const struct clk_hw*[]) {
988 				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
989 			},
990 			.num_parents = 1,
991 			.flags = CLK_SET_RATE_PARENT,
992 			.ops = &clk_branch2_ops,
993 		},
994 	},
995 };
996 
997 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
998 	.halt_reg = 0x8050,
999 	.halt_check = BRANCH_HALT,
1000 	.clkr = {
1001 		.enable_reg = 0x8050,
1002 		.enable_mask = BIT(0),
1003 		.hw.init = &(const struct clk_init_data) {
1004 			.name = "disp_cc_mdss_dptx0_pixel0_clk",
1005 			.parent_hws = (const struct clk_hw*[]) {
1006 				&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1007 			},
1008 			.num_parents = 1,
1009 			.flags = CLK_SET_RATE_PARENT,
1010 			.ops = &clk_branch2_ops,
1011 		},
1012 	},
1013 };
1014 
1015 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
1016 	.halt_reg = 0x8054,
1017 	.halt_check = BRANCH_HALT,
1018 	.clkr = {
1019 		.enable_reg = 0x8054,
1020 		.enable_mask = BIT(0),
1021 		.hw.init = &(const struct clk_init_data) {
1022 			.name = "disp_cc_mdss_dptx0_pixel1_clk",
1023 			.parent_hws = (const struct clk_hw*[]) {
1024 				&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1025 			},
1026 			.num_parents = 1,
1027 			.flags = CLK_SET_RATE_PARENT,
1028 			.ops = &clk_branch2_ops,
1029 		},
1030 	},
1031 };
1032 
1033 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1034 	.halt_reg = 0x8044,
1035 	.halt_check = BRANCH_HALT,
1036 	.clkr = {
1037 		.enable_reg = 0x8044,
1038 		.enable_mask = BIT(0),
1039 		.hw.init = &(const struct clk_init_data) {
1040 			.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1041 			.parent_hws = (const struct clk_hw*[]) {
1042 				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1043 			},
1044 			.num_parents = 1,
1045 			.flags = CLK_SET_RATE_PARENT,
1046 			.ops = &clk_branch2_ops,
1047 		},
1048 	},
1049 };
1050 
1051 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1052 	.halt_reg = 0x8074,
1053 	.halt_check = BRANCH_HALT,
1054 	.clkr = {
1055 		.enable_reg = 0x8074,
1056 		.enable_mask = BIT(0),
1057 		.hw.init = &(const struct clk_init_data) {
1058 			.name = "disp_cc_mdss_dptx1_aux_clk",
1059 			.parent_hws = (const struct clk_hw*[]) {
1060 				&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1061 			},
1062 			.num_parents = 1,
1063 			.flags = CLK_SET_RATE_PARENT,
1064 			.ops = &clk_branch2_ops,
1065 		},
1066 	},
1067 };
1068 
1069 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
1070 	.halt_reg = 0x8070,
1071 	.halt_check = BRANCH_HALT,
1072 	.clkr = {
1073 		.enable_reg = 0x8070,
1074 		.enable_mask = BIT(0),
1075 		.hw.init = &(const struct clk_init_data) {
1076 			.name = "disp_cc_mdss_dptx1_crypto_clk",
1077 			.parent_hws = (const struct clk_hw*[]) {
1078 				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1079 			},
1080 			.num_parents = 1,
1081 			.flags = CLK_SET_RATE_PARENT,
1082 			.ops = &clk_branch2_ops,
1083 		},
1084 	},
1085 };
1086 
1087 static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1088 	.halt_reg = 0x8064,
1089 	.halt_check = BRANCH_HALT,
1090 	.clkr = {
1091 		.enable_reg = 0x8064,
1092 		.enable_mask = BIT(0),
1093 		.hw.init = &(const struct clk_init_data) {
1094 			.name = "disp_cc_mdss_dptx1_link_clk",
1095 			.parent_hws = (const struct clk_hw*[]) {
1096 				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1097 			},
1098 			.num_parents = 1,
1099 			.flags = CLK_SET_RATE_PARENT,
1100 			.ops = &clk_branch2_ops,
1101 		},
1102 	},
1103 };
1104 
1105 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1106 	.halt_reg = 0x806c,
1107 	.halt_check = BRANCH_HALT,
1108 	.clkr = {
1109 		.enable_reg = 0x806c,
1110 		.enable_mask = BIT(0),
1111 		.hw.init = &(const struct clk_init_data) {
1112 			.name = "disp_cc_mdss_dptx1_link_intf_clk",
1113 			.parent_hws = (const struct clk_hw*[]) {
1114 				&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1115 			},
1116 			.num_parents = 1,
1117 			.flags = CLK_SET_RATE_PARENT,
1118 			.ops = &clk_branch2_ops,
1119 		},
1120 	},
1121 };
1122 
1123 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1124 	.halt_reg = 0x805c,
1125 	.halt_check = BRANCH_HALT,
1126 	.clkr = {
1127 		.enable_reg = 0x805c,
1128 		.enable_mask = BIT(0),
1129 		.hw.init = &(const struct clk_init_data) {
1130 			.name = "disp_cc_mdss_dptx1_pixel0_clk",
1131 			.parent_hws = (const struct clk_hw*[]) {
1132 				&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1133 			},
1134 			.num_parents = 1,
1135 			.flags = CLK_SET_RATE_PARENT,
1136 			.ops = &clk_branch2_ops,
1137 		},
1138 	},
1139 };
1140 
1141 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1142 	.halt_reg = 0x8060,
1143 	.halt_check = BRANCH_HALT,
1144 	.clkr = {
1145 		.enable_reg = 0x8060,
1146 		.enable_mask = BIT(0),
1147 		.hw.init = &(const struct clk_init_data) {
1148 			.name = "disp_cc_mdss_dptx1_pixel1_clk",
1149 			.parent_hws = (const struct clk_hw*[]) {
1150 				&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1151 			},
1152 			.num_parents = 1,
1153 			.flags = CLK_SET_RATE_PARENT,
1154 			.ops = &clk_branch2_ops,
1155 		},
1156 	},
1157 };
1158 
1159 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1160 	.halt_reg = 0x8068,
1161 	.halt_check = BRANCH_HALT,
1162 	.clkr = {
1163 		.enable_reg = 0x8068,
1164 		.enable_mask = BIT(0),
1165 		.hw.init = &(const struct clk_init_data) {
1166 			.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1167 			.parent_hws = (const struct clk_hw*[]) {
1168 				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1169 			},
1170 			.num_parents = 1,
1171 			.flags = CLK_SET_RATE_PARENT,
1172 			.ops = &clk_branch2_ops,
1173 		},
1174 	},
1175 };
1176 
1177 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1178 	.halt_reg = 0x808c,
1179 	.halt_check = BRANCH_HALT,
1180 	.clkr = {
1181 		.enable_reg = 0x808c,
1182 		.enable_mask = BIT(0),
1183 		.hw.init = &(const struct clk_init_data) {
1184 			.name = "disp_cc_mdss_dptx2_aux_clk",
1185 			.parent_hws = (const struct clk_hw*[]) {
1186 				&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1187 			},
1188 			.num_parents = 1,
1189 			.flags = CLK_SET_RATE_PARENT,
1190 			.ops = &clk_branch2_ops,
1191 		},
1192 	},
1193 };
1194 
1195 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
1196 	.halt_reg = 0x8088,
1197 	.halt_check = BRANCH_HALT,
1198 	.clkr = {
1199 		.enable_reg = 0x8088,
1200 		.enable_mask = BIT(0),
1201 		.hw.init = &(const struct clk_init_data) {
1202 			.name = "disp_cc_mdss_dptx2_crypto_clk",
1203 			.parent_hws = (const struct clk_hw*[]) {
1204 				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1205 			},
1206 			.num_parents = 1,
1207 			.flags = CLK_SET_RATE_PARENT,
1208 			.ops = &clk_branch2_ops,
1209 		},
1210 	},
1211 };
1212 
1213 static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1214 	.halt_reg = 0x8080,
1215 	.halt_check = BRANCH_HALT,
1216 	.clkr = {
1217 		.enable_reg = 0x8080,
1218 		.enable_mask = BIT(0),
1219 		.hw.init = &(const struct clk_init_data) {
1220 			.name = "disp_cc_mdss_dptx2_link_clk",
1221 			.parent_hws = (const struct clk_hw*[]) {
1222 				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1223 			},
1224 			.num_parents = 1,
1225 			.flags = CLK_SET_RATE_PARENT,
1226 			.ops = &clk_branch2_ops,
1227 		},
1228 	},
1229 };
1230 
1231 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1232 	.halt_reg = 0x8084,
1233 	.halt_check = BRANCH_HALT,
1234 	.clkr = {
1235 		.enable_reg = 0x8084,
1236 		.enable_mask = BIT(0),
1237 		.hw.init = &(const struct clk_init_data) {
1238 			.name = "disp_cc_mdss_dptx2_link_intf_clk",
1239 			.parent_hws = (const struct clk_hw*[]) {
1240 				&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1241 			},
1242 			.num_parents = 1,
1243 			.flags = CLK_SET_RATE_PARENT,
1244 			.ops = &clk_branch2_ops,
1245 		},
1246 	},
1247 };
1248 
1249 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1250 	.halt_reg = 0x8078,
1251 	.halt_check = BRANCH_HALT,
1252 	.clkr = {
1253 		.enable_reg = 0x8078,
1254 		.enable_mask = BIT(0),
1255 		.hw.init = &(const struct clk_init_data) {
1256 			.name = "disp_cc_mdss_dptx2_pixel0_clk",
1257 			.parent_hws = (const struct clk_hw*[]) {
1258 				&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1259 			},
1260 			.num_parents = 1,
1261 			.flags = CLK_SET_RATE_PARENT,
1262 			.ops = &clk_branch2_ops,
1263 		},
1264 	},
1265 };
1266 
1267 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1268 	.halt_reg = 0x807c,
1269 	.halt_check = BRANCH_HALT,
1270 	.clkr = {
1271 		.enable_reg = 0x807c,
1272 		.enable_mask = BIT(0),
1273 		.hw.init = &(const struct clk_init_data) {
1274 			.name = "disp_cc_mdss_dptx2_pixel1_clk",
1275 			.parent_hws = (const struct clk_hw*[]) {
1276 				&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1277 			},
1278 			.num_parents = 1,
1279 			.flags = CLK_SET_RATE_PARENT,
1280 			.ops = &clk_branch2_ops,
1281 		},
1282 	},
1283 };
1284 
1285 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1286 	.halt_reg = 0x809c,
1287 	.halt_check = BRANCH_HALT,
1288 	.clkr = {
1289 		.enable_reg = 0x809c,
1290 		.enable_mask = BIT(0),
1291 		.hw.init = &(const struct clk_init_data) {
1292 			.name = "disp_cc_mdss_dptx3_aux_clk",
1293 			.parent_hws = (const struct clk_hw*[]) {
1294 				&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1295 			},
1296 			.num_parents = 1,
1297 			.flags = CLK_SET_RATE_PARENT,
1298 			.ops = &clk_branch2_ops,
1299 		},
1300 	},
1301 };
1302 
1303 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
1304 	.halt_reg = 0x80a0,
1305 	.halt_check = BRANCH_HALT,
1306 	.clkr = {
1307 		.enable_reg = 0x80a0,
1308 		.enable_mask = BIT(0),
1309 		.hw.init = &(const struct clk_init_data) {
1310 			.name = "disp_cc_mdss_dptx3_crypto_clk",
1311 			.parent_hws = (const struct clk_hw*[]) {
1312 				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1313 			},
1314 			.num_parents = 1,
1315 			.flags = CLK_SET_RATE_PARENT,
1316 			.ops = &clk_branch2_ops,
1317 		},
1318 	},
1319 };
1320 
1321 static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1322 	.halt_reg = 0x8094,
1323 	.halt_check = BRANCH_HALT,
1324 	.clkr = {
1325 		.enable_reg = 0x8094,
1326 		.enable_mask = BIT(0),
1327 		.hw.init = &(const struct clk_init_data) {
1328 			.name = "disp_cc_mdss_dptx3_link_clk",
1329 			.parent_hws = (const struct clk_hw*[]) {
1330 				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1331 			},
1332 			.num_parents = 1,
1333 			.flags = CLK_SET_RATE_PARENT,
1334 			.ops = &clk_branch2_ops,
1335 		},
1336 	},
1337 };
1338 
1339 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1340 	.halt_reg = 0x8098,
1341 	.halt_check = BRANCH_HALT,
1342 	.clkr = {
1343 		.enable_reg = 0x8098,
1344 		.enable_mask = BIT(0),
1345 		.hw.init = &(const struct clk_init_data) {
1346 			.name = "disp_cc_mdss_dptx3_link_intf_clk",
1347 			.parent_hws = (const struct clk_hw*[]) {
1348 				&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1349 			},
1350 			.num_parents = 1,
1351 			.flags = CLK_SET_RATE_PARENT,
1352 			.ops = &clk_branch2_ops,
1353 		},
1354 	},
1355 };
1356 
1357 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1358 	.halt_reg = 0x8090,
1359 	.halt_check = BRANCH_HALT,
1360 	.clkr = {
1361 		.enable_reg = 0x8090,
1362 		.enable_mask = BIT(0),
1363 		.hw.init = &(const struct clk_init_data) {
1364 			.name = "disp_cc_mdss_dptx3_pixel0_clk",
1365 			.parent_hws = (const struct clk_hw*[]) {
1366 				&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1367 			},
1368 			.num_parents = 1,
1369 			.flags = CLK_SET_RATE_PARENT,
1370 			.ops = &clk_branch2_ops,
1371 		},
1372 	},
1373 };
1374 
1375 static struct clk_branch disp_cc_mdss_esc0_clk = {
1376 	.halt_reg = 0x8038,
1377 	.halt_check = BRANCH_HALT,
1378 	.clkr = {
1379 		.enable_reg = 0x8038,
1380 		.enable_mask = BIT(0),
1381 		.hw.init = &(const struct clk_init_data) {
1382 			.name = "disp_cc_mdss_esc0_clk",
1383 			.parent_hws = (const struct clk_hw*[]) {
1384 				&disp_cc_mdss_esc0_clk_src.clkr.hw,
1385 			},
1386 			.num_parents = 1,
1387 			.flags = CLK_SET_RATE_PARENT,
1388 			.ops = &clk_branch2_ops,
1389 		},
1390 	},
1391 };
1392 
1393 static struct clk_branch disp_cc_mdss_esc1_clk = {
1394 	.halt_reg = 0x803c,
1395 	.halt_check = BRANCH_HALT,
1396 	.clkr = {
1397 		.enable_reg = 0x803c,
1398 		.enable_mask = BIT(0),
1399 		.hw.init = &(const struct clk_init_data) {
1400 			.name = "disp_cc_mdss_esc1_clk",
1401 			.parent_hws = (const struct clk_hw*[]) {
1402 				&disp_cc_mdss_esc1_clk_src.clkr.hw,
1403 			},
1404 			.num_parents = 1,
1405 			.flags = CLK_SET_RATE_PARENT,
1406 			.ops = &clk_branch2_ops,
1407 		},
1408 	},
1409 };
1410 
1411 static struct clk_branch disp_cc_mdss_mdp1_clk = {
1412 	.halt_reg = 0xa004,
1413 	.halt_check = BRANCH_HALT,
1414 	.clkr = {
1415 		.enable_reg = 0xa004,
1416 		.enable_mask = BIT(0),
1417 		.hw.init = &(const struct clk_init_data) {
1418 			.name = "disp_cc_mdss_mdp1_clk",
1419 			.parent_hws = (const struct clk_hw*[]) {
1420 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1421 			},
1422 			.num_parents = 1,
1423 			.flags = CLK_SET_RATE_PARENT,
1424 			.ops = &clk_branch2_ops,
1425 		},
1426 	},
1427 };
1428 
1429 static struct clk_branch disp_cc_mdss_mdp_clk = {
1430 	.halt_reg = 0x800c,
1431 	.halt_check = BRANCH_HALT,
1432 	.clkr = {
1433 		.enable_reg = 0x800c,
1434 		.enable_mask = BIT(0),
1435 		.hw.init = &(const struct clk_init_data) {
1436 			.name = "disp_cc_mdss_mdp_clk",
1437 			.parent_hws = (const struct clk_hw*[]) {
1438 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1439 			},
1440 			.num_parents = 1,
1441 			.flags = CLK_SET_RATE_PARENT,
1442 			.ops = &clk_branch2_ops,
1443 		},
1444 	},
1445 };
1446 
1447 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1448 	.halt_reg = 0xa010,
1449 	.halt_check = BRANCH_HALT,
1450 	.clkr = {
1451 		.enable_reg = 0xa010,
1452 		.enable_mask = BIT(0),
1453 		.hw.init = &(const struct clk_init_data) {
1454 			.name = "disp_cc_mdss_mdp_lut1_clk",
1455 			.parent_hws = (const struct clk_hw*[]) {
1456 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1457 			},
1458 			.num_parents = 1,
1459 			.flags = CLK_SET_RATE_PARENT,
1460 			.ops = &clk_branch2_ops,
1461 		},
1462 	},
1463 };
1464 
1465 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1466 	.halt_reg = 0x8018,
1467 	.halt_check = BRANCH_HALT_VOTED,
1468 	.clkr = {
1469 		.enable_reg = 0x8018,
1470 		.enable_mask = BIT(0),
1471 		.hw.init = &(const struct clk_init_data) {
1472 			.name = "disp_cc_mdss_mdp_lut_clk",
1473 			.parent_hws = (const struct clk_hw*[]) {
1474 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1475 			},
1476 			.num_parents = 1,
1477 			.flags = CLK_SET_RATE_PARENT,
1478 			.ops = &clk_branch2_ops,
1479 		},
1480 	},
1481 };
1482 
1483 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1484 	.halt_reg = 0xc004,
1485 	.halt_check = BRANCH_HALT_VOTED,
1486 	.clkr = {
1487 		.enable_reg = 0xc004,
1488 		.enable_mask = BIT(0),
1489 		.hw.init = &(const struct clk_init_data) {
1490 			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
1491 			.parent_hws = (const struct clk_hw*[]) {
1492 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1493 			},
1494 			.num_parents = 1,
1495 			.flags = CLK_SET_RATE_PARENT,
1496 			.ops = &clk_branch2_ops,
1497 		},
1498 	},
1499 };
1500 
1501 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1502 	.halt_reg = 0x8004,
1503 	.halt_check = BRANCH_HALT,
1504 	.clkr = {
1505 		.enable_reg = 0x8004,
1506 		.enable_mask = BIT(0),
1507 		.hw.init = &(const struct clk_init_data) {
1508 			.name = "disp_cc_mdss_pclk0_clk",
1509 			.parent_hws = (const struct clk_hw*[]) {
1510 				&disp_cc_mdss_pclk0_clk_src.clkr.hw,
1511 			},
1512 			.num_parents = 1,
1513 			.flags = CLK_SET_RATE_PARENT,
1514 			.ops = &clk_branch2_ops,
1515 		},
1516 	},
1517 };
1518 
1519 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1520 	.halt_reg = 0x8008,
1521 	.halt_check = BRANCH_HALT,
1522 	.clkr = {
1523 		.enable_reg = 0x8008,
1524 		.enable_mask = BIT(0),
1525 		.hw.init = &(const struct clk_init_data) {
1526 			.name = "disp_cc_mdss_pclk1_clk",
1527 			.parent_hws = (const struct clk_hw*[]) {
1528 				&disp_cc_mdss_pclk1_clk_src.clkr.hw,
1529 			},
1530 			.num_parents = 1,
1531 			.flags = CLK_SET_RATE_PARENT,
1532 			.ops = &clk_branch2_ops,
1533 		},
1534 	},
1535 };
1536 
1537 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1538 	.halt_reg = 0xc00c,
1539 	.halt_check = BRANCH_HALT,
1540 	.clkr = {
1541 		.enable_reg = 0xc00c,
1542 		.enable_mask = BIT(0),
1543 		.hw.init = &(const struct clk_init_data) {
1544 			.name = "disp_cc_mdss_rscc_ahb_clk",
1545 			.parent_hws = (const struct clk_hw*[]) {
1546 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1547 			},
1548 			.num_parents = 1,
1549 			.flags = CLK_SET_RATE_PARENT,
1550 			.ops = &clk_branch2_ops,
1551 		},
1552 	},
1553 };
1554 
1555 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1556 	.halt_reg = 0xc008,
1557 	.halt_check = BRANCH_HALT,
1558 	.clkr = {
1559 		.enable_reg = 0xc008,
1560 		.enable_mask = BIT(0),
1561 		.hw.init = &(const struct clk_init_data) {
1562 			.name = "disp_cc_mdss_rscc_vsync_clk",
1563 			.parent_hws = (const struct clk_hw*[]) {
1564 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1565 			},
1566 			.num_parents = 1,
1567 			.flags = CLK_SET_RATE_PARENT,
1568 			.ops = &clk_branch2_ops,
1569 		},
1570 	},
1571 };
1572 
1573 static struct clk_branch disp_cc_mdss_vsync1_clk = {
1574 	.halt_reg = 0xa01c,
1575 	.halt_check = BRANCH_HALT,
1576 	.clkr = {
1577 		.enable_reg = 0xa01c,
1578 		.enable_mask = BIT(0),
1579 		.hw.init = &(const struct clk_init_data) {
1580 			.name = "disp_cc_mdss_vsync1_clk",
1581 			.parent_hws = (const struct clk_hw*[]) {
1582 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1583 			},
1584 			.num_parents = 1,
1585 			.flags = CLK_SET_RATE_PARENT,
1586 			.ops = &clk_branch2_ops,
1587 		},
1588 	},
1589 };
1590 
1591 static struct clk_branch disp_cc_mdss_vsync_clk = {
1592 	.halt_reg = 0x8024,
1593 	.halt_check = BRANCH_HALT,
1594 	.clkr = {
1595 		.enable_reg = 0x8024,
1596 		.enable_mask = BIT(0),
1597 		.hw.init = &(const struct clk_init_data) {
1598 			.name = "disp_cc_mdss_vsync_clk",
1599 			.parent_hws = (const struct clk_hw*[]) {
1600 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1601 			},
1602 			.num_parents = 1,
1603 			.flags = CLK_SET_RATE_PARENT,
1604 			.ops = &clk_branch2_ops,
1605 		},
1606 	},
1607 };
1608 
1609 static struct clk_branch disp_cc_sleep_clk = {
1610 	.halt_reg = 0xe074,
1611 	.halt_check = BRANCH_HALT,
1612 	.clkr = {
1613 		.enable_reg = 0xe074,
1614 		.enable_mask = BIT(0),
1615 		.hw.init = &(const struct clk_init_data) {
1616 			.name = "disp_cc_sleep_clk",
1617 			.parent_hws = (const struct clk_hw*[]) {
1618 				&disp_cc_sleep_clk_src.clkr.hw,
1619 			},
1620 			.num_parents = 1,
1621 			.flags = CLK_SET_RATE_PARENT,
1622 			.ops = &clk_branch2_ops,
1623 		},
1624 	},
1625 };
1626 
1627 static struct gdsc mdss_gdsc = {
1628 	.gdscr = 0x9000,
1629 	.pd = {
1630 		.name = "mdss_gdsc",
1631 	},
1632 	.pwrsts = PWRSTS_OFF_ON,
1633 	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1634 };
1635 
1636 static struct gdsc mdss_int2_gdsc = {
1637 	.gdscr = 0xb000,
1638 	.pd = {
1639 		.name = "mdss_int2_gdsc",
1640 	},
1641 	.pwrsts = PWRSTS_OFF_ON,
1642 	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1643 };
1644 
1645 static struct clk_regmap *disp_cc_sm8550_clocks[] = {
1646 	[DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr,
1647 	[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1648 	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1649 	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1650 	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1651 	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1652 	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1653 	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1654 	[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1655 	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1656 	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1657 	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1658 	[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1659 	[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1660 	[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
1661 	[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1662 	[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1663 	[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1664 	[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1665 	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1666 	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1667 	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1668 	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1669 	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1670 		&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1671 	[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1672 	[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1673 	[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
1674 	[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1675 	[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1676 	[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1677 	[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1678 	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1679 	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1680 	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1681 	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1682 	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1683 		&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1684 	[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1685 	[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1686 	[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
1687 	[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1688 	[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1689 	[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1690 	[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1691 	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1692 	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1693 	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1694 	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1695 	[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1696 	[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1697 	[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
1698 	[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1699 	[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1700 	[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1701 	[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1702 	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1703 	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1704 	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1705 	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1706 	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1707 	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1708 	[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1709 	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1710 	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1711 	[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1712 	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1713 	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1714 	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1715 	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1716 	[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1717 	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1718 	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1719 	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1720 	[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1721 	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1722 	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1723 	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1724 	[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1725 	[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
1726 	[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1727 	[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1728 };
1729 
1730 static const struct qcom_reset_map disp_cc_sm8550_resets[] = {
1731 	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1732 	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1733 	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1734 };
1735 
1736 static struct gdsc *disp_cc_sm8550_gdscs[] = {
1737 	[MDSS_GDSC] = &mdss_gdsc,
1738 	[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
1739 };
1740 
1741 static const struct regmap_config disp_cc_sm8550_regmap_config = {
1742 	.reg_bits = 32,
1743 	.reg_stride = 4,
1744 	.val_bits = 32,
1745 	.max_register = 0x11008,
1746 	.fast_io = true,
1747 };
1748 
1749 static struct qcom_cc_desc disp_cc_sm8550_desc = {
1750 	.config = &disp_cc_sm8550_regmap_config,
1751 	.clks = disp_cc_sm8550_clocks,
1752 	.num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks),
1753 	.resets = disp_cc_sm8550_resets,
1754 	.num_resets = ARRAY_SIZE(disp_cc_sm8550_resets),
1755 	.gdscs = disp_cc_sm8550_gdscs,
1756 	.num_gdscs = ARRAY_SIZE(disp_cc_sm8550_gdscs),
1757 };
1758 
1759 static const struct of_device_id disp_cc_sm8550_match_table[] = {
1760 	{ .compatible = "qcom,sar2130p-dispcc" },
1761 	{ .compatible = "qcom,sm8550-dispcc" },
1762 	{ .compatible = "qcom,sm8650-dispcc" },
1763 	{ }
1764 };
1765 MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table);
1766 
disp_cc_sm8550_probe(struct platform_device * pdev)1767 static int disp_cc_sm8550_probe(struct platform_device *pdev)
1768 {
1769 	struct regmap *regmap;
1770 	int ret;
1771 
1772 	ret = devm_pm_runtime_enable(&pdev->dev);
1773 	if (ret)
1774 		return ret;
1775 
1776 	ret = pm_runtime_resume_and_get(&pdev->dev);
1777 	if (ret)
1778 		return ret;
1779 
1780 	regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc);
1781 	if (IS_ERR(regmap)) {
1782 		ret = PTR_ERR(regmap);
1783 		goto err_put_rpm;
1784 	}
1785 
1786 	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-dispcc")) {
1787 		lucid_ole_vco[0].max_freq = 2100000000;
1788 		disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650;
1789 		disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] =
1790 			&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw;
1791 	} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) {
1792 		disp_cc_pll0_config.l = 0x1f;
1793 		disp_cc_pll0_config.alpha = 0x4000;
1794 		disp_cc_pll0_config.user_ctl_val = 0x1;
1795 		disp_cc_pll1_config.user_ctl_val = 0x1;
1796 		disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sar2130p;
1797 	}
1798 
1799 	clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1800 	clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1801 
1802 	/* Enable clock gating for MDP clocks */
1803 	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
1804 
1805 	/* Keep some clocks always-on */
1806 	qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
1807 
1808 	ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8550_desc, regmap);
1809 	if (ret)
1810 		goto err_put_rpm;
1811 
1812 	pm_runtime_put(&pdev->dev);
1813 
1814 	return 0;
1815 
1816 err_put_rpm:
1817 	pm_runtime_put_sync(&pdev->dev);
1818 
1819 	return ret;
1820 }
1821 
1822 static struct platform_driver disp_cc_sm8550_driver = {
1823 	.probe = disp_cc_sm8550_probe,
1824 	.driver = {
1825 		.name = "disp_cc-sm8550",
1826 		.of_match_table = disp_cc_sm8550_match_table,
1827 	},
1828 };
1829 
1830 module_platform_driver(disp_cc_sm8550_driver);
1831 
1832 MODULE_DESCRIPTION("QTI DISPCC SM8550 / SM8650  Driver");
1833 MODULE_LICENSE("GPL");
1834