xref: /illumos-gate/usr/src/uts/common/io/mega_sas/megaraid_sas.h (revision 14cd9973e77e9bfa1eca7f8e24ff5786853576c5)
1 /*
2  * megaraid_sas.h: header for mega_sas
3  *
4  * Solaris MegaRAID driver for SAS controllers
5  * Copyright (c) 2004-2008, LSI Logic Corporation.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright notice,
12  *    this list of conditions and the following disclaimer.
13  *
14  * 2. Redistributions in binary form must reproduce the above copyright notice,
15  *    this list of conditions and the following disclaimer in the documentation
16  *    and/or other materials provided with the distribution.
17  *
18  * 3. Neither the name of the author nor the names of its contributors may be
19  *    used to endorse or promote products derived from this software without
20  *    specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33  * DAMAGE.
34  */
35 
36 /*
37  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
38  * Use is subject to license terms.
39  */
40 
41 #ifndef	_MEGARAID_SAS_H_
42 #define	_MEGARAID_SAS_H_
43 
44 #ifdef	__cplusplus
45 extern "C" {
46 #endif
47 
48 #include <sys/scsi/scsi.h>
49 #include "list.h"
50 
51 /*
52  * MegaRAID SAS Driver meta data
53  */
54 #define	MEGASAS_VERSION				"LSIv1.28"
55 #define	MEGASAS_RELDATE				"Dec 4, 2008"
56 
57 #define	MEGASAS_TRUE				1
58 #define	MEGASAS_FALSE				0
59 
60 /*
61  * MegaRAID device id conversion definitions.
62  */
63 #define	INST2LSIRDCTL(x)		((x) << INST_MINOR_SHIFT)
64 
65 /*
66  * MegaRAID SAS supported controllers
67  */
68 #define	PCI_DEVICE_ID_LSI_1064			0x0411
69 #define	PCI_DEVICE_ID_LSI_1078			0x0060
70 #define	PCI_DEVICE_ID_LSI_1078DE		0x007C
71 
72 #define	PCI_DEVICE_ID_DELL_PERC5		0x0015
73 #define	PCI_DEVICE_ID_DELL_SAS5			0x0054
74 
75 #define	PCI_SUBSYSTEM_DELL_PERC5E		0x1F01
76 #define	PCI_SUBSYSTEM_DELL_PERC5I		0x1F02
77 #define	PCI_SUBSYSTEM_DELL_PERC5I_INTEGRATED	0x1F03
78 #define	PCI_SUBSYSTEM_DELL_SAS5I		0x1F05
79 #define	PCI_SUBSYSTEM_DELL_SAS5I_INTEGRATED	0x1F06
80 
81 #define	PCI_SUB_DEVICEID_FSC			0x1081
82 #define	PCI_SUB_VENDORID_FSC			0x1734
83 
84 #define	REGISTER_SET_IO				(1)
85 
86 #define	MEGASAS_MAX_SGE_CNT			0x50
87 
88 #define	MEGASAS_IOCTL_DRIVER			0x12341234
89 #define	MEGASAS_IOCTL_FIRMWARE			0x12345678
90 #define	MEGASAS_IOCTL_AEN			0x87654321
91 
92 #define	MEGASAS_1_SECOND			1000000
93 /*
94  * =====================================
95  * MegaRAID SAS MFI firmware definitions
96  * =====================================
97  */
98 /*
99  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
100  * protocol between the software and firmware. Commands are issued using
101  * "message frames"
102  */
103 
104 /*
105  * FW posts its state in upper 4 bits of outbound_msg_0 register
106  */
107 #define	MFI_STATE_MASK				0xF0000000
108 #define	MFI_STATE_UNDEFINED			0x00000000
109 #define	MFI_STATE_BB_INIT			0x10000000
110 #define	MFI_STATE_FW_INIT			0x40000000
111 #define	MFI_STATE_WAIT_HANDSHAKE		0x60000000
112 #define	MFI_STATE_FW_INIT_2			0x70000000
113 #define	MFI_STATE_DEVICE_SCAN			0x80000000
114 #define	MFI_STATE_BOOT_MESSAGE_PENDING		0x90000000
115 #define	MFI_STATE_FLUSH_CACHE			0xA0000000
116 #define	MFI_STATE_READY				0xB0000000
117 #define	MFI_STATE_OPERATIONAL			0xC0000000
118 #define	MFI_STATE_FAULT				0xF0000000
119 
120 #define	MEGAMFI_FRAME_SIZE			64
121 
122 /*
123  * During FW init, clear pending cmds & reset state using inbound_msg_0
124  *
125  * ABORT	: Abort all pending cmds
126  * READY	: Move from OPERATIONAL to READY state; discard queue info
127  * MFIMODE	: Discard (possible) low MFA posted in 64-bit mode (??)
128  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
129  */
130 #define	MFI_INIT_ABORT				0x00000001
131 #define	MFI_INIT_READY				0x00000002
132 #define	MFI_INIT_MFIMODE			0x00000004
133 #define	MFI_INIT_CLEAR_HANDSHAKE		0x00000008
134 #define	MFI_INIT_HOTPLUG			0x00000010
135 #define	MFI_STOP_ADP				0x00000020
136 #define	MFI_RESET_FLAGS		MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
137 
138 /*
139  * MFI frame flags
140  */
141 #define	MFI_FRAME_POST_IN_REPLY_QUEUE		0x0000
142 #define	MFI_FRAME_DONT_POST_IN_REPLY_QUEUE	0x0001
143 #define	MFI_FRAME_SGL32				0x0000
144 #define	MFI_FRAME_SGL64				0x0002
145 #define	MFI_FRAME_SENSE32			0x0000
146 #define	MFI_FRAME_SENSE64			0x0004
147 #define	MFI_FRAME_DIR_NONE			0x0000
148 #define	MFI_FRAME_DIR_WRITE			0x0008
149 #define	MFI_FRAME_DIR_READ			0x0010
150 #define	MFI_FRAME_DIR_BOTH			0x0018
151 
152 /*
153  * Definition for cmd_status
154  */
155 #define	MFI_CMD_STATUS_POLL_MODE		0xFF
156 #define	MFI_CMD_STATUS_SYNC_MODE		0xFF
157 
158 /*
159  * MFI command opcodes
160  */
161 #define	MFI_CMD_OP_INIT				0x00
162 #define	MFI_CMD_OP_LD_READ			0x01
163 #define	MFI_CMD_OP_LD_WRITE			0x02
164 #define	MFI_CMD_OP_LD_SCSI			0x03
165 #define	MFI_CMD_OP_PD_SCSI			0x04
166 #define	MFI_CMD_OP_DCMD				0x05
167 #define	MFI_CMD_OP_ABORT			0x06
168 #define	MFI_CMD_OP_SMP				0x07
169 #define	MFI_CMD_OP_STP				0x08
170 
171 #define	MR_DCMD_CTRL_GET_INFO			0x01010000
172 
173 #define	MR_DCMD_CTRL_CACHE_FLUSH		0x01101000
174 #define	MR_FLUSH_CTRL_CACHE			0x01
175 #define	MR_FLUSH_DISK_CACHE			0x02
176 
177 #define	MR_DCMD_CTRL_SHUTDOWN			0x01050000
178 #define	MR_ENABLE_DRIVE_SPINDOWN		0x01
179 
180 #define	MR_DCMD_CTRL_EVENT_GET_INFO		0x01040100
181 #define	MR_DCMD_CTRL_EVENT_GET			0x01040300
182 #define	MR_DCMD_CTRL_EVENT_WAIT			0x01040500
183 #define	MR_DCMD_LD_GET_PROPERTIES		0x03030000
184 
185 /*
186  * Solaris Specific MAX values
187  */
188 #define	MAX_SGL					24
189 /*
190  * MFI command completion codes
191  */
192 enum MFI_STAT {
193 	MFI_STAT_OK				= 0x00,
194 	MFI_STAT_INVALID_CMD			= 0x01,
195 	MFI_STAT_INVALID_DCMD			= 0x02,
196 	MFI_STAT_INVALID_PARAMETER		= 0x03,
197 	MFI_STAT_INVALID_SEQUENCE_NUMBER	= 0x04,
198 	MFI_STAT_ABORT_NOT_POSSIBLE		= 0x05,
199 	MFI_STAT_APP_HOST_CODE_NOT_FOUND	= 0x06,
200 	MFI_STAT_APP_IN_USE			= 0x07,
201 	MFI_STAT_APP_NOT_INITIALIZED		= 0x08,
202 	MFI_STAT_ARRAY_INDEX_INVALID		= 0x09,
203 	MFI_STAT_ARRAY_ROW_NOT_EMPTY		= 0x0a,
204 	MFI_STAT_CONFIG_RESOURCE_CONFLICT	= 0x0b,
205 	MFI_STAT_DEVICE_NOT_FOUND		= 0x0c,
206 	MFI_STAT_DRIVE_TOO_SMALL		= 0x0d,
207 	MFI_STAT_FLASH_ALLOC_FAIL		= 0x0e,
208 	MFI_STAT_FLASH_BUSY			= 0x0f,
209 	MFI_STAT_FLASH_ERROR			= 0x10,
210 	MFI_STAT_FLASH_IMAGE_BAD		= 0x11,
211 	MFI_STAT_FLASH_IMAGE_INCOMPLETE		= 0x12,
212 	MFI_STAT_FLASH_NOT_OPEN			= 0x13,
213 	MFI_STAT_FLASH_NOT_STARTED		= 0x14,
214 	MFI_STAT_FLUSH_FAILED			= 0x15,
215 	MFI_STAT_HOST_CODE_NOT_FOUNT		= 0x16,
216 	MFI_STAT_LD_CC_IN_PROGRESS		= 0x17,
217 	MFI_STAT_LD_INIT_IN_PROGRESS		= 0x18,
218 	MFI_STAT_LD_LBA_OUT_OF_RANGE		= 0x19,
219 	MFI_STAT_LD_MAX_CONFIGURED		= 0x1a,
220 	MFI_STAT_LD_NOT_OPTIMAL			= 0x1b,
221 	MFI_STAT_LD_RBLD_IN_PROGRESS		= 0x1c,
222 	MFI_STAT_LD_RECON_IN_PROGRESS		= 0x1d,
223 	MFI_STAT_LD_WRONG_RAID_LEVEL		= 0x1e,
224 	MFI_STAT_MAX_SPARES_EXCEEDED		= 0x1f,
225 	MFI_STAT_MEMORY_NOT_AVAILABLE		= 0x20,
226 	MFI_STAT_MFC_HW_ERROR			= 0x21,
227 	MFI_STAT_NO_HW_PRESENT			= 0x22,
228 	MFI_STAT_NOT_FOUND			= 0x23,
229 	MFI_STAT_NOT_IN_ENCL			= 0x24,
230 	MFI_STAT_PD_CLEAR_IN_PROGRESS		= 0x25,
231 	MFI_STAT_PD_TYPE_WRONG			= 0x26,
232 	MFI_STAT_PR_DISABLED			= 0x27,
233 	MFI_STAT_ROW_INDEX_INVALID		= 0x28,
234 	MFI_STAT_SAS_CONFIG_INVALID_ACTION	= 0x29,
235 	MFI_STAT_SAS_CONFIG_INVALID_DATA	= 0x2a,
236 	MFI_STAT_SAS_CONFIG_INVALID_PAGE	= 0x2b,
237 	MFI_STAT_SAS_CONFIG_INVALID_TYPE	= 0x2c,
238 	MFI_STAT_SCSI_DONE_WITH_ERROR		= 0x2d,
239 	MFI_STAT_SCSI_IO_FAILED			= 0x2e,
240 	MFI_STAT_SCSI_RESERVATION_CONFLICT	= 0x2f,
241 	MFI_STAT_SHUTDOWN_FAILED		= 0x30,
242 	MFI_STAT_TIME_NOT_SET			= 0x31,
243 	MFI_STAT_WRONG_STATE			= 0x32,
244 	MFI_STAT_LD_OFFLINE			= 0x33,
245 	MFI_STAT_INVALID_STATUS			= 0xFF
246 };
247 
248 enum MR_EVT_CLASS {
249 	MR_EVT_CLASS_DEBUG		= -2,
250 	MR_EVT_CLASS_PROGRESS		= -1,
251 	MR_EVT_CLASS_INFO		=  0,
252 	MR_EVT_CLASS_WARNING		=  1,
253 	MR_EVT_CLASS_CRITICAL		=  2,
254 	MR_EVT_CLASS_FATAL		=  3,
255 	MR_EVT_CLASS_DEAD		=  4
256 };
257 
258 enum MR_EVT_LOCALE {
259 	MR_EVT_LOCALE_LD		= 0x0001,
260 	MR_EVT_LOCALE_PD		= 0x0002,
261 	MR_EVT_LOCALE_ENCL		= 0x0004,
262 	MR_EVT_LOCALE_BBU		= 0x0008,
263 	MR_EVT_LOCALE_SAS		= 0x0010,
264 	MR_EVT_LOCALE_CTRL		= 0x0020,
265 	MR_EVT_LOCALE_CONFIG		= 0x0040,
266 	MR_EVT_LOCALE_CLUSTER		= 0x0080,
267 	MR_EVT_LOCALE_ALL		= 0xffff
268 };
269 
270 enum MR_EVT_ARGS {
271 	MR_EVT_ARGS_NONE,
272 	MR_EVT_ARGS_CDB_SENSE,
273 	MR_EVT_ARGS_LD,
274 	MR_EVT_ARGS_LD_COUNT,
275 	MR_EVT_ARGS_LD_LBA,
276 	MR_EVT_ARGS_LD_OWNER,
277 	MR_EVT_ARGS_LD_LBA_PD_LBA,
278 	MR_EVT_ARGS_LD_PROG,
279 	MR_EVT_ARGS_LD_STATE,
280 	MR_EVT_ARGS_LD_STRIP,
281 	MR_EVT_ARGS_PD,
282 	MR_EVT_ARGS_PD_ERR,
283 	MR_EVT_ARGS_PD_LBA,
284 	MR_EVT_ARGS_PD_LBA_LD,
285 	MR_EVT_ARGS_PD_PROG,
286 	MR_EVT_ARGS_PD_STATE,
287 	MR_EVT_ARGS_PCI,
288 	MR_EVT_ARGS_RATE,
289 	MR_EVT_ARGS_STR,
290 	MR_EVT_ARGS_TIME,
291 	MR_EVT_ARGS_ECC
292 };
293 
294 #pragma pack(1)
295 
296 /*
297  * SAS controller properties
298  */
299 struct megasas_ctrl_prop {
300 	uint16_t	seq_num;
301 	uint16_t	pred_fail_poll_interval;
302 	uint16_t	intr_throttle_count;
303 	uint16_t	intr_throttle_timeouts;
304 
305 	uint8_t		rebuild_rate;
306 	uint8_t		patrol_read_rate;
307 	uint8_t		bgi_rate;
308 	uint8_t		cc_rate;
309 	uint8_t		recon_rate;
310 
311 	uint8_t		cache_flush_interval;
312 
313 	uint8_t		spinup_drv_count;
314 	uint8_t		spinup_delay;
315 
316 	uint8_t		cluster_enable;
317 	uint8_t		coercion_mode;
318 	uint8_t		disk_write_cache_disable;
319 	uint8_t		alarm_enable;
320 
321 	uint8_t		reserved[44];
322 };
323 
324 /*
325  * SAS controller information
326  */
327 struct megasas_ctrl_info {
328 	/* PCI device information */
329 	struct {
330 		uint16_t	vendor_id;
331 		uint16_t	device_id;
332 		uint16_t	sub_vendor_id;
333 		uint16_t	sub_device_id;
334 		uint8_t	reserved[24];
335 	} pci;
336 
337 	/* Host interface information */
338 	struct {
339 		uint8_t	PCIX		: 1;
340 		uint8_t	PCIE		: 1;
341 		uint8_t	iSCSI		: 1;
342 		uint8_t	SAS_3G		: 1;
343 		uint8_t	reserved_0	: 4;
344 		uint8_t	reserved_1[6];
345 		uint8_t	port_count;
346 		uint64_t	port_addr[8];
347 	} host_interface;
348 
349 	/* Device (backend) interface information */
350 	struct {
351 		uint8_t	SPI		: 1;
352 		uint8_t	SAS_3G		: 1;
353 		uint8_t	SATA_1_5G	: 1;
354 		uint8_t	SATA_3G		: 1;
355 		uint8_t	reserved_0	: 4;
356 		uint8_t	reserved_1[6];
357 		uint8_t	port_count;
358 		uint64_t	port_addr[8];
359 	} device_interface;
360 
361 	/* List of components residing in flash. All str are null terminated */
362 	uint32_t	image_check_word;
363 	uint32_t	image_component_count;
364 
365 	struct {
366 		char	name[8];
367 		char	version[32];
368 		char	build_date[16];
369 		char	built_time[16];
370 	} image_component[8];
371 
372 	/*
373 	 * List of flash components that have been flashed on the card, but
374 	 * are not in use, pending reset of the adapter. This list will be
375 	 * empty if a flash operation has not occurred. All stings are null
376 	 * terminated
377 	 */
378 	uint32_t	pending_image_component_count;
379 
380 	struct {
381 		char	name[8];
382 		char	version[32];
383 		char	build_date[16];
384 		char	build_time[16];
385 	} pending_image_component[8];
386 
387 	uint8_t		max_arms;
388 	uint8_t		max_spans;
389 	uint8_t		max_arrays;
390 	uint8_t		max_lds;
391 
392 	char		product_name[80];
393 	char		serial_no[32];
394 
395 	/*
396 	 * Other physical/controller/operation information. Indicates the
397 	 * presence of the hardware
398 	 */
399 	struct {
400 		uint32_t	bbu		: 1;
401 		uint32_t	alarm		: 1;
402 		uint32_t	nvram		: 1;
403 		uint32_t	uart		: 1;
404 		uint32_t	reserved	: 28;
405 	} hw_present;
406 
407 	uint32_t	current_fw_time;
408 
409 	/* Maximum data transfer sizes */
410 	uint16_t		max_concurrent_cmds;
411 	uint16_t		max_sge_count;
412 	uint32_t		max_request_size;
413 
414 	/* Logical and physical device counts */
415 	uint16_t		ld_present_count;
416 	uint16_t		ld_degraded_count;
417 	uint16_t		ld_offline_count;
418 
419 	uint16_t		pd_present_count;
420 	uint16_t		pd_disk_present_count;
421 	uint16_t		pd_disk_pred_failure_count;
422 	uint16_t		pd_disk_failed_count;
423 
424 	/* Memory size information */
425 	uint16_t		nvram_size;
426 	uint16_t		memory_size;
427 	uint16_t		flash_size;
428 
429 	/* Error counters */
430 	uint16_t		mem_correctable_error_count;
431 	uint16_t		mem_uncorrectable_error_count;
432 
433 	/* Cluster information */
434 	uint8_t		cluster_permitted;
435 	uint8_t		cluster_active;
436 	uint8_t		reserved_1[2];
437 
438 	/* Controller capabilities structures */
439 	struct {
440 		uint32_t	raid_level_0	: 1;
441 		uint32_t	raid_level_1	: 1;
442 		uint32_t	raid_level_5	: 1;
443 		uint32_t	raid_level_1E	: 1;
444 		uint32_t	reserved	: 28;
445 	} raid_levels;
446 
447 	struct {
448 		uint32_t	rbld_rate		: 1;
449 		uint32_t	cc_rate			: 1;
450 		uint32_t	bgi_rate		: 1;
451 		uint32_t	recon_rate		: 1;
452 		uint32_t	patrol_rate		: 1;
453 		uint32_t	alarm_control		: 1;
454 		uint32_t	cluster_supported	: 1;
455 		uint32_t	bbu			: 1;
456 		uint32_t	spanning_allowed	: 1;
457 		uint32_t	dedicated_hotspares	: 1;
458 		uint32_t	revertible_hotspares	: 1;
459 		uint32_t	foreign_config_import	: 1;
460 		uint32_t	self_diagnostic		: 1;
461 		uint32_t	reserved		: 19;
462 	} adapter_operations;
463 
464 	struct {
465 		uint32_t	read_policy	: 1;
466 		uint32_t	write_policy	: 1;
467 		uint32_t	io_policy	: 1;
468 		uint32_t	access_policy	: 1;
469 		uint32_t	reserved	: 28;
470 	} ld_operations;
471 
472 	struct {
473 		uint8_t	min;
474 		uint8_t	max;
475 		uint8_t	reserved[2];
476 	} stripe_size_operations;
477 
478 	struct {
479 		uint32_t	force_online	: 1;
480 		uint32_t	force_offline	: 1;
481 		uint32_t	force_rebuild	: 1;
482 		uint32_t	reserved	: 29;
483 	} pd_operations;
484 
485 	struct {
486 		uint32_t	ctrl_supports_sas	: 1;
487 		uint32_t	ctrl_supports_sata	: 1;
488 		uint32_t	allow_mix_in_encl	: 1;
489 		uint32_t	allow_mix_in_ld		: 1;
490 		uint32_t	allow_sata_in_cluster	: 1;
491 		uint32_t	reserved		: 27;
492 	} pd_mix_support;
493 
494 	/* Include the controller properties (changeable items) */
495 	uint8_t				reserved_2[12];
496 	struct megasas_ctrl_prop	properties;
497 
498 	uint8_t				pad[0x800 - 0x640];
499 };
500 
501 /*
502  * ===============================
503  * MegaRAID SAS driver definitions
504  * ===============================
505  */
506 #define	MEGADRV_MAX_NUM_CMD			1024
507 
508 #define	MEGADRV_MAX_PD_CHANNELS			2
509 #define	MEGADRV_MAX_LD_CHANNELS			2
510 #define	MEGADRV_MAX_CHANNELS			(MEGADRV_MAX_PD_CHANNELS + \
511 						MEGADRV_MAX_LD_CHANNELS)
512 #define	MEGADRV_MAX_DEV_PER_CHANNEL		128
513 #define	MEGADRV_DEFAULT_INIT_ID			-1
514 #define	MEGADRV_MAX_CMD_PER_LUN			1000
515 #define	MEGADRV_MAX_LUN				8
516 #define	MEGADRV_MAX_LD				64
517 
518 #define	MEGADRV_RESET_WAIT_TIME			300
519 #define	MEGADRV_RESET_NOTICE_INTERVAL		5
520 
521 #define	MEGASAS_IOCTL_CMD			0
522 
523 /*
524  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
525  * SGLs based on the size of dma_addr_t
526  */
527 #define	IS_DMA64		(sizeof (dma_addr_t) == 8)
528 
529 #define	IB_MSG_0_OFF			0x10	/* XScale */
530 #define	OB_MSG_0_OFF			0x18	/* XScale */
531 #define	IB_DOORBELL_OFF			0x20	/* XScale & ROC */
532 #define	OB_INTR_STATUS_OFF		0x30	/* XScale & ROC */
533 #define	OB_INTR_MASK_OFF		0x34	/* XScale & ROC */
534 #define	IB_QPORT_OFF			0x40	/* XScale & ROC */
535 #define	OB_DOORBELL_CLEAR_OFF		0xA0	/* ROC */
536 #define	OB_SCRATCH_PAD_0_OFF		0xB0	/* ROC */
537 #define	OB_INTR_MASK			0xFFFFFFFF
538 #define	OB_DOORBELL_CLEAR_MASK		0xFFFFFFFF
539 
540 /*
541  * All MFI register set macros accept megasas_register_set*
542  */
543 #define	WR_IB_MSG_0(v, instance) 	ddi_put32((instance)->regmap_handle, \
544 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
545 
546 #define	RD_OB_MSG_0(instance) 		ddi_get32((instance)->regmap_handle, \
547 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
548 
549 #define	WR_IB_DOORBELL(v, instance)	ddi_put32((instance)->regmap_handle, \
550 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
551 
552 #define	RD_IB_DOORBELL(instance)	ddi_get32((instance)->regmap_handle, \
553 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
554 
555 #define	WR_OB_INTR_STATUS(v, instance) 	ddi_put32((instance)->regmap_handle, \
556 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
557 
558 #define	RD_OB_INTR_STATUS(instance) 	ddi_get32((instance)->regmap_handle, \
559 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
560 
561 #define	WR_OB_INTR_MASK(v, instance) 	ddi_put32((instance)->regmap_handle, \
562 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
563 
564 #define	RD_OB_INTR_MASK(instance) 	ddi_get32((instance)->regmap_handle, \
565 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
566 
567 #define	WR_IB_QPORT(v, instance) 	ddi_put32((instance)->regmap_handle, \
568 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
569 
570 #define	WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
571 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
572 	(v))
573 
574 #define	RD_OB_SCRATCH_PAD_0(instance) 	ddi_get32((instance)->regmap_handle, \
575 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
576 
577 /*
578  * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
579  * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
580  * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
581  */
582 #define	MFI_OB_INTR_STATUS_MASK		0x00000002
583 
584 /*
585  * This MFI_REPLY_1078_MESSAGE_INTR flag is used also
586  * in enable_intr_pcc also. Hence bit 2, i.e. 0x4 has
587  * been set in this flag along with bit 31.
588  */
589 #define	MFI_REPLY_1078_MESSAGE_INTR	0x80000004
590 
591 #define	MFI_POLL_TIMEOUT_SECS		60
592 
593 #define	MFI_ENABLE_INTR(instance)  ddi_put32((instance)->regmap_handle, \
594 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
595 #define	MFI_DISABLE_INTR(instance)					\
596 {									\
597 	uint32_t disable = 1;						\
598 	uint32_t mask =  ddi_get32((instance)->regmap_handle, 		\
599 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
600 	mask &= ~disable;						\
601 	ddi_put32((instance)->regmap_handle, (uint32_t *)		\
602 	    (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask);	\
603 }
604 
605 /* By default, the firmware programs for 8 Kbytes of memory */
606 #define	DEFAULT_MFI_MEM_SZ	8192
607 #define	MINIMUM_MFI_MEM_SZ	4096
608 
609 /* DCMD Message Frame MAILBOX0-11 */
610 #define	DCMD_MBOX_SZ		12
611 
612 
613 struct megasas_register_set {
614 	uint32_t	reserved_0[4];			/* 0000h */
615 
616 	uint32_t	inbound_msg_0;			/* 0010h */
617 	uint32_t	inbound_msg_1;			/* 0014h */
618 	uint32_t	outbound_msg_0;			/* 0018h */
619 	uint32_t	outbound_msg_1;			/* 001Ch */
620 
621 	uint32_t	inbound_doorbell;		/* 0020h */
622 	uint32_t	inbound_intr_status;		/* 0024h */
623 	uint32_t	inbound_intr_mask;		/* 0028h */
624 
625 	uint32_t	outbound_doorbell;		/* 002Ch */
626 	uint32_t	outbound_intr_status;		/* 0030h */
627 	uint32_t	outbound_intr_mask;		/* 0034h */
628 
629 	uint32_t	reserved_1[2];			/* 0038h */
630 
631 	uint32_t	inbound_queue_port;		/* 0040h */
632 	uint32_t	outbound_queue_port;		/* 0044h */
633 
634 	uint32_t 	reserved_2[22];			/* 0048h */
635 
636 	uint32_t 	outbound_doorbell_clear;	/* 00A0h */
637 
638 	uint32_t 	reserved_3[3];			/* 00A4h */
639 
640 	uint32_t 	outbound_scratch_pad;		/* 00B0h */
641 
642 	uint32_t 	reserved_4[3];			/* 00B4h */
643 
644 	uint32_t 	inbound_low_queue_port;		/* 00C0h */
645 
646 	uint32_t 	inbound_high_queue_port;	/* 00C4h */
647 
648 	uint32_t 	reserved_5;			/* 00C8h */
649 	uint32_t 	index_registers[820];		/* 00CCh */
650 };
651 
652 struct megasas_sge32 {
653 	uint32_t	phys_addr;
654 	uint32_t	length;
655 };
656 
657 struct megasas_sge64 {
658 	uint64_t	phys_addr;
659 	uint32_t	length;
660 };
661 
662 union megasas_sgl {
663 	struct megasas_sge32	sge32[1];
664 	struct megasas_sge64	sge64[1];
665 };
666 
667 struct megasas_header {
668 	uint8_t		cmd;				/* 00h */
669 	uint8_t		sense_len;			/* 01h */
670 	uint8_t		cmd_status;			/* 02h */
671 	uint8_t		scsi_status;			/* 03h */
672 
673 	uint8_t		target_id;			/* 04h */
674 	uint8_t		lun;				/* 05h */
675 	uint8_t		cdb_len;			/* 06h */
676 	uint8_t		sge_count;			/* 07h */
677 
678 	uint32_t	context;			/* 08h */
679 	uint32_t	pad_0;				/* 0Ch */
680 
681 	uint16_t	flags;				/* 10h */
682 	uint16_t	timeout;			/* 12h */
683 	uint32_t	data_xferlen;			/* 14h */
684 };
685 
686 union megasas_sgl_frame {
687 	struct megasas_sge32	sge32[8];
688 	struct megasas_sge64	sge64[5];
689 };
690 
691 struct megasas_init_frame {
692 	uint8_t		cmd;				/* 00h */
693 	uint8_t		reserved_0;			/* 01h */
694 	uint8_t		cmd_status;			/* 02h */
695 
696 	uint8_t		reserved_1;			/* 03h */
697 	uint32_t	reserved_2;			/* 04h */
698 
699 	uint32_t	context;			/* 08h */
700 	uint32_t	pad_0;				/* 0Ch */
701 
702 	uint16_t	flags;				/* 10h */
703 	uint16_t	reserved_3;			/* 12h */
704 	uint32_t	data_xfer_len;			/* 14h */
705 
706 	uint32_t	queue_info_new_phys_addr_lo;	/* 18h */
707 	uint32_t	queue_info_new_phys_addr_hi;	/* 1Ch */
708 	uint32_t	queue_info_old_phys_addr_lo;	/* 20h */
709 	uint32_t	queue_info_old_phys_addr_hi;	/* 24h */
710 
711 	uint32_t	reserved_4[6];			/* 28h */
712 };
713 
714 struct megasas_init_queue_info {
715 	uint32_t		init_flags;			/* 00h */
716 	uint32_t		reply_queue_entries;		/* 04h */
717 
718 	uint32_t		reply_queue_start_phys_addr_lo;	/* 08h */
719 	uint32_t		reply_queue_start_phys_addr_hi;	/* 0Ch */
720 	uint32_t		producer_index_phys_addr_lo;	/* 10h */
721 	uint32_t		producer_index_phys_addr_hi;	/* 14h */
722 	uint32_t		consumer_index_phys_addr_lo;	/* 18h */
723 	uint32_t		consumer_index_phys_addr_hi;	/* 1Ch */
724 };
725 
726 struct megasas_io_frame {
727 	uint8_t			cmd;			/* 00h */
728 	uint8_t			sense_len;		/* 01h */
729 	uint8_t			cmd_status;		/* 02h */
730 	uint8_t			scsi_status;		/* 03h */
731 
732 	uint8_t			target_id;		/* 04h */
733 	uint8_t			access_byte;		/* 05h */
734 	uint8_t			reserved_0;		/* 06h */
735 	uint8_t			sge_count;		/* 07h */
736 
737 	uint32_t		context;		/* 08h */
738 	uint32_t		pad_0;			/* 0Ch */
739 
740 	uint16_t		flags;			/* 10h */
741 	uint16_t		timeout;		/* 12h */
742 	uint32_t		lba_count;		/* 14h */
743 
744 	uint32_t		sense_buf_phys_addr_lo;	/* 18h */
745 	uint32_t		sense_buf_phys_addr_hi;	/* 1Ch */
746 
747 	uint32_t		start_lba_lo;		/* 20h */
748 	uint32_t		start_lba_hi;		/* 24h */
749 
750 	union megasas_sgl	sgl;			/* 28h */
751 };
752 
753 struct megasas_pthru_frame {
754 	uint8_t			cmd;			/* 00h */
755 	uint8_t			sense_len;		/* 01h */
756 	uint8_t			cmd_status;		/* 02h */
757 	uint8_t			scsi_status;		/* 03h */
758 
759 	uint8_t			target_id;		/* 04h */
760 	uint8_t			lun;			/* 05h */
761 	uint8_t			cdb_len;		/* 06h */
762 	uint8_t			sge_count;		/* 07h */
763 
764 	uint32_t		context;		/* 08h */
765 	uint32_t		pad_0;			/* 0Ch */
766 
767 	uint16_t		flags;			/* 10h */
768 	uint16_t		timeout;		/* 12h */
769 	uint32_t		data_xfer_len;		/* 14h */
770 
771 	uint32_t		sense_buf_phys_addr_lo;	/* 18h */
772 	uint32_t		sense_buf_phys_addr_hi;	/* 1Ch */
773 
774 	uint8_t			cdb[16];		/* 20h */
775 	union megasas_sgl	sgl;			/* 30h */
776 };
777 
778 struct megasas_dcmd_frame {
779 	uint8_t			cmd;			/* 00h */
780 	uint8_t			reserved_0;		/* 01h */
781 	uint8_t			cmd_status;		/* 02h */
782 	uint8_t			reserved_1[4];		/* 03h */
783 	uint8_t			sge_count;		/* 07h */
784 
785 	uint32_t		context;		/* 08h */
786 	uint32_t		pad_0;			/* 0Ch */
787 
788 	uint16_t		flags;			/* 10h */
789 	uint16_t		timeout;		/* 12h */
790 
791 	uint32_t		data_xfer_len;		/* 14h */
792 	uint32_t		opcode;			/* 18h */
793 
794 	/* uint8_t		mbox[DCMD_MBOX_SZ]; */	/* 1Ch */
795 	union {						/* 1Ch */
796 		uint8_t b[DCMD_MBOX_SZ];
797 		uint16_t s[6];
798 		uint32_t w[3];
799 	} mbox;
800 
801 	union megasas_sgl	sgl;			/* 28h */
802 };
803 
804 struct megasas_abort_frame {
805 	uint8_t		cmd;				/* 00h */
806 	uint8_t		reserved_0;			/* 01h */
807 	uint8_t		cmd_status;			/* 02h */
808 
809 	uint8_t		reserved_1;			/* 03h */
810 	uint32_t	reserved_2;			/* 04h */
811 
812 	uint32_t	context;			/* 08h */
813 	uint32_t	pad_0;				/* 0Ch */
814 
815 	uint16_t	flags;				/* 10h */
816 	uint16_t	reserved_3;			/* 12h */
817 	uint32_t	reserved_4;			/* 14h */
818 
819 	uint32_t	abort_context;			/* 18h */
820 	uint32_t	pad_1;				/* 1Ch */
821 
822 	uint32_t	abort_mfi_phys_addr_lo;		/* 20h */
823 	uint32_t	abort_mfi_phys_addr_hi;		/* 24h */
824 
825 	uint32_t	reserved_5[6];			/* 28h */
826 };
827 
828 struct megasas_smp_frame {
829 	uint8_t		cmd;				/* 00h */
830 	uint8_t		reserved_1;			/* 01h */
831 	uint8_t		cmd_status;			/* 02h */
832 	uint8_t		connection_status;		/* 03h */
833 
834 	uint8_t		reserved_2[3];			/* 04h */
835 	uint8_t		sge_count;			/* 07h */
836 
837 	uint32_t	context;			/* 08h */
838 	uint32_t	pad_0;				/* 0Ch */
839 
840 	uint16_t	flags;				/* 10h */
841 	uint16_t	timeout;			/* 12h */
842 
843 	uint32_t	data_xfer_len;			/* 14h */
844 
845 	uint64_t	sas_addr;			/* 20h */
846 
847 	union megasas_sgl	sgl[2];			/* 28h */
848 };
849 
850 struct megasas_stp_frame {
851 	uint8_t		cmd;				/* 00h */
852 	uint8_t		reserved_1;			/* 01h */
853 	uint8_t		cmd_status;			/* 02h */
854 	uint8_t		connection_status;		/* 03h */
855 
856 	uint8_t		target_id;			/* 04h */
857 	uint8_t		reserved_2[2];			/* 04h */
858 	uint8_t		sge_count;			/* 07h */
859 
860 	uint32_t	context;			/* 08h */
861 	uint32_t	pad_0;				/* 0Ch */
862 
863 	uint16_t	flags;				/* 10h */
864 	uint16_t	timeout;			/* 12h */
865 
866 	uint32_t	data_xfer_len;			/* 14h */
867 
868 	uint16_t	fis[10];			/* 28h */
869 	uint32_t	stp_flags;			/* 3C */
870 	union megasas_sgl	sgl;			/* 40 */
871 };
872 
873 union megasas_frame {
874 	struct megasas_header		hdr;
875 	struct megasas_init_frame	init;
876 	struct megasas_io_frame		io;
877 	struct megasas_pthru_frame	pthru;
878 	struct megasas_dcmd_frame	dcmd;
879 	struct megasas_abort_frame	abort;
880 	struct megasas_smp_frame	smp;
881 	struct megasas_stp_frame	stp;
882 
883 	uint8_t		raw_bytes[64];
884 };
885 
886 union megasas_evt_class_locale {
887 	struct {
888 		uint16_t	locale;
889 		uint8_t		reserved;
890 		int8_t		class;
891 	} members;
892 
893 	uint32_t	word;
894 };
895 
896 struct megasas_evt_log_info {
897 	uint32_t	newest_seq_num;
898 	uint32_t	oldest_seq_num;
899 	uint32_t	clear_seq_num;
900 	uint32_t	shutdown_seq_num;
901 	uint32_t	boot_seq_num;
902 };
903 
904 struct megasas_progress {
905 	uint16_t	progress;
906 	uint16_t	elapsed_seconds;
907 };
908 
909 struct megasas_evtarg_ld {
910 	uint16_t	target_id;
911 	uint8_t		ld_index;
912 	uint8_t		reserved;
913 };
914 
915 struct megasas_evtarg_pd {
916 	uint16_t	device_id;
917 	uint8_t		encl_index;
918 	uint8_t		slot_number;
919 };
920 
921 struct megasas_evt_detail {
922 	uint32_t	seq_num;
923 	uint32_t	time_stamp;
924 	uint32_t	code;
925 	union megasas_evt_class_locale	cl;
926 	uint8_t		arg_type;
927 	uint8_t		reserved1[15];
928 
929 	union {
930 		struct {
931 			struct megasas_evtarg_pd	pd;
932 			uint8_t				cdb_length;
933 			uint8_t				sense_length;
934 			uint8_t				reserved[2];
935 			uint8_t				cdb[16];
936 			uint8_t				sense[64];
937 		} cdbSense;
938 
939 		struct megasas_evtarg_ld		ld;
940 
941 		struct {
942 			struct megasas_evtarg_ld	ld;
943 			uint64_t			count;
944 		} ld_count;
945 
946 		struct {
947 			uint64_t			lba;
948 			struct megasas_evtarg_ld	ld;
949 		} ld_lba;
950 
951 		struct {
952 			struct megasas_evtarg_ld	ld;
953 			uint32_t			prevOwner;
954 			uint32_t			newOwner;
955 		} ld_owner;
956 
957 		struct {
958 			uint64_t			ld_lba;
959 			uint64_t			pd_lba;
960 			struct megasas_evtarg_ld	ld;
961 			struct megasas_evtarg_pd	pd;
962 		} ld_lba_pd_lba;
963 
964 		struct {
965 			struct megasas_evtarg_ld	ld;
966 			struct megasas_progress		prog;
967 		} ld_prog;
968 
969 		struct {
970 			struct megasas_evtarg_ld	ld;
971 			uint32_t			prev_state;
972 			uint32_t			new_state;
973 		} ld_state;
974 
975 		struct {
976 			uint64_t			strip;
977 			struct megasas_evtarg_ld	ld;
978 		} ld_strip;
979 
980 		struct megasas_evtarg_pd	pd;
981 
982 		struct {
983 			struct megasas_evtarg_pd	pd;
984 			uint32_t			err;
985 		} pd_err;
986 
987 		struct {
988 			uint64_t			lba;
989 			struct megasas_evtarg_pd	pd;
990 		} pd_lba;
991 
992 		struct {
993 			uint64_t			lba;
994 			struct megasas_evtarg_pd	pd;
995 			struct megasas_evtarg_ld	ld;
996 		} pd_lba_ld;
997 
998 		struct {
999 			struct megasas_evtarg_pd	pd;
1000 			struct megasas_progress		prog;
1001 		} pd_prog;
1002 
1003 		struct {
1004 			struct megasas_evtarg_pd	pd;
1005 			uint32_t			prevState;
1006 			uint32_t			newState;
1007 		} pd_state;
1008 
1009 		struct {
1010 			uint16_t	vendorId;
1011 			uint16_t	deviceId;
1012 			uint16_t	subVendorId;
1013 			uint16_t	subDeviceId;
1014 		} pci;
1015 
1016 		uint32_t	rate;
1017 		char		str[96];
1018 
1019 		struct {
1020 			uint32_t	rtc;
1021 			uint32_t	elapsedSeconds;
1022 		} time;
1023 
1024 		struct {
1025 			uint32_t	ecar;
1026 			uint32_t	elog;
1027 			char		str[64];
1028 		} ecc;
1029 
1030 		uint8_t		b[96];
1031 		uint16_t	s[48];
1032 		uint32_t	w[24];
1033 		uint64_t	d[12];
1034 	} args;
1035 
1036 	char	description[128];
1037 
1038 };
1039 
1040 /* only 63 are usable by the application */
1041 #define	MAX_LOGICAL_DRIVES			64
1042 /* only 255 physical devices may be used */
1043 #define	MAX_PHYSICAL_DEVICES			256
1044 #define	MAX_PD_PER_ENCLOSURE			64
1045 /* maximum disks per array */
1046 #define	MAX_ROW_SIZE				32
1047 /* maximum spans per logical drive */
1048 #define	MAX_SPAN_DEPTH				8
1049 /* maximum number of arrays a hot spare may be dedicated to */
1050 #define	MAX_ARRAYS_DEDICATED			16
1051 /* maximum number of arrays which may exist */
1052 #define	MAX_ARRAYS				128
1053 /* maximum number of foreign configs that may ha managed at once */
1054 #define	MAX_FOREIGN_CONFIGS			8
1055 /* maximum spares (global and dedicated combined) */
1056 #define	MAX_SPARES_FOR_THE_CONTROLLER		MAX_PHYSICAL_DEVICES
1057 /* maximum possible Target IDs (i.e. 0 to 63) */
1058 #define	MAX_TARGET_ID				63
1059 /* maximum number of supported enclosures */
1060 #define	MAX_ENCLOSURES				32
1061 /* maximum number of PHYs per controller */
1062 #define	MAX_PHYS_PER_CONTROLLER			16
1063 /* maximum number of LDs per array (due to DDF limitations) */
1064 #define	MAX_LDS_PER_ARRAY			16
1065 
1066 /*
1067  * -----------------------------------------------------------------------------
1068  * -----------------------------------------------------------------------------
1069  *
1070  * Logical Drive commands
1071  *
1072  * -----------------------------------------------------------------------------
1073  * -----------------------------------------------------------------------------
1074  */
1075 #define	MR_DCMD_LD	0x03000000,	/* Logical Device (LD) opcodes */
1076 
1077 /*
1078  * Input:	dcmd.opcode	- MR_DCMD_LD_GET_LIST
1079  *		dcmd.mbox	- reserved
1080  *		dcmd.sge IN	- ptr to returned MR_LD_LIST structure
1081  * Desc:	Return the logical drive list structure
1082  * Status:	No error
1083  */
1084 
1085 /*
1086  * defines the logical drive reference structure
1087  */
1088 typedef	union _MR_LD_REF {	/* LD reference structure */
1089 	struct {
1090 		uint8_t	targetId; /* LD target id (0 to MAX_TARGET_ID) */
1091 		uint8_t	reserved; /* reserved to make in line with MR_PD_REF */
1092 		uint16_t seqNum;  /* Sequence Number */
1093 	} ld_ref;
1094 	uint32_t ref;		/* shorthand reference to full 32-bits */
1095 } MR_LD_REF;			/* 4 bytes */
1096 
1097 /*
1098  * defines the logical drive list structure
1099  */
1100 typedef struct _MR_LD_LIST {
1101 	uint32_t	ldCount;	/* number of LDs */
1102 	uint32_t	reserved;	/* pad to 8-byte boundary */
1103 	struct {
1104 		MR_LD_REF ref;		/* LD reference */
1105 		uint8_t	state;		/* current LD state (MR_LD_STATE) */
1106 		uint8_t	reserved[3];	/* pad to 8-byte boundary */
1107 		uint64_t size;		/* LD size */
1108 	} ldList[MAX_LOGICAL_DRIVES];
1109 } MR_LD_LIST;
1110 /* 4 + 4 + (MAX_LOGICAL_DRIVES * 16), for 40LD it is = 648 bytes */
1111 
1112 #pragma pack()
1113 
1114 #define	DMA_OBJ_ALLOCATED	1
1115 #define	DMA_OBJ_REALLOCATED	2
1116 #define	DMA_OBJ_FREED		3
1117 
1118 /*
1119  * dma_obj_t	- Our DMA object
1120  * @param buffer	: kernel virtual address
1121  * @param size		: size of the data to be allocated
1122  * @param acc_handle	: access handle
1123  * @param dma_handle	: dma handle
1124  * @param dma_cookie	: scatter-gather list
1125  * @param dma_attr	: dma attributes for this buffer
1126  *
1127  * Our DMA object. The caller must initialize the size and dma attributes
1128  * (dma_attr) fields before allocating the resources.
1129  */
1130 typedef struct {
1131 	caddr_t			buffer;
1132 	uint32_t		size;
1133 	ddi_acc_handle_t	acc_handle;
1134 	ddi_dma_handle_t	dma_handle;
1135 	ddi_dma_cookie_t	dma_cookie[MEGASAS_MAX_SGE_CNT];
1136 	ddi_dma_attr_t		dma_attr;
1137 	uint8_t			status;
1138 } dma_obj_t;
1139 
1140 struct megasas_instance {
1141 	uint32_t	*producer;
1142 	uint32_t	*consumer;
1143 
1144 	uint32_t	*reply_queue;
1145 	dma_obj_t	mfi_internal_dma_obj;
1146 
1147 	uint8_t		init_id;
1148 	uint8_t		reserved[3];
1149 
1150 	uint16_t	max_num_sge;
1151 	uint16_t	max_fw_cmds;
1152 	uint32_t	max_sectors_per_req;
1153 
1154 	struct megasas_cmd	**cmd_list;
1155 
1156 	mlist_t		cmd_pool_list;
1157 	kmutex_t	cmd_pool_mtx;
1158 
1159 	mlist_t		cmd_pend_list;
1160 	kmutex_t	cmd_pend_mtx;
1161 
1162 	dma_obj_t	mfi_evt_detail_obj;
1163 	struct megasas_cmd	*aen_cmd;
1164 
1165 	uint32_t	aen_seq_num;
1166 	uint32_t	aen_class_locale_word;
1167 
1168 	scsi_hba_tran_t		*tran;
1169 
1170 	kcondvar_t	int_cmd_cv;
1171 	kmutex_t	int_cmd_mtx;
1172 
1173 	kcondvar_t	aen_cmd_cv;
1174 	kmutex_t	aen_cmd_mtx;
1175 
1176 	kcondvar_t	abort_cmd_cv;
1177 	kmutex_t	abort_cmd_mtx;
1178 
1179 	dev_info_t		*dip;
1180 	ddi_acc_handle_t	pci_handle;
1181 
1182 	timeout_id_t	timeout_id;
1183 	uint32_t	unique_id;
1184 	uint16_t	fw_outstanding;
1185 	caddr_t		regmap;
1186 	ddi_acc_handle_t	regmap_handle;
1187 	uint8_t		isr_level;
1188 	ddi_iblock_cookie_t	iblock_cookie;
1189 	ddi_iblock_cookie_t	soft_iblock_cookie;
1190 	ddi_softintr_t		soft_intr_id;
1191 	uint8_t		softint_running;
1192 	kmutex_t	completed_pool_mtx;
1193 	mlist_t		completed_pool_list;
1194 
1195 	caddr_t		internal_buf;
1196 	uint32_t	internal_buf_dmac_add;
1197 	uint32_t	internal_buf_size;
1198 
1199 	uint16_t	vendor_id;
1200 	uint16_t	device_id;
1201 	uint16_t	subsysvid;
1202 	uint16_t	subsysid;
1203 	int		baseaddress;
1204 	char		iocnode[16];
1205 
1206 	int		fm_capabilities;
1207 
1208 	struct megasas_func_ptr	*func_ptr;
1209 };
1210 
1211 struct megasas_func_ptr {
1212 	int (*read_fw_status_reg)(struct megasas_instance *);
1213 	void (*issue_cmd)(struct megasas_cmd *, struct megasas_instance *);
1214 	int (*issue_cmd_in_sync_mode)(struct megasas_instance *,
1215 	    struct megasas_cmd *);
1216 	int (*issue_cmd_in_poll_mode)(struct megasas_instance *,
1217 	    struct megasas_cmd *);
1218 	void (*enable_intr)(struct megasas_instance *);
1219 	void (*disable_intr)(struct megasas_instance *);
1220 	int (*intr_ack)(struct megasas_instance *);
1221 };
1222 
1223 /*
1224  * ### Helper routines ###
1225  */
1226 
1227 /*
1228  * con_log() - console log routine
1229  * @param level		: indicates the severity of the message.
1230  * @fparam mt		: format string
1231  *
1232  * con_log displays the error messages on the console based on the current
1233  * debug level. Also it attaches the appropriate kernel severity level with
1234  * the message.
1235  *
1236  *
1237  * console messages debug levels
1238  */
1239 #define	CL_ANN		0	/* print unconditionally, announcements */
1240 #define	CL_ANN1		1	/* No o/p  */
1241 #define	CL_DLEVEL1	2	/* debug level 1, informative */
1242 #define	CL_DLEVEL2	3	/* debug level 2, verbose */
1243 #define	CL_DLEVEL3	4	/* debug level 3, very verbose */
1244 
1245 #ifdef __SUNPRO_C
1246 #define	__func__ ""
1247 #endif
1248 
1249 #if DEBUG
1250 #define	con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
1251 #else
1252 #define	con_log(level, fmt)
1253 #endif /* DEBUG */
1254 
1255 /* byte-ordering macros */
1256 #ifdef __sparc
1257 #define	host_to_le16(s) ((s) & 0xFF) << 8 | ((s) & 0xFF00) >> 8
1258 #else
1259 #define	host_to_le16(s) (s)
1260 #endif
1261 
1262 #ifdef __sparc
1263 #define	host_to_le32(l) (((l) & 0xFF) << 24 | ((l) & 0xFF00) << 8 | \
1264 		((l) & 0xFF0000) >> 8 | ((l) & 0xFF000000) >> 24)
1265 #else
1266 #define	host_to_le32(l) (l)
1267 #endif
1268 
1269 #ifdef __sparc
1270 #define	host_to_le64(ull) ((host_to_le32(((ull) & 0xFFFFFFFF)) << 32) | \
1271 		(host_to_le32((((ull) & 0xFFFFFFFF00000000) >> 32))))
1272 #else
1273 #define	host_to_le64(ull) (ull)
1274 #endif
1275 
1276 /*
1277  * ### SCSA definitions ###
1278  */
1279 #define	PKT2TGT(pkt)	((pkt)->pkt_address.a_target)
1280 #define	PKT2LUN(pkt)	((pkt)->pkt_address.a_lun)
1281 #define	PKT2TRAN(pkt)	((pkt)->pkt_adress.a_hba_tran)
1282 #define	ADDR2TRAN(ap)	((ap)->a_hba_tran)
1283 
1284 #define	TRAN2MEGA(tran)	(struct megasas_instance *)(tran)->tran_hba_private)
1285 #define	ADDR2MEGA(ap)	(TRAN2MEGA(ADDR2TRAN(ap))
1286 
1287 #define	PKT2CMD(pkt)	((struct scsa_cmd *)(pkt)->pkt_ha_private)
1288 #define	CMD2PKT(sp)	((sp)->cmd_pkt)
1289 #define	PKT2REQ(pkt)	(&(PKT2CMD(pkt)->request))
1290 
1291 #define	CMD2ADDR(cmd)	(&CMD2PKT(cmd)->pkt_address)
1292 #define	CMD2TRAN(cmd)	(CMD2PKT(cmd)->pkt_address.a_hba_tran)
1293 #define	CMD2MEGA(cmd)	(TRAN2MEGA(CMD2TRAN(cmd)))
1294 
1295 #define	CFLAG_DMAVALID		0x0001	/* requires a dma operation */
1296 #define	CFLAG_DMASEND		0x0002	/* Transfer from the device */
1297 #define	CFLAG_CONSISTENT	0x0040	/* consistent data transfer */
1298 
1299 /*
1300  * ### Data structures for ioctl inteface and internal commands ###
1301  */
1302 
1303 /*
1304  * Data direction flags
1305  */
1306 #define	UIOC_RD		0x00001
1307 #define	UIOC_WR		0x00002
1308 
1309 #define	SCP2HOST(scp)		(scp)->device->host	/* to host */
1310 #define	SCP2HOSTDATA(scp)	SCP2HOST(scp)->hostdata	/* to soft state */
1311 #define	SCP2CHANNEL(scp)	(scp)->device->channel	/* to channel */
1312 #define	SCP2TARGET(scp)		(scp)->device->id	/* to target */
1313 #define	SCP2LUN(scp)		(scp)->device->lun	/* to LUN */
1314 
1315 #define	SCSIHOST2ADAP(host)	(((caddr_t *)(host->hostdata))[0])
1316 #define	SCP2ADAPTER(scp)				\
1317 	(struct megasas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
1318 
1319 #define	MEGADRV_IS_LOGICAL_SCSA(instance, acmd)		\
1320 	(acmd->device_id < MEGADRV_MAX_LD) ? 1 : 0
1321 #define	MEGADRV_IS_LOGICAL(ap)				\
1322 	(ap->a_target < MEGADRV_MAX_LD) ? 1 : 0
1323 #define	MAP_DEVICE_ID(instance, ap)			\
1324 	(ap->a_target % MEGADRV_MAX_LD)
1325 /*
1326  * #define MAP_DEVICE_ID(instance,ap)			\
1327  *       (ap->a_target)
1328  */
1329 
1330 #define	HIGH_LEVEL_INTR			1
1331 #define	NORMAL_LEVEL_INTR		0
1332 
1333 /*
1334  * scsa_cmd  - Per-command mega private data
1335  * @param cmd_dmahandle		:  dma handle
1336  * @param cmd_dmacookies	: current dma cookies
1337  * @param cmd_pkt		:  scsi_pkt reference
1338  * @param cmd_dmacount		:  dma count
1339  * @param cmd_cookie		:  next cookie
1340  * @param cmd_ncookies		:  cookies per window
1341  * @param cmd_cookiecnt		:  cookies per sub-win
1342  * @param cmd_nwin		:  number of dma windows
1343  * @param cmd_curwin		:  current dma window
1344  * @param cmd_dma_offset	:  current window offset
1345  * @param cmd_dma_len		:  current window length
1346  * @param cmd_flags		:  private flags
1347  * @param cmd_cdblen		:  length of cdb
1348  * @param cmd_scblen		:  length of scb
1349  * @param cmd_buf		:  command buffer
1350  * @param channel		:  channel for scsi sub-system
1351  * @param target		:  target for scsi sub-system
1352  * @param lun			:  LUN for scsi sub-system
1353  *
1354  * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
1355  * - Pointed to by pkt_ha_private field in scsi_pkt
1356  */
1357 struct scsa_cmd {
1358 	ddi_dma_handle_t	cmd_dmahandle;
1359 	ddi_dma_cookie_t	cmd_dmacookies[MEGASAS_MAX_SGE_CNT];
1360 	struct scsi_pkt		*cmd_pkt;
1361 	ulong_t			cmd_dmacount;
1362 	uint_t			cmd_cookie;
1363 	uint_t			cmd_ncookies;
1364 	uint_t			cmd_cookiecnt;
1365 	uint_t			cmd_nwin;
1366 	uint_t			cmd_curwin;
1367 	off_t			cmd_dma_offset;
1368 	ulong_t			cmd_dma_len;
1369 	ulong_t			cmd_flags;
1370 	uint_t			cmd_cdblen;
1371 	uint_t			cmd_scblen;
1372 	struct buf		*cmd_buf;
1373 	ushort_t		device_id;
1374 	uchar_t			islogical;
1375 	uchar_t			lun;
1376 };
1377 
1378 
1379 struct megasas_cmd {
1380 	union megasas_frame	*frame;
1381 	uint32_t		frame_phys_addr;
1382 	uint8_t			*sense;
1383 	uint32_t		sense_phys_addr;
1384 	dma_obj_t		frame_dma_obj;
1385 	uint8_t			frame_dma_obj_status;
1386 
1387 	uint32_t		index;
1388 	uint8_t			sync_cmd;
1389 	uint8_t			cmd_status;
1390 	uint16_t		abort_aen;
1391 	mlist_t			list;
1392 	uint32_t		frame_count;
1393 	struct scsa_cmd		*cmd;
1394 	struct scsi_pkt		*pkt;
1395 };
1396 
1397 #define	MAX_MGMT_ADAPTERS			1024
1398 #define	IOC_SIGNATURE				"MEGA-SAS"
1399 
1400 #define	IOC_CMD_FIRMWARE			0x0
1401 #define	MR_DRIVER_IOCTL_COMMON			0xF0010000
1402 #define	MR_DRIVER_IOCTL_DRIVER_VERSION		0xF0010100
1403 #define	MR_DRIVER_IOCTL_PCI_INFORMATION		0xF0010200
1404 #define	MR_DRIVER_IOCTL_MEGARAID_STATISTICS	0xF0010300
1405 
1406 
1407 #define	MR_MAX_SENSE_LENGTH			32
1408 
1409 struct megasas_mgmt_info {
1410 
1411 	uint16_t			count;
1412 	struct megasas_instance		*instance[MAX_MGMT_ADAPTERS];
1413 	uint16_t			map[MAX_MGMT_ADAPTERS];
1414 	int				max_index;
1415 };
1416 
1417 #pragma pack(1)
1418 
1419 struct megasas_drv_ver {
1420 	uint8_t	signature[12];
1421 	uint8_t	os_name[16];
1422 	uint8_t	os_ver[12];
1423 	uint8_t	drv_name[20];
1424 	uint8_t	drv_ver[32];
1425 	uint8_t	drv_rel_date[20];
1426 };
1427 
1428 #define	PCI_TYPE0_ADDRESSES		6
1429 #define	PCI_TYPE1_ADDRESSES		2
1430 #define	PCI_TYPE2_ADDRESSES		5
1431 
1432 struct megasas_pci_common_header {
1433 	uint16_t	vendorID;		/* (ro) */
1434 	uint16_t	deviceID;		/* (ro) */
1435 	uint16_t	command;		/* Device control */
1436 	uint16_t	status;
1437 	uint8_t		revisionID;		/* (ro) */
1438 	uint8_t		progIf;			/* (ro) */
1439 	uint8_t		subClass;		/* (ro) */
1440 	uint8_t		baseClass;		/* (ro) */
1441 	uint8_t		cacheLineSize;		/* (ro+) */
1442 	uint8_t		latencyTimer;		/* (ro+) */
1443 	uint8_t		headerType;		/* (ro) */
1444 	uint8_t		bist;			/* Built in self test */
1445 
1446 	union {
1447 	    struct {
1448 		uint32_t	baseAddresses[PCI_TYPE0_ADDRESSES];
1449 		uint32_t	cis;
1450 		uint16_t	subVendorID;
1451 		uint16_t	subSystemID;
1452 		uint32_t	romBaseAddress;
1453 		uint8_t		capabilitiesPtr;
1454 		uint8_t		reserved1[3];
1455 		uint32_t	reserved2;
1456 		uint8_t		interruptLine;
1457 		uint8_t		interruptPin;	/* (ro) */
1458 		uint8_t		minimumGrant;	/* (ro) */
1459 		uint8_t		maximumLatency;	/* (ro) */
1460 	    } type_0;
1461 
1462 	    struct {
1463 		uint32_t	baseAddresses[PCI_TYPE1_ADDRESSES];
1464 		uint8_t		primaryBus;
1465 		uint8_t		secondaryBus;
1466 		uint8_t		subordinateBus;
1467 		uint8_t		secondaryLatency;
1468 		uint8_t		ioBase;
1469 		uint8_t		ioLimit;
1470 		uint16_t	secondaryStatus;
1471 		uint16_t	memoryBase;
1472 		uint16_t	memoryLimit;
1473 		uint16_t	prefetchBase;
1474 		uint16_t	prefetchLimit;
1475 		uint32_t	prefetchBaseUpper32;
1476 		uint32_t	prefetchLimitUpper32;
1477 		uint16_t	ioBaseUpper16;
1478 		uint16_t	ioLimitUpper16;
1479 		uint8_t		capabilitiesPtr;
1480 		uint8_t		reserved1[3];
1481 		uint32_t	romBaseAddress;
1482 		uint8_t		interruptLine;
1483 		uint8_t		interruptPin;
1484 		uint16_t	bridgeControl;
1485 	    } type_1;
1486 
1487 	    struct {
1488 		uint32_t	socketRegistersBaseAddress;
1489 		uint8_t		capabilitiesPtr;
1490 		uint8_t		reserved;
1491 		uint16_t	secondaryStatus;
1492 		uint8_t		primaryBus;
1493 		uint8_t		secondaryBus;
1494 		uint8_t		subordinateBus;
1495 		uint8_t		secondaryLatency;
1496 		struct {
1497 			uint32_t	base;
1498 			uint32_t	limit;
1499 		} range[PCI_TYPE2_ADDRESSES-1];
1500 		uint8_t		interruptLine;
1501 		uint8_t		interruptPin;
1502 		uint16_t	bridgeControl;
1503 	    } type_2;
1504 	} header;
1505 };
1506 
1507 struct megasas_pci_link_capability {
1508 	union {
1509 	    struct {
1510 		uint32_t linkSpeed		:4;
1511 		uint32_t linkWidth		:6;
1512 		uint32_t aspmSupport		:2;
1513 		uint32_t losExitLatency		:3;
1514 		uint32_t l1ExitLatency		:3;
1515 		uint32_t rsvdp			:6;
1516 		uint32_t portNumber		:8;
1517 	    } bits;
1518 
1519 	    uint32_t asUlong;
1520 	} cap;
1521 
1522 };
1523 
1524 struct megasas_pci_link_status_capability {
1525 	union {
1526 	    struct {
1527 		uint16_t linkSpeed		:4;
1528 		uint16_t negotiatedLinkWidth	:6;
1529 		uint16_t linkTrainingError	:1;
1530 		uint16_t linkTraning		:1;
1531 		uint16_t slotClockConfig	:1;
1532 		uint16_t rsvdZ			:3;
1533 	    } bits;
1534 
1535 	    uint16_t asUshort;
1536 	} stat_cap;
1537 
1538 	uint16_t reserved;
1539 
1540 };
1541 
1542 struct megasas_pci_capabilities {
1543 	struct megasas_pci_link_capability	linkCapability;
1544 	struct megasas_pci_link_status_capability linkStatusCapability;
1545 };
1546 
1547 struct megasas_pci_information
1548 {
1549 	uint32_t		busNumber;
1550 	uint8_t			deviceNumber;
1551 	uint8_t			functionNumber;
1552 	uint8_t			interruptVector;
1553 	uint8_t			reserved;
1554 	struct megasas_pci_common_header pciHeaderInfo;
1555 	struct megasas_pci_capabilities capability;
1556 	uint8_t			reserved2[32];
1557 };
1558 
1559 struct megasas_ioctl {
1560 	uint16_t	version;
1561 	uint16_t	controller_id;
1562 	uint8_t		signature[8];
1563 	uint32_t	reserved_1;
1564 	uint32_t	control_code;
1565 	uint32_t	reserved_2[2];
1566 	uint8_t		frame[64];
1567 	union megasas_sgl_frame	sgl_frame;
1568 	uint8_t		sense_buff[MR_MAX_SENSE_LENGTH];
1569 	uint8_t		data[1];
1570 };
1571 
1572 struct megasas_aen {
1573 	uint16_t	host_no;
1574 	uint16_t	cmd_status;
1575 	uint32_t	seq_num;
1576 	uint32_t	class_locale_word;
1577 };
1578 
1579 #pragma pack()
1580 
1581 #ifndef	DDI_VENDOR_LSI
1582 #define	DDI_VENDOR_LSI		"LSI"
1583 #endif /* DDI_VENDOR_LSI */
1584 
1585 static int	megasas_getinfo(dev_info_t *, ddi_info_cmd_t,  void *, void **);
1586 static int	megasas_attach(dev_info_t *, ddi_attach_cmd_t);
1587 static int	megasas_reset(dev_info_t *, ddi_reset_cmd_t);
1588 static int	megasas_detach(dev_info_t *, ddi_detach_cmd_t);
1589 static int	megasas_open(dev_t *, int, int, cred_t *);
1590 static int	megasas_close(dev_t, int, int, cred_t *);
1591 static int	megasas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
1592 
1593 static int	megasas_tran_tgt_init(dev_info_t *, dev_info_t *,
1594 		    scsi_hba_tran_t *, struct scsi_device *);
1595 static struct scsi_pkt *megasas_tran_init_pkt(struct scsi_address *, register
1596 		    struct scsi_pkt *, struct buf *, int, int, int, int,
1597 		    int (*)(), caddr_t);
1598 static int	megasas_tran_start(struct scsi_address *,
1599 		    register struct scsi_pkt *);
1600 static int	megasas_tran_abort(struct scsi_address *, struct scsi_pkt *);
1601 static int	megasas_tran_reset(struct scsi_address *, int);
1602 static int	megasas_tran_bus_reset(dev_info_t *, int);
1603 static int	megasas_tran_getcap(struct scsi_address *, char *, int);
1604 static int	megasas_tran_setcap(struct scsi_address *, char *, int, int);
1605 static void	megasas_tran_destroy_pkt(struct scsi_address *,
1606 		    struct scsi_pkt *);
1607 static void	megasas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
1608 static void	megasas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
1609 static int	megasas_tran_quiesce(dev_info_t *dip);
1610 static int	megasas_tran_unquiesce(dev_info_t *dip);
1611 static uint_t	megasas_isr();
1612 static uint_t	megasas_softintr();
1613 
1614 static int	init_mfi(struct megasas_instance *);
1615 static int	mega_free_dma_obj(struct megasas_instance *, dma_obj_t);
1616 static int	mega_alloc_dma_obj(struct megasas_instance *, dma_obj_t *);
1617 static struct megasas_cmd *get_mfi_pkt(struct megasas_instance *);
1618 static void	return_mfi_pkt(struct megasas_instance *,
1619 		    struct megasas_cmd *);
1620 
1621 static void	free_space_for_mfi(struct megasas_instance *);
1622 static void	free_additional_dma_buffer(struct megasas_instance *);
1623 static int	alloc_additional_dma_buffer(struct megasas_instance *);
1624 static int	read_fw_status_reg_xscale(struct megasas_instance *);
1625 static int	read_fw_status_reg_ppc(struct megasas_instance *);
1626 static void	issue_cmd_xscale(struct megasas_cmd *,
1627 		    struct megasas_instance *);
1628 static void	issue_cmd_ppc(struct megasas_cmd *, struct megasas_instance *);
1629 static int	issue_cmd_in_poll_mode_xscale(struct megasas_instance *,
1630 		    struct megasas_cmd *);
1631 static int	issue_cmd_in_poll_mode_ppc(struct megasas_instance *,
1632 		    struct megasas_cmd *);
1633 static int	issue_cmd_in_sync_mode_xscale(struct megasas_instance *,
1634 		    struct megasas_cmd *);
1635 static int	issue_cmd_in_sync_mode_ppc(struct megasas_instance *,
1636 		    struct megasas_cmd *);
1637 static void	enable_intr_xscale(struct megasas_instance *);
1638 static void	enable_intr_ppc(struct megasas_instance *);
1639 static void	disable_intr_xscale(struct megasas_instance *);
1640 static void	disable_intr_ppc(struct megasas_instance *);
1641 static int	intr_ack_xscale(struct megasas_instance *);
1642 static int	intr_ack_ppc(struct megasas_instance *);
1643 static int	mfi_state_transition_to_ready(struct megasas_instance *);
1644 static void	destroy_mfi_frame_pool(struct megasas_instance *);
1645 static int	create_mfi_frame_pool(struct megasas_instance *);
1646 static int	megasas_dma_alloc(struct megasas_instance *, struct scsi_pkt *,
1647 		    struct buf *, int, int (*)());
1648 static int	megasas_dma_move(struct megasas_instance *,
1649 			struct scsi_pkt *, struct buf *);
1650 static void	flush_cache(struct megasas_instance *instance);
1651 static void	display_scsi_inquiry(caddr_t);
1652 static int	start_mfi_aen(struct megasas_instance *instance);
1653 static int	handle_drv_ioctl(struct megasas_instance *instance,
1654 		    struct megasas_ioctl *ioctl, int mode);
1655 static int	handle_mfi_ioctl(struct megasas_instance *instance,
1656 		    struct megasas_ioctl *ioctl, int mode);
1657 static int	handle_mfi_aen(struct megasas_instance *instance,
1658 		    struct megasas_aen *aen);
1659 static void	fill_up_drv_ver(struct megasas_drv_ver *dv);
1660 static struct megasas_cmd *build_cmd(struct megasas_instance *instance,
1661 		    struct scsi_address *ap, struct scsi_pkt *pkt,
1662 		    uchar_t *cmd_done);
1663 static int	wait_for_outstanding(struct megasas_instance *instance);
1664 static int	register_mfi_aen(struct megasas_instance *instance,
1665 		    uint32_t seq_num, uint32_t class_locale_word);
1666 static int	issue_mfi_pthru(struct megasas_instance *instance, struct
1667 		    megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode);
1668 static int	issue_mfi_dcmd(struct megasas_instance *instance, struct
1669 		    megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode);
1670 static int	issue_mfi_smp(struct megasas_instance *instance, struct
1671 		    megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode);
1672 static int	issue_mfi_stp(struct megasas_instance *instance, struct
1673 		    megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode);
1674 static int	abort_aen_cmd(struct megasas_instance *instance,
1675 		    struct megasas_cmd *cmd_to_abort);
1676 
1677 static int	megasas_common_check(struct megasas_instance *instance,
1678 		    struct  megasas_cmd *cmd);
1679 static void	megasas_fm_init(struct megasas_instance *instance);
1680 static void	megasas_fm_fini(struct megasas_instance *instance);
1681 static int	megasas_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
1682 		    const void *);
1683 static void	megasas_fm_ereport(struct megasas_instance *instance,
1684 		    char *detail);
1685 static int	megasas_check_dma_handle(ddi_dma_handle_t handle);
1686 static int	megasas_check_acc_handle(ddi_acc_handle_t handle);
1687 
1688 #ifdef	__cplusplus
1689 }
1690 #endif
1691 
1692 #endif /* _MEGARAID_SAS_H_ */
1693