1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com>
5 * Copyright 2018 Joyent, Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29 /*
30 XHCI options:
31 -s <n>,xhci,{devices}
32
33 devices:
34 tablet USB tablet mouse
35 */
36
37 #include <sys/param.h>
38 #include <sys/uio.h>
39 #include <sys/types.h>
40 #include <sys/queue.h>
41
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stdint.h>
45 #include <string.h>
46 #include <errno.h>
47 #include <pthread.h>
48 #include <unistd.h>
49
50 #include <dev/usb/usbdi.h>
51 #include <dev/usb/usb.h>
52 #include <dev/usb/usb_freebsd.h>
53 #include <xhcireg.h>
54
55 #include "bhyverun.h"
56 #include "config.h"
57 #include "debug.h"
58 #include "pci_emul.h"
59 #include "pci_xhci.h"
60 #include "usb_emul.h"
61
62
63 static int xhci_debug = 0;
64 #define DPRINTF(params) if (xhci_debug) PRINTLN params
65 #define WPRINTF(params) PRINTLN params
66
67
68 #define XHCI_NAME "xhci"
69 #define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */
70
71 #define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */
72
73 /*
74 * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping
75 * to 4k to avoid going over the guest physical memory barrier.
76 */
77 #define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */
78
79 #define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */
80
81 #define XHCI_CAPLEN (4*8) /* offset of op register space */
82 #define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */
83 #define XHCI_PORTREGS_START 0x400
84 #define XHCI_DOORBELL_MAX 256
85
86 #define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */
87
88 /* caplength and hci-version registers */
89 #define XHCI_SET_CAPLEN(x) ((x) & 0xFF)
90 #define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16)
91 #define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF)
92
93 /* hcsparams1 register */
94 #define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF)
95 #define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8)
96 #define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24)
97
98 /* hcsparams2 register */
99 #define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F)
100 #define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4)
101 #define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21)
102 #define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27)
103
104 /* hcsparams3 register */
105 #define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF)
106 #define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16)
107
108 /* hccparams1 register */
109 #define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01)
110 #define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1)
111 #define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2)
112 #define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3)
113 #define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4)
114 #define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5)
115 #define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6)
116 #define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7)
117 #define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8)
118 #define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9)
119 #define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10)
120 #define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11)
121 #define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12)
122 #define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16)
123
124 /* hccparams2 register */
125 #define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01)
126 #define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1)
127 #define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2)
128 #define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3)
129 #define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4)
130 #define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5)
131
132 /* other registers */
133 #define XHCI_SET_DOORBELL(x) ((x) & ~0x03)
134 #define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F)
135
136 /* register masks */
137 #define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */
138 #define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */
139 #define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */
140
141 /* port register set */
142 #define XHCI_PORTREGS_BASE 0x400 /* base offset */
143 #define XHCI_PORTREGS_PORT0 0x3F0
144 #define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */
145
146 #define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL)
147 #define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL)
148
149 #define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \
150 (((b) & (m)) << (s)))
151 #define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \
152 (((b) & ((m) << (s)))))
153
154 struct pci_xhci_trb_ring {
155 uint64_t ringaddr; /* current dequeue guest address */
156 uint32_t ccs; /* consumer cycle state */
157 };
158
159 /* device endpoint transfer/stream rings */
160 struct pci_xhci_dev_ep {
161 union {
162 struct xhci_trb *_epu_tr;
163 struct xhci_stream_ctx *_epu_sctx;
164 } _ep_trbsctx;
165 #define ep_tr _ep_trbsctx._epu_tr
166 #define ep_sctx _ep_trbsctx._epu_sctx
167
168 /*
169 * Caches the value of MaxPStreams from the endpoint context
170 * when an endpoint is initialized and is used to validate the
171 * use of ep_ringaddr vs ep_sctx_trbs[] as well as the length
172 * of ep_sctx_trbs[].
173 */
174 uint32_t ep_MaxPStreams;
175 union {
176 struct pci_xhci_trb_ring _epu_trb;
177 struct pci_xhci_trb_ring *_epu_sctx_trbs;
178 } _ep_trb_rings;
179 #define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr
180 #define ep_ccs _ep_trb_rings._epu_trb.ccs
181 #define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs
182
183 struct usb_data_xfer *ep_xfer; /* transfer chain */
184 };
185
186 /* device context base address array: maps slot->device context */
187 struct xhci_dcbaa {
188 uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */
189 };
190
191 /* port status registers */
192 struct pci_xhci_portregs {
193 uint32_t portsc; /* port status and control */
194 uint32_t portpmsc; /* port pwr mgmt status & control */
195 uint32_t portli; /* port link info */
196 uint32_t porthlpmc; /* port hardware LPM control */
197 } __packed;
198 #define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10)
199
200 /* xHC operational registers */
201 struct pci_xhci_opregs {
202 uint32_t usbcmd; /* usb command */
203 uint32_t usbsts; /* usb status */
204 uint32_t pgsz; /* page size */
205 uint32_t dnctrl; /* device notification control */
206 uint64_t crcr; /* command ring control */
207 uint64_t dcbaap; /* device ctx base addr array ptr */
208 uint32_t config; /* configure */
209
210 /* guest mapped addresses: */
211 struct xhci_trb *cr_p; /* crcr dequeue */
212 struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */
213 };
214
215 /* xHC runtime registers */
216 struct pci_xhci_rtsregs {
217 uint32_t mfindex; /* microframe index */
218 struct { /* interrupter register set */
219 uint32_t iman; /* interrupter management */
220 uint32_t imod; /* interrupter moderation */
221 uint32_t erstsz; /* event ring segment table size */
222 uint32_t rsvd;
223 uint64_t erstba; /* event ring seg-tbl base addr */
224 uint64_t erdp; /* event ring dequeue ptr */
225 } intrreg __packed;
226
227 /* guest mapped addresses */
228 struct xhci_event_ring_seg *erstba_p;
229 struct xhci_trb *erst_p; /* event ring segment tbl */
230 int er_deq_seg; /* event ring dequeue segment */
231 int er_enq_idx; /* event ring enqueue index - xHCI */
232 int er_enq_seg; /* event ring enqueue segment */
233 uint32_t er_events_cnt; /* number of events in ER */
234 uint32_t event_pcs; /* producer cycle state flag */
235 };
236
237
238 struct pci_xhci_softc;
239
240
241 /*
242 * USB device emulation container.
243 * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each
244 * emulated device instance.
245 */
246 struct pci_xhci_dev_emu {
247 struct pci_xhci_softc *xsc;
248
249 /* XHCI contexts */
250 struct xhci_dev_ctx *dev_ctx;
251 struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS];
252 int dev_slotstate;
253
254 struct usb_devemu *dev_ue; /* USB emulated dev */
255 void *dev_sc; /* device's softc */
256
257 struct usb_hci hci;
258 };
259
260 struct pci_xhci_softc {
261 struct pci_devinst *xsc_pi;
262
263 pthread_mutex_t mtx;
264
265 uint32_t caplength; /* caplen & hciversion */
266 uint32_t hcsparams1; /* structural parameters 1 */
267 uint32_t hcsparams2; /* structural parameters 2 */
268 uint32_t hcsparams3; /* structural parameters 3 */
269 uint32_t hccparams1; /* capability parameters 1 */
270 uint32_t dboff; /* doorbell offset */
271 uint32_t rtsoff; /* runtime register space offset */
272 uint32_t hccparams2; /* capability parameters 2 */
273
274 uint32_t regsend; /* end of configuration registers */
275
276 struct pci_xhci_opregs opregs;
277 struct pci_xhci_rtsregs rtsregs;
278
279 struct pci_xhci_portregs *portregs;
280 struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */
281 struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */
282
283 int usb2_port_start;
284 int usb3_port_start;
285 };
286
287
288 /* port and slot numbering start from 1 */
289 #define XHCI_PORTREG_PTR(x,n) &((x)->portregs[(n) - 1])
290 #define XHCI_DEVINST_PTR(x,n) ((x)->devices[(n) - 1])
291 #define XHCI_SLOTDEV_PTR(x,n) ((x)->slots[(n) - 1])
292
293 #define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH)
294
295 #define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \
296 (a), \
297 XHCI_PADDR_SZ - ((a) & (XHCI_PADDR_SZ-1)))
298
299 static int xhci_in_use;
300
301 /* map USB errors to XHCI */
302 static const int xhci_usb_errors[USB_ERR_MAX] = {
303 [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS,
304 [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE,
305 [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
306 [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID,
307 [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE,
308 [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED,
309 [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER,
310 [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER,
311 [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER,
312 [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL,
313 [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE,
314 [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE,
315 [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE,
316 [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED,
317 [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED,
318 [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE,
319 [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON,
320 [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE,
321 [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB,
322 [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON,
323 [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED,
324 [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT,
325 [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL,
326 [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED,
327 [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF,
328 [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB,
329 [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED,
330 [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED,
331 [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED,
332 };
333 #define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \
334 XHCI_TRB_ERROR_INVALID)
335
336 static int pci_xhci_insert_event(struct pci_xhci_softc *sc,
337 struct xhci_trb *evtrb, int do_intr);
338 static void pci_xhci_dump_trb(struct xhci_trb *trb);
339 static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc);
340 static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot);
341 static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm);
342 static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc,
343 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
344 struct xhci_endp_ctx *ep_ctx, uint32_t streamid,
345 uint64_t ringaddr, int ccs);
346 static int pci_xhci_validate_slot(uint32_t slot);
347
348 static void
pci_xhci_set_evtrb(struct xhci_trb * evtrb,uint64_t port,uint32_t errcode,uint32_t evtype)349 pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode,
350 uint32_t evtype)
351 {
352 evtrb->qwTrb0 = port << 24;
353 evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode);
354 evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype);
355 }
356
357
358 /* controller reset */
359 static void
pci_xhci_reset(struct pci_xhci_softc * sc)360 pci_xhci_reset(struct pci_xhci_softc *sc)
361 {
362 int i;
363
364 sc->rtsregs.er_enq_idx = 0;
365 sc->rtsregs.er_events_cnt = 0;
366 sc->rtsregs.event_pcs = 1;
367
368 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
369 pci_xhci_reset_slot(sc, i);
370 }
371 }
372
373 static uint32_t
pci_xhci_usbcmd_write(struct pci_xhci_softc * sc,uint32_t cmd)374 pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd)
375 {
376 int do_intr = 0;
377 int i;
378
379 if (cmd & XHCI_CMD_RS) {
380 do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0;
381
382 sc->opregs.usbcmd |= XHCI_CMD_RS;
383 sc->opregs.usbsts &= ~XHCI_STS_HCH;
384 sc->opregs.usbsts |= XHCI_STS_PCD;
385
386 /* Queue port change event on controller run from stop */
387 if (do_intr)
388 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
389 struct pci_xhci_dev_emu *dev;
390 struct pci_xhci_portregs *port;
391 struct xhci_trb evtrb;
392
393 if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL)
394 continue;
395
396 port = XHCI_PORTREG_PTR(sc, i);
397 port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS;
398 port->portsc &= ~XHCI_PS_PLS_MASK;
399
400 /*
401 * XHCI 4.19.3 USB2 RxDetect->Polling,
402 * USB3 Polling->U0
403 */
404 if (dev->dev_ue->ue_usbver == 2)
405 port->portsc |=
406 XHCI_PS_PLS_SET(UPS_PORT_LS_POLL);
407 else
408 port->portsc |=
409 XHCI_PS_PLS_SET(UPS_PORT_LS_U0);
410
411 pci_xhci_set_evtrb(&evtrb, i,
412 XHCI_TRB_ERROR_SUCCESS,
413 XHCI_TRB_EVENT_PORT_STS_CHANGE);
414
415 if (pci_xhci_insert_event(sc, &evtrb, 0) !=
416 XHCI_TRB_ERROR_SUCCESS)
417 break;
418 }
419 } else {
420 sc->opregs.usbcmd &= ~XHCI_CMD_RS;
421 sc->opregs.usbsts |= XHCI_STS_HCH;
422 sc->opregs.usbsts &= ~XHCI_STS_PCD;
423 }
424
425 /* start execution of schedule; stop when set to 0 */
426 cmd |= sc->opregs.usbcmd & XHCI_CMD_RS;
427
428 if (cmd & XHCI_CMD_HCRST) {
429 /* reset controller */
430 pci_xhci_reset(sc);
431 cmd &= ~XHCI_CMD_HCRST;
432 }
433
434 cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS);
435
436 if (do_intr)
437 pci_xhci_assert_interrupt(sc);
438
439 return (cmd);
440 }
441
442 static void
pci_xhci_portregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)443 pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset,
444 uint64_t value)
445 {
446 struct xhci_trb evtrb;
447 struct pci_xhci_portregs *p;
448 int port;
449 uint32_t oldpls, newpls;
450
451 if (sc->portregs == NULL)
452 return;
453
454 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ;
455 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ;
456
457 DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx",
458 offset, port, value));
459
460 assert(port >= 0);
461
462 if (port > XHCI_MAX_DEVS) {
463 DPRINTF(("pci_xhci: portregs_write port %d > ndevices",
464 port));
465 return;
466 }
467
468 if (XHCI_DEVINST_PTR(sc, port) == NULL) {
469 DPRINTF(("pci_xhci: portregs_write to unattached port %d",
470 port));
471 }
472
473 p = XHCI_PORTREG_PTR(sc, port);
474 switch (offset) {
475 case 0:
476 /* port reset or warm reset */
477 if (value & (XHCI_PS_PR | XHCI_PS_WPR)) {
478 pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR);
479 break;
480 }
481
482 if ((p->portsc & XHCI_PS_PP) == 0) {
483 WPRINTF(("pci_xhci: portregs_write to unpowered "
484 "port %d", port));
485 break;
486 }
487
488 /* Port status and control register */
489 oldpls = XHCI_PS_PLS_GET(p->portsc);
490 newpls = XHCI_PS_PLS_GET(value);
491
492 #ifndef __FreeBSD__
493 p->portsc &= XHCI_PS_PED | XHCI_PS_PP | XHCI_PS_PLS_MASK |
494 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
495 #else
496 p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK |
497 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK;
498 #endif
499
500 if (XHCI_DEVINST_PTR(sc, port))
501 p->portsc |= XHCI_PS_CCS;
502
503 p->portsc |= (value &
504 ~(XHCI_PS_OCA |
505 XHCI_PS_PR |
506 XHCI_PS_PED |
507 XHCI_PS_PLS_MASK | /* link state */
508 XHCI_PS_SPEED_MASK |
509 XHCI_PS_PIC_MASK | /* port indicator */
510 XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR));
511
512 /* clear control bits */
513 p->portsc &= ~(value &
514 (XHCI_PS_CSC |
515 XHCI_PS_PEC |
516 XHCI_PS_WRC |
517 XHCI_PS_OCC |
518 XHCI_PS_PRC |
519 XHCI_PS_PLC |
520 XHCI_PS_CEC |
521 XHCI_PS_CAS));
522
523 /* port disable request; for USB3, don't care */
524 if (value & XHCI_PS_PED)
525 DPRINTF(("Disable port %d request", port));
526
527 if (!(value & XHCI_PS_LWS))
528 break;
529
530 DPRINTF(("Port new PLS: %d", newpls));
531 switch (newpls) {
532 case 0: /* U0 */
533 case 3: /* U3 */
534 if (oldpls != newpls) {
535 p->portsc &= ~XHCI_PS_PLS_MASK;
536 p->portsc |= XHCI_PS_PLS_SET(newpls) |
537 XHCI_PS_PLC;
538
539 if (oldpls != 0 && newpls == 0) {
540 pci_xhci_set_evtrb(&evtrb, port,
541 XHCI_TRB_ERROR_SUCCESS,
542 XHCI_TRB_EVENT_PORT_STS_CHANGE);
543
544 pci_xhci_insert_event(sc, &evtrb, 1);
545 }
546 }
547 break;
548
549 default:
550 DPRINTF(("Unhandled change port %d PLS %u",
551 port, newpls));
552 break;
553 }
554 break;
555 case 4:
556 /* Port power management status and control register */
557 p->portpmsc = value;
558 break;
559 case 8:
560 /* Port link information register */
561 DPRINTF(("pci_xhci attempted write to PORTLI, port %d",
562 port));
563 break;
564 case 12:
565 /*
566 * Port hardware LPM control register.
567 * For USB3, this register is reserved.
568 */
569 p->porthlpmc = value;
570 break;
571 default:
572 DPRINTF(("pci_xhci: unaligned portreg write offset %#lx",
573 offset));
574 break;
575 }
576 }
577
578 static struct xhci_dev_ctx *
pci_xhci_get_dev_ctx(struct pci_xhci_softc * sc,uint32_t slot)579 pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot)
580 {
581 uint64_t devctx_addr;
582 struct xhci_dev_ctx *devctx;
583
584 assert(slot > 0 && slot <= XHCI_MAX_SLOTS);
585 assert(XHCI_SLOTDEV_PTR(sc, slot) != NULL);
586 assert(sc->opregs.dcbaa_p != NULL);
587
588 devctx_addr = sc->opregs.dcbaa_p->dcba[slot];
589
590 if (devctx_addr == 0) {
591 DPRINTF(("get_dev_ctx devctx_addr == 0"));
592 return (NULL);
593 }
594
595 DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx",
596 slot, devctx_addr));
597 devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL);
598
599 return (devctx);
600 }
601
602 static struct xhci_trb *
pci_xhci_trb_next(struct pci_xhci_softc * sc,struct xhci_trb * curtrb,uint64_t * guestaddr)603 pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb,
604 uint64_t *guestaddr)
605 {
606 struct xhci_trb *next;
607
608 assert(curtrb != NULL);
609
610 if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) {
611 if (guestaddr)
612 *guestaddr = curtrb->qwTrb0 & ~0xFUL;
613
614 next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL);
615 } else {
616 if (guestaddr)
617 *guestaddr += sizeof(struct xhci_trb) & ~0xFUL;
618
619 next = curtrb + 1;
620 }
621
622 return (next);
623 }
624
625 static void
pci_xhci_assert_interrupt(struct pci_xhci_softc * sc)626 pci_xhci_assert_interrupt(struct pci_xhci_softc *sc)
627 {
628
629 sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY;
630 sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND;
631 sc->opregs.usbsts |= XHCI_STS_EINT;
632
633 /* only trigger interrupt if permitted */
634 if ((sc->opregs.usbcmd & XHCI_CMD_INTE) &&
635 (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) {
636 if (pci_msi_enabled(sc->xsc_pi))
637 pci_generate_msi(sc->xsc_pi, 0);
638 else
639 pci_lintr_assert(sc->xsc_pi);
640 }
641 }
642
643 static void
pci_xhci_deassert_interrupt(struct pci_xhci_softc * sc)644 pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc)
645 {
646
647 if (!pci_msi_enabled(sc->xsc_pi))
648 pci_lintr_assert(sc->xsc_pi);
649 }
650
651 static void
pci_xhci_init_ep(struct pci_xhci_dev_emu * dev,int epid)652 pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid)
653 {
654 struct xhci_dev_ctx *dev_ctx;
655 struct pci_xhci_dev_ep *devep;
656 struct xhci_endp_ctx *ep_ctx;
657 uint32_t i, pstreams;
658
659 dev_ctx = dev->dev_ctx;
660 ep_ctx = &dev_ctx->ctx_ep[epid];
661 devep = &dev->eps[epid];
662 pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0);
663 if (pstreams > 0) {
664 DPRINTF(("init_ep %d with pstreams %u", epid, pstreams));
665 assert(devep->ep_sctx_trbs == NULL);
666
667 devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 &
668 XHCI_EPCTX_2_TR_DQ_PTR_MASK);
669 devep->ep_sctx_trbs = calloc(pstreams,
670 sizeof(struct pci_xhci_trb_ring));
671 for (i = 0; i < pstreams; i++) {
672 devep->ep_sctx_trbs[i].ringaddr =
673 devep->ep_sctx[i].qwSctx0 &
674 XHCI_SCTX_0_TR_DQ_PTR_MASK;
675 devep->ep_sctx_trbs[i].ccs =
676 XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0);
677 }
678 } else {
679 DPRINTF(("init_ep %d with no pstreams", epid));
680 devep->ep_ringaddr = ep_ctx->qwEpCtx2 &
681 XHCI_EPCTX_2_TR_DQ_PTR_MASK;
682 devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2);
683 devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr);
684 DPRINTF(("init_ep tr DCS %x", devep->ep_ccs));
685 }
686 devep->ep_MaxPStreams = pstreams;
687
688 if (devep->ep_xfer == NULL) {
689 devep->ep_xfer = malloc(sizeof(struct usb_data_xfer));
690 USB_DATA_XFER_INIT(devep->ep_xfer);
691 }
692 }
693
694 static void
pci_xhci_disable_ep(struct pci_xhci_dev_emu * dev,int epid)695 pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid)
696 {
697 struct xhci_dev_ctx *dev_ctx;
698 struct pci_xhci_dev_ep *devep;
699 struct xhci_endp_ctx *ep_ctx;
700
701 DPRINTF(("pci_xhci disable_ep %d", epid));
702
703 dev_ctx = dev->dev_ctx;
704 ep_ctx = &dev_ctx->ctx_ep[epid];
705 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED;
706
707 devep = &dev->eps[epid];
708 if (devep->ep_MaxPStreams > 0)
709 free(devep->ep_sctx_trbs);
710
711 if (devep->ep_xfer != NULL) {
712 free(devep->ep_xfer);
713 devep->ep_xfer = NULL;
714 }
715
716 memset(devep, 0, sizeof(struct pci_xhci_dev_ep));
717 }
718
719
720 /* reset device at slot and data structures related to it */
721 static void
pci_xhci_reset_slot(struct pci_xhci_softc * sc,int slot)722 pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot)
723 {
724 struct pci_xhci_dev_emu *dev;
725
726 dev = XHCI_SLOTDEV_PTR(sc, slot);
727
728 if (!dev) {
729 DPRINTF(("xhci reset unassigned slot (%d)?", slot));
730 } else {
731 dev->dev_slotstate = XHCI_ST_DISABLED;
732 }
733
734 /* TODO: reset ring buffer pointers */
735 }
736
737 static int
pci_xhci_insert_event(struct pci_xhci_softc * sc,struct xhci_trb * evtrb,int do_intr)738 pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb,
739 int do_intr)
740 {
741 struct pci_xhci_rtsregs *rts;
742 uint64_t erdp;
743 int erdp_idx;
744 int err;
745 struct xhci_trb *evtrbptr;
746
747 err = XHCI_TRB_ERROR_SUCCESS;
748
749 rts = &sc->rtsregs;
750
751 erdp = rts->intrreg.erdp & ~0xF;
752 erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) /
753 sizeof(struct xhci_trb);
754
755 DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]",
756 evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3));
757 DPRINTF(("\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u",
758 erdp_idx, rts->er_deq_seg, rts->er_enq_idx,
759 rts->er_enq_seg, rts->event_pcs));
760 DPRINTF(("\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)",
761 erdp, rts->erstba_p->qwEvrsTablePtr,
762 rts->erstba_p->dwEvrsTableSize, do_intr));
763
764 evtrbptr = &rts->erst_p[rts->er_enq_idx];
765
766 /* TODO: multi-segment table */
767 if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) {
768 DPRINTF(("pci_xhci[%d] cannot insert event; ring full",
769 __LINE__));
770 err = XHCI_TRB_ERROR_EV_RING_FULL;
771 goto done;
772 }
773
774 if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) {
775 struct xhci_trb errev;
776
777 if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) {
778
779 DPRINTF(("pci_xhci[%d] insert evt err: ring full",
780 __LINE__));
781
782 errev.qwTrb0 = 0;
783 errev.dwTrb2 = XHCI_TRB_2_ERROR_SET(
784 XHCI_TRB_ERROR_EV_RING_FULL);
785 errev.dwTrb3 = XHCI_TRB_3_TYPE_SET(
786 XHCI_TRB_EVENT_HOST_CTRL) |
787 rts->event_pcs;
788 rts->er_events_cnt++;
789 memcpy(&rts->erst_p[rts->er_enq_idx], &errev,
790 sizeof(struct xhci_trb));
791 rts->er_enq_idx = (rts->er_enq_idx + 1) %
792 rts->erstba_p->dwEvrsTableSize;
793 err = XHCI_TRB_ERROR_EV_RING_FULL;
794 do_intr = 1;
795
796 goto done;
797 }
798 } else {
799 rts->er_events_cnt++;
800 }
801
802 evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT;
803 evtrb->dwTrb3 |= rts->event_pcs;
804
805 memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb));
806 rts->er_enq_idx = (rts->er_enq_idx + 1) %
807 rts->erstba_p->dwEvrsTableSize;
808
809 if (rts->er_enq_idx == 0)
810 rts->event_pcs ^= 1;
811
812 done:
813 if (do_intr)
814 pci_xhci_assert_interrupt(sc);
815
816 return (err);
817 }
818
819 static uint32_t
pci_xhci_cmd_enable_slot(struct pci_xhci_softc * sc,uint32_t * slot)820 pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot)
821 {
822 struct pci_xhci_dev_emu *dev;
823 uint32_t cmderr;
824 int i;
825
826 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
827 if (sc->portregs != NULL)
828 for (i = 1; i <= XHCI_MAX_SLOTS; i++) {
829 dev = XHCI_SLOTDEV_PTR(sc, i);
830 if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) {
831 *slot = i;
832 dev->dev_slotstate = XHCI_ST_ENABLED;
833 cmderr = XHCI_TRB_ERROR_SUCCESS;
834 dev->hci.hci_address = i;
835 break;
836 }
837 }
838
839 DPRINTF(("pci_xhci enable slot (error=%d) slot %u",
840 cmderr != XHCI_TRB_ERROR_SUCCESS, *slot));
841
842 return (cmderr);
843 }
844
845 static uint32_t
pci_xhci_cmd_disable_slot(struct pci_xhci_softc * sc,uint32_t slot)846 pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot)
847 {
848 struct pci_xhci_dev_emu *dev;
849 uint32_t cmderr;
850
851 DPRINTF(("pci_xhci disable slot %u", slot));
852
853 if (sc->portregs == NULL) {
854 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
855 goto done;
856 }
857
858 cmderr = pci_xhci_validate_slot(slot);
859 if (cmderr != XHCI_TRB_ERROR_SUCCESS)
860 goto done;
861
862 dev = XHCI_SLOTDEV_PTR(sc, slot);
863 if (dev) {
864 if (dev->dev_slotstate == XHCI_ST_DISABLED) {
865 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
866 } else {
867 dev->dev_slotstate = XHCI_ST_DISABLED;
868 /* TODO: reset events and endpoints */
869 }
870 } else
871 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
872
873 done:
874 return (cmderr);
875 }
876
877 static uint32_t
pci_xhci_cmd_reset_device(struct pci_xhci_softc * sc,uint32_t slot)878 pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot)
879 {
880 struct pci_xhci_dev_emu *dev;
881 struct xhci_dev_ctx *dev_ctx;
882 struct xhci_endp_ctx *ep_ctx;
883 uint32_t cmderr;
884 int i;
885
886 if (sc->portregs == NULL) {
887 cmderr = XHCI_TRB_ERROR_NO_SLOTS;
888 goto done;
889 }
890
891 DPRINTF(("pci_xhci reset device slot %u", slot));
892
893 cmderr = pci_xhci_validate_slot(slot);
894 if (cmderr != XHCI_TRB_ERROR_SUCCESS)
895 goto done;
896
897 dev = XHCI_SLOTDEV_PTR(sc, slot);
898 if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED)
899 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
900 else {
901 dev->dev_slotstate = XHCI_ST_DEFAULT;
902
903 dev->hci.hci_address = 0;
904 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
905 if (dev_ctx == NULL) {
906 cmderr = XHCI_TRB_ERROR_PARAMETER;
907 goto done;
908 }
909
910 /* slot state */
911 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
912 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT,
913 0x1F, 27);
914
915 /* number of contexts */
916 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
917 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
918
919 /* reset all eps other than ep-0 */
920 for (i = 2; i <= 31; i++) {
921 ep_ctx = &dev_ctx->ctx_ep[i];
922 ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0,
923 XHCI_ST_EPCTX_DISABLED, 0x7, 0);
924 }
925 }
926
927 pci_xhci_reset_slot(sc, slot);
928
929 done:
930 return (cmderr);
931 }
932
933 static uint32_t
pci_xhci_cmd_address_device(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)934 pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot,
935 struct xhci_trb *trb)
936 {
937 struct pci_xhci_dev_emu *dev;
938 struct xhci_input_dev_ctx *input_ctx;
939 struct xhci_slot_ctx *islot_ctx;
940 struct xhci_dev_ctx *dev_ctx;
941 struct xhci_endp_ctx *ep0_ctx;
942 uint32_t cmderr;
943
944 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
945 islot_ctx = &input_ctx->ctx_slot;
946 ep0_ctx = &input_ctx->ctx_ep[1];
947
948 DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,",
949 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
950 DPRINTF((" slot %08x %08x %08x %08x",
951 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
952 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
953 DPRINTF((" ep0 %08x %08x %016lx %08x",
954 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
955 ep0_ctx->dwEpCtx4));
956
957 /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */
958 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
959 (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) {
960 DPRINTF(("pci_xhci: address device, input ctl invalid"));
961 cmderr = XHCI_TRB_ERROR_TRB;
962 goto done;
963 }
964
965 cmderr = pci_xhci_validate_slot(slot);
966 if (cmderr != XHCI_TRB_ERROR_SUCCESS)
967 goto done;
968
969 /* assign address to slot */
970 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
971 if (dev_ctx == NULL) {
972 cmderr = XHCI_TRB_ERROR_PARAMETER;
973 goto done;
974 }
975
976 DPRINTF(("pci_xhci: address device, dev ctx"));
977 DPRINTF((" slot %08x %08x %08x %08x",
978 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
979 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
980
981 dev = XHCI_SLOTDEV_PTR(sc, slot);
982 assert(dev != NULL);
983
984 dev->hci.hci_address = slot;
985 dev->dev_ctx = dev_ctx;
986
987 if (dev->dev_ue->ue_reset == NULL ||
988 dev->dev_ue->ue_reset(dev->dev_sc) < 0) {
989 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
990 goto done;
991 }
992
993 memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx));
994
995 dev_ctx->ctx_slot.dwSctx3 =
996 XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) |
997 XHCI_SCTX_3_DEV_ADDR_SET(slot);
998
999 memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx));
1000 ep0_ctx = &dev_ctx->ctx_ep[1];
1001 ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) |
1002 XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING);
1003
1004 pci_xhci_init_ep(dev, 1);
1005
1006 dev->dev_slotstate = XHCI_ST_ADDRESSED;
1007
1008 DPRINTF(("pci_xhci: address device, output ctx"));
1009 DPRINTF((" slot %08x %08x %08x %08x",
1010 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1011 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1012 DPRINTF((" ep0 %08x %08x %016lx %08x",
1013 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1014 ep0_ctx->dwEpCtx4));
1015
1016 done:
1017 return (cmderr);
1018 }
1019
1020 static uint32_t
pci_xhci_cmd_config_ep(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1021 pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot,
1022 struct xhci_trb *trb)
1023 {
1024 struct xhci_input_dev_ctx *input_ctx;
1025 struct pci_xhci_dev_emu *dev;
1026 struct xhci_dev_ctx *dev_ctx;
1027 struct xhci_endp_ctx *ep_ctx, *iep_ctx;
1028 uint32_t cmderr;
1029 int i;
1030
1031 DPRINTF(("pci_xhci config_ep slot %u", slot));
1032
1033 cmderr = pci_xhci_validate_slot(slot);
1034 if (cmderr != XHCI_TRB_ERROR_SUCCESS)
1035 goto done;
1036
1037 dev = XHCI_SLOTDEV_PTR(sc, slot);
1038 assert(dev != NULL);
1039
1040 if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) {
1041 DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u",
1042 slot));
1043 if (dev->dev_ue->ue_stop != NULL)
1044 dev->dev_ue->ue_stop(dev->dev_sc);
1045
1046 dev->dev_slotstate = XHCI_ST_ADDRESSED;
1047
1048 dev->hci.hci_address = 0;
1049 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1050 if (dev_ctx == NULL) {
1051 cmderr = XHCI_TRB_ERROR_PARAMETER;
1052 goto done;
1053 }
1054
1055 /* number of contexts */
1056 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE(
1057 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27);
1058
1059 /* slot state */
1060 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1061 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED,
1062 0x1F, 27);
1063
1064 /* disable endpoints */
1065 for (i = 2; i < 32; i++)
1066 pci_xhci_disable_ep(dev, i);
1067
1068 cmderr = XHCI_TRB_ERROR_SUCCESS;
1069
1070 goto done;
1071 }
1072
1073 if (dev->dev_slotstate < XHCI_ST_ADDRESSED) {
1074 DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed",
1075 dev->dev_slotstate));
1076 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON;
1077 goto done;
1078 }
1079
1080 /* In addressed/configured state;
1081 * for each drop endpoint ctx flag:
1082 * ep->state = DISABLED
1083 * for each add endpoint ctx flag:
1084 * cp(ep-in, ep-out)
1085 * ep->state = RUNNING
1086 * for each drop+add endpoint flag:
1087 * reset ep resources
1088 * cp(ep-in, ep-out)
1089 * ep->state = RUNNING
1090 * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled)
1091 * slot->state = configured
1092 */
1093
1094 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1095 dev_ctx = dev->dev_ctx;
1096 DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x",
1097 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1,
1098 input_ctx->ctx_input.dwInCtx7));
1099
1100 for (i = 2; i <= 31; i++) {
1101 ep_ctx = &dev_ctx->ctx_ep[i];
1102
1103 if (input_ctx->ctx_input.dwInCtx0 &
1104 XHCI_INCTX_0_DROP_MASK(i)) {
1105 DPRINTF((" config ep - dropping ep %d", i));
1106 pci_xhci_disable_ep(dev, i);
1107 }
1108
1109 if (input_ctx->ctx_input.dwInCtx1 &
1110 XHCI_INCTX_1_ADD_MASK(i)) {
1111 iep_ctx = &input_ctx->ctx_ep[i];
1112
1113 DPRINTF((" enable ep[%d] %08x %08x %016lx %08x",
1114 i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1,
1115 iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4));
1116
1117 memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx));
1118
1119 pci_xhci_init_ep(dev, i);
1120
1121 /* ep state */
1122 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1123 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1124 }
1125 }
1126
1127 /* slot state to configured */
1128 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE(
1129 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27);
1130 dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY(
1131 dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27);
1132 dev->dev_slotstate = XHCI_ST_CONFIGURED;
1133
1134 DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x "
1135 "[3]=0x%08x",
1136 slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1137 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1138
1139 done:
1140 return (cmderr);
1141 }
1142
1143 static uint32_t
pci_xhci_cmd_reset_ep(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1144 pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot,
1145 struct xhci_trb *trb)
1146 {
1147 struct pci_xhci_dev_emu *dev;
1148 struct pci_xhci_dev_ep *devep;
1149 struct xhci_dev_ctx *dev_ctx;
1150 struct xhci_endp_ctx *ep_ctx;
1151 uint32_t cmderr, epid;
1152 uint32_t type;
1153
1154 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1155
1156 DPRINTF(("pci_xhci: reset ep %u: slot %u", epid, slot));
1157
1158 cmderr = pci_xhci_validate_slot(slot);
1159 if (cmderr != XHCI_TRB_ERROR_SUCCESS)
1160 goto done;
1161
1162 dev = XHCI_SLOTDEV_PTR(sc, slot);
1163 assert(dev != NULL);
1164
1165 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1166
1167 if (type == XHCI_TRB_TYPE_STOP_EP &&
1168 (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) {
1169 /* XXX suspend endpoint for 10ms */
1170 }
1171
1172 if (epid < 1 || epid > 31) {
1173 DPRINTF(("pci_xhci: reset ep: invalid epid %u", epid));
1174 cmderr = XHCI_TRB_ERROR_TRB;
1175 goto done;
1176 }
1177
1178 devep = &dev->eps[epid];
1179 if (devep->ep_xfer != NULL)
1180 USB_DATA_XFER_RESET(devep->ep_xfer);
1181
1182 dev_ctx = dev->dev_ctx;
1183 assert(dev_ctx != NULL);
1184
1185 ep_ctx = &dev_ctx->ctx_ep[epid];
1186
1187 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1188
1189 if (devep->ep_MaxPStreams == 0)
1190 ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs;
1191
1192 DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x",
1193 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1194 ep_ctx->dwEpCtx4));
1195
1196 if (type == XHCI_TRB_TYPE_RESET_EP &&
1197 (dev->dev_ue->ue_reset == NULL ||
1198 dev->dev_ue->ue_reset(dev->dev_sc) < 0)) {
1199 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON;
1200 goto done;
1201 }
1202
1203 done:
1204 return (cmderr);
1205 }
1206
1207
1208 static uint32_t
pci_xhci_find_stream(struct pci_xhci_softc * sc,struct xhci_endp_ctx * ep,struct pci_xhci_dev_ep * devep,uint32_t streamid)1209 pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep,
1210 struct pci_xhci_dev_ep *devep, uint32_t streamid)
1211 {
1212 struct xhci_stream_ctx *sctx;
1213
1214 if (devep->ep_MaxPStreams == 0)
1215 return (XHCI_TRB_ERROR_TRB);
1216
1217 if (devep->ep_MaxPStreams > XHCI_STREAMS_MAX)
1218 return (XHCI_TRB_ERROR_INVALID_SID);
1219
1220 if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) {
1221 DPRINTF(("pci_xhci: find_stream; LSA bit not set"));
1222 return (XHCI_TRB_ERROR_INVALID_SID);
1223 }
1224
1225 /* only support primary stream */
1226 if (streamid >= devep->ep_MaxPStreams)
1227 return (XHCI_TRB_ERROR_STREAM_TYPE);
1228
1229 sctx = (struct xhci_stream_ctx *)XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) +
1230 streamid;
1231 if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0))
1232 return (XHCI_TRB_ERROR_STREAM_TYPE);
1233
1234 return (XHCI_TRB_ERROR_SUCCESS);
1235 }
1236
1237
1238 static uint32_t
pci_xhci_cmd_set_tr(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1239 pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot,
1240 struct xhci_trb *trb)
1241 {
1242 struct pci_xhci_dev_emu *dev;
1243 struct pci_xhci_dev_ep *devep;
1244 struct xhci_dev_ctx *dev_ctx;
1245 struct xhci_endp_ctx *ep_ctx;
1246 uint32_t cmderr, epid;
1247 uint32_t streamid;
1248
1249 cmderr = pci_xhci_validate_slot(slot);
1250 if (cmderr != XHCI_TRB_ERROR_SUCCESS)
1251 goto done;
1252
1253 dev = XHCI_SLOTDEV_PTR(sc, slot);
1254 assert(dev != NULL);
1255
1256 DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u",
1257 (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7),
1258 (uint32_t)(trb->qwTrb0 & 0x1)));
1259 DPRINTF((" stream-id %u, slot %u, epid %u, C %u",
1260 (trb->dwTrb2 >> 16) & 0xFFFF,
1261 XHCI_TRB_3_SLOT_GET(trb->dwTrb3),
1262 XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1));
1263
1264 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);
1265 if (epid < 1 || epid > 31) {
1266 DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u", epid));
1267 cmderr = XHCI_TRB_ERROR_TRB;
1268 goto done;
1269 }
1270
1271 dev_ctx = dev->dev_ctx;
1272 assert(dev_ctx != NULL);
1273
1274 ep_ctx = &dev_ctx->ctx_ep[epid];
1275 devep = &dev->eps[epid];
1276
1277 switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) {
1278 case XHCI_ST_EPCTX_STOPPED:
1279 case XHCI_ST_EPCTX_ERROR:
1280 break;
1281 default:
1282 DPRINTF(("pci_xhci cmd set_tr invalid state %x",
1283 XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)));
1284 cmderr = XHCI_TRB_ERROR_CONTEXT_STATE;
1285 goto done;
1286 }
1287
1288 streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2);
1289 if (devep->ep_MaxPStreams > 0) {
1290 cmderr = pci_xhci_find_stream(sc, ep_ctx, devep, streamid);
1291 if (cmderr == XHCI_TRB_ERROR_SUCCESS) {
1292 assert(devep->ep_sctx != NULL);
1293
1294 devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0;
1295 devep->ep_sctx_trbs[streamid].ringaddr =
1296 trb->qwTrb0 & ~0xF;
1297 devep->ep_sctx_trbs[streamid].ccs =
1298 XHCI_EPCTX_2_DCS_GET(trb->qwTrb0);
1299 }
1300 } else {
1301 if (streamid != 0) {
1302 DPRINTF(("pci_xhci cmd set_tr streamid %x != 0",
1303 streamid));
1304 }
1305 ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL;
1306 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL;
1307 devep->ep_ccs = trb->qwTrb0 & 0x1;
1308 devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr);
1309
1310 DPRINTF(("pci_xhci set_tr first TRB:"));
1311 pci_xhci_dump_trb(devep->ep_tr);
1312 }
1313 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED;
1314
1315 done:
1316 return (cmderr);
1317 }
1318
1319 static uint32_t
pci_xhci_cmd_eval_ctx(struct pci_xhci_softc * sc,uint32_t slot,struct xhci_trb * trb)1320 pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot,
1321 struct xhci_trb *trb)
1322 {
1323 struct xhci_input_dev_ctx *input_ctx;
1324 struct xhci_slot_ctx *islot_ctx;
1325 struct xhci_dev_ctx *dev_ctx;
1326 struct xhci_endp_ctx *ep0_ctx;
1327 uint32_t cmderr;
1328
1329 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL);
1330 islot_ctx = &input_ctx->ctx_slot;
1331 ep0_ctx = &input_ctx->ctx_ep[1];
1332
1333 DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,",
1334 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1));
1335 DPRINTF((" slot %08x %08x %08x %08x",
1336 islot_ctx->dwSctx0, islot_ctx->dwSctx1,
1337 islot_ctx->dwSctx2, islot_ctx->dwSctx3));
1338 DPRINTF((" ep0 %08x %08x %016lx %08x",
1339 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1340 ep0_ctx->dwEpCtx4));
1341
1342 /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */
1343 if ((input_ctx->ctx_input.dwInCtx0 != 0) ||
1344 (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) {
1345 DPRINTF(("pci_xhci: eval ctx, input ctl invalid"));
1346 cmderr = XHCI_TRB_ERROR_TRB;
1347 goto done;
1348 }
1349
1350 cmderr = pci_xhci_validate_slot(slot);
1351 if (cmderr != XHCI_TRB_ERROR_SUCCESS)
1352 goto done;
1353
1354 /* assign address to slot; in this emulation, slot_id = address */
1355 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1356 if (dev_ctx == NULL) {
1357 cmderr = XHCI_TRB_ERROR_PARAMETER;
1358 goto done;
1359 }
1360
1361 DPRINTF(("pci_xhci: eval ctx, dev ctx"));
1362 DPRINTF((" slot %08x %08x %08x %08x",
1363 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1364 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1365
1366 if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */
1367 /* set max exit latency */
1368 dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY(
1369 dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1,
1370 0xFFFF, 0);
1371
1372 /* set interrupter target */
1373 dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY(
1374 dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2,
1375 0x3FF, 22);
1376 }
1377 if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */
1378 /* set max packet size */
1379 dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY(
1380 dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1,
1381 0xFFFF, 16);
1382
1383 ep0_ctx = &dev_ctx->ctx_ep[1];
1384 }
1385
1386 DPRINTF(("pci_xhci: eval ctx, output ctx"));
1387 DPRINTF((" slot %08x %08x %08x %08x",
1388 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1,
1389 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3));
1390 DPRINTF((" ep0 %08x %08x %016lx %08x",
1391 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2,
1392 ep0_ctx->dwEpCtx4));
1393
1394 done:
1395 return (cmderr);
1396 }
1397
1398 static int
pci_xhci_complete_commands(struct pci_xhci_softc * sc)1399 pci_xhci_complete_commands(struct pci_xhci_softc *sc)
1400 {
1401 struct xhci_trb evtrb;
1402 struct xhci_trb *trb;
1403 uint64_t crcr;
1404 uint32_t ccs; /* cycle state (XHCI 4.9.2) */
1405 uint32_t type;
1406 uint32_t slot;
1407 uint32_t cmderr;
1408 int error;
1409
1410 error = 0;
1411 sc->opregs.crcr |= XHCI_CRCR_LO_CRR;
1412
1413 trb = sc->opregs.cr_p;
1414 ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS;
1415 crcr = sc->opregs.crcr & ~0xF;
1416
1417 while (1) {
1418 sc->opregs.cr_p = trb;
1419
1420 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1421
1422 if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) !=
1423 (ccs & XHCI_TRB_3_CYCLE_BIT))
1424 break;
1425
1426 DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x"
1427 " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u",
1428 type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3,
1429 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs));
1430
1431 cmderr = XHCI_TRB_ERROR_SUCCESS;
1432 evtrb.dwTrb2 = 0;
1433 evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) |
1434 XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE);
1435 slot = 0;
1436
1437 switch (type) {
1438 case XHCI_TRB_TYPE_LINK: /* 0x06 */
1439 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1440 ccs ^= XHCI_CRCR_LO_RCS;
1441 break;
1442
1443 case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */
1444 cmderr = pci_xhci_cmd_enable_slot(sc, &slot);
1445 break;
1446
1447 case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */
1448 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1449 cmderr = pci_xhci_cmd_disable_slot(sc, slot);
1450 break;
1451
1452 case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */
1453 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1454 cmderr = pci_xhci_cmd_address_device(sc, slot, trb);
1455 break;
1456
1457 case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */
1458 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1459 cmderr = pci_xhci_cmd_config_ep(sc, slot, trb);
1460 break;
1461
1462 case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */
1463 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1464 cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb);
1465 break;
1466
1467 case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */
1468 DPRINTF(("Reset Endpoint on slot %d", slot));
1469 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1470 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1471 break;
1472
1473 case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */
1474 DPRINTF(("Stop Endpoint on slot %d", slot));
1475 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1476 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb);
1477 break;
1478
1479 case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */
1480 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1481 cmderr = pci_xhci_cmd_set_tr(sc, slot, trb);
1482 break;
1483
1484 case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */
1485 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);
1486 cmderr = pci_xhci_cmd_reset_device(sc, slot);
1487 break;
1488
1489 case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */
1490 /* TODO: */
1491 break;
1492
1493 case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */
1494 break;
1495
1496 case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */
1497 break;
1498
1499 case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */
1500 break;
1501
1502 case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */
1503 break;
1504
1505 case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */
1506 break;
1507
1508 default:
1509 DPRINTF(("pci_xhci: unsupported cmd %x", type));
1510 break;
1511 }
1512
1513 if (type != XHCI_TRB_TYPE_LINK) {
1514 /*
1515 * insert command completion event and assert intr
1516 */
1517 evtrb.qwTrb0 = crcr;
1518 evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr);
1519 evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot);
1520 DPRINTF(("pci_xhci: command 0x%x result: 0x%x",
1521 type, cmderr));
1522 pci_xhci_insert_event(sc, &evtrb, 1);
1523 }
1524
1525 trb = pci_xhci_trb_next(sc, trb, &crcr);
1526 }
1527
1528 sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs;
1529 sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR;
1530 return (error);
1531 }
1532
1533 static void
pci_xhci_dump_trb(struct xhci_trb * trb)1534 pci_xhci_dump_trb(struct xhci_trb *trb)
1535 {
1536 static const char *trbtypes[] = {
1537 "RESERVED",
1538 "NORMAL",
1539 "SETUP_STAGE",
1540 "DATA_STAGE",
1541 "STATUS_STAGE",
1542 "ISOCH",
1543 "LINK",
1544 "EVENT_DATA",
1545 "NOOP",
1546 "ENABLE_SLOT",
1547 "DISABLE_SLOT",
1548 "ADDRESS_DEVICE",
1549 "CONFIGURE_EP",
1550 "EVALUATE_CTX",
1551 "RESET_EP",
1552 "STOP_EP",
1553 "SET_TR_DEQUEUE",
1554 "RESET_DEVICE",
1555 "FORCE_EVENT",
1556 "NEGOTIATE_BW",
1557 "SET_LATENCY_TOL",
1558 "GET_PORT_BW",
1559 "FORCE_HEADER",
1560 "NOOP_CMD"
1561 };
1562 uint32_t type;
1563
1564 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);
1565 DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x",
1566 trb, type,
1567 type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID",
1568 trb->qwTrb0, trb->dwTrb2, trb->dwTrb3));
1569 }
1570
1571 static int
pci_xhci_xfer_complete(struct pci_xhci_softc * sc,struct usb_data_xfer * xfer,uint32_t slot,uint32_t epid,int * do_intr)1572 pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer,
1573 uint32_t slot, uint32_t epid, int *do_intr)
1574 {
1575 struct pci_xhci_dev_emu *dev;
1576 struct pci_xhci_dev_ep *devep;
1577 struct xhci_dev_ctx *dev_ctx;
1578 struct xhci_endp_ctx *ep_ctx;
1579 struct xhci_trb *trb;
1580 struct xhci_trb evtrb;
1581 uint32_t trbflags;
1582 uint32_t edtla;
1583 int i, err;
1584
1585 dev = XHCI_SLOTDEV_PTR(sc, slot);
1586 devep = &dev->eps[epid];
1587 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1588 if (dev_ctx == NULL) {
1589 return XHCI_TRB_ERROR_PARAMETER;
1590 }
1591
1592 ep_ctx = &dev_ctx->ctx_ep[epid];
1593
1594 err = XHCI_TRB_ERROR_SUCCESS;
1595 *do_intr = 0;
1596 edtla = 0;
1597
1598 /* go through list of TRBs and insert event(s) */
1599 for (i = xfer->head; xfer->ndata > 0; ) {
1600 evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data;
1601 trb = XHCI_GADDR(sc, evtrb.qwTrb0);
1602 trbflags = trb->dwTrb3;
1603
1604 DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x "
1605 "(err %d) IOC?%d",
1606 i, xfer->data[i].processed, xfer->data[i].blen,
1607 XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0,
1608 trbflags, err,
1609 trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0));
1610
1611 if (!xfer->data[i].processed) {
1612 xfer->head = i;
1613 break;
1614 }
1615
1616 xfer->ndata--;
1617 edtla += xfer->data[i].bdone;
1618
1619 trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs);
1620
1621 pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx,
1622 xfer->data[i].streamid, xfer->data[i].trbnext,
1623 xfer->data[i].ccs);
1624
1625 /* Only interrupt if IOC or short packet */
1626 if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) &&
1627 !((err == XHCI_TRB_ERROR_SHORT_PKT) &&
1628 (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) {
1629
1630 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1631 continue;
1632 }
1633
1634 evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) |
1635 XHCI_TRB_2_REM_SET(xfer->data[i].blen);
1636
1637 evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) |
1638 XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid);
1639
1640 if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) {
1641 DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla));
1642 evtrb.qwTrb0 = trb->qwTrb0;
1643 evtrb.dwTrb2 = (edtla & 0xFFFFF) |
1644 XHCI_TRB_2_ERROR_SET(err);
1645 evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT;
1646 edtla = 0;
1647 }
1648
1649 *do_intr = 1;
1650
1651 err = pci_xhci_insert_event(sc, &evtrb, 0);
1652 if (err != XHCI_TRB_ERROR_SUCCESS) {
1653 break;
1654 }
1655
1656 i = (i + 1) % USB_MAX_XFER_BLOCKS;
1657 }
1658
1659 return (err);
1660 }
1661
1662 static void
pci_xhci_update_ep_ring(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev __unused,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,uint32_t streamid,uint64_t ringaddr,int ccs)1663 pci_xhci_update_ep_ring(struct pci_xhci_softc *sc,
1664 struct pci_xhci_dev_emu *dev __unused, struct pci_xhci_dev_ep *devep,
1665 struct xhci_endp_ctx *ep_ctx, uint32_t streamid, uint64_t ringaddr, int ccs)
1666 {
1667
1668 if (devep->ep_MaxPStreams != 0) {
1669 devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) |
1670 (ccs & 0x1);
1671
1672 devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL;
1673 devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1;
1674 ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1);
1675
1676 DPRINTF(("xhci update ep-ring stream %d, addr %lx",
1677 streamid, devep->ep_sctx[streamid].qwSctx0));
1678 } else {
1679 devep->ep_ringaddr = ringaddr & ~0xFUL;
1680 devep->ep_ccs = ccs & 0x1;
1681 devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL);
1682 ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1);
1683
1684 DPRINTF(("xhci update ep-ring, addr %lx",
1685 (devep->ep_ringaddr | devep->ep_ccs)));
1686 }
1687 }
1688
1689 static int
pci_xhci_validate_slot(uint32_t slot)1690 pci_xhci_validate_slot(uint32_t slot)
1691 {
1692 if (slot == 0)
1693 return (XHCI_TRB_ERROR_TRB);
1694 else if (slot > XHCI_MAX_SLOTS)
1695 return (XHCI_TRB_ERROR_SLOT_NOT_ON);
1696 else
1697 return (XHCI_TRB_ERROR_SUCCESS);
1698 }
1699
1700 /*
1701 * Outstanding transfer still in progress (device NAK'd earlier) so retry
1702 * the transfer again to see if it succeeds.
1703 */
1704 static int
pci_xhci_try_usb_xfer(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,uint32_t slot,uint32_t epid)1705 pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc,
1706 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1707 struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid)
1708 {
1709 struct usb_data_xfer *xfer;
1710 int err;
1711 int do_intr;
1712
1713 ep_ctx->dwEpCtx0 = FIELD_REPLACE(
1714 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1715
1716 err = 0;
1717 do_intr = 0;
1718
1719 xfer = devep->ep_xfer;
1720 #ifdef __FreeBSD__
1721 USB_DATA_XFER_LOCK(xfer);
1722 #else
1723 /*
1724 * At least one caller needs to hold this lock across the call to this
1725 * function and other code. To avoid deadlock from a recursive mutex
1726 * enter, we ensure that all callers hold this lock.
1727 */
1728 assert(USB_DATA_XFER_LOCK_HELD(xfer));
1729 #endif
1730
1731 /* outstanding requests queued up */
1732 if (dev->dev_ue->ue_data != NULL) {
1733 err = dev->dev_ue->ue_data(dev->dev_sc, xfer,
1734 epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2);
1735 if (err == USB_ERR_CANCELLED) {
1736 if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) ==
1737 USB_NAK)
1738 err = XHCI_TRB_ERROR_SUCCESS;
1739 } else {
1740 err = pci_xhci_xfer_complete(sc, xfer, slot, epid,
1741 &do_intr);
1742 if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) {
1743 pci_xhci_assert_interrupt(sc);
1744 }
1745
1746
1747 /* XXX should not do it if error? */
1748 USB_DATA_XFER_RESET(xfer);
1749 }
1750 }
1751
1752 #ifdef __FreeBSD__
1753 USB_DATA_XFER_UNLOCK(xfer);
1754 #endif
1755
1756 return (err);
1757 }
1758
1759
1760 static int
pci_xhci_handle_transfer(struct pci_xhci_softc * sc,struct pci_xhci_dev_emu * dev,struct pci_xhci_dev_ep * devep,struct xhci_endp_ctx * ep_ctx,struct xhci_trb * trb,uint32_t slot,uint32_t epid,uint64_t addr,uint32_t ccs,uint32_t streamid)1761 pci_xhci_handle_transfer(struct pci_xhci_softc *sc,
1762 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep,
1763 struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot,
1764 uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid)
1765 {
1766 struct xhci_trb *setup_trb;
1767 struct usb_data_xfer *xfer;
1768 struct usb_data_xfer_block *xfer_block;
1769 uint64_t val;
1770 uint32_t trbflags;
1771 int do_intr, err;
1772 int do_retry;
1773
1774 ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0,
1775 XHCI_ST_EPCTX_RUNNING, 0x7, 0);
1776
1777 xfer = devep->ep_xfer;
1778 USB_DATA_XFER_LOCK(xfer);
1779
1780 DPRINTF(("pci_xhci handle_transfer slot %u", slot));
1781
1782 retry:
1783 err = XHCI_TRB_ERROR_INVALID;
1784 do_retry = 0;
1785 do_intr = 0;
1786 setup_trb = NULL;
1787
1788 while (1) {
1789 pci_xhci_dump_trb(trb);
1790
1791 trbflags = trb->dwTrb3;
1792
1793 if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK &&
1794 (trbflags & XHCI_TRB_3_CYCLE_BIT) !=
1795 (ccs & XHCI_TRB_3_CYCLE_BIT)) {
1796 DPRINTF(("Cycle-bit changed trbflags %x, ccs %x",
1797 trbflags & XHCI_TRB_3_CYCLE_BIT, ccs));
1798 break;
1799 }
1800
1801 xfer_block = NULL;
1802
1803 switch (XHCI_TRB_3_TYPE_GET(trbflags)) {
1804 case XHCI_TRB_TYPE_LINK:
1805 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)
1806 ccs ^= 0x1;
1807
1808 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1809 (void *)addr, ccs);
1810 xfer_block->processed = 1;
1811 break;
1812
1813 case XHCI_TRB_TYPE_SETUP_STAGE:
1814 if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 ||
1815 XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) {
1816 DPRINTF(("pci_xhci: invalid setup trb"));
1817 err = XHCI_TRB_ERROR_TRB;
1818 goto errout;
1819 }
1820 setup_trb = trb;
1821
1822 val = trb->qwTrb0;
1823 if (!xfer->ureq)
1824 xfer->ureq = malloc(
1825 sizeof(struct usb_device_request));
1826 memcpy(xfer->ureq, &val,
1827 sizeof(struct usb_device_request));
1828
1829 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1830 (void *)addr, ccs);
1831 xfer_block->processed = 1;
1832 break;
1833
1834 case XHCI_TRB_TYPE_NORMAL:
1835 case XHCI_TRB_TYPE_ISOCH:
1836 if (setup_trb != NULL) {
1837 DPRINTF(("pci_xhci: trb not supposed to be in "
1838 "ctl scope"));
1839 err = XHCI_TRB_ERROR_TRB;
1840 goto errout;
1841 }
1842 /* fall through */
1843
1844 case XHCI_TRB_TYPE_DATA_STAGE:
1845 xfer_block = usb_data_xfer_append(xfer,
1846 (void *)(trbflags & XHCI_TRB_3_IDT_BIT ?
1847 &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)),
1848 trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs);
1849 break;
1850
1851 case XHCI_TRB_TYPE_STATUS_STAGE:
1852 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1853 (void *)addr, ccs);
1854 break;
1855
1856 case XHCI_TRB_TYPE_NOOP:
1857 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1858 (void *)addr, ccs);
1859 xfer_block->processed = 1;
1860 break;
1861
1862 case XHCI_TRB_TYPE_EVENT_DATA:
1863 xfer_block = usb_data_xfer_append(xfer, NULL, 0,
1864 (void *)addr, ccs);
1865 if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) {
1866 xfer_block->processed = 1;
1867 }
1868 break;
1869
1870 default:
1871 DPRINTF(("pci_xhci: handle xfer unexpected trb type "
1872 "0x%x",
1873 XHCI_TRB_3_TYPE_GET(trbflags)));
1874 err = XHCI_TRB_ERROR_TRB;
1875 goto errout;
1876 }
1877
1878 trb = pci_xhci_trb_next(sc, trb, &addr);
1879
1880 DPRINTF(("pci_xhci: next trb: 0x%lx", (uint64_t)trb));
1881
1882 if (xfer_block) {
1883 xfer_block->trbnext = addr;
1884 xfer_block->streamid = streamid;
1885 }
1886
1887 if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) &&
1888 XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) {
1889 break;
1890 }
1891
1892 /* handle current batch that requires interrupt on complete */
1893 if (trbflags & XHCI_TRB_3_IOC_BIT) {
1894 DPRINTF(("pci_xhci: trb IOC bit set"));
1895 if (epid == 1)
1896 do_retry = 1;
1897 break;
1898 }
1899 }
1900
1901 DPRINTF(("pci_xhci[%d]: xfer->ndata %u", __LINE__, xfer->ndata));
1902
1903 if (xfer->ndata <= 0)
1904 goto errout;
1905
1906 if (epid == 1) {
1907 int usberr;
1908
1909 if (dev->dev_ue->ue_request != NULL)
1910 usberr = dev->dev_ue->ue_request(dev->dev_sc, xfer);
1911 else
1912 usberr = USB_ERR_NOT_STARTED;
1913 err = USB_TO_XHCI_ERR(usberr);
1914 if (err == XHCI_TRB_ERROR_SUCCESS ||
1915 err == XHCI_TRB_ERROR_STALL ||
1916 err == XHCI_TRB_ERROR_SHORT_PKT) {
1917 err = pci_xhci_xfer_complete(sc, xfer, slot, epid,
1918 &do_intr);
1919 if (err != XHCI_TRB_ERROR_SUCCESS)
1920 do_retry = 0;
1921 }
1922
1923 } else {
1924 /* handle data transfer */
1925 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
1926 err = XHCI_TRB_ERROR_SUCCESS;
1927 }
1928
1929 errout:
1930 if (err == XHCI_TRB_ERROR_EV_RING_FULL)
1931 DPRINTF(("pci_xhci[%d]: event ring full", __LINE__));
1932
1933 if (!do_retry)
1934 USB_DATA_XFER_UNLOCK(xfer);
1935
1936 if (do_intr)
1937 pci_xhci_assert_interrupt(sc);
1938
1939 if (do_retry) {
1940 USB_DATA_XFER_RESET(xfer);
1941 DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs",
1942 __LINE__));
1943 goto retry;
1944 }
1945
1946 if (epid == 1)
1947 USB_DATA_XFER_RESET(xfer);
1948
1949 return (err);
1950 }
1951
1952 static void
pci_xhci_device_doorbell(struct pci_xhci_softc * sc,uint32_t slot,uint32_t epid,uint32_t streamid)1953 pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot,
1954 uint32_t epid, uint32_t streamid)
1955 {
1956 struct pci_xhci_dev_emu *dev;
1957 struct pci_xhci_dev_ep *devep;
1958 struct xhci_dev_ctx *dev_ctx;
1959 struct xhci_endp_ctx *ep_ctx;
1960 struct pci_xhci_trb_ring *sctx_tr;
1961 struct xhci_trb *trb;
1962 uint64_t ringaddr;
1963 uint32_t ccs;
1964 int error;
1965
1966 DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u",
1967 slot, epid, streamid));
1968
1969 if (slot == 0 || slot > XHCI_MAX_SLOTS) {
1970 DPRINTF(("pci_xhci: invalid doorbell slot %u", slot));
1971 return;
1972 }
1973
1974 if (epid == 0 || epid >= XHCI_MAX_ENDPOINTS) {
1975 DPRINTF(("pci_xhci: invalid endpoint %u", epid));
1976 return;
1977 }
1978
1979 dev = XHCI_SLOTDEV_PTR(sc, slot);
1980 devep = &dev->eps[epid];
1981 dev_ctx = pci_xhci_get_dev_ctx(sc, slot);
1982 if (!dev_ctx) {
1983 return;
1984 }
1985 ep_ctx = &dev_ctx->ctx_ep[epid];
1986
1987 sctx_tr = NULL;
1988
1989 DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x",
1990 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2,
1991 ep_ctx->dwEpCtx4));
1992
1993 if (ep_ctx->qwEpCtx2 == 0)
1994 return;
1995
1996 /* handle pending transfers */
1997 if (devep->ep_xfer->ndata > 0) {
1998 #ifndef __FreeBSD__
1999 USB_DATA_XFER_LOCK(devep->ep_xfer);
2000 #endif
2001 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid);
2002 #ifndef __FreeBSD__
2003 USB_DATA_XFER_UNLOCK(devep->ep_xfer);
2004 #endif
2005 return;
2006 }
2007
2008 /* get next trb work item */
2009 if (devep->ep_MaxPStreams != 0) {
2010 /*
2011 * Stream IDs of 0, 65535 (any stream), and 65534
2012 * (prime) are invalid.
2013 */
2014 if (streamid == 0 || streamid == 65534 || streamid == 65535) {
2015 DPRINTF(("pci_xhci: invalid stream %u", streamid));
2016 return;
2017 }
2018
2019 error = pci_xhci_find_stream(sc, ep_ctx, devep, streamid);
2020 if (error != XHCI_TRB_ERROR_SUCCESS) {
2021 DPRINTF(("pci_xhci: invalid stream %u: %d",
2022 streamid, error));
2023 return;
2024 }
2025 sctx_tr = &devep->ep_sctx_trbs[streamid];
2026 ringaddr = sctx_tr->ringaddr;
2027 ccs = sctx_tr->ccs;
2028 trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL);
2029 DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x",
2030 streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
2031 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
2032 } else {
2033 if (streamid != 0) {
2034 DPRINTF(("pci_xhci: invalid stream %u", streamid));
2035 return;
2036 }
2037 ringaddr = devep->ep_ringaddr;
2038 ccs = devep->ep_ccs;
2039 trb = devep->ep_tr;
2040 DPRINTF(("doorbell, ccs %lx, trb ccs %x",
2041 ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT,
2042 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));
2043 }
2044
2045 if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) {
2046 DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?",
2047 ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid));
2048 return;
2049 }
2050
2051 pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid,
2052 ringaddr, ccs, streamid);
2053 }
2054
2055 static void
pci_xhci_dbregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2056 pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset,
2057 uint64_t value)
2058 {
2059
2060 offset = (offset - sc->dboff) / sizeof(uint32_t);
2061
2062 DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx",
2063 offset, value));
2064
2065 if (XHCI_HALTED(sc)) {
2066 DPRINTF(("pci_xhci: controller halted"));
2067 return;
2068 }
2069
2070 if (offset == 0)
2071 pci_xhci_complete_commands(sc);
2072 else if (sc->portregs != NULL)
2073 pci_xhci_device_doorbell(sc, offset,
2074 XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value));
2075 }
2076
2077 static void
pci_xhci_rtsregs_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2078 pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset,
2079 uint64_t value)
2080 {
2081 struct pci_xhci_rtsregs *rts;
2082
2083 offset -= sc->rtsoff;
2084
2085 if (offset == 0) {
2086 DPRINTF(("pci_xhci attempted write to MFINDEX"));
2087 return;
2088 }
2089
2090 DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx",
2091 offset, value));
2092
2093 offset -= 0x20; /* start of intrreg */
2094
2095 rts = &sc->rtsregs;
2096
2097 switch (offset) {
2098 case 0x00:
2099 if (value & XHCI_IMAN_INTR_PEND)
2100 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2101 rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) |
2102 (rts->intrreg.iman & XHCI_IMAN_INTR_PEND);
2103
2104 if (!(value & XHCI_IMAN_INTR_ENA))
2105 pci_xhci_deassert_interrupt(sc);
2106
2107 break;
2108
2109 case 0x04:
2110 rts->intrreg.imod = value;
2111 break;
2112
2113 case 0x08:
2114 rts->intrreg.erstsz = value & 0xFFFF;
2115 break;
2116
2117 case 0x10:
2118 /* ERSTBA low bits */
2119 rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) |
2120 (value & ~0x3F);
2121 break;
2122
2123 case 0x14:
2124 /* ERSTBA high bits */
2125 rts->intrreg.erstba = (value << 32) |
2126 MASK_64_LO(sc->rtsregs.intrreg.erstba);
2127
2128 rts->erstba_p = XHCI_GADDR(sc,
2129 sc->rtsregs.intrreg.erstba & ~0x3FUL);
2130
2131 rts->erst_p = XHCI_GADDR(sc,
2132 sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL);
2133
2134 rts->er_enq_idx = 0;
2135 rts->er_events_cnt = 0;
2136
2137 DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u",
2138 rts->erstba_p,
2139 rts->erstba_p->qwEvrsTablePtr,
2140 rts->erstba_p->dwEvrsTableSize));
2141 break;
2142
2143 case 0x18:
2144 /* ERDP low bits */
2145 rts->intrreg.erdp =
2146 MASK_64_HI(sc->rtsregs.intrreg.erdp) |
2147 (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) |
2148 (value & ~0xF);
2149 if (value & XHCI_ERDP_LO_BUSY) {
2150 rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY;
2151 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND;
2152 }
2153
2154 rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value);
2155
2156 break;
2157
2158 case 0x1C:
2159 /* ERDP high bits */
2160 rts->intrreg.erdp = (value << 32) |
2161 MASK_64_LO(sc->rtsregs.intrreg.erdp);
2162
2163 if (rts->er_events_cnt > 0) {
2164 uint64_t erdp;
2165 int erdp_i;
2166
2167 erdp = rts->intrreg.erdp & ~0xF;
2168 erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) /
2169 sizeof(struct xhci_trb);
2170
2171 if (erdp_i <= rts->er_enq_idx)
2172 rts->er_events_cnt = rts->er_enq_idx - erdp_i;
2173 else
2174 rts->er_events_cnt =
2175 rts->erstba_p->dwEvrsTableSize -
2176 (erdp_i - rts->er_enq_idx);
2177
2178 DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u",
2179 erdp, rts->er_events_cnt));
2180 }
2181
2182 break;
2183
2184 default:
2185 DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx",
2186 offset));
2187 break;
2188 }
2189 }
2190
2191 static uint64_t
pci_xhci_portregs_read(struct pci_xhci_softc * sc,uint64_t offset)2192 pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2193 {
2194 struct pci_xhci_portregs *portregs;
2195 int port;
2196 uint32_t reg;
2197
2198 if (sc->portregs == NULL)
2199 return (0);
2200
2201 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ;
2202 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ;
2203
2204 if (port > XHCI_MAX_DEVS) {
2205 DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS",
2206 port));
2207
2208 /* return default value for unused port */
2209 return (XHCI_PS_SPEED_SET(3));
2210 }
2211
2212 portregs = XHCI_PORTREG_PTR(sc, port);
2213 switch (offset) {
2214 case 0:
2215 reg = portregs->portsc;
2216 break;
2217 case 4:
2218 reg = portregs->portpmsc;
2219 break;
2220 case 8:
2221 reg = portregs->portli;
2222 break;
2223 case 12:
2224 reg = portregs->porthlpmc;
2225 break;
2226 default:
2227 DPRINTF(("pci_xhci: unaligned portregs read offset %#lx",
2228 offset));
2229 reg = 0xffffffff;
2230 break;
2231 }
2232
2233 DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x",
2234 offset, port, reg));
2235
2236 return (reg);
2237 }
2238
2239 static void
pci_xhci_hostop_write(struct pci_xhci_softc * sc,uint64_t offset,uint64_t value)2240 pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset,
2241 uint64_t value)
2242 {
2243 offset -= XHCI_CAPLEN;
2244
2245 if (offset < 0x400)
2246 DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx",
2247 offset, value));
2248
2249 switch (offset) {
2250 case XHCI_USBCMD:
2251 sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F);
2252 break;
2253
2254 case XHCI_USBSTS:
2255 /* clear bits on write */
2256 sc->opregs.usbsts &= ~(value &
2257 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS|
2258 XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR));
2259 break;
2260
2261 case XHCI_PAGESIZE:
2262 /* read only */
2263 break;
2264
2265 case XHCI_DNCTRL:
2266 sc->opregs.dnctrl = value & 0xFFFF;
2267 break;
2268
2269 case XHCI_CRCR_LO:
2270 if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) {
2271 sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2272 sc->opregs.crcr |= value &
2273 (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA);
2274 } else {
2275 sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) |
2276 (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS));
2277 }
2278 break;
2279
2280 case XHCI_CRCR_HI:
2281 if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) {
2282 sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) |
2283 (value << 32);
2284
2285 sc->opregs.cr_p = XHCI_GADDR(sc,
2286 sc->opregs.crcr & ~0xF);
2287 }
2288
2289 if (sc->opregs.crcr & XHCI_CRCR_LO_CS) {
2290 /* Stop operation of Command Ring */
2291 }
2292
2293 if (sc->opregs.crcr & XHCI_CRCR_LO_CA) {
2294 /* Abort command */
2295 }
2296
2297 break;
2298
2299 case XHCI_DCBAAP_LO:
2300 sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) |
2301 (value & 0xFFFFFFC0);
2302 break;
2303
2304 case XHCI_DCBAAP_HI:
2305 sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) |
2306 (value << 32);
2307 sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL);
2308
2309 DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)",
2310 sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p));
2311 break;
2312
2313 case XHCI_CONFIG:
2314 sc->opregs.config = value & 0x03FF;
2315 break;
2316
2317 default:
2318 if (offset >= 0x400)
2319 pci_xhci_portregs_write(sc, offset, value);
2320
2321 break;
2322 }
2323 }
2324
2325
2326 static void
pci_xhci_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size __unused,uint64_t value)2327 pci_xhci_write(struct pci_devinst *pi, int baridx, uint64_t offset,
2328 int size __unused, uint64_t value)
2329 {
2330 struct pci_xhci_softc *sc;
2331
2332 sc = pi->pi_arg;
2333
2334 assert(baridx == 0);
2335
2336
2337 pthread_mutex_lock(&sc->mtx);
2338 if (offset < XHCI_CAPLEN) /* read only registers */
2339 WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset));
2340 else if (offset < sc->dboff)
2341 pci_xhci_hostop_write(sc, offset, value);
2342 else if (offset < sc->rtsoff)
2343 pci_xhci_dbregs_write(sc, offset, value);
2344 else if (offset < sc->regsend)
2345 pci_xhci_rtsregs_write(sc, offset, value);
2346 else
2347 WPRINTF(("pci_xhci: write invalid offset %ld", offset));
2348
2349 pthread_mutex_unlock(&sc->mtx);
2350 }
2351
2352 static uint64_t
pci_xhci_hostcap_read(struct pci_xhci_softc * sc,uint64_t offset)2353 pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset)
2354 {
2355 uint64_t value;
2356
2357 switch (offset) {
2358 case XHCI_CAPLENGTH: /* 0x00 */
2359 value = sc->caplength;
2360 break;
2361
2362 case XHCI_HCSPARAMS1: /* 0x04 */
2363 value = sc->hcsparams1;
2364 break;
2365
2366 case XHCI_HCSPARAMS2: /* 0x08 */
2367 value = sc->hcsparams2;
2368 break;
2369
2370 case XHCI_HCSPARAMS3: /* 0x0C */
2371 value = sc->hcsparams3;
2372 break;
2373
2374 case XHCI_HCSPARAMS0: /* 0x10 */
2375 value = sc->hccparams1;
2376 break;
2377
2378 case XHCI_DBOFF: /* 0x14 */
2379 value = sc->dboff;
2380 break;
2381
2382 case XHCI_RTSOFF: /* 0x18 */
2383 value = sc->rtsoff;
2384 break;
2385
2386 case XHCI_HCCPRAMS2: /* 0x1C */
2387 value = sc->hccparams2;
2388 break;
2389
2390 default:
2391 value = 0;
2392 break;
2393 }
2394
2395 DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx",
2396 offset, value));
2397
2398 return (value);
2399 }
2400
2401 static uint64_t
pci_xhci_hostop_read(struct pci_xhci_softc * sc,uint64_t offset)2402 pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset)
2403 {
2404 uint64_t value;
2405
2406 offset = (offset - XHCI_CAPLEN);
2407
2408 switch (offset) {
2409 case XHCI_USBCMD: /* 0x00 */
2410 value = sc->opregs.usbcmd;
2411 break;
2412
2413 case XHCI_USBSTS: /* 0x04 */
2414 value = sc->opregs.usbsts;
2415 break;
2416
2417 case XHCI_PAGESIZE: /* 0x08 */
2418 value = sc->opregs.pgsz;
2419 break;
2420
2421 case XHCI_DNCTRL: /* 0x14 */
2422 value = sc->opregs.dnctrl;
2423 break;
2424
2425 case XHCI_CRCR_LO: /* 0x18 */
2426 value = sc->opregs.crcr & XHCI_CRCR_LO_CRR;
2427 break;
2428
2429 case XHCI_CRCR_HI: /* 0x1C */
2430 value = 0;
2431 break;
2432
2433 case XHCI_DCBAAP_LO: /* 0x30 */
2434 value = sc->opregs.dcbaap & 0xFFFFFFFF;
2435 break;
2436
2437 case XHCI_DCBAAP_HI: /* 0x34 */
2438 value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF;
2439 break;
2440
2441 case XHCI_CONFIG: /* 0x38 */
2442 value = sc->opregs.config;
2443 break;
2444
2445 default:
2446 if (offset >= 0x400)
2447 value = pci_xhci_portregs_read(sc, offset);
2448 else
2449 value = 0;
2450
2451 break;
2452 }
2453
2454 if (offset < 0x400)
2455 DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx",
2456 offset, value));
2457
2458 return (value);
2459 }
2460
2461 static uint64_t
pci_xhci_dbregs_read(struct pci_xhci_softc * sc __unused,uint64_t offset __unused)2462 pci_xhci_dbregs_read(struct pci_xhci_softc *sc __unused,
2463 uint64_t offset __unused)
2464 {
2465 /* read doorbell always returns 0 */
2466 return (0);
2467 }
2468
2469 static uint64_t
pci_xhci_rtsregs_read(struct pci_xhci_softc * sc,uint64_t offset)2470 pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset)
2471 {
2472 uint32_t value;
2473
2474 offset -= sc->rtsoff;
2475 value = 0;
2476
2477 if (offset == XHCI_MFINDEX) {
2478 value = sc->rtsregs.mfindex;
2479 } else if (offset >= 0x20) {
2480 int item;
2481 uint32_t *p;
2482
2483 offset -= 0x20;
2484 item = offset % 32;
2485
2486 assert(offset < sizeof(sc->rtsregs.intrreg));
2487
2488 p = &sc->rtsregs.intrreg.iman;
2489 p += item / sizeof(uint32_t);
2490 value = *p;
2491 }
2492
2493 DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x",
2494 offset, value));
2495
2496 return (value);
2497 }
2498
2499 static uint64_t
pci_xhci_xecp_read(struct pci_xhci_softc * sc,uint64_t offset)2500 pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset)
2501 {
2502 uint32_t value;
2503
2504 offset -= sc->regsend;
2505 value = 0;
2506
2507 switch (offset) {
2508 case 0:
2509 /* rev major | rev minor | next-cap | cap-id */
2510 value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS;
2511 break;
2512 case 4:
2513 /* name string = "USB" */
2514 value = 0x20425355;
2515 break;
2516 case 8:
2517 /* psic | proto-defined | compat # | compat offset */
2518 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start;
2519 break;
2520 case 12:
2521 break;
2522 case 16:
2523 /* rev major | rev minor | next-cap | cap-id */
2524 value = (0x03 << 24) | XHCI_ID_PROTOCOLS;
2525 break;
2526 case 20:
2527 /* name string = "USB" */
2528 value = 0x20425355;
2529 break;
2530 case 24:
2531 /* psic | proto-defined | compat # | compat offset */
2532 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start;
2533 break;
2534 case 28:
2535 break;
2536 default:
2537 DPRINTF(("pci_xhci: xecp invalid offset 0x%lx", offset));
2538 break;
2539 }
2540
2541 DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x",
2542 offset, value));
2543
2544 return (value);
2545 }
2546
2547
2548 static uint64_t
pci_xhci_read(struct pci_devinst * pi,int baridx,uint64_t offset,int size)2549 pci_xhci_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2550 {
2551 struct pci_xhci_softc *sc;
2552 uint32_t value;
2553
2554 sc = pi->pi_arg;
2555
2556 assert(baridx == 0);
2557
2558 pthread_mutex_lock(&sc->mtx);
2559 if (offset < XHCI_CAPLEN)
2560 value = pci_xhci_hostcap_read(sc, offset);
2561 else if (offset < sc->dboff)
2562 value = pci_xhci_hostop_read(sc, offset);
2563 else if (offset < sc->rtsoff)
2564 value = pci_xhci_dbregs_read(sc, offset);
2565 else if (offset < sc->regsend)
2566 value = pci_xhci_rtsregs_read(sc, offset);
2567 else if (offset < (sc->regsend + 4*32))
2568 value = pci_xhci_xecp_read(sc, offset);
2569 else {
2570 value = 0;
2571 WPRINTF(("pci_xhci: read invalid offset %ld", offset));
2572 }
2573
2574 pthread_mutex_unlock(&sc->mtx);
2575
2576 switch (size) {
2577 case 1:
2578 value &= 0xFF;
2579 break;
2580 case 2:
2581 value &= 0xFFFF;
2582 break;
2583 case 4:
2584 value &= 0xFFFFFFFF;
2585 break;
2586 }
2587
2588 return (value);
2589 }
2590
2591 static void
pci_xhci_reset_port(struct pci_xhci_softc * sc,int portn,int warm)2592 pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm)
2593 {
2594 struct pci_xhci_portregs *port;
2595 struct pci_xhci_dev_emu *dev;
2596 struct xhci_trb evtrb;
2597 int error;
2598
2599 assert(portn <= XHCI_MAX_DEVS);
2600
2601 DPRINTF(("xhci reset port %d", portn));
2602
2603 port = XHCI_PORTREG_PTR(sc, portn);
2604 dev = XHCI_DEVINST_PTR(sc, portn);
2605 if (dev) {
2606 port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC);
2607 port->portsc |= XHCI_PS_PED |
2608 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2609
2610 if (warm && dev->dev_ue->ue_usbver == 3) {
2611 port->portsc |= XHCI_PS_WRC;
2612 }
2613
2614 if ((port->portsc & XHCI_PS_PRC) == 0) {
2615 port->portsc |= XHCI_PS_PRC;
2616
2617 pci_xhci_set_evtrb(&evtrb, portn,
2618 XHCI_TRB_ERROR_SUCCESS,
2619 XHCI_TRB_EVENT_PORT_STS_CHANGE);
2620 error = pci_xhci_insert_event(sc, &evtrb, 1);
2621 if (error != XHCI_TRB_ERROR_SUCCESS)
2622 DPRINTF(("xhci reset port insert event "
2623 "failed"));
2624 }
2625 }
2626 }
2627
2628 static void
pci_xhci_init_port(struct pci_xhci_softc * sc,int portn)2629 pci_xhci_init_port(struct pci_xhci_softc *sc, int portn)
2630 {
2631 struct pci_xhci_portregs *port;
2632 struct pci_xhci_dev_emu *dev;
2633
2634 port = XHCI_PORTREG_PTR(sc, portn);
2635 dev = XHCI_DEVINST_PTR(sc, portn);
2636 if (dev) {
2637 port->portsc = XHCI_PS_CCS | /* connected */
2638 XHCI_PS_PP; /* port power */
2639
2640 if (dev->dev_ue->ue_usbver == 2) {
2641 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) |
2642 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2643 } else {
2644 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) |
2645 XHCI_PS_PED | /* enabled */
2646 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed);
2647 }
2648
2649 DPRINTF(("Init port %d 0x%x", portn, port->portsc));
2650 } else {
2651 port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP;
2652 DPRINTF(("Init empty port %d 0x%x", portn, port->portsc));
2653 }
2654 }
2655
2656 static int
pci_xhci_dev_intr(struct usb_hci * hci,int epctx)2657 pci_xhci_dev_intr(struct usb_hci *hci, int epctx)
2658 {
2659 struct pci_xhci_dev_emu *dev;
2660 struct xhci_dev_ctx *dev_ctx;
2661 struct xhci_trb evtrb;
2662 struct pci_xhci_softc *sc;
2663 struct pci_xhci_portregs *p;
2664 struct xhci_endp_ctx *ep_ctx;
2665 int error = 0;
2666 int dir_in;
2667 int epid;
2668
2669 dir_in = epctx & 0x80;
2670 epid = epctx & ~0x80;
2671
2672 /* HW endpoint contexts are 0-15; convert to epid based on dir */
2673 epid = (epid * 2) + (dir_in ? 1 : 0);
2674
2675 assert(epid >= 1 && epid <= 31);
2676
2677 dev = hci->hci_sc;
2678 sc = dev->xsc;
2679
2680 /* check if device is ready; OS has to initialise it */
2681 if (sc->rtsregs.erstba_p == NULL ||
2682 (sc->opregs.usbcmd & XHCI_CMD_RS) == 0 ||
2683 dev->dev_ctx == NULL)
2684 return (0);
2685
2686 p = XHCI_PORTREG_PTR(sc, hci->hci_port);
2687
2688 /* raise event if link U3 (suspended) state */
2689 if (XHCI_PS_PLS_GET(p->portsc) == 3) {
2690 p->portsc &= ~XHCI_PS_PLS_MASK;
2691 p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME);
2692 if ((p->portsc & XHCI_PS_PLC) != 0)
2693 return (0);
2694
2695 p->portsc |= XHCI_PS_PLC;
2696
2697 pci_xhci_set_evtrb(&evtrb, hci->hci_port,
2698 XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE);
2699 error = pci_xhci_insert_event(sc, &evtrb, 0);
2700 if (error != XHCI_TRB_ERROR_SUCCESS)
2701 goto done;
2702 }
2703
2704 dev_ctx = dev->dev_ctx;
2705 ep_ctx = &dev_ctx->ctx_ep[epid];
2706 if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) {
2707 DPRINTF(("xhci device interrupt on disabled endpoint %d",
2708 epid));
2709 return (0);
2710 }
2711
2712 DPRINTF(("xhci device interrupt on endpoint %d", epid));
2713
2714 pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0);
2715
2716 done:
2717 return (error);
2718 }
2719
2720 static int
pci_xhci_dev_event(struct usb_hci * hci,enum hci_usbev evid __unused,void * param __unused)2721 pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid __unused,
2722 void *param __unused)
2723 {
2724 DPRINTF(("xhci device event port %d", hci->hci_port));
2725 return (0);
2726 }
2727
2728 /*
2729 * Each controller contains a "slot" node which contains a list of
2730 * child nodes each of which is a device. Each slot node's name
2731 * corresponds to a specific controller slot. These nodes
2732 * contain a "device" variable identifying the device model of the
2733 * USB device. For example:
2734 *
2735 * pci.0.1.0
2736 * .device="xhci"
2737 * .slot
2738 * .1
2739 * .device="tablet"
2740 */
2741 static int
pci_xhci_legacy_config(nvlist_t * nvl,const char * opts)2742 pci_xhci_legacy_config(nvlist_t *nvl, const char *opts)
2743 {
2744 char node_name[16];
2745 nvlist_t *slots_nvl, *slot_nvl;
2746 char *cp, *opt, *str, *tofree;
2747 int slot;
2748
2749 if (opts == NULL)
2750 return (0);
2751
2752 slots_nvl = create_relative_config_node(nvl, "slot");
2753 slot = 1;
2754 tofree = str = strdup(opts);
2755 while ((opt = strsep(&str, ",")) != NULL) {
2756 /* device[=<config>] */
2757 cp = strchr(opt, '=');
2758 if (cp != NULL) {
2759 *cp = '\0';
2760 cp++;
2761 }
2762
2763 snprintf(node_name, sizeof(node_name), "%d", slot);
2764 slot++;
2765 slot_nvl = create_relative_config_node(slots_nvl, node_name);
2766 set_config_value_node(slot_nvl, "device", opt);
2767
2768 /*
2769 * NB: Given that we split on commas above, the legacy
2770 * format only supports a single option.
2771 */
2772 if (cp != NULL && *cp != '\0')
2773 pci_parse_legacy_config(slot_nvl, cp);
2774 }
2775 free(tofree);
2776 return (0);
2777 }
2778
2779 static int
pci_xhci_parse_devices(struct pci_xhci_softc * sc,nvlist_t * nvl)2780 pci_xhci_parse_devices(struct pci_xhci_softc *sc, nvlist_t *nvl)
2781 {
2782 struct pci_xhci_dev_emu *dev;
2783 struct usb_devemu *ue;
2784 const nvlist_t *slots_nvl, *slot_nvl;
2785 const char *name, *device;
2786 char *cp;
2787 void *devsc, *cookie;
2788 long slot;
2789 int type, usb3_port, usb2_port, i, ndevices;
2790
2791 usb3_port = sc->usb3_port_start;
2792 usb2_port = sc->usb2_port_start;
2793
2794 sc->devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *));
2795 sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *));
2796
2797 ndevices = 0;
2798
2799 slots_nvl = find_relative_config_node(nvl, "slot");
2800 if (slots_nvl == NULL)
2801 goto portsfinal;
2802
2803 cookie = NULL;
2804 while ((name = nvlist_next(slots_nvl, &type, &cookie)) != NULL) {
2805 if (usb2_port == ((sc->usb2_port_start) + XHCI_MAX_DEVS/2) ||
2806 usb3_port == ((sc->usb3_port_start) + XHCI_MAX_DEVS/2)) {
2807 WPRINTF(("pci_xhci max number of USB 2 or 3 "
2808 "devices reached, max %d", XHCI_MAX_DEVS/2));
2809 goto bad;
2810 }
2811
2812 if (type != NV_TYPE_NVLIST) {
2813 EPRINTLN(
2814 "pci_xhci: config variable '%s' under slot node",
2815 name);
2816 goto bad;
2817 }
2818
2819 slot = strtol(name, &cp, 0);
2820 if (*cp != '\0' || slot <= 0 || slot > XHCI_MAX_SLOTS) {
2821 EPRINTLN("pci_xhci: invalid slot '%s'", name);
2822 goto bad;
2823 }
2824
2825 if (XHCI_SLOTDEV_PTR(sc, slot) != NULL) {
2826 EPRINTLN("pci_xhci: duplicate slot '%s'", name);
2827 goto bad;
2828 }
2829
2830 slot_nvl = nvlist_get_nvlist(slots_nvl, name);
2831 device = get_config_value_node(slot_nvl, "device");
2832 if (device == NULL) {
2833 EPRINTLN(
2834 "pci_xhci: missing \"device\" value for slot '%s'",
2835 name);
2836 goto bad;
2837 }
2838
2839 ue = usb_emu_finddev(device);
2840 if (ue == NULL) {
2841 EPRINTLN("pci_xhci: unknown device model \"%s\"",
2842 device);
2843 goto bad;
2844 }
2845
2846 DPRINTF(("pci_xhci adding device %s", device));
2847
2848 dev = calloc(1, sizeof(struct pci_xhci_dev_emu));
2849 dev->xsc = sc;
2850 dev->hci.hci_sc = dev;
2851 dev->hci.hci_intr = pci_xhci_dev_intr;
2852 dev->hci.hci_event = pci_xhci_dev_event;
2853
2854 if (ue->ue_usbver == 2) {
2855 if (usb2_port == sc->usb2_port_start +
2856 XHCI_MAX_DEVS / 2) {
2857 WPRINTF(("pci_xhci max number of USB 2 devices "
2858 "reached, max %d", XHCI_MAX_DEVS / 2));
2859 goto bad;
2860 }
2861 dev->hci.hci_port = usb2_port;
2862 usb2_port++;
2863 } else {
2864 if (usb3_port == sc->usb3_port_start +
2865 XHCI_MAX_DEVS / 2) {
2866 WPRINTF(("pci_xhci max number of USB 3 devices "
2867 "reached, max %d", XHCI_MAX_DEVS / 2));
2868 goto bad;
2869 }
2870 dev->hci.hci_port = usb3_port;
2871 usb3_port++;
2872 }
2873 XHCI_DEVINST_PTR(sc, dev->hci.hci_port) = dev;
2874
2875 dev->hci.hci_address = 0;
2876 devsc = ue->ue_init(&dev->hci, nvl);
2877 if (devsc == NULL) {
2878 goto bad;
2879 }
2880
2881 dev->dev_ue = ue;
2882 dev->dev_sc = devsc;
2883
2884 XHCI_SLOTDEV_PTR(sc, slot) = dev;
2885 ndevices++;
2886 }
2887
2888 portsfinal:
2889 sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs));
2890
2891 if (ndevices > 0) {
2892 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
2893 pci_xhci_init_port(sc, i);
2894 }
2895 } else {
2896 WPRINTF(("pci_xhci no USB devices configured"));
2897 }
2898 return (0);
2899
2900 bad:
2901 for (i = 1; i <= XHCI_MAX_DEVS; i++) {
2902 free(XHCI_DEVINST_PTR(sc, i));
2903 }
2904
2905 free(sc->devices);
2906 free(sc->slots);
2907
2908 return (-1);
2909 }
2910
2911 static int
pci_xhci_init(struct pci_devinst * pi,nvlist_t * nvl)2912 pci_xhci_init(struct pci_devinst *pi, nvlist_t *nvl)
2913 {
2914 struct pci_xhci_softc *sc;
2915 int error;
2916
2917 #ifndef __FreeBSD__
2918 if (get_config_bool_default("xhci.debug", false))
2919 xhci_debug = 1;
2920 #endif
2921
2922 if (xhci_in_use) {
2923 WPRINTF(("pci_xhci controller already defined"));
2924 return (-1);
2925 }
2926 xhci_in_use = 1;
2927
2928 sc = calloc(1, sizeof(struct pci_xhci_softc));
2929 pi->pi_arg = sc;
2930 sc->xsc_pi = pi;
2931
2932 sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1;
2933 sc->usb3_port_start = 1;
2934
2935 /* discover devices */
2936 error = pci_xhci_parse_devices(sc, nvl);
2937 if (error < 0)
2938 goto done;
2939 else
2940 error = 0;
2941
2942 sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) |
2943 XHCI_SET_HCIVERSION(0x0100);
2944 sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) |
2945 XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */
2946 XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS);
2947 sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) |
2948 XHCI_SET_HCSP2_IST(0x04);
2949 sc->hcsparams3 = 0; /* no latency */
2950 sc->hccparams1 = XHCI_SET_HCCP1_AC64(1) | /* 64-bit addrs */
2951 XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */
2952 XHCI_SET_HCCP1_SPC(1) | /* short packet */
2953 XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX);
2954 sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) |
2955 XHCI_SET_HCCP2_U3C(1);
2956 sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START +
2957 XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs));
2958
2959 /* dboff must be 32-bit aligned */
2960 if (sc->dboff & 0x3)
2961 sc->dboff = (sc->dboff + 0x3) & ~0x3;
2962
2963 /* rtsoff must be 32-bytes aligned */
2964 sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32);
2965 if (sc->rtsoff & 0x1F)
2966 sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F;
2967
2968 DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x", sc->dboff,
2969 sc->rtsoff));
2970
2971 sc->opregs.usbsts = XHCI_STS_HCH;
2972 sc->opregs.pgsz = XHCI_PAGESIZE_4K;
2973
2974 pci_xhci_reset(sc);
2975
2976 sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */
2977
2978 /*
2979 * Set extended capabilities pointer to be after regsend;
2980 * value of xecp field is 32-bit offset.
2981 */
2982 sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4);
2983
2984 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31);
2985 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2986 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS);
2987 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB);
2988 pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI);
2989 pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0);
2990
2991 pci_emul_add_msicap(pi, 1);
2992
2993 /* regsend + xecp registers */
2994 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32);
2995 DPRINTF(("pci_xhci pci_emu_alloc: %d", sc->regsend + 4*32));
2996
2997
2998 pci_lintr_request(pi);
2999
3000 pthread_mutex_init(&sc->mtx, NULL);
3001
3002 done:
3003 if (error) {
3004 free(sc);
3005 }
3006
3007 return (error);
3008 }
3009
3010 static const struct pci_devemu pci_de_xhci = {
3011 .pe_emu = "xhci",
3012 .pe_init = pci_xhci_init,
3013 .pe_legacy_config = pci_xhci_legacy_config,
3014 .pe_barwrite = pci_xhci_write,
3015 .pe_barread = pci_xhci_read
3016 };
3017 PCI_EMUL_SET(pci_de_xhci);
3018