1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2021 HiSilicon Ltd. */ 3 4 #ifndef HISI_ACC_VFIO_PCI_H 5 #define HISI_ACC_VFIO_PCI_H 6 7 #include <linux/hisi_acc_qm.h> 8 9 #define MB_POLL_PERIOD_US 10 10 #define MB_POLL_TIMEOUT_US 1000 11 #define QM_CACHE_WB_START 0x204 12 #define QM_CACHE_WB_DONE 0x208 13 #define QM_MB_CMD_PAUSE_QM 0xe 14 #define QM_ABNORMAL_INT_STATUS 0x100008 15 #define QM_IFC_INT_STATUS 0x0028 16 #define SEC_CORE_INT_STATUS 0x301008 17 #define HPRE_HAC_INT_STATUS 0x301800 18 #define HZIP_CORE_INT_STATUS 0x3010AC 19 20 #define QM_VFT_CFG_RDY 0x10006c 21 #define QM_VFT_CFG_OP_WR 0x100058 22 #define QM_VFT_CFG_TYPE 0x10005c 23 #define QM_VFT_CFG 0x100060 24 #define QM_VFT_CFG_OP_ENABLE 0x100054 25 #define QM_VFT_CFG_DATA_L 0x100064 26 #define QM_VFT_CFG_DATA_H 0x100068 27 28 #define ERROR_CHECK_TIMEOUT 100 29 #define CHECK_DELAY_TIME 100 30 31 #define QM_SQC_VFT_BASE_SHIFT_V2 28 32 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0) 33 #define QM_SQC_VFT_NUM_SHIFT_V2 45 34 #define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0) 35 #define QM_MB_CMD_NOT_READY 0xffffffff 36 37 /* RW regs */ 38 #define QM_REGS_MAX_LEN 7 39 #define QM_REG_ADDR_OFFSET 0x0004 40 41 #define QM_XQC_ADDR_OFFSET 32U 42 #define QM_XQC_ADDR_LOW 0x1 43 #define QM_XQC_ADDR_HIGH 0x2 44 45 #define QM_VF_AEQ_INT_MASK 0x0004 46 #define QM_VF_EQ_INT_MASK 0x000c 47 #define QM_IFC_INT_SOURCE_V 0x0020 48 #define QM_IFC_INT_MASK 0x0024 49 #define QM_IFC_INT_SET_V 0x002c 50 #define QM_QUE_ISO_CFG_V 0x0030 51 #define QM_PAGE_SIZE 0x0034 52 53 #define QM_EQC_DW0 0X8000 54 #define QM_AEQC_DW0 0X8020 55 56 #define ACC_DRV_MAJOR_VER 1 57 #define ACC_DRV_MINOR_VER 0 58 59 #define ACC_DEV_MAGIC_V1 0XCDCDCDCDFEEDAACC 60 #define ACC_DEV_MAGIC_V2 0xAACCFEEDDECADEDE 61 62 struct acc_vf_data { 63 #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state) 64 /* QM match information */ 65 u64 acc_magic; 66 u32 qp_num; 67 u32 dev_id; 68 u32 que_iso_cfg; 69 u32 qp_base; 70 u32 vf_qm_state; 71 /* QM reserved match information */ 72 u16 major_ver; 73 u16 minor_ver; 74 u32 qm_rsv_state[2]; 75 76 /* QM RW regs */ 77 u32 aeq_int_mask; 78 u32 eq_int_mask; 79 u32 ifc_int_source; 80 u32 ifc_int_mask; 81 u32 ifc_int_set; 82 u32 page_size; 83 84 /* QM_EQC_DW has 7 regs */ 85 u32 qm_eqc_dw[7]; 86 87 /* QM_AEQC_DW has 7 regs */ 88 u32 qm_aeqc_dw[7]; 89 90 /* QM reserved 5 regs */ 91 u32 qm_rsv_regs[5]; 92 u32 padding; 93 /* QM memory init information */ 94 u64 eqe_dma; 95 u64 aeqe_dma; 96 u64 sqc_dma; 97 u64 cqc_dma; 98 }; 99 100 struct hisi_acc_vf_migration_file { 101 struct file *filp; 102 struct mutex lock; 103 bool disabled; 104 105 struct hisi_acc_vf_core_device *hisi_acc_vdev; 106 struct acc_vf_data vf_data; 107 size_t total_length; 108 }; 109 110 struct hisi_acc_vf_core_device { 111 struct vfio_pci_core_device core_device; 112 u8 match_done; 113 /* 114 * io_base is only valid when dev_opened is true, 115 * which is protected by open_mutex. 116 */ 117 bool dev_opened; 118 /* Ensure the accuracy of dev_opened operation */ 119 struct mutex open_mutex; 120 121 /* For migration state */ 122 struct mutex state_mutex; 123 enum vfio_device_mig_state mig_state; 124 struct pci_dev *pf_dev; 125 struct pci_dev *vf_dev; 126 struct hisi_qm *pf_qm; 127 struct hisi_qm vf_qm; 128 /* 129 * vf_qm_state represents the QM_VF_STATE register value. 130 * It is set by Guest driver for the ACC VF dev indicating 131 * the driver has loaded and configured the dev correctly. 132 */ 133 u32 vf_qm_state; 134 int vf_id; 135 struct hisi_acc_vf_migration_file *resuming_migf; 136 struct hisi_acc_vf_migration_file *saving_migf; 137 138 /* 139 * It holds migration data corresponding to the last migration 140 * and is used by the debugfs interface to report it. 141 */ 142 struct hisi_acc_vf_migration_file *debug_migf; 143 }; 144 #endif /* HISI_ACC_VFIO_PCI_H */ 145