1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dcn321_dio_link_encoder.h"
31 #include "dcn31/dcn31_dio_link_encoder.h"
32 #include "stream_encoder.h"
33 #include "dc_bios_types.h"
34
35 #include "gpio_service_interface.h"
36
37 #ifndef MIN
38 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
39 #endif
40
41 #define CTX \
42 enc10->base.ctx
43 #define DC_LOGGER \
44 enc10->base.ctx->logger
45
46 #define REG(reg)\
47 (enc10->link_regs->reg)
48
49 #undef FN
50 #define FN(reg_name, field_name) \
51 enc10->link_shift->field_name, enc10->link_mask->field_name
52
53 #define AUX_REG(reg)\
54 (enc10->aux_regs->reg)
55
56 #define AUX_REG_READ(reg_name) \
57 dm_read_reg(CTX, AUX_REG(reg_name))
58
59 #define AUX_REG_WRITE(reg_name, val) \
60 dm_write_reg(CTX, AUX_REG(reg_name), val)
61
62 static const struct link_encoder_funcs dcn321_link_enc_funcs = {
63 .read_state = link_enc2_read_state,
64 .validate_output_with_stream =
65 dcn30_link_encoder_validate_output_with_stream,
66 .hw_init = enc32_hw_init,
67 .setup = dcn10_link_encoder_setup,
68 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
69 .enable_dp_output = dcn32_link_encoder_enable_dp_output,
70 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
71 .disable_output = dcn10_link_encoder_disable_output,
72 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
73 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
74 .update_mst_stream_allocation_table =
75 dcn10_link_encoder_update_mst_stream_allocation_table,
76 .psr_program_dp_dphy_fast_training =
77 dcn10_psr_program_dp_dphy_fast_training,
78 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
79 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
80 .enable_hpd = dcn10_link_encoder_enable_hpd,
81 .disable_hpd = dcn10_link_encoder_disable_hpd,
82 .is_dig_enabled = dcn10_is_dig_enabled,
83 .destroy = dcn10_link_encoder_destroy,
84 .fec_set_enable = enc2_fec_set_enable,
85 .fec_set_ready = enc2_fec_set_ready,
86 .fec_is_active = enc2_fec_is_active,
87 .get_dig_frontend = dcn10_get_dig_frontend,
88 .get_dig_mode = dcn10_get_dig_mode,
89 .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
90 .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
91 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
92 };
93
dcn321_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)94 void dcn321_link_encoder_construct(
95 struct dcn20_link_encoder *enc20,
96 const struct encoder_init_data *init_data,
97 const struct encoder_feature_support *enc_features,
98 const struct dcn10_link_enc_registers *link_regs,
99 const struct dcn10_link_enc_aux_registers *aux_regs,
100 const struct dcn10_link_enc_hpd_registers *hpd_regs,
101 const struct dcn10_link_enc_shift *link_shift,
102 const struct dcn10_link_enc_mask *link_mask)
103 {
104 struct bp_connector_speed_cap_info bp_cap_info = {0};
105 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
106 enum bp_result result = BP_RESULT_OK;
107 struct dcn10_link_encoder *enc10 = &enc20->enc10;
108
109 enc10->base.funcs = &dcn321_link_enc_funcs;
110 enc10->base.ctx = init_data->ctx;
111 enc10->base.id = init_data->encoder;
112
113 enc10->base.hpd_source = init_data->hpd_source;
114 enc10->base.connector = init_data->connector;
115
116 if (enc10->base.connector.id == CONNECTOR_ID_USBC)
117 enc10->base.features.flags.bits.DP_IS_USB_C = 1;
118
119 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
120
121 enc10->base.features = *enc_features;
122
123 enc10->base.transmitter = init_data->transmitter;
124
125 /* set the flag to indicate whether driver poll the I2C data pin
126 * while doing the DP sink detect
127 */
128
129 enc10->base.output_signals =
130 SIGNAL_TYPE_DVI_SINGLE_LINK |
131 SIGNAL_TYPE_DVI_DUAL_LINK |
132 SIGNAL_TYPE_LVDS |
133 SIGNAL_TYPE_DISPLAY_PORT |
134 SIGNAL_TYPE_DISPLAY_PORT_MST |
135 SIGNAL_TYPE_EDP |
136 SIGNAL_TYPE_HDMI_TYPE_A;
137
138 enc10->link_regs = link_regs;
139 enc10->aux_regs = aux_regs;
140 enc10->hpd_regs = hpd_regs;
141 enc10->link_shift = link_shift;
142 enc10->link_mask = link_mask;
143
144 switch (enc10->base.transmitter) {
145 case TRANSMITTER_UNIPHY_A:
146 enc10->base.preferred_engine = ENGINE_ID_DIGA;
147 break;
148 case TRANSMITTER_UNIPHY_B:
149 enc10->base.preferred_engine = ENGINE_ID_DIGB;
150 break;
151 case TRANSMITTER_UNIPHY_C:
152 enc10->base.preferred_engine = ENGINE_ID_DIGC;
153 break;
154 case TRANSMITTER_UNIPHY_D:
155 enc10->base.preferred_engine = ENGINE_ID_DIGD;
156 break;
157 case TRANSMITTER_UNIPHY_E:
158 enc10->base.preferred_engine = ENGINE_ID_DIGE;
159 break;
160 default:
161 ASSERT_CRITICAL(false);
162 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
163 }
164
165 /* default to one to mirror Windows behavior */
166 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
167
168 if (bp_funcs->get_connector_speed_cap_info)
169 result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
170 enc10->base.connector, &bp_cap_info);
171
172 /* Override features with DCE-specific values */
173 if (result == BP_RESULT_OK) {
174 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
175 bp_cap_info.DP_HBR2_EN;
176 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
177 bp_cap_info.DP_HBR3_EN;
178 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
179 enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
180 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
181 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
182 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
183 } else {
184 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
185 __func__,
186 result);
187 }
188 if (enc10->base.ctx->dc->debug.hdmi20_disable)
189 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
190 }
191