1 /*
2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn301/dcn301_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn30/dcn30_resource.h"
35 #include "dcn301_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn301/dcn301_hubbub.h"
41 #include "dcn30/dcn30_mpc.h"
42 #include "dcn30/dcn30_hubp.h"
43 #include "irq/dcn30/irq_service_dcn30.h"
44 #include "dcn30/dcn30_dpp.h"
45 #include "dcn301/dcn301_optc.h"
46 #include "dcn20/dcn20_hwseq.h"
47 #include "dcn30/dcn30_hwseq.h"
48 #include "dce110/dce110_hwseq.h"
49 #include "dcn30/dcn30_opp.h"
50 #include "dcn20/dcn20_dsc.h"
51 #include "dcn30/dcn30_vpg.h"
52 #include "dcn30/dcn30_afmt.h"
53 #include "dce/dce_clock_source.h"
54 #include "dce/dce_audio.h"
55 #include "dce/dce_hwseq.h"
56 #include "clk_mgr.h"
57 #include "dio/virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn301/dcn301_dccg.h"
61 #include "dcn10/dcn10_resource.h"
62 #include "dio/dcn10/dcn10_dio.h"
63 #include "dcn30/dcn30_dio_stream_encoder.h"
64 #include "dcn301/dcn301_dio_link_encoder.h"
65 #include "dcn301/dcn301_panel_cntl.h"
66
67 #include "vangogh_ip_offset.h"
68
69 #include "dcn30/dcn30_dwb.h"
70 #include "dcn30/dcn30_mmhubbub.h"
71
72 #include "dcn/dcn_3_0_1_offset.h"
73 #include "dcn/dcn_3_0_1_sh_mask.h"
74
75 #include "nbio/nbio_7_2_0_offset.h"
76
77 #include "dpcs/dpcs_3_0_0_offset.h"
78 #include "dpcs/dpcs_3_0_0_sh_mask.h"
79
80 #include "reg_helper.h"
81 #include "dce/dmub_abm.h"
82 #include "dce/dce_aux.h"
83 #include "dce/dce_i2c.h"
84
85 #include "dml/dcn30/dcn30_fpu.h"
86
87 #include "dml/dcn30/display_mode_vba_30.h"
88 #include "dml/dcn301/dcn301_fpu.h"
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91 #include "amdgpu_socbb.h"
92
93 #define TO_DCN301_RES_POOL(pool)\
94 container_of(pool, struct dcn301_resource_pool, base)
95
96 #define DC_LOGGER \
97 dc->ctx->logger
98 #define DC_LOGGER_INIT(logger)
99
100 enum dcn301_clk_src_array_id {
101 DCN301_CLK_SRC_PLL0,
102 DCN301_CLK_SRC_PLL1,
103 DCN301_CLK_SRC_PLL2,
104 DCN301_CLK_SRC_PLL3,
105 DCN301_CLK_SRC_TOTAL
106 };
107
108 /* begin *********************
109 * macros to expend register list macro defined in HW object header file
110 */
111
112 /* DCN */
113 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
114
115 #define BASE(seg) BASE_INNER(seg)
116
117 #define SR(reg_name)\
118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
119 mm ## reg_name
120
121 #define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
124
125 #define SRI2(reg_name, block, id)\
126 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
127 mm ## reg_name
128
129 #define SRIR(var_name, reg_name, block, id)\
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
132
133 #define SRII(reg_name, block, id)\
134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## id ## _ ## reg_name
136
137 #define SRII2(reg_name_pre, reg_name_post, id)\
138 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \
139 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
140 mm ## reg_name_pre ## id ## _ ## reg_name_post
141
142 #define SRII_MPC_RMU(reg_name, block, id)\
143 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
144 mm ## block ## id ## _ ## reg_name
145
146 #define SRII_DWB(reg_name, temp_name, block, id)\
147 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
148 mm ## block ## id ## _ ## temp_name
149
150 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
151 .field_name = reg_name ## __ ## field_name ## post_fix
152
153 #define DCCG_SRII(reg_name, block, id)\
154 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 mm ## block ## id ## _ ## reg_name
156
157 #define VUPDATE_SRII(reg_name, block, id)\
158 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
159 mm ## reg_name ## _ ## block ## id
160
161 /* NBIO */
162 #define NBIO_BASE_INNER(seg) \
163 NBIO_BASE__INST0_SEG ## seg
164
165 #define NBIO_BASE(seg) \
166 NBIO_BASE_INNER(seg)
167
168 #define NBIO_SR(reg_name)\
169 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
170 regBIF_BX0_ ## reg_name
171
172 /* MMHUB */
173 #define MMHUB_BASE_INNER(seg) \
174 MMHUB_BASE__INST0_SEG ## seg
175
176 #define MMHUB_BASE(seg) \
177 MMHUB_BASE_INNER(seg)
178
179 #define MMHUB_SR(reg_name)\
180 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
181 regMM ## reg_name
182
183 /* CLOCK */
184 #define CLK_BASE_INNER(seg) \
185 CLK_BASE__INST0_SEG ## seg
186
187 #define CLK_BASE(seg) \
188 CLK_BASE_INNER(seg)
189
190 #define CLK_SRI(reg_name, block, inst)\
191 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
192 mm ## block ## _ ## inst ## _ ## reg_name
193
194 static const struct bios_registers bios_regs = {
195 NBIO_SR(BIOS_SCRATCH_3),
196 NBIO_SR(BIOS_SCRATCH_6)
197 };
198
199 #define clk_src_regs(index, pllid)\
200 [index] = {\
201 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
202 }
203
204 static const struct dce110_clk_src_regs clk_src_regs[] = {
205 clk_src_regs(0, A),
206 clk_src_regs(1, B),
207 clk_src_regs(2, C),
208 clk_src_regs(3, D)
209 };
210
211 static const struct dce110_clk_src_shift cs_shift = {
212 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
213 };
214
215 static const struct dce110_clk_src_mask cs_mask = {
216 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
217 };
218
219 #define abm_regs(id)\
220 [id] = {\
221 ABM_DCN301_REG_LIST(id)\
222 }
223
224 static const struct dce_abm_registers abm_regs[] = {
225 abm_regs(0),
226 abm_regs(1),
227 abm_regs(2),
228 abm_regs(3),
229 };
230
231 static const struct dce_abm_shift abm_shift = {
232 ABM_MASK_SH_LIST_DCN30(__SHIFT)
233 };
234
235 static const struct dce_abm_mask abm_mask = {
236 ABM_MASK_SH_LIST_DCN30(_MASK)
237 };
238
239 #define audio_regs(id)\
240 [id] = {\
241 AUD_COMMON_REG_LIST(id)\
242 }
243
244 static const struct dce_audio_registers audio_regs[] = {
245 audio_regs(0),
246 audio_regs(1),
247 audio_regs(2),
248 audio_regs(3),
249 audio_regs(4),
250 audio_regs(5),
251 audio_regs(6)
252 };
253
254 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
256 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
257 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
258
259 static const struct dce_audio_shift audio_shift = {
260 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
261 };
262
263 static const struct dce_audio_mask audio_mask = {
264 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
265 };
266
267 #define vpg_regs(id)\
268 [id] = {\
269 VPG_DCN3_REG_LIST(id)\
270 }
271
272 static const struct dcn30_vpg_registers vpg_regs[] = {
273 vpg_regs(0),
274 vpg_regs(1),
275 vpg_regs(2),
276 vpg_regs(3),
277 };
278
279 static const struct dcn30_vpg_shift vpg_shift = {
280 DCN3_VPG_MASK_SH_LIST(__SHIFT)
281 };
282
283 static const struct dcn30_vpg_mask vpg_mask = {
284 DCN3_VPG_MASK_SH_LIST(_MASK)
285 };
286
287 #define afmt_regs(id)\
288 [id] = {\
289 AFMT_DCN3_REG_LIST(id)\
290 }
291
292 static const struct dcn30_afmt_registers afmt_regs[] = {
293 afmt_regs(0),
294 afmt_regs(1),
295 afmt_regs(2),
296 afmt_regs(3),
297 };
298
299 static const struct dcn30_afmt_shift afmt_shift = {
300 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
301 };
302
303 static const struct dcn30_afmt_mask afmt_mask = {
304 DCN3_AFMT_MASK_SH_LIST(_MASK)
305 };
306
307 #define stream_enc_regs(id)\
308 [id] = {\
309 SE_DCN3_REG_LIST(id)\
310 }
311
312 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
313 stream_enc_regs(0),
314 stream_enc_regs(1),
315 stream_enc_regs(2),
316 stream_enc_regs(3),
317 };
318
319 static const struct dcn10_stream_encoder_shift se_shift = {
320 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
321 };
322
323 static const struct dcn10_stream_encoder_mask se_mask = {
324 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
325 };
326
327
328 #define aux_regs(id)\
329 [id] = {\
330 DCN2_AUX_REG_LIST(id)\
331 }
332
333 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
334 aux_regs(0),
335 aux_regs(1),
336 aux_regs(2),
337 aux_regs(3),
338 };
339
340 #define hpd_regs(id)\
341 [id] = {\
342 HPD_REG_LIST(id)\
343 }
344
345 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
346 hpd_regs(0),
347 hpd_regs(1),
348 hpd_regs(2),
349 hpd_regs(3),
350 };
351
352
353 #define link_regs(id, phyid)\
354 [id] = {\
355 LE_DCN301_REG_LIST(id), \
356 UNIPHY_DCN2_REG_LIST(phyid), \
357 DPCS_DCN2_REG_LIST(id), \
358 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
359 }
360
361 static const struct dce110_aux_registers_shift aux_shift = {
362 DCN_AUX_MASK_SH_LIST(__SHIFT)
363 };
364
365 static const struct dce110_aux_registers_mask aux_mask = {
366 DCN_AUX_MASK_SH_LIST(_MASK)
367 };
368
369 static const struct dcn10_link_enc_registers link_enc_regs[] = {
370 link_regs(0, A),
371 link_regs(1, B),
372 link_regs(2, C),
373 link_regs(3, D),
374 };
375
376 static const struct dcn10_link_enc_shift le_shift = {
377 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\
378 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
379 };
380
381 static const struct dcn10_link_enc_mask le_mask = {
382 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\
383 DPCS_DCN2_MASK_SH_LIST(_MASK)
384 };
385
386 #define panel_cntl_regs(id)\
387 [id] = {\
388 DCN301_PANEL_CNTL_REG_LIST(id),\
389 }
390
391 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
392 panel_cntl_regs(0),
393 panel_cntl_regs(1),
394 };
395
396 static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
397 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
398 };
399
400 static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
401 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
402 };
403
404 #define dpp_regs(id)\
405 [id] = {\
406 DPP_REG_LIST_DCN30(id),\
407 }
408
409 static const struct dcn3_dpp_registers dpp_regs[] = {
410 dpp_regs(0),
411 dpp_regs(1),
412 dpp_regs(2),
413 dpp_regs(3),
414 };
415
416 static const struct dcn3_dpp_shift tf_shift = {
417 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
418 };
419
420 static const struct dcn3_dpp_mask tf_mask = {
421 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
422 };
423
424 #define opp_regs(id)\
425 [id] = {\
426 OPP_REG_LIST_DCN30(id),\
427 }
428
429 static const struct dcn20_opp_registers opp_regs[] = {
430 opp_regs(0),
431 opp_regs(1),
432 opp_regs(2),
433 opp_regs(3),
434 };
435
436 static const struct dcn20_opp_shift opp_shift = {
437 OPP_MASK_SH_LIST_DCN20(__SHIFT)
438 };
439
440 static const struct dcn20_opp_mask opp_mask = {
441 OPP_MASK_SH_LIST_DCN20(_MASK)
442 };
443
444 #define aux_engine_regs(id)\
445 [id] = {\
446 AUX_COMMON_REG_LIST0(id), \
447 .AUXN_IMPCAL = 0, \
448 .AUXP_IMPCAL = 0, \
449 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
450 }
451
452 static const struct dce110_aux_registers aux_engine_regs[] = {
453 aux_engine_regs(0),
454 aux_engine_regs(1),
455 aux_engine_regs(2),
456 aux_engine_regs(3),
457 };
458
459 #define dwbc_regs_dcn3(id)\
460 [id] = {\
461 DWBC_COMMON_REG_LIST_DCN30(id),\
462 }
463
464 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
465 dwbc_regs_dcn3(0),
466 };
467
468 static const struct dcn30_dwbc_shift dwbc30_shift = {
469 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
470 };
471
472 static const struct dcn30_dwbc_mask dwbc30_mask = {
473 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
474 };
475
476 #define mcif_wb_regs_dcn3(id)\
477 [id] = {\
478 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
479 }
480
481 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
482 mcif_wb_regs_dcn3(0)
483 };
484
485 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
486 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
487 };
488
489 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
490 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
491 };
492
493 #define dsc_regsDCN20(id)\
494 [id] = {\
495 DSC_REG_LIST_DCN20(id)\
496 }
497
498 static const struct dcn20_dsc_registers dsc_regs[] = {
499 dsc_regsDCN20(0),
500 dsc_regsDCN20(1),
501 dsc_regsDCN20(2),
502 };
503
504 static const struct dcn20_dsc_shift dsc_shift = {
505 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
506 };
507
508 static const struct dcn20_dsc_mask dsc_mask = {
509 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
510 };
511
512 static const struct dcn30_mpc_registers mpc_regs = {
513 MPC_REG_LIST_DCN3_0(0),
514 MPC_REG_LIST_DCN3_0(1),
515 MPC_REG_LIST_DCN3_0(2),
516 MPC_REG_LIST_DCN3_0(3),
517 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
518 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
519 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
520 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
521 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
522 MPC_RMU_REG_LIST_DCN3AG(0),
523 MPC_RMU_REG_LIST_DCN3AG(1),
524 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
525 };
526
527 static const struct dcn30_mpc_shift mpc_shift = {
528 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
529 };
530
531 static const struct dcn30_mpc_mask mpc_mask = {
532 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
533 };
534
535 #define optc_regs(id)\
536 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
537
538
539 static const struct dcn_optc_registers optc_regs[] = {
540 optc_regs(0),
541 optc_regs(1),
542 optc_regs(2),
543 optc_regs(3),
544 };
545
546 static const struct dcn_optc_shift optc_shift = {
547 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
548 };
549
550 static const struct dcn_optc_mask optc_mask = {
551 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
552 };
553
554 #define hubp_regs(id)\
555 [id] = {\
556 HUBP_REG_LIST_DCN30(id)\
557 }
558
559 static const struct dcn_hubp2_registers hubp_regs[] = {
560 hubp_regs(0),
561 hubp_regs(1),
562 hubp_regs(2),
563 hubp_regs(3),
564 };
565
566 static const struct dcn_hubp2_shift hubp_shift = {
567 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
568 };
569
570 static const struct dcn_hubp2_mask hubp_mask = {
571 HUBP_MASK_SH_LIST_DCN30(_MASK)
572 };
573
574 static const struct dcn_hubbub_registers hubbub_reg = {
575 HUBBUB_REG_LIST_DCN301(0)
576 };
577
578 static const struct dcn_hubbub_shift hubbub_shift = {
579 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
580 };
581
582 static const struct dcn_hubbub_mask hubbub_mask = {
583 HUBBUB_MASK_SH_LIST_DCN301(_MASK)
584 };
585
586 static const struct dccg_registers dccg_regs = {
587 DCCG_REG_LIST_DCN301()
588 };
589
590 static const struct dccg_shift dccg_shift = {
591 DCCG_MASK_SH_LIST_DCN301(__SHIFT)
592 };
593
594 static const struct dccg_mask dccg_mask = {
595 DCCG_MASK_SH_LIST_DCN301(_MASK)
596 };
597
598 static const struct dce_hwseq_registers hwseq_reg = {
599 HWSEQ_DCN301_REG_LIST()
600 };
601
602 static const struct dce_hwseq_shift hwseq_shift = {
603 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
604 };
605
606 static const struct dce_hwseq_mask hwseq_mask = {
607 HWSEQ_DCN301_MASK_SH_LIST(_MASK)
608 };
609 #define vmid_regs(id)\
610 [id] = {\
611 DCN20_VMID_REG_LIST(id)\
612 }
613
614 static const struct dcn_vmid_registers vmid_regs[] = {
615 vmid_regs(0),
616 vmid_regs(1),
617 vmid_regs(2),
618 vmid_regs(3),
619 vmid_regs(4),
620 vmid_regs(5),
621 vmid_regs(6),
622 vmid_regs(7),
623 vmid_regs(8),
624 vmid_regs(9),
625 vmid_regs(10),
626 vmid_regs(11),
627 vmid_regs(12),
628 vmid_regs(13),
629 vmid_regs(14),
630 vmid_regs(15)
631 };
632
633 static const struct dcn20_vmid_shift vmid_shifts = {
634 DCN20_VMID_MASK_SH_LIST(__SHIFT)
635 };
636
637 static const struct dcn20_vmid_mask vmid_masks = {
638 DCN20_VMID_MASK_SH_LIST(_MASK)
639 };
640
641 static struct resource_caps res_cap_dcn301 = {
642 .num_timing_generator = 4,
643 .num_opp = 4,
644 .num_video_plane = 4,
645 .num_audio = 4,
646 .num_stream_encoder = 4,
647 .num_pll = 4,
648 .num_dwb = 1,
649 .num_ddc = 4,
650 .num_vmid = 16,
651 .num_mpc_3dlut = 2,
652 .num_dsc = 3,
653 };
654
655 static const struct dc_plane_cap plane_cap = {
656 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
657 .per_pixel_alpha = true,
658
659 .pixel_format_support = {
660 .argb8888 = true,
661 .nv12 = true,
662 .fp16 = true,
663 .p010 = true,
664 .ayuv = false,
665 },
666
667 .max_upscale_factor = {
668 .argb8888 = 16000,
669 .nv12 = 16000,
670 .fp16 = 16000
671 },
672
673 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
674 .max_downscale_factor = {
675 .argb8888 = 358,
676 .nv12 = 358,
677 .fp16 = 358
678 },
679 64,
680 64
681 };
682
683 static const struct dc_debug_options debug_defaults_drv = {
684 .disable_dmcu = true,
685 .force_abm_enable = false,
686 .clock_trace = true,
687 .disable_dpp_power_gate = false,
688 .disable_hubp_power_gate = false,
689 .disable_clock_gate = true,
690 .disable_pplib_clock_request = true,
691 .disable_pplib_wm_range = true,
692 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
693 .force_single_disp_pipe_split = false,
694 .disable_dcc = DCC_ENABLE,
695 .vsr_support = true,
696 .performance_trace = false,
697 .max_downscale_src_width = 4096,/*upto true 4k*/
698 .scl_reset_length10 = true,
699 .sanity_checks = false,
700 .underflow_assert_delay_us = 0xFFFFFFFF,
701 .dwb_fi_phase = -1, // -1 = disable
702 .dmub_command_table = true,
703 .use_max_lb = false,
704 .exit_idle_opt_for_cursor_updates = true,
705 .using_dml2 = false,
706 };
707
708 static const struct dc_check_config config_defaults = {
709 .enable_legacy_fast_update = true,
710 };
711
dcn301_dpp_destroy(struct dpp ** dpp)712 static void dcn301_dpp_destroy(struct dpp **dpp)
713 {
714 kfree(TO_DCN20_DPP(*dpp));
715 *dpp = NULL;
716 }
717
dcn301_dpp_create(struct dc_context * ctx,uint32_t inst)718 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
719 {
720 struct dcn3_dpp *dpp =
721 kzalloc_obj(struct dcn3_dpp);
722
723 if (!dpp)
724 return NULL;
725
726 if (dpp3_construct(dpp, ctx, inst,
727 &dpp_regs[inst], &tf_shift, &tf_mask))
728 return &dpp->base;
729
730 BREAK_TO_DEBUGGER();
731 kfree(dpp);
732 return NULL;
733 }
dcn301_opp_create(struct dc_context * ctx,uint32_t inst)734 static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx,
735 uint32_t inst)
736 {
737 struct dcn20_opp *opp =
738 kzalloc_obj(struct dcn20_opp);
739
740 if (!opp) {
741 BREAK_TO_DEBUGGER();
742 return NULL;
743 }
744
745 dcn20_opp_construct(opp, ctx, inst,
746 &opp_regs[inst], &opp_shift, &opp_mask);
747 return &opp->base;
748 }
749
dcn301_aux_engine_create(struct dc_context * ctx,uint32_t inst)750 static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
751 {
752 struct aux_engine_dce110 *aux_engine =
753 kzalloc_obj(struct aux_engine_dce110);
754
755 if (!aux_engine)
756 return NULL;
757
758 dce110_aux_engine_construct(aux_engine, ctx, inst,
759 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
760 &aux_engine_regs[inst],
761 &aux_mask,
762 &aux_shift,
763 ctx->dc->caps.extended_aux_timeout_support);
764
765 return &aux_engine->base;
766 }
767 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
768
769 static const struct dce_i2c_registers i2c_hw_regs[] = {
770 i2c_inst_regs(1),
771 i2c_inst_regs(2),
772 i2c_inst_regs(3),
773 i2c_inst_regs(4),
774 };
775
776 static const struct dce_i2c_shift i2c_shifts = {
777 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
778 };
779
780 static const struct dce_i2c_mask i2c_masks = {
781 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
782 };
783
dcn301_i2c_hw_create(struct dc_context * ctx,uint32_t inst)784 static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
785 {
786 struct dce_i2c_hw *dce_i2c_hw =
787 kzalloc_obj(struct dce_i2c_hw);
788
789 if (!dce_i2c_hw)
790 return NULL;
791
792 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
793 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
794
795 return dce_i2c_hw;
796 }
dcn301_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)797 static struct mpc *dcn301_mpc_create(
798 struct dc_context *ctx,
799 int num_mpcc,
800 int num_rmu)
801 {
802 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
803
804 if (!mpc30)
805 return NULL;
806
807 dcn30_mpc_construct(mpc30, ctx,
808 &mpc_regs,
809 &mpc_shift,
810 &mpc_mask,
811 num_mpcc,
812 num_rmu);
813
814 return &mpc30->base;
815 }
816
dcn301_hubbub_create(struct dc_context * ctx)817 static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
818 {
819 int i;
820
821 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
822
823 if (!hubbub3)
824 return NULL;
825
826 hubbub301_construct(hubbub3, ctx,
827 &hubbub_reg,
828 &hubbub_shift,
829 &hubbub_mask);
830
831
832 for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
833 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
834
835 vmid->ctx = ctx;
836
837 vmid->regs = &vmid_regs[i];
838 vmid->shifts = &vmid_shifts;
839 vmid->masks = &vmid_masks;
840 }
841
842 hubbub3->num_vmid = res_cap_dcn301.num_vmid;
843
844 return &hubbub3->base;
845 }
846
847 static const struct dcn_dio_registers dio_regs = {
848 DIO_REG_LIST_DCN10()
849 };
850
851 #define DIO_MASK_SH_LIST(mask_sh)\
852 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
853
854 static const struct dcn_dio_shift dio_shift = {
855 DIO_MASK_SH_LIST(__SHIFT)
856 };
857
858 static const struct dcn_dio_mask dio_mask = {
859 DIO_MASK_SH_LIST(_MASK)
860 };
861
dcn301_dio_create(struct dc_context * ctx)862 static struct dio *dcn301_dio_create(struct dc_context *ctx)
863 {
864 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
865
866 if (!dio10)
867 return NULL;
868
869 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
870
871 return &dio10->base;
872 }
873
dcn301_timing_generator_create(struct dc_context * ctx,uint32_t instance)874 static struct timing_generator *dcn301_timing_generator_create(
875 struct dc_context *ctx, uint32_t instance)
876 {
877 struct optc *tgn10 =
878 kzalloc_obj(struct optc);
879
880 if (!tgn10)
881 return NULL;
882
883 tgn10->base.inst = instance;
884 tgn10->base.ctx = ctx;
885
886 tgn10->tg_regs = &optc_regs[instance];
887 tgn10->tg_shift = &optc_shift;
888 tgn10->tg_mask = &optc_mask;
889
890 dcn301_timing_generator_init(tgn10);
891
892 return &tgn10->base;
893 }
894
895 static const struct encoder_feature_support link_enc_feature = {
896 .max_hdmi_deep_color = COLOR_DEPTH_121212,
897 .max_hdmi_pixel_clock = 600000,
898 .hdmi_ycbcr420_supported = true,
899 .dp_ycbcr420_supported = true,
900 .fec_supported = true,
901 .flags.bits.IS_HBR2_CAPABLE = true,
902 .flags.bits.IS_HBR3_CAPABLE = true,
903 .flags.bits.IS_TPS3_CAPABLE = true,
904 .flags.bits.IS_TPS4_CAPABLE = true
905 };
906
dcn301_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)907 static struct link_encoder *dcn301_link_encoder_create(
908 struct dc_context *ctx,
909 const struct encoder_init_data *enc_init_data)
910 {
911 (void)ctx;
912 struct dcn20_link_encoder *enc20 =
913 kzalloc_obj(struct dcn20_link_encoder);
914
915 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
916 return NULL;
917
918 dcn301_link_encoder_construct(enc20,
919 enc_init_data,
920 &link_enc_feature,
921 &link_enc_regs[enc_init_data->transmitter],
922 &link_enc_aux_regs[enc_init_data->channel - 1],
923 &link_enc_hpd_regs[enc_init_data->hpd_source],
924 &le_shift,
925 &le_mask);
926
927 return &enc20->enc10.base;
928 }
929
dcn301_panel_cntl_create(const struct panel_cntl_init_data * init_data)930 static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
931 {
932 struct dcn301_panel_cntl *panel_cntl =
933 kzalloc_obj(struct dcn301_panel_cntl);
934
935 if (!panel_cntl)
936 return NULL;
937
938 dcn301_panel_cntl_construct(panel_cntl,
939 init_data,
940 &panel_cntl_regs[init_data->inst],
941 &panel_cntl_shift,
942 &panel_cntl_mask);
943
944 return &panel_cntl->base;
945 }
946
947
948 #define CTX ctx
949
950 #define REG(reg_name) \
951 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
952
read_pipe_fuses(struct dc_context * ctx)953 static uint32_t read_pipe_fuses(struct dc_context *ctx)
954 {
955 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
956 /* RV1 support max 4 pipes */
957 value = value & 0xf;
958 return value;
959 }
960
961
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)962 static void read_dce_straps(
963 struct dc_context *ctx,
964 struct resource_straps *straps)
965 {
966 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
967 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
968
969 }
970
dcn301_create_audio(struct dc_context * ctx,unsigned int inst)971 static struct audio *dcn301_create_audio(
972 struct dc_context *ctx, unsigned int inst)
973 {
974 return dce_audio_create(ctx, inst,
975 &audio_regs[inst], &audio_shift, &audio_mask);
976 }
977
dcn301_vpg_create(struct dc_context * ctx,uint32_t inst)978 static struct vpg *dcn301_vpg_create(
979 struct dc_context *ctx,
980 uint32_t inst)
981 {
982 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
983
984 if (!vpg3)
985 return NULL;
986
987 vpg3_construct(vpg3, ctx, inst,
988 &vpg_regs[inst],
989 &vpg_shift,
990 &vpg_mask);
991
992 return &vpg3->base;
993 }
994
dcn301_afmt_create(struct dc_context * ctx,uint32_t inst)995 static struct afmt *dcn301_afmt_create(
996 struct dc_context *ctx,
997 uint32_t inst)
998 {
999 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
1000
1001 if (!afmt3)
1002 return NULL;
1003
1004 afmt3_construct(afmt3, ctx, inst,
1005 &afmt_regs[inst],
1006 &afmt_shift,
1007 &afmt_mask);
1008
1009 return &afmt3->base;
1010 }
1011
dcn301_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1012 static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id,
1013 struct dc_context *ctx)
1014 {
1015 struct dcn10_stream_encoder *enc1;
1016 struct vpg *vpg;
1017 struct afmt *afmt;
1018 int vpg_inst;
1019 int afmt_inst;
1020
1021 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1022 if (eng_id <= ENGINE_ID_DIGF) {
1023 vpg_inst = eng_id;
1024 afmt_inst = eng_id;
1025 } else
1026 return NULL;
1027
1028 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1029 vpg = dcn301_vpg_create(ctx, vpg_inst);
1030 afmt = dcn301_afmt_create(ctx, afmt_inst);
1031
1032 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1033 kfree(enc1);
1034 kfree(vpg);
1035 kfree(afmt);
1036 return NULL;
1037 }
1038
1039 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1040 eng_id, vpg, afmt,
1041 &stream_enc_regs[eng_id],
1042 &se_shift, &se_mask);
1043
1044 return &enc1->base;
1045 }
1046
dcn301_hwseq_create(struct dc_context * ctx)1047 static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)
1048 {
1049 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1050
1051 if (hws) {
1052 hws->ctx = ctx;
1053 hws->regs = &hwseq_reg;
1054 hws->shifts = &hwseq_shift;
1055 hws->masks = &hwseq_mask;
1056 }
1057 return hws;
1058 }
1059 static const struct resource_create_funcs res_create_funcs = {
1060 .read_dce_straps = read_dce_straps,
1061 .create_audio = dcn301_create_audio,
1062 .create_stream_encoder = dcn301_stream_encoder_create,
1063 .create_hwseq = dcn301_hwseq_create,
1064 };
1065
dcn301_destruct(struct dcn301_resource_pool * pool)1066 static void dcn301_destruct(struct dcn301_resource_pool *pool)
1067 {
1068 unsigned int i;
1069
1070 for (i = 0; i < pool->base.stream_enc_count; i++) {
1071 if (pool->base.stream_enc[i] != NULL) {
1072 if (pool->base.stream_enc[i]->vpg != NULL) {
1073 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1074 pool->base.stream_enc[i]->vpg = NULL;
1075 }
1076 if (pool->base.stream_enc[i]->afmt != NULL) {
1077 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1078 pool->base.stream_enc[i]->afmt = NULL;
1079 }
1080 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1081 pool->base.stream_enc[i] = NULL;
1082 }
1083 }
1084
1085 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1086 if (pool->base.dscs[i] != NULL)
1087 dcn20_dsc_destroy(&pool->base.dscs[i]);
1088 }
1089
1090 if (pool->base.mpc != NULL) {
1091 kfree(TO_DCN20_MPC(pool->base.mpc));
1092 pool->base.mpc = NULL;
1093 }
1094 if (pool->base.hubbub != NULL) {
1095 kfree(pool->base.hubbub);
1096 pool->base.hubbub = NULL;
1097 }
1098
1099 if (pool->base.dio != NULL) {
1100 kfree(TO_DCN10_DIO(pool->base.dio));
1101 pool->base.dio = NULL;
1102 }
1103
1104 for (i = 0; i < pool->base.pipe_count; i++) {
1105 if (pool->base.dpps[i] != NULL)
1106 dcn301_dpp_destroy(&pool->base.dpps[i]);
1107
1108 if (pool->base.ipps[i] != NULL)
1109 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1110
1111 if (pool->base.hubps[i] != NULL) {
1112 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1113 pool->base.hubps[i] = NULL;
1114 }
1115
1116 if (pool->base.irqs != NULL) {
1117 dal_irq_service_destroy(&pool->base.irqs);
1118 }
1119 }
1120
1121 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1122 if (pool->base.engines[i] != NULL)
1123 dce110_engine_destroy(&pool->base.engines[i]);
1124 if (pool->base.hw_i2cs[i] != NULL) {
1125 kfree(pool->base.hw_i2cs[i]);
1126 pool->base.hw_i2cs[i] = NULL;
1127 }
1128 if (pool->base.sw_i2cs[i] != NULL) {
1129 kfree(pool->base.sw_i2cs[i]);
1130 pool->base.sw_i2cs[i] = NULL;
1131 }
1132 }
1133
1134 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1135 if (pool->base.opps[i] != NULL)
1136 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1137 }
1138
1139 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1140 if (pool->base.timing_generators[i] != NULL) {
1141 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1142 pool->base.timing_generators[i] = NULL;
1143 }
1144 }
1145
1146 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1147 if (pool->base.dwbc[i] != NULL) {
1148 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1149 pool->base.dwbc[i] = NULL;
1150 }
1151 if (pool->base.mcif_wb[i] != NULL) {
1152 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1153 pool->base.mcif_wb[i] = NULL;
1154 }
1155 }
1156
1157 for (i = 0; i < pool->base.audio_count; i++) {
1158 if (pool->base.audios[i])
1159 dce_aud_destroy(&pool->base.audios[i]);
1160 }
1161
1162 for (i = 0; i < pool->base.clk_src_count; i++) {
1163 if (pool->base.clock_sources[i] != NULL) {
1164 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1165 pool->base.clock_sources[i] = NULL;
1166 }
1167 }
1168
1169 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1170 if (pool->base.mpc_lut[i] != NULL) {
1171 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1172 pool->base.mpc_lut[i] = NULL;
1173 }
1174 if (pool->base.mpc_shaper[i] != NULL) {
1175 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1176 pool->base.mpc_shaper[i] = NULL;
1177 }
1178 }
1179
1180 if (pool->base.dp_clock_source != NULL) {
1181 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1182 pool->base.dp_clock_source = NULL;
1183 }
1184
1185 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1186 if (pool->base.multiple_abms[i] != NULL)
1187 dce_abm_destroy(&pool->base.multiple_abms[i]);
1188 }
1189
1190 if (pool->base.dccg != NULL)
1191 dcn_dccg_destroy(&pool->base.dccg);
1192 }
1193
dcn301_hubp_create(struct dc_context * ctx,uint32_t inst)1194 static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
1195 {
1196 struct dcn20_hubp *hubp2 =
1197 kzalloc_obj(struct dcn20_hubp);
1198
1199 if (!hubp2)
1200 return NULL;
1201
1202 if (hubp3_construct(hubp2, ctx, inst,
1203 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1204 return &hubp2->base;
1205
1206 BREAK_TO_DEBUGGER();
1207 kfree(hubp2);
1208 return NULL;
1209 }
1210
dcn301_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1211 static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1212 {
1213 int i;
1214 uint32_t pipe_count = pool->res_cap->num_dwb;
1215
1216 for (i = 0; i < pipe_count; i++) {
1217 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1218
1219 if (!dwbc30) {
1220 dm_error("DC: failed to create dwbc30!\n");
1221 return false;
1222 }
1223
1224 dcn30_dwbc_construct(dwbc30, ctx,
1225 &dwbc30_regs[i],
1226 &dwbc30_shift,
1227 &dwbc30_mask,
1228 i);
1229
1230 pool->dwbc[i] = &dwbc30->base;
1231 }
1232 return true;
1233 }
1234
dcn301_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1235 static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1236 {
1237 int i;
1238 uint32_t pipe_count = pool->res_cap->num_dwb;
1239
1240 for (i = 0; i < pipe_count; i++) {
1241 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1242
1243 if (!mcif_wb30) {
1244 dm_error("DC: failed to create mcif_wb30!\n");
1245 return false;
1246 }
1247
1248 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1249 &mcif_wb30_regs[i],
1250 &mcif_wb30_shift,
1251 &mcif_wb30_mask,
1252 i);
1253
1254 pool->mcif_wb[i] = &mcif_wb30->base;
1255 }
1256 return true;
1257 }
1258
dcn301_dsc_create(struct dc_context * ctx,uint32_t inst)1259 static struct display_stream_compressor *dcn301_dsc_create(
1260 struct dc_context *ctx, uint32_t inst)
1261 {
1262 struct dcn20_dsc *dsc =
1263 kzalloc_obj(struct dcn20_dsc);
1264
1265 if (!dsc) {
1266 BREAK_TO_DEBUGGER();
1267 return NULL;
1268 }
1269
1270 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1271 return &dsc->base;
1272 }
1273
1274
dcn301_destroy_resource_pool(struct resource_pool ** pool)1275 static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1276 {
1277 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1278
1279 dcn301_destruct(dcn301_pool);
1280 kfree(dcn301_pool);
1281 *pool = NULL;
1282 }
1283
dcn301_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1284 static struct clock_source *dcn301_clock_source_create(
1285 struct dc_context *ctx,
1286 struct dc_bios *bios,
1287 enum clock_source_id id,
1288 const struct dce110_clk_src_regs *regs,
1289 bool dp_clk_src)
1290 {
1291 struct dce110_clk_src *clk_src =
1292 kzalloc_obj(struct dce110_clk_src);
1293
1294 if (!clk_src)
1295 return NULL;
1296
1297 if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1298 regs, &cs_shift, &cs_mask)) {
1299 clk_src->base.dp_clk_src = dp_clk_src;
1300 return &clk_src->base;
1301 }
1302
1303 kfree(clk_src);
1304 BREAK_TO_DEBUGGER();
1305 return NULL;
1306 }
1307
1308 static struct dc_cap_funcs cap_funcs = {
1309 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1310 };
1311
1312
is_soc_bounding_box_valid(struct dc * dc)1313 static bool is_soc_bounding_box_valid(struct dc *dc)
1314 {
1315 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1316
1317 if (ASICREV_IS_VANGOGH(hw_internal_rev))
1318 return true;
1319
1320 return false;
1321 }
1322
init_soc_bounding_box(struct dc * dc,struct dcn301_resource_pool * pool)1323 static bool init_soc_bounding_box(struct dc *dc,
1324 struct dcn301_resource_pool *pool)
1325 {
1326 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1327 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1328
1329 DC_LOGGER_INIT(dc->ctx->logger);
1330
1331 if (!is_soc_bounding_box_valid(dc)) {
1332 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1333 return false;
1334 }
1335
1336 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1337 loaded_ip->max_num_dpp = pool->base.pipe_count;
1338 DC_FP_START();
1339 dcn20_patch_bounding_box(dc, loaded_bb);
1340 DC_FP_END();
1341
1342 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1343 struct bp_soc_bb_info bb_info = {0};
1344
1345 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1346 DC_FP_START();
1347 dcn301_fpu_init_soc_bounding_box(bb_info);
1348 DC_FP_END();
1349 }
1350 }
1351
1352 return true;
1353 }
1354
1355
set_wm_ranges(struct pp_smu_funcs * pp_smu,struct _vcs_dpi_soc_bounding_box_st * loaded_bb)1356 static void set_wm_ranges(
1357 struct pp_smu_funcs *pp_smu,
1358 struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1359 {
1360 struct pp_smu_wm_range_sets ranges = {0};
1361 int i;
1362
1363 ranges.num_reader_wm_sets = 0;
1364
1365 if (loaded_bb->num_states == 1) {
1366 ranges.reader_wm_sets[0].wm_inst = 0;
1367 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1368 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1369 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1370 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1371
1372 ranges.num_reader_wm_sets = 1;
1373 } else if (loaded_bb->num_states > 1) {
1374 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1375 ranges.reader_wm_sets[i].wm_inst = i;
1376 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1377 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1378 DC_FP_START();
1379 dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb);
1380 DC_FP_END();
1381 ranges.num_reader_wm_sets = i + 1;
1382 }
1383
1384 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1385 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1386 }
1387
1388 ranges.num_writer_wm_sets = 1;
1389
1390 ranges.writer_wm_sets[0].wm_inst = 0;
1391 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1392 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1393 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1394 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1395
1396 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1397 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1398 }
1399
dcn301_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1400 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1401 {
1402 DC_FP_START();
1403 dcn301_fpu_update_bw_bounding_box(dc, bw_params);
1404 DC_FP_END();
1405 }
1406
dcn301_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel_req)1407 static void dcn301_calculate_wm_and_dlg(struct dc *dc,
1408 struct dc_state *context,
1409 display_e2e_pipe_params_st *pipes,
1410 int pipe_cnt,
1411 int vlevel_req)
1412 {
1413 DC_FP_START();
1414 dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req);
1415 DC_FP_END();
1416 }
1417
1418 static struct resource_funcs dcn301_res_pool_funcs = {
1419 .destroy = dcn301_destroy_resource_pool,
1420 .link_enc_create = dcn301_link_encoder_create,
1421 .panel_cntl_create = dcn301_panel_cntl_create,
1422 .validate_bandwidth = dcn30_validate_bandwidth,
1423 .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1424 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1425 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1426 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1427 .release_pipe = dcn20_release_pipe,
1428 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1429 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1430 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1431 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1432 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1433 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1434 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1435 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1436 .update_bw_bounding_box = dcn301_update_bw_bounding_box,
1437 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1438 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1439 .get_default_tiling_info = dcn10_get_default_tiling_info,
1440 };
1441
dcn301_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn301_resource_pool * pool)1442 static bool dcn301_resource_construct(
1443 uint8_t num_virtual_links,
1444 struct dc *dc,
1445 struct dcn301_resource_pool *pool)
1446 {
1447 int i, j;
1448 struct dc_context *ctx = dc->ctx;
1449 struct irq_service_init_data init_data;
1450 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1451 uint32_t num_pipes = 0;
1452
1453 DC_LOGGER_INIT(dc->ctx->logger);
1454
1455 ctx->dc_bios->regs = &bios_regs;
1456
1457 if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435)
1458 res_cap_dcn301.num_pll = 2;
1459 pool->base.res_cap = &res_cap_dcn301;
1460
1461 pool->base.funcs = &dcn301_res_pool_funcs;
1462
1463 /*************************************************
1464 * Resource + asic cap harcoding *
1465 *************************************************/
1466 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1467 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1468 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1469 dc->caps.max_downscale_ratio = 600;
1470 dc->caps.i2c_speed_in_khz = 100;
1471 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/
1472 dc->caps.max_cursor_size = 256;
1473 dc->caps.min_horizontal_blanking_period = 80;
1474 dc->caps.dmdata_alloc_size = 2048;
1475 dc->caps.max_slave_planes = 2;
1476 dc->caps.max_slave_yuv_planes = 2;
1477 dc->caps.max_slave_rgb_planes = 2;
1478 dc->caps.is_apu = true;
1479 dc->caps.post_blend_color_processing = true;
1480 dc->caps.force_dp_tps4_for_cp2520 = true;
1481 dc->caps.extended_aux_timeout_support = true;
1482 dc->caps.dmcub_support = true;
1483
1484 /* Color pipeline capabilities */
1485 dc->caps.color.dpp.dcn_arch = 1;
1486 dc->caps.color.dpp.input_lut_shared = 0;
1487 dc->caps.color.dpp.icsc = 1;
1488 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1489 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1490 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1491 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1492 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1493 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1494 dc->caps.color.dpp.post_csc = 1;
1495 dc->caps.color.dpp.gamma_corr = 1;
1496 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1497
1498 dc->caps.color.dpp.hw_3d_lut = 1;
1499 dc->caps.color.dpp.ogam_ram = 1;
1500 // no OGAM ROM on DCN301
1501 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1502 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1503 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1504 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1505 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1506 dc->caps.color.dpp.ocsc = 0;
1507
1508 dc->caps.color.mpc.gamut_remap = 1;
1509 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1510 dc->caps.color.mpc.ogam_ram = 1;
1511 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1512 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1513 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1514 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1515 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1516 dc->caps.color.mpc.ocsc = 1;
1517
1518 dc->caps.dp_hdmi21_pcon_support = true;
1519
1520 /* read VBIOS LTTPR caps */
1521 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1522 enum bp_result bp_query_result;
1523 uint8_t is_vbios_lttpr_enable = 0;
1524
1525 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1526 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1527 }
1528
1529 if (ctx->dc_bios->funcs->get_lttpr_interop) {
1530 enum bp_result bp_query_result;
1531 uint8_t is_vbios_interop_enabled = 0;
1532
1533 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1534 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1535 }
1536 dc->check_config = config_defaults;
1537
1538 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1539 dc->debug = debug_defaults_drv;
1540
1541 // Init the vm_helper
1542 if (dc->vm_helper)
1543 vm_helper_init(dc->vm_helper, 16);
1544
1545 /*************************************************
1546 * Create resources *
1547 *************************************************/
1548
1549 /* Clock Sources for Pixel Clock*/
1550 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1551 dcn301_clock_source_create(ctx, ctx->dc_bios,
1552 CLOCK_SOURCE_COMBO_PHY_PLL0,
1553 &clk_src_regs[0], false);
1554 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1555 dcn301_clock_source_create(ctx, ctx->dc_bios,
1556 CLOCK_SOURCE_COMBO_PHY_PLL1,
1557 &clk_src_regs[1], false);
1558 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1559 dcn301_clock_source_create(ctx, ctx->dc_bios,
1560 CLOCK_SOURCE_COMBO_PHY_PLL2,
1561 &clk_src_regs[2], false);
1562 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1563 dcn301_clock_source_create(ctx, ctx->dc_bios,
1564 CLOCK_SOURCE_COMBO_PHY_PLL3,
1565 &clk_src_regs[3], false);
1566
1567 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1568
1569 /* todo: not reuse phy_pll registers */
1570 pool->base.dp_clock_source =
1571 dcn301_clock_source_create(ctx, ctx->dc_bios,
1572 CLOCK_SOURCE_ID_DP_DTO,
1573 &clk_src_regs[0], true);
1574
1575 for (i = 0; i < pool->base.clk_src_count; i++) {
1576 if (pool->base.clock_sources[i] == NULL) {
1577 dm_error("DC: failed to create clock sources!\n");
1578 BREAK_TO_DEBUGGER();
1579 goto create_fail;
1580 }
1581 }
1582
1583 /* DCCG */
1584 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1585 if (pool->base.dccg == NULL) {
1586 dm_error("DC: failed to create dccg!\n");
1587 BREAK_TO_DEBUGGER();
1588 goto create_fail;
1589 }
1590
1591 init_soc_bounding_box(dc, pool);
1592
1593 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1594 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1595
1596 num_pipes = dcn3_01_ip.max_num_dpp;
1597
1598 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1599 if (pipe_fuses & 1 << i)
1600 num_pipes--;
1601 dcn3_01_ip.max_num_dpp = num_pipes;
1602 dcn3_01_ip.max_num_otg = num_pipes;
1603
1604
1605 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1606
1607 /* IRQ */
1608 init_data.ctx = dc->ctx;
1609 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1610 if (!pool->base.irqs)
1611 goto create_fail;
1612
1613 /* HUBBUB */
1614 pool->base.hubbub = dcn301_hubbub_create(ctx);
1615 if (pool->base.hubbub == NULL) {
1616 BREAK_TO_DEBUGGER();
1617 dm_error("DC: failed to create hubbub!\n");
1618 goto create_fail;
1619 }
1620
1621 /* DIO */
1622 pool->base.dio = dcn301_dio_create(ctx);
1623 if (pool->base.dio == NULL) {
1624 BREAK_TO_DEBUGGER();
1625 dm_error("DC: failed to create dio!\n");
1626 goto create_fail;
1627 }
1628
1629 j = 0;
1630 /* HUBPs, DPPs, OPPs and TGs */
1631 for (i = 0; i < pool->base.pipe_count; i++) {
1632
1633 /* if pipe is disabled, skip instance of HW pipe,
1634 * i.e, skip ASIC register instance
1635 */
1636 if ((pipe_fuses & (1 << i)) != 0) {
1637 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1638 continue;
1639 }
1640
1641 pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1642 if (pool->base.hubps[j] == NULL) {
1643 BREAK_TO_DEBUGGER();
1644 dm_error(
1645 "DC: failed to create hubps!\n");
1646 goto create_fail;
1647 }
1648
1649 pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1650 if (pool->base.dpps[j] == NULL) {
1651 BREAK_TO_DEBUGGER();
1652 dm_error(
1653 "DC: failed to create dpps!\n");
1654 goto create_fail;
1655 }
1656
1657 pool->base.opps[j] = dcn301_opp_create(ctx, i);
1658 if (pool->base.opps[j] == NULL) {
1659 BREAK_TO_DEBUGGER();
1660 dm_error(
1661 "DC: failed to create output pixel processor!\n");
1662 goto create_fail;
1663 }
1664
1665 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1666 if (pool->base.timing_generators[j] == NULL) {
1667 BREAK_TO_DEBUGGER();
1668 dm_error("DC: failed to create tg!\n");
1669 goto create_fail;
1670 }
1671 j++;
1672 }
1673 pool->base.timing_generator_count = j;
1674 pool->base.pipe_count = j;
1675 pool->base.mpcc_count = j;
1676
1677 /* ABM (or ABMs for NV2x) */
1678 /* TODO: */
1679 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1680 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1681 &abm_regs[i],
1682 &abm_shift,
1683 &abm_mask);
1684 if (pool->base.multiple_abms[i] == NULL) {
1685 dm_error("DC: failed to create abm for pipe %d!\n", i);
1686 BREAK_TO_DEBUGGER();
1687 goto create_fail;
1688 }
1689 }
1690
1691 /* MPC and DSC */
1692 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1693 if (pool->base.mpc == NULL) {
1694 BREAK_TO_DEBUGGER();
1695 dm_error("DC: failed to create mpc!\n");
1696 goto create_fail;
1697 }
1698
1699 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1700 pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1701 if (pool->base.dscs[i] == NULL) {
1702 BREAK_TO_DEBUGGER();
1703 dm_error("DC: failed to create display stream compressor %d!\n", i);
1704 goto create_fail;
1705 }
1706 }
1707
1708 /* DWB and MMHUBBUB */
1709 if (!dcn301_dwbc_create(ctx, &pool->base)) {
1710 BREAK_TO_DEBUGGER();
1711 dm_error("DC: failed to create dwbc!\n");
1712 goto create_fail;
1713 }
1714
1715 if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1716 BREAK_TO_DEBUGGER();
1717 dm_error("DC: failed to create mcif_wb!\n");
1718 goto create_fail;
1719 }
1720
1721 /* AUX and I2C */
1722 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1723 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1724 if (pool->base.engines[i] == NULL) {
1725 BREAK_TO_DEBUGGER();
1726 dm_error(
1727 "DC:failed to create aux engine!!\n");
1728 goto create_fail;
1729 }
1730 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1731 if (pool->base.hw_i2cs[i] == NULL) {
1732 BREAK_TO_DEBUGGER();
1733 dm_error(
1734 "DC:failed to create hw i2c!!\n");
1735 goto create_fail;
1736 }
1737 pool->base.sw_i2cs[i] = NULL;
1738 }
1739
1740 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1741 if (!resource_construct(num_virtual_links, dc, &pool->base,
1742 &res_create_funcs))
1743 goto create_fail;
1744
1745 /* HW Sequencer and Plane caps */
1746 dcn301_hw_sequencer_construct(dc);
1747
1748 dc->caps.max_planes = pool->base.pipe_count;
1749
1750 for (i = 0; i < dc->caps.max_planes; ++i)
1751 dc->caps.planes[i] = plane_cap;
1752
1753 dc->caps.max_odm_combine_factor = 4;
1754
1755 dc->cap_funcs = cap_funcs;
1756
1757 return true;
1758
1759 create_fail:
1760
1761 dcn301_destruct(pool);
1762
1763 return false;
1764 }
1765
dcn301_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1766 struct resource_pool *dcn301_create_resource_pool(
1767 const struct dc_init_data *init_data,
1768 struct dc *dc)
1769 {
1770 struct dcn301_resource_pool *pool =
1771 kzalloc_obj(struct dcn301_resource_pool);
1772
1773 if (!pool)
1774 return NULL;
1775
1776 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
1777 return &pool->base;
1778
1779 BREAK_TO_DEBUGGER();
1780 kfree(pool);
1781 return NULL;
1782 }
1783