1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc.h"
28
29 #include "dcn10/dcn10_init.h"
30
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dcn10/dcn10_resource.h"
34 #include "dcn10/dcn10_ipp.h"
35 #include "dcn10/dcn10_mpc.h"
36
37 #include "dcn10/dcn10_dwb.h"
38
39 #include "irq/dcn10/irq_service_dcn10.h"
40 #include "dcn10/dcn10_dpp.h"
41 #include "dcn10/dcn10_optc.h"
42 #include "dcn10/dcn10_hwseq.h"
43 #include "dce110/dce110_hwseq.h"
44 #include "dcn10/dcn10_opp.h"
45 #include "dcn10/dcn10_link_encoder.h"
46 #include "dcn10/dcn10_stream_encoder.h"
47 #include "dce/dce_clock_source.h"
48 #include "dce/dce_audio.h"
49 #include "dce/dce_hwseq.h"
50 #include "virtual/virtual_stream_encoder.h"
51 #include "dce110/dce110_resource.h"
52 #include "dce112/dce112_resource.h"
53 #include "dcn10/dcn10_hubp.h"
54 #include "dcn10/dcn10_hubbub.h"
55 #include "dce/dce_panel_cntl.h"
56
57 #include "soc15_hw_ip.h"
58 #include "vega10_ip_offset.h"
59
60 #include "dcn/dcn_1_0_offset.h"
61 #include "dcn/dcn_1_0_sh_mask.h"
62
63 #include "nbio/nbio_7_0_offset.h"
64
65 #include "mmhub/mmhub_9_1_offset.h"
66 #include "mmhub/mmhub_9_1_sh_mask.h"
67
68 #include "reg_helper.h"
69 #include "dce/dce_abm.h"
70 #include "dce/dce_dmcu.h"
71 #include "dce/dce_aux.h"
72 #include "dce/dce_i2c.h"
73
74 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
75 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
76 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
77 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
78 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
80 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
82 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
84 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
85 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
86 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
87 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
88 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
89 #endif
90
91
92 enum dcn10_clk_src_array_id {
93 DCN10_CLK_SRC_PLL0,
94 DCN10_CLK_SRC_PLL1,
95 DCN10_CLK_SRC_PLL2,
96 DCN10_CLK_SRC_PLL3,
97 DCN10_CLK_SRC_TOTAL,
98 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
99 };
100
101 /* begin *********************
102 * macros to expend register list macro defined in HW object header file */
103
104 /* DCN */
105 #define BASE_INNER(seg) \
106 DCE_BASE__INST0_SEG ## seg
107
108 #define BASE(seg) \
109 BASE_INNER(seg)
110
111 #define SR(reg_name)\
112 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
113 mm ## reg_name
114
115 #define SRI(reg_name, block, id)\
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
118
119
120 #define SRII(reg_name, block, id)\
121 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
123
124 #define VUPDATE_SRII(reg_name, block, id)\
125 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
126 mm ## reg_name ## 0 ## _ ## block ## id
127
128 /* set field/register/bitfield name */
129 #define SFRB(field_name, reg_name, bitfield, post_fix)\
130 .field_name = reg_name ## __ ## bitfield ## post_fix
131
132 /* NBIO */
133 #define NBIO_BASE_INNER(seg) \
134 NBIF_BASE__INST0_SEG ## seg
135
136 #define NBIO_BASE(seg) \
137 NBIO_BASE_INNER(seg)
138
139 #define NBIO_SR(reg_name)\
140 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
141 mm ## reg_name
142
143 /* MMHUB */
144 #define MMHUB_BASE_INNER(seg) \
145 MMHUB_BASE__INST0_SEG ## seg
146
147 #define MMHUB_BASE(seg) \
148 MMHUB_BASE_INNER(seg)
149
150 #define MMHUB_SR(reg_name)\
151 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
152 mm ## reg_name
153
154 /* macros to expend register list macro defined in HW object header file
155 * end *********************/
156
157
158 static const struct dce_dmcu_registers dmcu_regs = {
159 DMCU_DCN10_REG_LIST()
160 };
161
162 static const struct dce_dmcu_shift dmcu_shift = {
163 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
164 };
165
166 static const struct dce_dmcu_mask dmcu_mask = {
167 DMCU_MASK_SH_LIST_DCN10(_MASK)
168 };
169
170 static const struct dce_abm_registers abm_regs = {
171 ABM_DCN10_REG_LIST(0)
172 };
173
174 static const struct dce_abm_shift abm_shift = {
175 ABM_MASK_SH_LIST_DCN10(__SHIFT)
176 };
177
178 static const struct dce_abm_mask abm_mask = {
179 ABM_MASK_SH_LIST_DCN10(_MASK)
180 };
181
182 #define stream_enc_regs(id)\
183 [id] = {\
184 SE_DCN_REG_LIST(id)\
185 }
186
187 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
188 stream_enc_regs(0),
189 stream_enc_regs(1),
190 stream_enc_regs(2),
191 stream_enc_regs(3),
192 };
193
194 static const struct dcn10_stream_encoder_shift se_shift = {
195 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
196 };
197
198 static const struct dcn10_stream_encoder_mask se_mask = {
199 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
200 };
201
202 #define audio_regs(id)\
203 [id] = {\
204 AUD_COMMON_REG_LIST(id)\
205 }
206
207 static const struct dce_audio_registers audio_regs[] = {
208 audio_regs(0),
209 audio_regs(1),
210 audio_regs(2),
211 audio_regs(3),
212 };
213
214 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
215 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
216 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
217 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
218
219 static const struct dce_audio_shift audio_shift = {
220 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
221 };
222
223 static const struct dce_audio_mask audio_mask = {
224 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
225 };
226
227 #define aux_regs(id)\
228 [id] = {\
229 AUX_REG_LIST(id)\
230 }
231
232 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
233 aux_regs(0),
234 aux_regs(1),
235 aux_regs(2),
236 aux_regs(3)
237 };
238
239 #define hpd_regs(id)\
240 [id] = {\
241 HPD_REG_LIST(id)\
242 }
243
244 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
245 hpd_regs(0),
246 hpd_regs(1),
247 hpd_regs(2),
248 hpd_regs(3)
249 };
250
251 #define link_regs(id)\
252 [id] = {\
253 LE_DCN10_REG_LIST(id), \
254 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
255 }
256
257 static const struct dcn10_link_enc_registers link_enc_regs[] = {
258 link_regs(0),
259 link_regs(1),
260 link_regs(2),
261 link_regs(3)
262 };
263
264 static const struct dcn10_link_enc_shift le_shift = {
265 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
266 };
267
268 static const struct dcn10_link_enc_mask le_mask = {
269 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
270 };
271
272 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
273 { DCN_PANEL_CNTL_REG_LIST() }
274 };
275
276 static const struct dce_panel_cntl_shift panel_cntl_shift = {
277 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
278 };
279
280 static const struct dce_panel_cntl_mask panel_cntl_mask = {
281 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
282 };
283
284 static const struct dce110_aux_registers_shift aux_shift = {
285 DCN10_AUX_MASK_SH_LIST(__SHIFT)
286 };
287
288 static const struct dce110_aux_registers_mask aux_mask = {
289 DCN10_AUX_MASK_SH_LIST(_MASK)
290 };
291
292 #define ipp_regs(id)\
293 [id] = {\
294 IPP_REG_LIST_DCN10(id),\
295 }
296
297 static const struct dcn10_ipp_registers ipp_regs[] = {
298 ipp_regs(0),
299 ipp_regs(1),
300 ipp_regs(2),
301 ipp_regs(3),
302 };
303
304 static const struct dcn10_ipp_shift ipp_shift = {
305 IPP_MASK_SH_LIST_DCN10(__SHIFT)
306 };
307
308 static const struct dcn10_ipp_mask ipp_mask = {
309 IPP_MASK_SH_LIST_DCN10(_MASK),
310 };
311
312 #define opp_regs(id)\
313 [id] = {\
314 OPP_REG_LIST_DCN10(id),\
315 }
316
317 static const struct dcn10_opp_registers opp_regs[] = {
318 opp_regs(0),
319 opp_regs(1),
320 opp_regs(2),
321 opp_regs(3),
322 };
323
324 static const struct dcn10_opp_shift opp_shift = {
325 OPP_MASK_SH_LIST_DCN10(__SHIFT)
326 };
327
328 static const struct dcn10_opp_mask opp_mask = {
329 OPP_MASK_SH_LIST_DCN10(_MASK),
330 };
331
332 #define aux_engine_regs(id)\
333 [id] = {\
334 AUX_COMMON_REG_LIST(id), \
335 .AUX_RESET_MASK = 0 \
336 }
337
338 static const struct dce110_aux_registers aux_engine_regs[] = {
339 aux_engine_regs(0),
340 aux_engine_regs(1),
341 aux_engine_regs(2),
342 aux_engine_regs(3),
343 aux_engine_regs(4),
344 aux_engine_regs(5)
345 };
346
347 #define tf_regs(id)\
348 [id] = {\
349 TF_REG_LIST_DCN10(id),\
350 }
351
352 static const struct dcn_dpp_registers tf_regs[] = {
353 tf_regs(0),
354 tf_regs(1),
355 tf_regs(2),
356 tf_regs(3),
357 };
358
359 static const struct dcn_dpp_shift tf_shift = {
360 TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
361 TF_DEBUG_REG_LIST_SH_DCN10
362
363 };
364
365 static const struct dcn_dpp_mask tf_mask = {
366 TF_REG_LIST_SH_MASK_DCN10(_MASK),
367 TF_DEBUG_REG_LIST_MASK_DCN10
368 };
369
370 static const struct dcn_mpc_registers mpc_regs = {
371 MPC_COMMON_REG_LIST_DCN1_0(0),
372 MPC_COMMON_REG_LIST_DCN1_0(1),
373 MPC_COMMON_REG_LIST_DCN1_0(2),
374 MPC_COMMON_REG_LIST_DCN1_0(3),
375 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
376 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
377 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
378 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
379 };
380
381 static const struct dcn_mpc_shift mpc_shift = {
382 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
383 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
384 };
385
386 static const struct dcn_mpc_mask mpc_mask = {
387 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
388 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
389 };
390
391 #define tg_regs(id)\
392 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
393
394 static const struct dcn_optc_registers tg_regs[] = {
395 tg_regs(0),
396 tg_regs(1),
397 tg_regs(2),
398 tg_regs(3),
399 };
400
401 static const struct dcn_optc_shift tg_shift = {
402 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
403 };
404
405 static const struct dcn_optc_mask tg_mask = {
406 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
407 };
408
409 static const struct bios_registers bios_regs = {
410 NBIO_SR(BIOS_SCRATCH_3),
411 NBIO_SR(BIOS_SCRATCH_6)
412 };
413
414 #define hubp_regs(id)\
415 [id] = {\
416 HUBP_REG_LIST_DCN10(id)\
417 }
418
419 static const struct dcn_mi_registers hubp_regs[] = {
420 hubp_regs(0),
421 hubp_regs(1),
422 hubp_regs(2),
423 hubp_regs(3),
424 };
425
426 static const struct dcn_mi_shift hubp_shift = {
427 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
428 };
429
430 static const struct dcn_mi_mask hubp_mask = {
431 HUBP_MASK_SH_LIST_DCN10(_MASK)
432 };
433
434 static const struct dcn_hubbub_registers hubbub_reg = {
435 HUBBUB_REG_LIST_DCN10(0)
436 };
437
438 static const struct dcn_hubbub_shift hubbub_shift = {
439 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
440 };
441
442 static const struct dcn_hubbub_mask hubbub_mask = {
443 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
444 };
445
map_transmitter_id_to_phy_instance(enum transmitter transmitter)446 static int map_transmitter_id_to_phy_instance(
447 enum transmitter transmitter)
448 {
449 switch (transmitter) {
450 case TRANSMITTER_UNIPHY_A:
451 return 0;
452 break;
453 case TRANSMITTER_UNIPHY_B:
454 return 1;
455 break;
456 case TRANSMITTER_UNIPHY_C:
457 return 2;
458 break;
459 case TRANSMITTER_UNIPHY_D:
460 return 3;
461 break;
462 default:
463 ASSERT(0);
464 return 0;
465 }
466 }
467
468 #define clk_src_regs(index, pllid)\
469 [index] = {\
470 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
471 }
472
473 static const struct dce110_clk_src_regs clk_src_regs[] = {
474 clk_src_regs(0, A),
475 clk_src_regs(1, B),
476 clk_src_regs(2, C),
477 clk_src_regs(3, D)
478 };
479
480 static const struct dce110_clk_src_shift cs_shift = {
481 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
482 };
483
484 static const struct dce110_clk_src_mask cs_mask = {
485 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
486 };
487
488 static const struct resource_caps res_cap = {
489 .num_timing_generator = 4,
490 .num_opp = 4,
491 .num_video_plane = 4,
492 .num_audio = 4,
493 .num_stream_encoder = 4,
494 .num_pll = 4,
495 .num_ddc = 4,
496 };
497
498 static const struct resource_caps rv2_res_cap = {
499 .num_timing_generator = 3,
500 .num_opp = 3,
501 .num_video_plane = 3,
502 .num_audio = 3,
503 .num_stream_encoder = 3,
504 .num_pll = 3,
505 .num_ddc = 4,
506 };
507
508 static const struct dc_plane_cap plane_cap = {
509 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
510 .per_pixel_alpha = true,
511
512 .pixel_format_support = {
513 .argb8888 = true,
514 .nv12 = true,
515 .fp16 = true,
516 .p010 = false
517 },
518
519 .max_upscale_factor = {
520 .argb8888 = 16000,
521 .nv12 = 16000,
522 .fp16 = 1
523 },
524
525 .max_downscale_factor = {
526 .argb8888 = 250,
527 .nv12 = 250,
528 .fp16 = 1
529 }
530 };
531
532 static const struct dc_debug_options debug_defaults_drv = {
533 .sanity_checks = true,
534 .disable_dmcu = false,
535 .force_abm_enable = false,
536 .clock_trace = true,
537
538 /* raven smu dones't allow 0 disp clk,
539 * smu min disp clk limit is 50Mhz
540 * keep min disp clk 100Mhz avoid smu hang
541 */
542 .min_disp_clk_khz = 100000,
543
544 .disable_pplib_clock_request = false,
545 .disable_pplib_wm_range = false,
546 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
547 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
548 .force_single_disp_pipe_split = true,
549 .disable_dcc = DCC_ENABLE,
550 .voltage_align_fclk = true,
551 .disable_stereo_support = true,
552 .vsr_support = true,
553 .performance_trace = false,
554 .az_endpoint_mute_only = true,
555 .recovery_enabled = false, /*enable this by default after testing.*/
556 .max_downscale_src_width = 3840,
557 .underflow_assert_delay_us = 0xFFFFFFFF,
558 .enable_legacy_fast_update = true,
559 .using_dml2 = false,
560 };
561
dcn10_dpp_destroy(struct dpp ** dpp)562 static void dcn10_dpp_destroy(struct dpp **dpp)
563 {
564 kfree(TO_DCN10_DPP(*dpp));
565 *dpp = NULL;
566 }
567
dcn10_dpp_create(struct dc_context * ctx,uint32_t inst)568 static struct dpp *dcn10_dpp_create(
569 struct dc_context *ctx,
570 uint32_t inst)
571 {
572 struct dcn10_dpp *dpp =
573 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
574
575 if (!dpp)
576 return NULL;
577
578 dpp1_construct(dpp, ctx, inst,
579 &tf_regs[inst], &tf_shift, &tf_mask);
580 return &dpp->base;
581 }
582
dcn10_ipp_create(struct dc_context * ctx,uint32_t inst)583 static struct input_pixel_processor *dcn10_ipp_create(
584 struct dc_context *ctx, uint32_t inst)
585 {
586 struct dcn10_ipp *ipp =
587 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
588
589 if (!ipp) {
590 BREAK_TO_DEBUGGER();
591 return NULL;
592 }
593
594 dcn10_ipp_construct(ipp, ctx, inst,
595 &ipp_regs[inst], &ipp_shift, &ipp_mask);
596 return &ipp->base;
597 }
598
599
dcn10_opp_create(struct dc_context * ctx,uint32_t inst)600 static struct output_pixel_processor *dcn10_opp_create(
601 struct dc_context *ctx, uint32_t inst)
602 {
603 struct dcn10_opp *opp =
604 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
605
606 if (!opp) {
607 BREAK_TO_DEBUGGER();
608 return NULL;
609 }
610
611 dcn10_opp_construct(opp, ctx, inst,
612 &opp_regs[inst], &opp_shift, &opp_mask);
613 return &opp->base;
614 }
615
dcn10_aux_engine_create(struct dc_context * ctx,uint32_t inst)616 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
617 uint32_t inst)
618 {
619 struct aux_engine_dce110 *aux_engine =
620 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
621
622 if (!aux_engine)
623 return NULL;
624
625 dce110_aux_engine_construct(aux_engine, ctx, inst,
626 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
627 &aux_engine_regs[inst],
628 &aux_mask,
629 &aux_shift,
630 ctx->dc->caps.extended_aux_timeout_support);
631
632 return &aux_engine->base;
633 }
634 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
635
636 static const struct dce_i2c_registers i2c_hw_regs[] = {
637 i2c_inst_regs(1),
638 i2c_inst_regs(2),
639 i2c_inst_regs(3),
640 i2c_inst_regs(4),
641 i2c_inst_regs(5),
642 i2c_inst_regs(6),
643 };
644
645 static const struct dce_i2c_shift i2c_shifts = {
646 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
647 };
648
649 static const struct dce_i2c_mask i2c_masks = {
650 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
651 };
652
dcn10_i2c_hw_create(struct dc_context * ctx,uint32_t inst)653 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
654 uint32_t inst)
655 {
656 struct dce_i2c_hw *dce_i2c_hw =
657 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
658
659 if (!dce_i2c_hw)
660 return NULL;
661
662 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
663 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
664
665 return dce_i2c_hw;
666 }
dcn10_mpc_create(struct dc_context * ctx)667 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
668 {
669 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
670 GFP_KERNEL);
671
672 if (!mpc10)
673 return NULL;
674
675 dcn10_mpc_construct(mpc10, ctx,
676 &mpc_regs,
677 &mpc_shift,
678 &mpc_mask,
679 4);
680
681 return &mpc10->base;
682 }
683
dcn10_hubbub_create(struct dc_context * ctx)684 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
685 {
686 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
687 GFP_KERNEL);
688
689 if (!dcn10_hubbub)
690 return NULL;
691
692 hubbub1_construct(&dcn10_hubbub->base, ctx,
693 &hubbub_reg,
694 &hubbub_shift,
695 &hubbub_mask);
696
697 return &dcn10_hubbub->base;
698 }
699
dcn10_timing_generator_create(struct dc_context * ctx,uint32_t instance)700 static struct timing_generator *dcn10_timing_generator_create(
701 struct dc_context *ctx,
702 uint32_t instance)
703 {
704 struct optc *tgn10 =
705 kzalloc(sizeof(struct optc), GFP_KERNEL);
706
707 if (!tgn10)
708 return NULL;
709
710 tgn10->base.inst = instance;
711 tgn10->base.ctx = ctx;
712
713 tgn10->tg_regs = &tg_regs[instance];
714 tgn10->tg_shift = &tg_shift;
715 tgn10->tg_mask = &tg_mask;
716
717 dcn10_timing_generator_init(tgn10);
718
719 return &tgn10->base;
720 }
721
722 static const struct encoder_feature_support link_enc_feature = {
723 .max_hdmi_deep_color = COLOR_DEPTH_121212,
724 .max_hdmi_pixel_clock = 600000,
725 .hdmi_ycbcr420_supported = true,
726 .dp_ycbcr420_supported = true,
727 .flags.bits.IS_HBR2_CAPABLE = true,
728 .flags.bits.IS_HBR3_CAPABLE = true,
729 .flags.bits.IS_TPS3_CAPABLE = true,
730 .flags.bits.IS_TPS4_CAPABLE = true
731 };
732
dcn10_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)733 static struct link_encoder *dcn10_link_encoder_create(
734 struct dc_context *ctx,
735 const struct encoder_init_data *enc_init_data)
736 {
737 struct dcn10_link_encoder *enc10 =
738 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
739 int link_regs_id;
740
741 if (!enc10 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
742 return NULL;
743
744 link_regs_id =
745 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
746
747 dcn10_link_encoder_construct(enc10,
748 enc_init_data,
749 &link_enc_feature,
750 &link_enc_regs[link_regs_id],
751 &link_enc_aux_regs[enc_init_data->channel - 1],
752 &link_enc_hpd_regs[enc_init_data->hpd_source],
753 &le_shift,
754 &le_mask);
755
756 return &enc10->base;
757 }
758
dcn10_panel_cntl_create(const struct panel_cntl_init_data * init_data)759 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
760 {
761 struct dce_panel_cntl *panel_cntl =
762 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
763
764 if (!panel_cntl)
765 return NULL;
766
767 dce_panel_cntl_construct(panel_cntl,
768 init_data,
769 &panel_cntl_regs[init_data->inst],
770 &panel_cntl_shift,
771 &panel_cntl_mask);
772
773 return &panel_cntl->base;
774 }
775
dcn10_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)776 static struct clock_source *dcn10_clock_source_create(
777 struct dc_context *ctx,
778 struct dc_bios *bios,
779 enum clock_source_id id,
780 const struct dce110_clk_src_regs *regs,
781 bool dp_clk_src)
782 {
783 struct dce110_clk_src *clk_src =
784 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
785
786 if (!clk_src)
787 return NULL;
788
789 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
790 regs, &cs_shift, &cs_mask)) {
791 clk_src->base.dp_clk_src = dp_clk_src;
792 return &clk_src->base;
793 }
794
795 kfree(clk_src);
796 BREAK_TO_DEBUGGER();
797 return NULL;
798 }
799
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)800 static void read_dce_straps(
801 struct dc_context *ctx,
802 struct resource_straps *straps)
803 {
804 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
805 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
806 }
807
create_audio(struct dc_context * ctx,unsigned int inst)808 static struct audio *create_audio(
809 struct dc_context *ctx, unsigned int inst)
810 {
811 return dce_audio_create(ctx, inst,
812 &audio_regs[inst], &audio_shift, &audio_mask);
813 }
814
dcn10_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)815 static struct stream_encoder *dcn10_stream_encoder_create(
816 enum engine_id eng_id,
817 struct dc_context *ctx)
818 {
819 struct dcn10_stream_encoder *enc1 =
820 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
821
822 if (!enc1)
823 return NULL;
824
825 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
826 &stream_enc_regs[eng_id],
827 &se_shift, &se_mask);
828 return &enc1->base;
829 }
830
831 static const struct dce_hwseq_registers hwseq_reg = {
832 HWSEQ_DCN1_REG_LIST()
833 };
834
835 static const struct dce_hwseq_shift hwseq_shift = {
836 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
837 };
838
839 static const struct dce_hwseq_mask hwseq_mask = {
840 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
841 };
842
dcn10_hwseq_create(struct dc_context * ctx)843 static struct dce_hwseq *dcn10_hwseq_create(
844 struct dc_context *ctx)
845 {
846 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
847
848 if (hws) {
849 hws->ctx = ctx;
850 hws->regs = &hwseq_reg;
851 hws->shifts = &hwseq_shift;
852 hws->masks = &hwseq_mask;
853 hws->wa.DEGVIDCN10_253 = true;
854 hws->wa.false_optc_underflow = true;
855 hws->wa.DEGVIDCN10_254 = true;
856
857 if ((ctx->asic_id.chip_family == FAMILY_RV) &&
858 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev))
859 switch (ctx->asic_id.pci_revision_id) {
860 case PRID_POLLOCK_94:
861 case PRID_POLLOCK_95:
862 case PRID_POLLOCK_E9:
863 case PRID_POLLOCK_EA:
864 case PRID_POLLOCK_EB:
865 hws->wa.wait_hubpret_read_start_during_mpo_transition = true;
866 break;
867 default:
868 hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
869 break;
870 }
871 }
872 return hws;
873 }
874
875 static const struct resource_create_funcs res_create_funcs = {
876 .read_dce_straps = read_dce_straps,
877 .create_audio = create_audio,
878 .create_stream_encoder = dcn10_stream_encoder_create,
879 .create_hwseq = dcn10_hwseq_create,
880 };
881
dcn10_clock_source_destroy(struct clock_source ** clk_src)882 static void dcn10_clock_source_destroy(struct clock_source **clk_src)
883 {
884 kfree(TO_DCE110_CLK_SRC(*clk_src));
885 *clk_src = NULL;
886 }
887
dcn10_pp_smu_create(struct dc_context * ctx)888 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
889 {
890 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
891
892 if (!pp_smu)
893 return pp_smu;
894
895 dm_pp_get_funcs(ctx, pp_smu);
896 return pp_smu;
897 }
898
dcn10_resource_destruct(struct dcn10_resource_pool * pool)899 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
900 {
901 unsigned int i;
902
903 for (i = 0; i < pool->base.stream_enc_count; i++) {
904 if (pool->base.stream_enc[i] != NULL) {
905 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
906 pool->base.stream_enc[i] = NULL;
907 }
908 }
909
910 if (pool->base.mpc != NULL) {
911 kfree(TO_DCN10_MPC(pool->base.mpc));
912 pool->base.mpc = NULL;
913 }
914
915 kfree(pool->base.hubbub);
916 pool->base.hubbub = NULL;
917
918 for (i = 0; i < pool->base.pipe_count; i++) {
919 if (pool->base.opps[i] != NULL)
920 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
921
922 if (pool->base.dpps[i] != NULL)
923 dcn10_dpp_destroy(&pool->base.dpps[i]);
924
925 if (pool->base.ipps[i] != NULL)
926 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
927
928 if (pool->base.hubps[i] != NULL) {
929 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
930 pool->base.hubps[i] = NULL;
931 }
932
933 if (pool->base.irqs != NULL) {
934 dal_irq_service_destroy(&pool->base.irqs);
935 }
936
937 if (pool->base.timing_generators[i] != NULL) {
938 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
939 pool->base.timing_generators[i] = NULL;
940 }
941 }
942
943 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
944 if (pool->base.engines[i] != NULL)
945 dce110_engine_destroy(&pool->base.engines[i]);
946 kfree(pool->base.hw_i2cs[i]);
947 pool->base.hw_i2cs[i] = NULL;
948 kfree(pool->base.sw_i2cs[i]);
949 pool->base.sw_i2cs[i] = NULL;
950 }
951
952 for (i = 0; i < pool->base.audio_count; i++) {
953 if (pool->base.audios[i])
954 dce_aud_destroy(&pool->base.audios[i]);
955 }
956
957 for (i = 0; i < pool->base.clk_src_count; i++) {
958 if (pool->base.clock_sources[i] != NULL) {
959 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
960 pool->base.clock_sources[i] = NULL;
961 }
962 }
963
964 if (pool->base.dp_clock_source != NULL) {
965 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
966 pool->base.dp_clock_source = NULL;
967 }
968
969 if (pool->base.abm != NULL)
970 dce_abm_destroy(&pool->base.abm);
971
972 if (pool->base.dmcu != NULL)
973 dce_dmcu_destroy(&pool->base.dmcu);
974
975 kfree(pool->base.pp_smu);
976 }
977
dcn10_hubp_create(struct dc_context * ctx,uint32_t inst)978 static struct hubp *dcn10_hubp_create(
979 struct dc_context *ctx,
980 uint32_t inst)
981 {
982 struct dcn10_hubp *hubp1 =
983 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
984
985 if (!hubp1)
986 return NULL;
987
988 dcn10_hubp_construct(hubp1, ctx, inst,
989 &hubp_regs[inst], &hubp_shift, &hubp_mask);
990 return &hubp1->base;
991 }
992
get_pixel_clock_parameters(const struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)993 static void get_pixel_clock_parameters(
994 const struct pipe_ctx *pipe_ctx,
995 struct pixel_clk_params *pixel_clk_params)
996 {
997 const struct dc_stream_state *stream = pipe_ctx->stream;
998 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
999 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1000 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1001 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1002 /* TODO: un-hardcode*/
1003 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1004 LINK_RATE_REF_FREQ_IN_KHZ;
1005 pixel_clk_params->flags.ENABLE_SS = 0;
1006 pixel_clk_params->color_depth =
1007 stream->timing.display_color_depth;
1008 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1009 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1010
1011 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1012 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1013
1014 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1015 pixel_clk_params->requested_pix_clk_100hz /= 2;
1016 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1017 pixel_clk_params->requested_pix_clk_100hz *= 2;
1018
1019 }
1020
build_clamping_params(struct dc_stream_state * stream)1021 static void build_clamping_params(struct dc_stream_state *stream)
1022 {
1023 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1024 stream->clamping.c_depth = stream->timing.display_color_depth;
1025 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1026 }
1027
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1028 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1029 {
1030
1031 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1032
1033 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1034 pipe_ctx->clock_source,
1035 &pipe_ctx->stream_res.pix_clk_params,
1036 &pipe_ctx->pll_settings);
1037
1038 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1039
1040 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1041 &pipe_ctx->stream->bit_depth_params);
1042 build_clamping_params(pipe_ctx->stream);
1043 }
1044
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1045 static enum dc_status build_mapped_resource(
1046 const struct dc *dc,
1047 struct dc_state *context,
1048 struct dc_stream_state *stream)
1049 {
1050 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1051
1052 if (!pipe_ctx)
1053 return DC_ERROR_UNEXPECTED;
1054
1055 build_pipe_hw_param(pipe_ctx);
1056 return DC_OK;
1057 }
1058
dcn10_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1059 static enum dc_status dcn10_add_stream_to_ctx(
1060 struct dc *dc,
1061 struct dc_state *new_ctx,
1062 struct dc_stream_state *dc_stream)
1063 {
1064 enum dc_status result = DC_ERROR_UNEXPECTED;
1065
1066 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1067
1068 if (result == DC_OK)
1069 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1070
1071
1072 if (result == DC_OK)
1073 result = build_mapped_resource(dc, new_ctx, dc_stream);
1074
1075 return result;
1076 }
1077
dcn10_acquire_free_pipe_for_layer(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)1078 static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(
1079 const struct dc_state *cur_ctx,
1080 struct dc_state *new_ctx,
1081 const struct resource_pool *pool,
1082 const struct pipe_ctx *opp_head_pipe)
1083 {
1084 struct resource_context *res_ctx = &new_ctx->res_ctx;
1085 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1086 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1087
1088 if (!head_pipe) {
1089 ASSERT(0);
1090 return NULL;
1091 }
1092
1093 if (!idle_pipe)
1094 return NULL;
1095
1096 idle_pipe->stream = head_pipe->stream;
1097 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1098 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1099 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1100
1101 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1102 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1103 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1104 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1105
1106 return idle_pipe;
1107 }
1108
dcn10_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)1109 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1110 const struct dc_dcc_surface_param *input,
1111 struct dc_surface_dcc_cap *output)
1112 {
1113 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1114 dc->res_pool->hubbub,
1115 input,
1116 output);
1117 }
1118
dcn10_destroy_resource_pool(struct resource_pool ** pool)1119 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1120 {
1121 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1122
1123 dcn10_resource_destruct(dcn10_pool);
1124 kfree(dcn10_pool);
1125 *pool = NULL;
1126 }
1127
dcn10_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1128 static bool dcn10_validate_bandwidth(
1129 struct dc *dc,
1130 struct dc_state *context,
1131 bool fast_validate)
1132 {
1133 bool voltage_supported;
1134
1135 DC_FP_START();
1136 voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);
1137 DC_FP_END();
1138
1139 return voltage_supported;
1140 }
1141
dcn10_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)1142 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1143 {
1144 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1145 && caps->max_video_width != 0
1146 && plane_state->src_rect.width > caps->max_video_width)
1147 return DC_FAIL_SURFACE_VALIDATE;
1148
1149 return DC_OK;
1150 }
1151
dcn10_validate_global(struct dc * dc,struct dc_state * context)1152 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1153 {
1154 int i, j;
1155 bool video_down_scaled = false;
1156 bool video_large = false;
1157 bool desktop_large = false;
1158 bool dcc_disabled = false;
1159 bool mpo_enabled = false;
1160
1161 for (i = 0; i < context->stream_count; i++) {
1162 if (context->stream_status[i].plane_count == 0)
1163 continue;
1164
1165 if (context->stream_status[i].plane_count > 2)
1166 return DC_FAIL_UNSUPPORTED_1;
1167
1168 if (context->stream_status[i].plane_count > 1)
1169 mpo_enabled = true;
1170
1171 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1172 struct dc_plane_state *plane =
1173 context->stream_status[i].plane_states[j];
1174
1175
1176 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1177
1178 if (plane->src_rect.width > plane->dst_rect.width ||
1179 plane->src_rect.height > plane->dst_rect.height)
1180 video_down_scaled = true;
1181
1182 if (plane->src_rect.width >= 3840)
1183 video_large = true;
1184
1185 } else {
1186 if (plane->src_rect.width >= 3840)
1187 desktop_large = true;
1188 if (!plane->dcc.enable)
1189 dcc_disabled = true;
1190 }
1191 }
1192 }
1193
1194 /* Disable MPO in multi-display configurations. */
1195 if (context->stream_count > 1 && mpo_enabled)
1196 return DC_FAIL_UNSUPPORTED_1;
1197
1198 /*
1199 * Workaround: On DCN10 there is UMC issue that causes underflow when
1200 * playing 4k video on 4k desktop with video downscaled and single channel
1201 * memory
1202 */
1203 if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1204 dc->dcn_soc->number_of_channels == 1)
1205 return DC_FAIL_SURFACE_VALIDATE;
1206
1207 return DC_OK;
1208 }
1209
dcn10_patch_unknown_plane_state(struct dc_plane_state * plane_state)1210 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1211 {
1212 enum surface_pixel_format surf_pix_format = plane_state->format;
1213 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1214
1215 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1216
1217 if (bpp == 64)
1218 swizzle = DC_SW_64KB_D;
1219 else
1220 swizzle = DC_SW_64KB_S;
1221
1222 plane_state->tiling_info.gfx9.swizzle = swizzle;
1223 return DC_OK;
1224 }
1225
dcn10_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1226 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1227 struct resource_context *res_ctx,
1228 const struct resource_pool *pool,
1229 struct dc_stream_state *stream)
1230 {
1231 int i;
1232 int j = -1;
1233 struct dc_link *link = stream->link;
1234
1235 for (i = 0; i < pool->stream_enc_count; i++) {
1236 if (!res_ctx->is_stream_enc_acquired[i] &&
1237 pool->stream_enc[i]) {
1238 /* Store first available for MST second display
1239 * in daisy chain use case
1240 */
1241
1242 if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)
1243 j = i;
1244
1245 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
1246 link->link_enc->preferred_engine)
1247 return pool->stream_enc[i];
1248 }
1249 }
1250
1251 /*
1252 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1253 */
1254
1255 if (j >= 0)
1256 return pool->stream_enc[j];
1257
1258 return NULL;
1259 }
1260
dcn10_get_vstartup_for_pipe(struct pipe_ctx * pipe_ctx)1261 unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1262 {
1263 return pipe_ctx->pipe_dlg_param.vstartup_start;
1264 }
1265
1266 static const struct dc_cap_funcs cap_funcs = {
1267 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1268 };
1269
1270 static const struct resource_funcs dcn10_res_pool_funcs = {
1271 .destroy = dcn10_destroy_resource_pool,
1272 .link_enc_create = dcn10_link_encoder_create,
1273 .panel_cntl_create = dcn10_panel_cntl_create,
1274 .validate_bandwidth = dcn10_validate_bandwidth,
1275 .acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer,
1276 .validate_plane = dcn10_validate_plane,
1277 .validate_global = dcn10_validate_global,
1278 .add_stream_to_ctx = dcn10_add_stream_to_ctx,
1279 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1280 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1281 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1282 };
1283
read_pipe_fuses(struct dc_context * ctx)1284 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1285 {
1286 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1287 /* RV1 support max 4 pipes */
1288 value = value & 0xf;
1289 return value;
1290 }
1291
verify_clock_values(struct dm_pp_clock_levels_with_voltage * clks)1292 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1293 {
1294 int i;
1295
1296 if (clks->num_levels == 0)
1297 return false;
1298
1299 for (i = 0; i < clks->num_levels; i++)
1300 /* Ensure that the result is sane */
1301 if (clks->data[i].clocks_in_khz == 0)
1302 return false;
1303
1304 return true;
1305 }
1306
dcn10_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn10_resource_pool * pool)1307 static bool dcn10_resource_construct(
1308 uint8_t num_virtual_links,
1309 struct dc *dc,
1310 struct dcn10_resource_pool *pool)
1311 {
1312 int i;
1313 int j;
1314 struct dc_context *ctx = dc->ctx;
1315 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1316 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1317 int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1318 bool res;
1319
1320 ctx->dc_bios->regs = &bios_regs;
1321
1322 if (ctx->dce_version == DCN_VERSION_1_01)
1323 pool->base.res_cap = &rv2_res_cap;
1324 else
1325 pool->base.res_cap = &res_cap;
1326 pool->base.funcs = &dcn10_res_pool_funcs;
1327
1328 /*
1329 * TODO fill in from actual raven resource when we create
1330 * more than virtual encoder
1331 */
1332
1333 /*************************************************
1334 * Resource + asic cap harcoding *
1335 *************************************************/
1336 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1337
1338 /* max pipe num for ASIC before check pipe fuses */
1339 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1340
1341 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1342 pool->base.pipe_count = 3;
1343 dc->caps.max_video_width = 3840;
1344 dc->caps.max_downscale_ratio = 200;
1345 dc->caps.i2c_speed_in_khz = 100;
1346 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1347 dc->caps.max_cursor_size = 256;
1348 dc->caps.min_horizontal_blanking_period = 80;
1349 dc->caps.max_slave_planes = 1;
1350 dc->caps.max_slave_yuv_planes = 1;
1351 dc->caps.max_slave_rgb_planes = 0;
1352 dc->caps.is_apu = true;
1353 dc->caps.post_blend_color_processing = false;
1354 dc->caps.extended_aux_timeout_support = false;
1355
1356 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1357 dc->caps.force_dp_tps4_for_cp2520 = true;
1358
1359 /* Color pipeline capabilities */
1360 dc->caps.color.dpp.dcn_arch = 1;
1361 dc->caps.color.dpp.input_lut_shared = 1;
1362 dc->caps.color.dpp.icsc = 1;
1363 dc->caps.color.dpp.dgam_ram = 1;
1364 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1365 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1366 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1367 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1368 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1369 dc->caps.color.dpp.post_csc = 0;
1370 dc->caps.color.dpp.gamma_corr = 0;
1371 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1372
1373 dc->caps.color.dpp.hw_3d_lut = 0;
1374 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
1375 dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
1376 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
1377 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1378 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1379 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1380 dc->caps.color.dpp.ocsc = 1;
1381
1382 /* no post-blend color operations */
1383 dc->caps.color.mpc.gamut_remap = 0;
1384 dc->caps.color.mpc.num_3dluts = 0;
1385 dc->caps.color.mpc.shared_3d_lut = 0;
1386 dc->caps.color.mpc.ogam_ram = 0;
1387 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1388 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1389 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1390 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1391 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1392 dc->caps.color.mpc.ocsc = 0;
1393
1394 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1395 dc->debug = debug_defaults_drv;
1396
1397 /*************************************************
1398 * Create resources *
1399 *************************************************/
1400
1401 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1402 dcn10_clock_source_create(ctx, ctx->dc_bios,
1403 CLOCK_SOURCE_COMBO_PHY_PLL0,
1404 &clk_src_regs[0], false);
1405 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1406 dcn10_clock_source_create(ctx, ctx->dc_bios,
1407 CLOCK_SOURCE_COMBO_PHY_PLL1,
1408 &clk_src_regs[1], false);
1409 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1410 dcn10_clock_source_create(ctx, ctx->dc_bios,
1411 CLOCK_SOURCE_COMBO_PHY_PLL2,
1412 &clk_src_regs[2], false);
1413
1414 if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1415 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1416 dcn10_clock_source_create(ctx, ctx->dc_bios,
1417 CLOCK_SOURCE_COMBO_PHY_PLL3,
1418 &clk_src_regs[3], false);
1419 }
1420
1421 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1422
1423 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1424 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1425
1426 pool->base.dp_clock_source =
1427 dcn10_clock_source_create(ctx, ctx->dc_bios,
1428 CLOCK_SOURCE_ID_DP_DTO,
1429 /* todo: not reuse phy_pll registers */
1430 &clk_src_regs[0], true);
1431
1432 for (i = 0; i < pool->base.clk_src_count; i++) {
1433 if (pool->base.clock_sources[i] == NULL) {
1434 dm_error("DC: failed to create clock sources!\n");
1435 BREAK_TO_DEBUGGER();
1436 goto fail;
1437 }
1438 }
1439
1440 pool->base.dmcu = dcn10_dmcu_create(ctx,
1441 &dmcu_regs,
1442 &dmcu_shift,
1443 &dmcu_mask);
1444 if (pool->base.dmcu == NULL) {
1445 dm_error("DC: failed to create dmcu!\n");
1446 BREAK_TO_DEBUGGER();
1447 goto fail;
1448 }
1449
1450 pool->base.abm = dce_abm_create(ctx,
1451 &abm_regs,
1452 &abm_shift,
1453 &abm_mask);
1454 if (pool->base.abm == NULL) {
1455 dm_error("DC: failed to create abm!\n");
1456 BREAK_TO_DEBUGGER();
1457 goto fail;
1458 }
1459
1460 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1461 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1462 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1463
1464 DC_FP_START();
1465 dcn10_resource_construct_fp(dc);
1466 DC_FP_END();
1467
1468 if (!dc->config.is_vmin_only_asic)
1469 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))
1470 switch (dc->ctx->asic_id.pci_revision_id) {
1471 case PRID_DALI_DE:
1472 case PRID_DALI_DF:
1473 case PRID_DALI_E3:
1474 case PRID_DALI_E4:
1475 case PRID_POLLOCK_94:
1476 case PRID_POLLOCK_95:
1477 case PRID_POLLOCK_E9:
1478 case PRID_POLLOCK_EA:
1479 case PRID_POLLOCK_EB:
1480 dc->config.is_vmin_only_asic = true;
1481 break;
1482 default:
1483 break;
1484 }
1485
1486 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1487
1488 /*
1489 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1490 * implemented. So AZ D3 should work.For issue 197007. *
1491 */
1492 if (pool->base.pp_smu != NULL
1493 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1494 dc->debug.az_endpoint_mute_only = false;
1495
1496
1497 if (!dc->debug.disable_pplib_clock_request) {
1498 /*
1499 * TODO: This is not the proper way to obtain
1500 * fabric_and_dram_bandwidth, should be min(fclk, memclk).
1501 */
1502 res = dm_pp_get_clock_levels_by_type_with_voltage(
1503 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1504
1505 DC_FP_START();
1506
1507 if (res)
1508 res = verify_clock_values(&fclks);
1509
1510 if (res)
1511 dcn_bw_update_from_pplib_fclks(dc, &fclks);
1512 else
1513 BREAK_TO_DEBUGGER();
1514
1515 DC_FP_END();
1516
1517 res = dm_pp_get_clock_levels_by_type_with_voltage(
1518 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1519
1520 DC_FP_START();
1521
1522 if (res)
1523 res = verify_clock_values(&dcfclks);
1524
1525 if (res)
1526 dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);
1527 else
1528 BREAK_TO_DEBUGGER();
1529
1530 DC_FP_END();
1531 }
1532
1533 dcn_bw_sync_calcs_and_dml(dc);
1534 if (!dc->debug.disable_pplib_wm_range) {
1535 dc->res_pool = &pool->base;
1536 DC_FP_START();
1537 dcn_get_soc_clks(
1538 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
1539 DC_FP_END();
1540 dcn_bw_notify_pplib_of_wm_ranges(
1541 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
1542 }
1543
1544 {
1545 struct irq_service_init_data init_data;
1546 init_data.ctx = dc->ctx;
1547 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1548 if (!pool->base.irqs)
1549 goto fail;
1550 }
1551
1552 /* index to valid pipe resource */
1553 j = 0;
1554 /* mem input -> ipp -> dpp -> opp -> TG */
1555 for (i = 0; i < pool->base.pipe_count; i++) {
1556 /* if pipe is disabled, skip instance of HW pipe,
1557 * i.e, skip ASIC register instance
1558 */
1559 if ((pipe_fuses & (1 << i)) != 0)
1560 continue;
1561
1562 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1563 if (pool->base.hubps[j] == NULL) {
1564 BREAK_TO_DEBUGGER();
1565 dm_error(
1566 "DC: failed to create memory input!\n");
1567 goto fail;
1568 }
1569
1570 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1571 if (pool->base.ipps[j] == NULL) {
1572 BREAK_TO_DEBUGGER();
1573 dm_error(
1574 "DC: failed to create input pixel processor!\n");
1575 goto fail;
1576 }
1577
1578 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1579 if (pool->base.dpps[j] == NULL) {
1580 BREAK_TO_DEBUGGER();
1581 dm_error(
1582 "DC: failed to create dpp!\n");
1583 goto fail;
1584 }
1585
1586 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1587 if (pool->base.opps[j] == NULL) {
1588 BREAK_TO_DEBUGGER();
1589 dm_error(
1590 "DC: failed to create output pixel processor!\n");
1591 goto fail;
1592 }
1593
1594 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1595 ctx, i);
1596 if (pool->base.timing_generators[j] == NULL) {
1597 BREAK_TO_DEBUGGER();
1598 dm_error("DC: failed to create tg!\n");
1599 goto fail;
1600 }
1601 /* check next valid pipe */
1602 j++;
1603 }
1604
1605 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1606 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1607 if (pool->base.engines[i] == NULL) {
1608 BREAK_TO_DEBUGGER();
1609 dm_error(
1610 "DC:failed to create aux engine!!\n");
1611 goto fail;
1612 }
1613 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1614 if (pool->base.hw_i2cs[i] == NULL) {
1615 BREAK_TO_DEBUGGER();
1616 dm_error(
1617 "DC:failed to create hw i2c!!\n");
1618 goto fail;
1619 }
1620 pool->base.sw_i2cs[i] = NULL;
1621 }
1622
1623 /* valid pipe num */
1624 pool->base.pipe_count = j;
1625 pool->base.timing_generator_count = j;
1626 pool->base.mpcc_count = j;
1627
1628 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1629 * the value may be changed
1630 */
1631 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1632 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1633
1634 pool->base.mpc = dcn10_mpc_create(ctx);
1635 if (pool->base.mpc == NULL) {
1636 BREAK_TO_DEBUGGER();
1637 dm_error("DC: failed to create mpc!\n");
1638 goto fail;
1639 }
1640
1641 pool->base.hubbub = dcn10_hubbub_create(ctx);
1642 if (pool->base.hubbub == NULL) {
1643 BREAK_TO_DEBUGGER();
1644 dm_error("DC: failed to create hubbub!\n");
1645 goto fail;
1646 }
1647
1648 if (!resource_construct(num_virtual_links, dc, &pool->base,
1649 &res_create_funcs))
1650 goto fail;
1651
1652 dcn10_hw_sequencer_construct(dc);
1653 dc->caps.max_planes = pool->base.pipe_count;
1654
1655 for (i = 0; i < dc->caps.max_planes; ++i)
1656 dc->caps.planes[i] = plane_cap;
1657
1658 dc->cap_funcs = cap_funcs;
1659
1660 return true;
1661
1662 fail:
1663
1664 dcn10_resource_destruct(pool);
1665
1666 return false;
1667 }
1668
dcn10_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1669 struct resource_pool *dcn10_create_resource_pool(
1670 const struct dc_init_data *init_data,
1671 struct dc *dc)
1672 {
1673 struct dcn10_resource_pool *pool =
1674 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1675
1676 if (!pool)
1677 return NULL;
1678
1679 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1680 return &pool->base;
1681
1682 kfree(pool);
1683 BREAK_TO_DEBUGGER();
1684 return NULL;
1685 }
1686