1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc.h"
28
29 #include "dcn10/dcn10_init.h"
30
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dcn10/dcn10_resource.h"
34 #include "dcn10/dcn10_ipp.h"
35 #include "dcn10/dcn10_mpc.h"
36
37 #include "dcn10/dcn10_dwb.h"
38
39 #include "irq/dcn10/irq_service_dcn10.h"
40 #include "dcn10/dcn10_dpp.h"
41 #include "dcn10/dcn10_optc.h"
42 #include "dcn10/dcn10_hwseq.h"
43 #include "dce110/dce110_hwseq.h"
44 #include "dcn10/dcn10_opp.h"
45 #include "dcn10/dcn10_link_encoder.h"
46 #include "dcn10/dcn10_stream_encoder.h"
47 #include "dce/dce_clock_source.h"
48 #include "dce/dce_audio.h"
49 #include "dce/dce_hwseq.h"
50 #include "virtual/virtual_stream_encoder.h"
51 #include "dce110/dce110_resource.h"
52 #include "dce112/dce112_resource.h"
53 #include "dcn10/dcn10_hubp.h"
54 #include "dcn10/dcn10_hubbub.h"
55 #include "dce/dce_panel_cntl.h"
56
57 #include "soc15_hw_ip.h"
58 #include "vega10_ip_offset.h"
59
60 #include "dcn/dcn_1_0_offset.h"
61 #include "dcn/dcn_1_0_sh_mask.h"
62
63 #include "nbio/nbio_7_0_offset.h"
64
65 #include "mmhub/mmhub_9_1_offset.h"
66 #include "mmhub/mmhub_9_1_sh_mask.h"
67
68 #include "reg_helper.h"
69 #include "dce/dce_abm.h"
70 #include "dce/dce_dmcu.h"
71 #include "dce/dce_aux.h"
72 #include "dce/dce_i2c.h"
73
74 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
75 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
76 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
77 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
78 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
80 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
82 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
84 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
85 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
86 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
87 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
88 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
89 #endif
90
91
92 enum dcn10_clk_src_array_id {
93 DCN10_CLK_SRC_PLL0,
94 DCN10_CLK_SRC_PLL1,
95 DCN10_CLK_SRC_PLL2,
96 DCN10_CLK_SRC_PLL3,
97 DCN10_CLK_SRC_TOTAL,
98 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
99 };
100
101 /* begin *********************
102 * macros to expend register list macro defined in HW object header file */
103
104 /* DCN */
105 #define BASE_INNER(seg) \
106 DCE_BASE__INST0_SEG ## seg
107
108 #define BASE(seg) \
109 BASE_INNER(seg)
110
111 #define SR(reg_name)\
112 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
113 mm ## reg_name
114
115 #define SRI(reg_name, block, id)\
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
118
119
120 #define SRII(reg_name, block, id)\
121 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
123
124 #define VUPDATE_SRII(reg_name, block, id)\
125 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
126 mm ## reg_name ## 0 ## _ ## block ## id
127
128 /* set field/register/bitfield name */
129 #define SFRB(field_name, reg_name, bitfield, post_fix)\
130 .field_name = reg_name ## __ ## bitfield ## post_fix
131
132 /* NBIO */
133 #define NBIO_BASE_INNER(seg) \
134 NBIF_BASE__INST0_SEG ## seg
135
136 #define NBIO_BASE(seg) \
137 NBIO_BASE_INNER(seg)
138
139 #define NBIO_SR(reg_name)\
140 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
141 mm ## reg_name
142
143 /* MMHUB */
144 #define MMHUB_BASE_INNER(seg) \
145 MMHUB_BASE__INST0_SEG ## seg
146
147 #define MMHUB_BASE(seg) \
148 MMHUB_BASE_INNER(seg)
149
150 #define MMHUB_SR(reg_name)\
151 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
152 mm ## reg_name
153
154 /* macros to expend register list macro defined in HW object header file
155 * end *********************/
156
157
158 static const struct dce_dmcu_registers dmcu_regs = {
159 DMCU_DCN10_REG_LIST()
160 };
161
162 static const struct dce_dmcu_shift dmcu_shift = {
163 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
164 };
165
166 static const struct dce_dmcu_mask dmcu_mask = {
167 DMCU_MASK_SH_LIST_DCN10(_MASK)
168 };
169
170 static const struct dce_abm_registers abm_regs = {
171 ABM_DCN10_REG_LIST(0)
172 };
173
174 static const struct dce_abm_shift abm_shift = {
175 ABM_MASK_SH_LIST_DCN10(__SHIFT)
176 };
177
178 static const struct dce_abm_mask abm_mask = {
179 ABM_MASK_SH_LIST_DCN10(_MASK)
180 };
181
182 #define stream_enc_regs(id)\
183 [id] = {\
184 SE_DCN_REG_LIST(id)\
185 }
186
187 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
188 stream_enc_regs(0),
189 stream_enc_regs(1),
190 stream_enc_regs(2),
191 stream_enc_regs(3),
192 };
193
194 static const struct dcn10_stream_encoder_shift se_shift = {
195 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
196 };
197
198 static const struct dcn10_stream_encoder_mask se_mask = {
199 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
200 };
201
202 #define audio_regs(id)\
203 [id] = {\
204 AUD_COMMON_REG_LIST(id)\
205 }
206
207 static const struct dce_audio_registers audio_regs[] = {
208 audio_regs(0),
209 audio_regs(1),
210 audio_regs(2),
211 audio_regs(3),
212 };
213
214 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
215 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
216 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
217 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
218
219 static const struct dce_audio_shift audio_shift = {
220 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
221 };
222
223 static const struct dce_audio_mask audio_mask = {
224 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
225 };
226
227 #define aux_regs(id)\
228 [id] = {\
229 AUX_REG_LIST(id)\
230 }
231
232 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
233 aux_regs(0),
234 aux_regs(1),
235 aux_regs(2),
236 aux_regs(3)
237 };
238
239 #define hpd_regs(id)\
240 [id] = {\
241 HPD_REG_LIST(id)\
242 }
243
244 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
245 hpd_regs(0),
246 hpd_regs(1),
247 hpd_regs(2),
248 hpd_regs(3)
249 };
250
251 #define link_regs(id)\
252 [id] = {\
253 LE_DCN10_REG_LIST(id), \
254 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
255 }
256
257 static const struct dcn10_link_enc_registers link_enc_regs[] = {
258 link_regs(0),
259 link_regs(1),
260 link_regs(2),
261 link_regs(3)
262 };
263
264 static const struct dcn10_link_enc_shift le_shift = {
265 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
266 };
267
268 static const struct dcn10_link_enc_mask le_mask = {
269 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
270 };
271
272 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
273 { DCN_PANEL_CNTL_REG_LIST() }
274 };
275
276 static const struct dce_panel_cntl_shift panel_cntl_shift = {
277 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
278 };
279
280 static const struct dce_panel_cntl_mask panel_cntl_mask = {
281 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
282 };
283
284 static const struct dce110_aux_registers_shift aux_shift = {
285 DCN10_AUX_MASK_SH_LIST(__SHIFT)
286 };
287
288 static const struct dce110_aux_registers_mask aux_mask = {
289 DCN10_AUX_MASK_SH_LIST(_MASK)
290 };
291
292 #define ipp_regs(id)\
293 [id] = {\
294 IPP_REG_LIST_DCN10(id),\
295 }
296
297 static const struct dcn10_ipp_registers ipp_regs[] = {
298 ipp_regs(0),
299 ipp_regs(1),
300 ipp_regs(2),
301 ipp_regs(3),
302 };
303
304 static const struct dcn10_ipp_shift ipp_shift = {
305 IPP_MASK_SH_LIST_DCN10(__SHIFT)
306 };
307
308 static const struct dcn10_ipp_mask ipp_mask = {
309 IPP_MASK_SH_LIST_DCN10(_MASK),
310 };
311
312 #define opp_regs(id)\
313 [id] = {\
314 OPP_REG_LIST_DCN10(id),\
315 }
316
317 static const struct dcn10_opp_registers opp_regs[] = {
318 opp_regs(0),
319 opp_regs(1),
320 opp_regs(2),
321 opp_regs(3),
322 };
323
324 static const struct dcn10_opp_shift opp_shift = {
325 OPP_MASK_SH_LIST_DCN10(__SHIFT)
326 };
327
328 static const struct dcn10_opp_mask opp_mask = {
329 OPP_MASK_SH_LIST_DCN10(_MASK),
330 };
331
332 #define aux_engine_regs(id)\
333 [id] = {\
334 AUX_COMMON_REG_LIST(id), \
335 .AUX_RESET_MASK = 0 \
336 }
337
338 static const struct dce110_aux_registers aux_engine_regs[] = {
339 aux_engine_regs(0),
340 aux_engine_regs(1),
341 aux_engine_regs(2),
342 aux_engine_regs(3),
343 aux_engine_regs(4),
344 aux_engine_regs(5)
345 };
346
347 #define tf_regs(id)\
348 [id] = {\
349 TF_REG_LIST_DCN10(id),\
350 }
351
352 static const struct dcn_dpp_registers tf_regs[] = {
353 tf_regs(0),
354 tf_regs(1),
355 tf_regs(2),
356 tf_regs(3),
357 };
358
359 static const struct dcn_dpp_shift tf_shift = {
360 TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
361 TF_DEBUG_REG_LIST_SH_DCN10
362
363 };
364
365 static const struct dcn_dpp_mask tf_mask = {
366 TF_REG_LIST_SH_MASK_DCN10(_MASK),
367 TF_DEBUG_REG_LIST_MASK_DCN10
368 };
369
370 static const struct dcn_mpc_registers mpc_regs = {
371 MPC_COMMON_REG_LIST_DCN1_0(0),
372 MPC_COMMON_REG_LIST_DCN1_0(1),
373 MPC_COMMON_REG_LIST_DCN1_0(2),
374 MPC_COMMON_REG_LIST_DCN1_0(3),
375 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
376 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
377 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
378 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
379 };
380
381 static const struct dcn_mpc_shift mpc_shift = {
382 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
383 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
384 };
385
386 static const struct dcn_mpc_mask mpc_mask = {
387 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
388 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
389 };
390
391 #define tg_regs(id)\
392 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
393
394 static const struct dcn_optc_registers tg_regs[] = {
395 tg_regs(0),
396 tg_regs(1),
397 tg_regs(2),
398 tg_regs(3),
399 };
400
401 static const struct dcn_optc_shift tg_shift = {
402 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
403 };
404
405 static const struct dcn_optc_mask tg_mask = {
406 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
407 };
408
409 static const struct bios_registers bios_regs = {
410 NBIO_SR(BIOS_SCRATCH_3),
411 NBIO_SR(BIOS_SCRATCH_6)
412 };
413
414 #define hubp_regs(id)\
415 [id] = {\
416 HUBP_REG_LIST_DCN10(id)\
417 }
418
419 static const struct dcn_mi_registers hubp_regs[] = {
420 hubp_regs(0),
421 hubp_regs(1),
422 hubp_regs(2),
423 hubp_regs(3),
424 };
425
426 static const struct dcn_mi_shift hubp_shift = {
427 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
428 };
429
430 static const struct dcn_mi_mask hubp_mask = {
431 HUBP_MASK_SH_LIST_DCN10(_MASK)
432 };
433
434 static const struct dcn_hubbub_registers hubbub_reg = {
435 HUBBUB_REG_LIST_DCN10(0)
436 };
437
438 static const struct dcn_hubbub_shift hubbub_shift = {
439 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
440 };
441
442 static const struct dcn_hubbub_mask hubbub_mask = {
443 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
444 };
445
map_transmitter_id_to_phy_instance(enum transmitter transmitter)446 static int map_transmitter_id_to_phy_instance(
447 enum transmitter transmitter)
448 {
449 switch (transmitter) {
450 case TRANSMITTER_UNIPHY_A:
451 return 0;
452 break;
453 case TRANSMITTER_UNIPHY_B:
454 return 1;
455 break;
456 case TRANSMITTER_UNIPHY_C:
457 return 2;
458 break;
459 case TRANSMITTER_UNIPHY_D:
460 return 3;
461 break;
462 default:
463 ASSERT(0);
464 return 0;
465 }
466 }
467
468 #define clk_src_regs(index, pllid)\
469 [index] = {\
470 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
471 }
472
473 static const struct dce110_clk_src_regs clk_src_regs[] = {
474 clk_src_regs(0, A),
475 clk_src_regs(1, B),
476 clk_src_regs(2, C),
477 clk_src_regs(3, D)
478 };
479
480 static const struct dce110_clk_src_shift cs_shift = {
481 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
482 };
483
484 static const struct dce110_clk_src_mask cs_mask = {
485 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
486 };
487
488 static const struct resource_caps res_cap = {
489 .num_timing_generator = 4,
490 .num_opp = 4,
491 .num_video_plane = 4,
492 .num_audio = 4,
493 .num_stream_encoder = 4,
494 .num_pll = 4,
495 .num_ddc = 4,
496 };
497
498 static const struct resource_caps rv2_res_cap = {
499 .num_timing_generator = 3,
500 .num_opp = 3,
501 .num_video_plane = 3,
502 .num_audio = 3,
503 .num_stream_encoder = 3,
504 .num_pll = 3,
505 .num_ddc = 4,
506 };
507
508 static const struct dc_plane_cap plane_cap = {
509 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
510 .per_pixel_alpha = true,
511
512 .pixel_format_support = {
513 .argb8888 = true,
514 .nv12 = true,
515 .fp16 = true,
516 .p010 = false
517 },
518
519 .max_upscale_factor = {
520 .argb8888 = 16000,
521 .nv12 = 16000,
522 .fp16 = 1
523 },
524
525 .max_downscale_factor = {
526 .argb8888 = 250,
527 .nv12 = 250,
528 .fp16 = 1
529 }
530 };
531
532 static const struct dc_debug_options debug_defaults_drv = {
533 .sanity_checks = true,
534 .disable_dmcu = false,
535 .force_abm_enable = false,
536 .timing_trace = false,
537 .clock_trace = true,
538
539 /* raven smu dones't allow 0 disp clk,
540 * smu min disp clk limit is 50Mhz
541 * keep min disp clk 100Mhz avoid smu hang
542 */
543 .min_disp_clk_khz = 100000,
544
545 .disable_pplib_clock_request = false,
546 .disable_pplib_wm_range = false,
547 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
548 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
549 .force_single_disp_pipe_split = true,
550 .disable_dcc = DCC_ENABLE,
551 .voltage_align_fclk = true,
552 .disable_stereo_support = true,
553 .vsr_support = true,
554 .performance_trace = false,
555 .az_endpoint_mute_only = true,
556 .recovery_enabled = false, /*enable this by default after testing.*/
557 .max_downscale_src_width = 3840,
558 .underflow_assert_delay_us = 0xFFFFFFFF,
559 .enable_legacy_fast_update = true,
560 .using_dml2 = false,
561 };
562
563 static const struct dc_debug_options debug_defaults_diags = {
564 .disable_dmcu = false,
565 .force_abm_enable = false,
566 .timing_trace = true,
567 .clock_trace = true,
568 .disable_stutter = true,
569 .disable_pplib_clock_request = true,
570 .disable_pplib_wm_range = true,
571 .underflow_assert_delay_us = 0xFFFFFFFF,
572 .enable_legacy_fast_update = true,
573 };
574
dcn10_dpp_destroy(struct dpp ** dpp)575 static void dcn10_dpp_destroy(struct dpp **dpp)
576 {
577 kfree(TO_DCN10_DPP(*dpp));
578 *dpp = NULL;
579 }
580
dcn10_dpp_create(struct dc_context * ctx,uint32_t inst)581 static struct dpp *dcn10_dpp_create(
582 struct dc_context *ctx,
583 uint32_t inst)
584 {
585 struct dcn10_dpp *dpp =
586 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
587
588 if (!dpp)
589 return NULL;
590
591 dpp1_construct(dpp, ctx, inst,
592 &tf_regs[inst], &tf_shift, &tf_mask);
593 return &dpp->base;
594 }
595
dcn10_ipp_create(struct dc_context * ctx,uint32_t inst)596 static struct input_pixel_processor *dcn10_ipp_create(
597 struct dc_context *ctx, uint32_t inst)
598 {
599 struct dcn10_ipp *ipp =
600 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
601
602 if (!ipp) {
603 BREAK_TO_DEBUGGER();
604 return NULL;
605 }
606
607 dcn10_ipp_construct(ipp, ctx, inst,
608 &ipp_regs[inst], &ipp_shift, &ipp_mask);
609 return &ipp->base;
610 }
611
612
dcn10_opp_create(struct dc_context * ctx,uint32_t inst)613 static struct output_pixel_processor *dcn10_opp_create(
614 struct dc_context *ctx, uint32_t inst)
615 {
616 struct dcn10_opp *opp =
617 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
618
619 if (!opp) {
620 BREAK_TO_DEBUGGER();
621 return NULL;
622 }
623
624 dcn10_opp_construct(opp, ctx, inst,
625 &opp_regs[inst], &opp_shift, &opp_mask);
626 return &opp->base;
627 }
628
dcn10_aux_engine_create(struct dc_context * ctx,uint32_t inst)629 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
630 uint32_t inst)
631 {
632 struct aux_engine_dce110 *aux_engine =
633 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
634
635 if (!aux_engine)
636 return NULL;
637
638 dce110_aux_engine_construct(aux_engine, ctx, inst,
639 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
640 &aux_engine_regs[inst],
641 &aux_mask,
642 &aux_shift,
643 ctx->dc->caps.extended_aux_timeout_support);
644
645 return &aux_engine->base;
646 }
647 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
648
649 static const struct dce_i2c_registers i2c_hw_regs[] = {
650 i2c_inst_regs(1),
651 i2c_inst_regs(2),
652 i2c_inst_regs(3),
653 i2c_inst_regs(4),
654 i2c_inst_regs(5),
655 i2c_inst_regs(6),
656 };
657
658 static const struct dce_i2c_shift i2c_shifts = {
659 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
660 };
661
662 static const struct dce_i2c_mask i2c_masks = {
663 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
664 };
665
dcn10_i2c_hw_create(struct dc_context * ctx,uint32_t inst)666 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
667 uint32_t inst)
668 {
669 struct dce_i2c_hw *dce_i2c_hw =
670 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
671
672 if (!dce_i2c_hw)
673 return NULL;
674
675 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
676 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
677
678 return dce_i2c_hw;
679 }
dcn10_mpc_create(struct dc_context * ctx)680 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
681 {
682 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
683 GFP_KERNEL);
684
685 if (!mpc10)
686 return NULL;
687
688 dcn10_mpc_construct(mpc10, ctx,
689 &mpc_regs,
690 &mpc_shift,
691 &mpc_mask,
692 4);
693
694 return &mpc10->base;
695 }
696
dcn10_hubbub_create(struct dc_context * ctx)697 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
698 {
699 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
700 GFP_KERNEL);
701
702 if (!dcn10_hubbub)
703 return NULL;
704
705 hubbub1_construct(&dcn10_hubbub->base, ctx,
706 &hubbub_reg,
707 &hubbub_shift,
708 &hubbub_mask);
709
710 return &dcn10_hubbub->base;
711 }
712
dcn10_timing_generator_create(struct dc_context * ctx,uint32_t instance)713 static struct timing_generator *dcn10_timing_generator_create(
714 struct dc_context *ctx,
715 uint32_t instance)
716 {
717 struct optc *tgn10 =
718 kzalloc(sizeof(struct optc), GFP_KERNEL);
719
720 if (!tgn10)
721 return NULL;
722
723 tgn10->base.inst = instance;
724 tgn10->base.ctx = ctx;
725
726 tgn10->tg_regs = &tg_regs[instance];
727 tgn10->tg_shift = &tg_shift;
728 tgn10->tg_mask = &tg_mask;
729
730 dcn10_timing_generator_init(tgn10);
731
732 return &tgn10->base;
733 }
734
735 static const struct encoder_feature_support link_enc_feature = {
736 .max_hdmi_deep_color = COLOR_DEPTH_121212,
737 .max_hdmi_pixel_clock = 600000,
738 .hdmi_ycbcr420_supported = true,
739 .dp_ycbcr420_supported = true,
740 .flags.bits.IS_HBR2_CAPABLE = true,
741 .flags.bits.IS_HBR3_CAPABLE = true,
742 .flags.bits.IS_TPS3_CAPABLE = true,
743 .flags.bits.IS_TPS4_CAPABLE = true
744 };
745
dcn10_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)746 static struct link_encoder *dcn10_link_encoder_create(
747 struct dc_context *ctx,
748 const struct encoder_init_data *enc_init_data)
749 {
750 struct dcn10_link_encoder *enc10 =
751 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
752 int link_regs_id;
753
754 if (!enc10)
755 return NULL;
756
757 link_regs_id =
758 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
759
760 dcn10_link_encoder_construct(enc10,
761 enc_init_data,
762 &link_enc_feature,
763 &link_enc_regs[link_regs_id],
764 &link_enc_aux_regs[enc_init_data->channel - 1],
765 &link_enc_hpd_regs[enc_init_data->hpd_source],
766 &le_shift,
767 &le_mask);
768
769 return &enc10->base;
770 }
771
dcn10_panel_cntl_create(const struct panel_cntl_init_data * init_data)772 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
773 {
774 struct dce_panel_cntl *panel_cntl =
775 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
776
777 if (!panel_cntl)
778 return NULL;
779
780 dce_panel_cntl_construct(panel_cntl,
781 init_data,
782 &panel_cntl_regs[init_data->inst],
783 &panel_cntl_shift,
784 &panel_cntl_mask);
785
786 return &panel_cntl->base;
787 }
788
dcn10_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)789 static struct clock_source *dcn10_clock_source_create(
790 struct dc_context *ctx,
791 struct dc_bios *bios,
792 enum clock_source_id id,
793 const struct dce110_clk_src_regs *regs,
794 bool dp_clk_src)
795 {
796 struct dce110_clk_src *clk_src =
797 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
798
799 if (!clk_src)
800 return NULL;
801
802 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
803 regs, &cs_shift, &cs_mask)) {
804 clk_src->base.dp_clk_src = dp_clk_src;
805 return &clk_src->base;
806 }
807
808 kfree(clk_src);
809 BREAK_TO_DEBUGGER();
810 return NULL;
811 }
812
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)813 static void read_dce_straps(
814 struct dc_context *ctx,
815 struct resource_straps *straps)
816 {
817 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
818 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
819 }
820
create_audio(struct dc_context * ctx,unsigned int inst)821 static struct audio *create_audio(
822 struct dc_context *ctx, unsigned int inst)
823 {
824 return dce_audio_create(ctx, inst,
825 &audio_regs[inst], &audio_shift, &audio_mask);
826 }
827
dcn10_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)828 static struct stream_encoder *dcn10_stream_encoder_create(
829 enum engine_id eng_id,
830 struct dc_context *ctx)
831 {
832 struct dcn10_stream_encoder *enc1 =
833 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
834
835 if (!enc1)
836 return NULL;
837
838 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
839 &stream_enc_regs[eng_id],
840 &se_shift, &se_mask);
841 return &enc1->base;
842 }
843
844 static const struct dce_hwseq_registers hwseq_reg = {
845 HWSEQ_DCN1_REG_LIST()
846 };
847
848 static const struct dce_hwseq_shift hwseq_shift = {
849 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
850 };
851
852 static const struct dce_hwseq_mask hwseq_mask = {
853 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
854 };
855
dcn10_hwseq_create(struct dc_context * ctx)856 static struct dce_hwseq *dcn10_hwseq_create(
857 struct dc_context *ctx)
858 {
859 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
860
861 if (hws) {
862 hws->ctx = ctx;
863 hws->regs = &hwseq_reg;
864 hws->shifts = &hwseq_shift;
865 hws->masks = &hwseq_mask;
866 hws->wa.DEGVIDCN10_253 = true;
867 hws->wa.false_optc_underflow = true;
868 hws->wa.DEGVIDCN10_254 = true;
869
870 if ((ctx->asic_id.chip_family == FAMILY_RV) &&
871 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev))
872 switch (ctx->asic_id.pci_revision_id) {
873 case PRID_POLLOCK_94:
874 case PRID_POLLOCK_95:
875 case PRID_POLLOCK_E9:
876 case PRID_POLLOCK_EA:
877 case PRID_POLLOCK_EB:
878 hws->wa.wait_hubpret_read_start_during_mpo_transition = true;
879 break;
880 default:
881 hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
882 break;
883 }
884 }
885 return hws;
886 }
887
888 static const struct resource_create_funcs res_create_funcs = {
889 .read_dce_straps = read_dce_straps,
890 .create_audio = create_audio,
891 .create_stream_encoder = dcn10_stream_encoder_create,
892 .create_hwseq = dcn10_hwseq_create,
893 };
894
dcn10_clock_source_destroy(struct clock_source ** clk_src)895 static void dcn10_clock_source_destroy(struct clock_source **clk_src)
896 {
897 kfree(TO_DCE110_CLK_SRC(*clk_src));
898 *clk_src = NULL;
899 }
900
dcn10_pp_smu_create(struct dc_context * ctx)901 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
902 {
903 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
904
905 if (!pp_smu)
906 return pp_smu;
907
908 dm_pp_get_funcs(ctx, pp_smu);
909 return pp_smu;
910 }
911
dcn10_resource_destruct(struct dcn10_resource_pool * pool)912 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
913 {
914 unsigned int i;
915
916 for (i = 0; i < pool->base.stream_enc_count; i++) {
917 if (pool->base.stream_enc[i] != NULL) {
918 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
919 pool->base.stream_enc[i] = NULL;
920 }
921 }
922
923 if (pool->base.mpc != NULL) {
924 kfree(TO_DCN10_MPC(pool->base.mpc));
925 pool->base.mpc = NULL;
926 }
927
928 kfree(pool->base.hubbub);
929 pool->base.hubbub = NULL;
930
931 for (i = 0; i < pool->base.pipe_count; i++) {
932 if (pool->base.opps[i] != NULL)
933 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
934
935 if (pool->base.dpps[i] != NULL)
936 dcn10_dpp_destroy(&pool->base.dpps[i]);
937
938 if (pool->base.ipps[i] != NULL)
939 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
940
941 if (pool->base.hubps[i] != NULL) {
942 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
943 pool->base.hubps[i] = NULL;
944 }
945
946 if (pool->base.irqs != NULL) {
947 dal_irq_service_destroy(&pool->base.irqs);
948 }
949
950 if (pool->base.timing_generators[i] != NULL) {
951 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
952 pool->base.timing_generators[i] = NULL;
953 }
954 }
955
956 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
957 if (pool->base.engines[i] != NULL)
958 dce110_engine_destroy(&pool->base.engines[i]);
959 kfree(pool->base.hw_i2cs[i]);
960 pool->base.hw_i2cs[i] = NULL;
961 kfree(pool->base.sw_i2cs[i]);
962 pool->base.sw_i2cs[i] = NULL;
963 }
964
965 for (i = 0; i < pool->base.audio_count; i++) {
966 if (pool->base.audios[i])
967 dce_aud_destroy(&pool->base.audios[i]);
968 }
969
970 for (i = 0; i < pool->base.clk_src_count; i++) {
971 if (pool->base.clock_sources[i] != NULL) {
972 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
973 pool->base.clock_sources[i] = NULL;
974 }
975 }
976
977 if (pool->base.dp_clock_source != NULL) {
978 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
979 pool->base.dp_clock_source = NULL;
980 }
981
982 if (pool->base.abm != NULL)
983 dce_abm_destroy(&pool->base.abm);
984
985 if (pool->base.dmcu != NULL)
986 dce_dmcu_destroy(&pool->base.dmcu);
987
988 kfree(pool->base.pp_smu);
989 }
990
dcn10_hubp_create(struct dc_context * ctx,uint32_t inst)991 static struct hubp *dcn10_hubp_create(
992 struct dc_context *ctx,
993 uint32_t inst)
994 {
995 struct dcn10_hubp *hubp1 =
996 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
997
998 if (!hubp1)
999 return NULL;
1000
1001 dcn10_hubp_construct(hubp1, ctx, inst,
1002 &hubp_regs[inst], &hubp_shift, &hubp_mask);
1003 return &hubp1->base;
1004 }
1005
get_pixel_clock_parameters(const struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1006 static void get_pixel_clock_parameters(
1007 const struct pipe_ctx *pipe_ctx,
1008 struct pixel_clk_params *pixel_clk_params)
1009 {
1010 const struct dc_stream_state *stream = pipe_ctx->stream;
1011 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1012 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1013 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1014 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1015 /* TODO: un-hardcode*/
1016 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1017 LINK_RATE_REF_FREQ_IN_KHZ;
1018 pixel_clk_params->flags.ENABLE_SS = 0;
1019 pixel_clk_params->color_depth =
1020 stream->timing.display_color_depth;
1021 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1022 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1023
1024 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1025 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1026
1027 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1028 pixel_clk_params->requested_pix_clk_100hz /= 2;
1029 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1030 pixel_clk_params->requested_pix_clk_100hz *= 2;
1031
1032 }
1033
build_clamping_params(struct dc_stream_state * stream)1034 static void build_clamping_params(struct dc_stream_state *stream)
1035 {
1036 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1037 stream->clamping.c_depth = stream->timing.display_color_depth;
1038 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1039 }
1040
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1041 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1042 {
1043
1044 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1045
1046 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1047 pipe_ctx->clock_source,
1048 &pipe_ctx->stream_res.pix_clk_params,
1049 &pipe_ctx->pll_settings);
1050
1051 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1052
1053 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1054 &pipe_ctx->stream->bit_depth_params);
1055 build_clamping_params(pipe_ctx->stream);
1056 }
1057
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1058 static enum dc_status build_mapped_resource(
1059 const struct dc *dc,
1060 struct dc_state *context,
1061 struct dc_stream_state *stream)
1062 {
1063 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1064
1065 if (!pipe_ctx)
1066 return DC_ERROR_UNEXPECTED;
1067
1068 build_pipe_hw_param(pipe_ctx);
1069 return DC_OK;
1070 }
1071
dcn10_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1072 static enum dc_status dcn10_add_stream_to_ctx(
1073 struct dc *dc,
1074 struct dc_state *new_ctx,
1075 struct dc_stream_state *dc_stream)
1076 {
1077 enum dc_status result = DC_ERROR_UNEXPECTED;
1078
1079 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1080
1081 if (result == DC_OK)
1082 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1083
1084
1085 if (result == DC_OK)
1086 result = build_mapped_resource(dc, new_ctx, dc_stream);
1087
1088 return result;
1089 }
1090
dcn10_acquire_free_pipe_for_layer(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)1091 static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(
1092 const struct dc_state *cur_ctx,
1093 struct dc_state *new_ctx,
1094 const struct resource_pool *pool,
1095 const struct pipe_ctx *opp_head_pipe)
1096 {
1097 struct resource_context *res_ctx = &new_ctx->res_ctx;
1098 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1099 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1100
1101 if (!head_pipe) {
1102 ASSERT(0);
1103 return NULL;
1104 }
1105
1106 if (!idle_pipe)
1107 return NULL;
1108
1109 idle_pipe->stream = head_pipe->stream;
1110 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1111 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1112 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1113
1114 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1115 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1116 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1117 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1118
1119 return idle_pipe;
1120 }
1121
dcn10_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)1122 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1123 const struct dc_dcc_surface_param *input,
1124 struct dc_surface_dcc_cap *output)
1125 {
1126 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1127 dc->res_pool->hubbub,
1128 input,
1129 output);
1130 }
1131
dcn10_destroy_resource_pool(struct resource_pool ** pool)1132 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1133 {
1134 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1135
1136 dcn10_resource_destruct(dcn10_pool);
1137 kfree(dcn10_pool);
1138 *pool = NULL;
1139 }
1140
dcn10_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1141 static bool dcn10_validate_bandwidth(
1142 struct dc *dc,
1143 struct dc_state *context,
1144 bool fast_validate)
1145 {
1146 bool voltage_supported;
1147
1148 DC_FP_START();
1149 voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);
1150 DC_FP_END();
1151
1152 return voltage_supported;
1153 }
1154
dcn10_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)1155 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1156 {
1157 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1158 && caps->max_video_width != 0
1159 && plane_state->src_rect.width > caps->max_video_width)
1160 return DC_FAIL_SURFACE_VALIDATE;
1161
1162 return DC_OK;
1163 }
1164
dcn10_validate_global(struct dc * dc,struct dc_state * context)1165 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1166 {
1167 int i, j;
1168 bool video_down_scaled = false;
1169 bool video_large = false;
1170 bool desktop_large = false;
1171 bool dcc_disabled = false;
1172 bool mpo_enabled = false;
1173
1174 for (i = 0; i < context->stream_count; i++) {
1175 if (context->stream_status[i].plane_count == 0)
1176 continue;
1177
1178 if (context->stream_status[i].plane_count > 2)
1179 return DC_FAIL_UNSUPPORTED_1;
1180
1181 if (context->stream_status[i].plane_count > 1)
1182 mpo_enabled = true;
1183
1184 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1185 struct dc_plane_state *plane =
1186 context->stream_status[i].plane_states[j];
1187
1188
1189 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1190
1191 if (plane->src_rect.width > plane->dst_rect.width ||
1192 plane->src_rect.height > plane->dst_rect.height)
1193 video_down_scaled = true;
1194
1195 if (plane->src_rect.width >= 3840)
1196 video_large = true;
1197
1198 } else {
1199 if (plane->src_rect.width >= 3840)
1200 desktop_large = true;
1201 if (!plane->dcc.enable)
1202 dcc_disabled = true;
1203 }
1204 }
1205 }
1206
1207 /* Disable MPO in multi-display configurations. */
1208 if (context->stream_count > 1 && mpo_enabled)
1209 return DC_FAIL_UNSUPPORTED_1;
1210
1211 /*
1212 * Workaround: On DCN10 there is UMC issue that causes underflow when
1213 * playing 4k video on 4k desktop with video downscaled and single channel
1214 * memory
1215 */
1216 if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1217 dc->dcn_soc->number_of_channels == 1)
1218 return DC_FAIL_SURFACE_VALIDATE;
1219
1220 return DC_OK;
1221 }
1222
dcn10_patch_unknown_plane_state(struct dc_plane_state * plane_state)1223 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1224 {
1225 enum surface_pixel_format surf_pix_format = plane_state->format;
1226 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1227
1228 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1229
1230 if (bpp == 64)
1231 swizzle = DC_SW_64KB_D;
1232 else
1233 swizzle = DC_SW_64KB_S;
1234
1235 plane_state->tiling_info.gfx9.swizzle = swizzle;
1236 return DC_OK;
1237 }
1238
dcn10_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1239 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1240 struct resource_context *res_ctx,
1241 const struct resource_pool *pool,
1242 struct dc_stream_state *stream)
1243 {
1244 int i;
1245 int j = -1;
1246 struct dc_link *link = stream->link;
1247
1248 for (i = 0; i < pool->stream_enc_count; i++) {
1249 if (!res_ctx->is_stream_enc_acquired[i] &&
1250 pool->stream_enc[i]) {
1251 /* Store first available for MST second display
1252 * in daisy chain use case
1253 */
1254
1255 if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)
1256 j = i;
1257
1258 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
1259 link->link_enc->preferred_engine)
1260 return pool->stream_enc[i];
1261 }
1262 }
1263
1264 /*
1265 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1266 */
1267
1268 if (j >= 0)
1269 return pool->stream_enc[j];
1270
1271 return NULL;
1272 }
1273
1274 static const struct dc_cap_funcs cap_funcs = {
1275 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1276 };
1277
1278 static const struct resource_funcs dcn10_res_pool_funcs = {
1279 .destroy = dcn10_destroy_resource_pool,
1280 .link_enc_create = dcn10_link_encoder_create,
1281 .panel_cntl_create = dcn10_panel_cntl_create,
1282 .validate_bandwidth = dcn10_validate_bandwidth,
1283 .acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer,
1284 .validate_plane = dcn10_validate_plane,
1285 .validate_global = dcn10_validate_global,
1286 .add_stream_to_ctx = dcn10_add_stream_to_ctx,
1287 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1288 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1289 };
1290
read_pipe_fuses(struct dc_context * ctx)1291 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1292 {
1293 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1294 /* RV1 support max 4 pipes */
1295 value = value & 0xf;
1296 return value;
1297 }
1298
verify_clock_values(struct dm_pp_clock_levels_with_voltage * clks)1299 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1300 {
1301 int i;
1302
1303 if (clks->num_levels == 0)
1304 return false;
1305
1306 for (i = 0; i < clks->num_levels; i++)
1307 /* Ensure that the result is sane */
1308 if (clks->data[i].clocks_in_khz == 0)
1309 return false;
1310
1311 return true;
1312 }
1313
dcn10_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn10_resource_pool * pool)1314 static bool dcn10_resource_construct(
1315 uint8_t num_virtual_links,
1316 struct dc *dc,
1317 struct dcn10_resource_pool *pool)
1318 {
1319 int i;
1320 int j;
1321 struct dc_context *ctx = dc->ctx;
1322 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1323 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1324 int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1325 bool res;
1326
1327 ctx->dc_bios->regs = &bios_regs;
1328
1329 if (ctx->dce_version == DCN_VERSION_1_01)
1330 pool->base.res_cap = &rv2_res_cap;
1331 else
1332 pool->base.res_cap = &res_cap;
1333 pool->base.funcs = &dcn10_res_pool_funcs;
1334
1335 /*
1336 * TODO fill in from actual raven resource when we create
1337 * more than virtual encoder
1338 */
1339
1340 /*************************************************
1341 * Resource + asic cap harcoding *
1342 *************************************************/
1343 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1344
1345 /* max pipe num for ASIC before check pipe fuses */
1346 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1347
1348 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1349 pool->base.pipe_count = 3;
1350 dc->caps.max_video_width = 3840;
1351 dc->caps.max_downscale_ratio = 200;
1352 dc->caps.i2c_speed_in_khz = 100;
1353 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1354 dc->caps.max_cursor_size = 256;
1355 dc->caps.min_horizontal_blanking_period = 80;
1356 dc->caps.max_slave_planes = 1;
1357 dc->caps.max_slave_yuv_planes = 1;
1358 dc->caps.max_slave_rgb_planes = 0;
1359 dc->caps.is_apu = true;
1360 dc->caps.post_blend_color_processing = false;
1361 dc->caps.extended_aux_timeout_support = false;
1362
1363 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1364 dc->caps.force_dp_tps4_for_cp2520 = true;
1365
1366 /* Color pipeline capabilities */
1367 dc->caps.color.dpp.dcn_arch = 1;
1368 dc->caps.color.dpp.input_lut_shared = 1;
1369 dc->caps.color.dpp.icsc = 1;
1370 dc->caps.color.dpp.dgam_ram = 1;
1371 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1372 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1373 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1374 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1375 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1376 dc->caps.color.dpp.post_csc = 0;
1377 dc->caps.color.dpp.gamma_corr = 0;
1378 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1379
1380 dc->caps.color.dpp.hw_3d_lut = 0;
1381 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
1382 dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
1383 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
1384 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1385 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1386 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1387 dc->caps.color.dpp.ocsc = 1;
1388
1389 /* no post-blend color operations */
1390 dc->caps.color.mpc.gamut_remap = 0;
1391 dc->caps.color.mpc.num_3dluts = 0;
1392 dc->caps.color.mpc.shared_3d_lut = 0;
1393 dc->caps.color.mpc.ogam_ram = 0;
1394 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1395 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1396 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1397 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1398 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1399 dc->caps.color.mpc.ocsc = 0;
1400
1401 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1402 dc->debug = debug_defaults_drv;
1403 else
1404 dc->debug = debug_defaults_diags;
1405
1406 /*************************************************
1407 * Create resources *
1408 *************************************************/
1409
1410 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1411 dcn10_clock_source_create(ctx, ctx->dc_bios,
1412 CLOCK_SOURCE_COMBO_PHY_PLL0,
1413 &clk_src_regs[0], false);
1414 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1415 dcn10_clock_source_create(ctx, ctx->dc_bios,
1416 CLOCK_SOURCE_COMBO_PHY_PLL1,
1417 &clk_src_regs[1], false);
1418 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1419 dcn10_clock_source_create(ctx, ctx->dc_bios,
1420 CLOCK_SOURCE_COMBO_PHY_PLL2,
1421 &clk_src_regs[2], false);
1422
1423 if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1424 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1425 dcn10_clock_source_create(ctx, ctx->dc_bios,
1426 CLOCK_SOURCE_COMBO_PHY_PLL3,
1427 &clk_src_regs[3], false);
1428 }
1429
1430 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1431
1432 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1433 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1434
1435 pool->base.dp_clock_source =
1436 dcn10_clock_source_create(ctx, ctx->dc_bios,
1437 CLOCK_SOURCE_ID_DP_DTO,
1438 /* todo: not reuse phy_pll registers */
1439 &clk_src_regs[0], true);
1440
1441 for (i = 0; i < pool->base.clk_src_count; i++) {
1442 if (pool->base.clock_sources[i] == NULL) {
1443 dm_error("DC: failed to create clock sources!\n");
1444 BREAK_TO_DEBUGGER();
1445 goto fail;
1446 }
1447 }
1448
1449 pool->base.dmcu = dcn10_dmcu_create(ctx,
1450 &dmcu_regs,
1451 &dmcu_shift,
1452 &dmcu_mask);
1453 if (pool->base.dmcu == NULL) {
1454 dm_error("DC: failed to create dmcu!\n");
1455 BREAK_TO_DEBUGGER();
1456 goto fail;
1457 }
1458
1459 pool->base.abm = dce_abm_create(ctx,
1460 &abm_regs,
1461 &abm_shift,
1462 &abm_mask);
1463 if (pool->base.abm == NULL) {
1464 dm_error("DC: failed to create abm!\n");
1465 BREAK_TO_DEBUGGER();
1466 goto fail;
1467 }
1468
1469 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1470 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1471 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1472
1473 DC_FP_START();
1474 dcn10_resource_construct_fp(dc);
1475 DC_FP_END();
1476
1477 if (!dc->config.is_vmin_only_asic)
1478 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))
1479 switch (dc->ctx->asic_id.pci_revision_id) {
1480 case PRID_DALI_DE:
1481 case PRID_DALI_DF:
1482 case PRID_DALI_E3:
1483 case PRID_DALI_E4:
1484 case PRID_POLLOCK_94:
1485 case PRID_POLLOCK_95:
1486 case PRID_POLLOCK_E9:
1487 case PRID_POLLOCK_EA:
1488 case PRID_POLLOCK_EB:
1489 dc->config.is_vmin_only_asic = true;
1490 break;
1491 default:
1492 break;
1493 }
1494
1495 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1496
1497 /*
1498 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1499 * implemented. So AZ D3 should work.For issue 197007. *
1500 */
1501 if (pool->base.pp_smu != NULL
1502 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1503 dc->debug.az_endpoint_mute_only = false;
1504
1505
1506 if (!dc->debug.disable_pplib_clock_request) {
1507 /*
1508 * TODO: This is not the proper way to obtain
1509 * fabric_and_dram_bandwidth, should be min(fclk, memclk).
1510 */
1511 res = dm_pp_get_clock_levels_by_type_with_voltage(
1512 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1513
1514 DC_FP_START();
1515
1516 if (res)
1517 res = verify_clock_values(&fclks);
1518
1519 if (res)
1520 dcn_bw_update_from_pplib_fclks(dc, &fclks);
1521 else
1522 BREAK_TO_DEBUGGER();
1523
1524 DC_FP_END();
1525
1526 res = dm_pp_get_clock_levels_by_type_with_voltage(
1527 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1528
1529 DC_FP_START();
1530
1531 if (res)
1532 res = verify_clock_values(&dcfclks);
1533
1534 if (res)
1535 dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);
1536 else
1537 BREAK_TO_DEBUGGER();
1538
1539 DC_FP_END();
1540 }
1541
1542 dcn_bw_sync_calcs_and_dml(dc);
1543 if (!dc->debug.disable_pplib_wm_range) {
1544 dc->res_pool = &pool->base;
1545 DC_FP_START();
1546 dcn_get_soc_clks(
1547 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
1548 DC_FP_END();
1549 dcn_bw_notify_pplib_of_wm_ranges(
1550 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
1551 }
1552
1553 {
1554 struct irq_service_init_data init_data;
1555 init_data.ctx = dc->ctx;
1556 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1557 if (!pool->base.irqs)
1558 goto fail;
1559 }
1560
1561 /* index to valid pipe resource */
1562 j = 0;
1563 /* mem input -> ipp -> dpp -> opp -> TG */
1564 for (i = 0; i < pool->base.pipe_count; i++) {
1565 /* if pipe is disabled, skip instance of HW pipe,
1566 * i.e, skip ASIC register instance
1567 */
1568 if ((pipe_fuses & (1 << i)) != 0)
1569 continue;
1570
1571 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1572 if (pool->base.hubps[j] == NULL) {
1573 BREAK_TO_DEBUGGER();
1574 dm_error(
1575 "DC: failed to create memory input!\n");
1576 goto fail;
1577 }
1578
1579 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1580 if (pool->base.ipps[j] == NULL) {
1581 BREAK_TO_DEBUGGER();
1582 dm_error(
1583 "DC: failed to create input pixel processor!\n");
1584 goto fail;
1585 }
1586
1587 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1588 if (pool->base.dpps[j] == NULL) {
1589 BREAK_TO_DEBUGGER();
1590 dm_error(
1591 "DC: failed to create dpp!\n");
1592 goto fail;
1593 }
1594
1595 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1596 if (pool->base.opps[j] == NULL) {
1597 BREAK_TO_DEBUGGER();
1598 dm_error(
1599 "DC: failed to create output pixel processor!\n");
1600 goto fail;
1601 }
1602
1603 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1604 ctx, i);
1605 if (pool->base.timing_generators[j] == NULL) {
1606 BREAK_TO_DEBUGGER();
1607 dm_error("DC: failed to create tg!\n");
1608 goto fail;
1609 }
1610 /* check next valid pipe */
1611 j++;
1612 }
1613
1614 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1615 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1616 if (pool->base.engines[i] == NULL) {
1617 BREAK_TO_DEBUGGER();
1618 dm_error(
1619 "DC:failed to create aux engine!!\n");
1620 goto fail;
1621 }
1622 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1623 if (pool->base.hw_i2cs[i] == NULL) {
1624 BREAK_TO_DEBUGGER();
1625 dm_error(
1626 "DC:failed to create hw i2c!!\n");
1627 goto fail;
1628 }
1629 pool->base.sw_i2cs[i] = NULL;
1630 }
1631
1632 /* valid pipe num */
1633 pool->base.pipe_count = j;
1634 pool->base.timing_generator_count = j;
1635 pool->base.mpcc_count = j;
1636
1637 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1638 * the value may be changed
1639 */
1640 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1641 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1642
1643 pool->base.mpc = dcn10_mpc_create(ctx);
1644 if (pool->base.mpc == NULL) {
1645 BREAK_TO_DEBUGGER();
1646 dm_error("DC: failed to create mpc!\n");
1647 goto fail;
1648 }
1649
1650 pool->base.hubbub = dcn10_hubbub_create(ctx);
1651 if (pool->base.hubbub == NULL) {
1652 BREAK_TO_DEBUGGER();
1653 dm_error("DC: failed to create hubbub!\n");
1654 goto fail;
1655 }
1656
1657 if (!resource_construct(num_virtual_links, dc, &pool->base,
1658 &res_create_funcs))
1659 goto fail;
1660
1661 dcn10_hw_sequencer_construct(dc);
1662 dc->caps.max_planes = pool->base.pipe_count;
1663
1664 for (i = 0; i < dc->caps.max_planes; ++i)
1665 dc->caps.planes[i] = plane_cap;
1666
1667 dc->cap_funcs = cap_funcs;
1668
1669 return true;
1670
1671 fail:
1672
1673 dcn10_resource_destruct(pool);
1674
1675 return false;
1676 }
1677
dcn10_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1678 struct resource_pool *dcn10_create_resource_pool(
1679 const struct dc_init_data *init_data,
1680 struct dc *dc)
1681 {
1682 struct dcn10_resource_pool *pool =
1683 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1684
1685 if (!pool)
1686 return NULL;
1687
1688 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1689 return &pool->base;
1690
1691 kfree(pool);
1692 BREAK_TO_DEBUGGER();
1693 return NULL;
1694 }
1695