xref: /linux/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #include "resource.h"
26 #include "dce_i2c.h"
27 #include "dce_i2c_hw.h"
28 #include "reg_helper.h"
29 #include "include/gpio_service_interface.h"
30 
31 #define CTX \
32 	dce_i2c_hw->ctx
33 #define REG(reg)\
34 	dce_i2c_hw->regs->reg
35 
36 #undef FN
37 #define FN(reg_name, field_name) \
38 	dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
39 
execute_transaction(struct dce_i2c_hw * dce_i2c_hw)40 static void execute_transaction(
41 	struct dce_i2c_hw *dce_i2c_hw)
42 {
43 	REG_UPDATE_N(SETUP, 5,
44 		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0,
45 		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0,
46 		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0,
47 		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0,
48 		     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0);
49 
50 
51 	REG_UPDATE_5(DC_I2C_CONTROL,
52 		     DC_I2C_SOFT_RESET, 0,
53 		     DC_I2C_SW_STATUS_RESET, 0,
54 		     DC_I2C_SEND_RESET, 0,
55 		     DC_I2C_GO, 0,
56 		     DC_I2C_TRANSACTION_COUNT, dce_i2c_hw->transaction_count - 1);
57 
58 	/* start I2C transfer */
59 	REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
60 
61 	/* all transactions were executed and HW buffer became empty
62 	 * (even though it actually happens when status becomes DONE)
63 	 */
64 	dce_i2c_hw->transaction_count = 0;
65 	dce_i2c_hw->buffer_used_bytes = 0;
66 }
67 
get_channel_status(struct dce_i2c_hw * dce_i2c_hw,uint8_t * returned_bytes)68 static enum i2c_channel_operation_result get_channel_status(
69 	struct dce_i2c_hw *dce_i2c_hw,
70 	uint8_t *returned_bytes)
71 {
72 	uint32_t i2c_sw_status = 0;
73 	uint32_t value =
74 		REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
75 	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
76 		return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
77 	else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK)
78 		return I2C_CHANNEL_OPERATION_NO_RESPONSE;
79 	else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT)
80 		return I2C_CHANNEL_OPERATION_TIMEOUT;
81 	else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED)
82 		return I2C_CHANNEL_OPERATION_FAILED;
83 	else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE)
84 		return I2C_CHANNEL_OPERATION_SUCCEEDED;
85 
86 	/*
87 	 * this is the case when HW used for communication, I2C_SW_STATUS
88 	 * could be zero
89 	 */
90 	return I2C_CHANNEL_OPERATION_SUCCEEDED;
91 }
92 
get_hw_buffer_available_size(const struct dce_i2c_hw * dce_i2c_hw)93 static uint32_t get_hw_buffer_available_size(
94 	const struct dce_i2c_hw *dce_i2c_hw)
95 {
96 	return dce_i2c_hw->buffer_size -
97 			dce_i2c_hw->buffer_used_bytes;
98 }
99 
process_channel_reply(struct dce_i2c_hw * dce_i2c_hw,struct i2c_payload * reply)100 static void process_channel_reply(
101 	struct dce_i2c_hw *dce_i2c_hw,
102 	struct i2c_payload *reply)
103 {
104 	uint32_t length = reply->length;
105 	uint8_t *buffer = reply->data;
106 
107 	REG_SET_3(DC_I2C_DATA, 0,
108 		 DC_I2C_INDEX, dce_i2c_hw->buffer_used_write,
109 		 DC_I2C_DATA_RW, 1,
110 		 DC_I2C_INDEX_WRITE, 1);
111 
112 	while (length) {
113 		/* after reading the status,
114 		 * if the I2C operation executed successfully
115 		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
116 		 * should read data bytes from I2C circular data buffer
117 		 */
118 
119 		uint32_t i2c_data;
120 
121 		REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
122 		*buffer++ = i2c_data;
123 
124 		--length;
125 	}
126 }
127 
is_engine_available(struct dce_i2c_hw * dce_i2c_hw)128 static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw)
129 {
130 	unsigned int arbitrate;
131 	unsigned int i2c_hw_status;
132 
133 	REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status);
134 	if (i2c_hw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW)
135 		return false;
136 
137 	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
138 	if (arbitrate == DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY)
139 		return false;
140 
141 	return true;
142 }
143 
is_hw_busy(struct dce_i2c_hw * dce_i2c_hw)144 static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw)
145 {
146 	uint32_t i2c_sw_status = 0;
147 
148 	REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
149 	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
150 		return false;
151 
152 	if (is_engine_available(dce_i2c_hw))
153 		return false;
154 
155 	return true;
156 }
157 
process_transaction(struct dce_i2c_hw * dce_i2c_hw,struct i2c_request_transaction_data * request)158 static bool process_transaction(
159 	struct dce_i2c_hw *dce_i2c_hw,
160 	struct i2c_request_transaction_data *request)
161 {
162 	uint32_t length = request->length;
163 	uint8_t *buffer = request->data;
164 
165 	bool last_transaction = false;
166 	uint32_t value = 0;
167 
168 	if (is_hw_busy(dce_i2c_hw)) {
169 		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
170 		return false;
171 	}
172 
173 	last_transaction = ((dce_i2c_hw->transaction_count == 3) ||
174 			(request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) ||
175 			(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ));
176 
177 
178 	switch (dce_i2c_hw->transaction_count) {
179 	case 0:
180 		REG_UPDATE_5(DC_I2C_TRANSACTION0,
181 				 DC_I2C_STOP_ON_NACK0, 1,
182 				 DC_I2C_START0, 1,
183 				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
184 				 DC_I2C_COUNT0, length,
185 				 DC_I2C_STOP0, last_transaction ? 1 : 0);
186 		break;
187 	case 1:
188 		REG_UPDATE_5(DC_I2C_TRANSACTION1,
189 				 DC_I2C_STOP_ON_NACK0, 1,
190 				 DC_I2C_START0, 1,
191 				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
192 				 DC_I2C_COUNT0, length,
193 				 DC_I2C_STOP0, last_transaction ? 1 : 0);
194 		break;
195 	case 2:
196 		REG_UPDATE_5(DC_I2C_TRANSACTION2,
197 				 DC_I2C_STOP_ON_NACK0, 1,
198 				 DC_I2C_START0, 1,
199 				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
200 				 DC_I2C_COUNT0, length,
201 				 DC_I2C_STOP0, last_transaction ? 1 : 0);
202 		break;
203 	case 3:
204 		REG_UPDATE_5(DC_I2C_TRANSACTION3,
205 				 DC_I2C_STOP_ON_NACK0, 1,
206 				 DC_I2C_START0, 1,
207 				 DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
208 				 DC_I2C_COUNT0, length,
209 				 DC_I2C_STOP0, last_transaction ? 1 : 0);
210 		break;
211 	default:
212 		/* TODO Warning ? */
213 		break;
214 	}
215 
216 	/* Write the I2C address and I2C data
217 	 * into the hardware circular buffer, one byte per entry.
218 	 * As an example, the 7-bit I2C slave address for CRT monitor
219 	 * for reading DDC/EDID information is 0b1010001.
220 	 * For an I2C send operation, the LSB must be programmed to 0;
221 	 * for I2C receive operation, the LSB must be programmed to 1.
222 	 */
223 	if (dce_i2c_hw->transaction_count == 0) {
224 		value = REG_SET_4(DC_I2C_DATA, 0,
225 				  DC_I2C_DATA_RW, false,
226 				  DC_I2C_DATA, request->address,
227 				  DC_I2C_INDEX, 0,
228 				  DC_I2C_INDEX_WRITE, 1);
229 		dce_i2c_hw->buffer_used_write = 0;
230 	} else
231 		value = REG_SET_2(DC_I2C_DATA, 0,
232 			  DC_I2C_DATA_RW, false,
233 			  DC_I2C_DATA, request->address);
234 
235 	dce_i2c_hw->buffer_used_write++;
236 
237 	if (!(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ)) {
238 		while (length) {
239 			REG_SET_2(DC_I2C_DATA, value,
240 				  DC_I2C_INDEX_WRITE, 0,
241 				  DC_I2C_DATA, *buffer++);
242 			dce_i2c_hw->buffer_used_write++;
243 			--length;
244 		}
245 	}
246 
247 	++dce_i2c_hw->transaction_count;
248 	dce_i2c_hw->buffer_used_bytes += length + 1;
249 
250 	return last_transaction;
251 }
252 
reset_hw_engine(struct dce_i2c_hw * dce_i2c_hw)253 static inline void reset_hw_engine(struct dce_i2c_hw *dce_i2c_hw)
254 {
255 	REG_UPDATE_2(DC_I2C_CONTROL,
256 		     DC_I2C_SW_STATUS_RESET, 1,
257 		     DC_I2C_SW_STATUS_RESET, 1);
258 }
259 
set_speed(struct dce_i2c_hw * dce_i2c_hw,uint32_t speed)260 static void set_speed(
261 	struct dce_i2c_hw *dce_i2c_hw,
262 	uint32_t speed)
263 {
264 	uint32_t xtal_ref_div = 0, ref_base_div = 0;
265 	uint32_t prescale = 0;
266 	uint32_t i2c_ref_clock = 0;
267 
268 	if (speed == 0)
269 		return;
270 
271 	REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div,
272 		XTAL_REF_DIV, &xtal_ref_div);
273 
274 	if (xtal_ref_div == 0)
275 		xtal_ref_div = 2;
276 
277 	if (ref_base_div == 0)
278 		i2c_ref_clock = (dce_i2c_hw->reference_frequency * 2);
279 	else
280 		i2c_ref_clock = ref_base_div * 1000;
281 
282 	prescale = (i2c_ref_clock / xtal_ref_div) / speed;
283 
284 	if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
285 		REG_UPDATE_N(SPEED, 3,
286 			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale,
287 			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2,
288 			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
289 	else
290 		REG_UPDATE_N(SPEED, 2,
291 			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale,
292 			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
293 }
294 
setup_engine(struct dce_i2c_hw * dce_i2c_hw)295 static bool setup_engine(
296 	struct dce_i2c_hw *dce_i2c_hw)
297 {
298 	uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
299 	uint32_t  reset_length = 0;
300 
301 	if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
302 		if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) {
303 			REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);
304 			REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);
305 		}
306 	}
307 
308 	if (dce_i2c_hw->masks->DC_I2C_DDC1_CLK_EN)
309 		REG_UPDATE_N(SETUP, 1,
310 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_EN), 1);
311 
312 	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
313 	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
314 
315 	/*set SW requested I2c speed to default, if API calls in it will be override later*/
316 	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
317 
318 	if (dce_i2c_hw->setup_limit != 0)
319 		i2c_setup_limit = dce_i2c_hw->setup_limit;
320 
321 	/* Program pin select */
322 	REG_UPDATE_6(DC_I2C_CONTROL,
323 		     DC_I2C_GO, 0,
324 		     DC_I2C_SOFT_RESET, 0,
325 		     DC_I2C_SEND_RESET, 0,
326 		     DC_I2C_SW_STATUS_RESET, 1,
327 		     DC_I2C_TRANSACTION_COUNT, 0,
328 		     DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id);
329 
330 	/* Program time limit */
331 	if (dce_i2c_hw->send_reset_length == 0) {
332 		/*pre-dcn*/
333 		REG_UPDATE_N(SETUP, 2,
334 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
335 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
336 	} else {
337 		reset_length = dce_i2c_hw->send_reset_length;
338 		REG_UPDATE_N(SETUP, 3,
339 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
340 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length,
341 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
342 	}
343 	/* Program HW priority
344 	 * set to High - interrupt software I2C at any time
345 	 * Enable restart of SW I2C that was interrupted by HW
346 	 * disable queuing of software while I2C is in use by HW
347 	 */
348 	REG_UPDATE(DC_I2C_ARBITRATION,
349 			DC_I2C_NO_QUEUED_SW_GO, 0);
350 
351 	return true;
352 }
353 
release_engine(struct dce_i2c_hw * dce_i2c_hw)354 static void release_engine(
355 	struct dce_i2c_hw *dce_i2c_hw)
356 {
357 	bool safe_to_reset;
358 
359 
360 	/* Reset HW engine */
361 	{
362 		uint32_t i2c_sw_status = 0;
363 
364 		REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
365 		/* if used by SW, safe to reset */
366 		safe_to_reset = (i2c_sw_status == 1);
367 	}
368 
369 	if (safe_to_reset)
370 		REG_UPDATE_2(DC_I2C_CONTROL,
371 			     DC_I2C_SOFT_RESET, 1,
372 			     DC_I2C_SW_STATUS_RESET, 1);
373 	else
374 		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
375 	/* HW I2c engine - clock gating feature */
376 	if (!dce_i2c_hw->engine_keep_power_up_count)
377 		REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0);
378 
379 	/*for HW HDCP Ri polling failure w/a test*/
380 	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);
381 	/* Release I2C after reset, so HW or DMCU could use it */
382 	REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
383 		DC_I2C_SW_USE_I2C_REG_REQ, 0);
384 
385 	if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
386 		if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL)
387 			REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
388 	}
389 }
390 
acquire_i2c_hw_engine(struct resource_pool * pool,struct ddc * ddc)391 struct dce_i2c_hw *acquire_i2c_hw_engine(
392 	struct resource_pool *pool,
393 	struct ddc *ddc)
394 {
395 	uint32_t counter = 0;
396 	enum gpio_result result;
397 	struct dce_i2c_hw *dce_i2c_hw = NULL;
398 
399 	if (!ddc)
400 		return NULL;
401 
402 	if (ddc->hw_info.hw_supported) {
403 		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
404 
405 		if (line < pool->res_cap->num_ddc)
406 			dce_i2c_hw = pool->hw_i2cs[line];
407 	}
408 
409 	if (!dce_i2c_hw)
410 		return NULL;
411 
412 	if (pool->i2c_hw_buffer_in_use || !is_engine_available(dce_i2c_hw))
413 		return NULL;
414 
415 	do {
416 		result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
417 			GPIO_DDC_CONFIG_TYPE_MODE_I2C);
418 
419 		if (result == GPIO_RESULT_OK)
420 			break;
421 
422 		/* i2c_engine is busy by VBios, lets wait and retry */
423 
424 		udelay(10);
425 
426 		++counter;
427 	} while (counter < 2);
428 
429 	if (result != GPIO_RESULT_OK)
430 		return NULL;
431 
432 	dce_i2c_hw->ddc = ddc;
433 
434 	if (!setup_engine(dce_i2c_hw)) {
435 		release_engine(dce_i2c_hw);
436 		return NULL;
437 	}
438 
439 	pool->i2c_hw_buffer_in_use = true;
440 	return dce_i2c_hw;
441 }
442 
dce_i2c_hw_engine_wait_on_operation_result(struct dce_i2c_hw * dce_i2c_hw,uint32_t timeout,enum i2c_channel_operation_result expected_result)443 static enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result(struct dce_i2c_hw *dce_i2c_hw,
444 										    uint32_t timeout,
445 										    enum i2c_channel_operation_result expected_result)
446 {
447 	enum i2c_channel_operation_result result;
448 	uint32_t i = 0;
449 
450 	if (!timeout)
451 		return I2C_CHANNEL_OPERATION_SUCCEEDED;
452 
453 	do {
454 
455 		result = get_channel_status(
456 				dce_i2c_hw, NULL);
457 
458 		if (result != expected_result)
459 			break;
460 
461 		udelay(1);
462 
463 		++i;
464 	} while (i < timeout);
465 	return result;
466 }
467 
submit_channel_request_hw(struct dce_i2c_hw * dce_i2c_hw,struct i2c_request_transaction_data * request)468 static void submit_channel_request_hw(
469 	struct dce_i2c_hw *dce_i2c_hw,
470 	struct i2c_request_transaction_data *request)
471 {
472 	request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
473 
474 	if (!process_transaction(dce_i2c_hw, request))
475 		return;
476 
477 	if (is_hw_busy(dce_i2c_hw)) {
478 		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
479 		return;
480 	}
481 	reset_hw_engine(dce_i2c_hw);
482 
483 	execute_transaction(dce_i2c_hw);
484 
485 
486 }
487 
get_transaction_timeout_hw(const struct dce_i2c_hw * dce_i2c_hw,uint32_t length,uint32_t speed)488 static uint32_t get_transaction_timeout_hw(
489 	const struct dce_i2c_hw *dce_i2c_hw,
490 	uint32_t length,
491 	uint32_t speed)
492 {
493 	uint32_t period_timeout;
494 	uint32_t num_of_clock_stretches;
495 
496 	if (!speed)
497 		return 0;
498 
499 	period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
500 
501 	num_of_clock_stretches = 1 + (length << 3) + 1;
502 	num_of_clock_stretches +=
503 		(dce_i2c_hw->buffer_used_bytes << 3) +
504 		(dce_i2c_hw->transaction_count << 1);
505 
506 	return period_timeout * num_of_clock_stretches;
507 }
508 
dce_i2c_hw_engine_submit_payload(struct dce_i2c_hw * dce_i2c_hw,struct i2c_payload * payload,bool middle_of_transaction,uint32_t speed)509 static bool dce_i2c_hw_engine_submit_payload(struct dce_i2c_hw *dce_i2c_hw,
510 					     struct i2c_payload *payload,
511 					     bool middle_of_transaction,
512 					     uint32_t speed)
513 {
514 
515 	struct i2c_request_transaction_data request;
516 
517 	uint32_t transaction_timeout;
518 
519 	enum i2c_channel_operation_result operation_result;
520 
521 	bool result = false;
522 
523 	/* We need following:
524 	 * transaction length will not exceed
525 	 * the number of free bytes in HW buffer (minus one for address)
526 	 */
527 
528 	if (payload->length >=
529 			get_hw_buffer_available_size(dce_i2c_hw)) {
530 		return false;
531 	}
532 
533 	if (!payload->write)
534 		request.action = middle_of_transaction ?
535 			DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT :
536 			DCE_I2C_TRANSACTION_ACTION_I2C_READ;
537 	else
538 		request.action = middle_of_transaction ?
539 			DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT :
540 			DCE_I2C_TRANSACTION_ACTION_I2C_WRITE;
541 
542 
543 	request.address = (uint8_t) ((payload->address << 1) | !payload->write);
544 	request.length = payload->length;
545 	request.data = payload->data;
546 
547 	/* obtain timeout value before submitting request */
548 
549 	transaction_timeout = get_transaction_timeout_hw(
550 		dce_i2c_hw, payload->length + 1, speed);
551 
552 	submit_channel_request_hw(
553 		dce_i2c_hw, &request);
554 
555 	if ((request.status == I2C_CHANNEL_OPERATION_FAILED) ||
556 		(request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY))
557 		return false;
558 
559 	/* wait until transaction proceed */
560 
561 	operation_result = dce_i2c_hw_engine_wait_on_operation_result(
562 		dce_i2c_hw,
563 		transaction_timeout,
564 		I2C_CHANNEL_OPERATION_ENGINE_BUSY);
565 
566 	/* update transaction status */
567 
568 	if (operation_result == I2C_CHANNEL_OPERATION_SUCCEEDED)
569 		result = true;
570 
571 	if (result && (!payload->write))
572 		process_channel_reply(dce_i2c_hw, payload);
573 
574 	return result;
575 }
576 
dce_i2c_submit_command_hw(struct resource_pool * pool,struct ddc * ddc,struct i2c_command * cmd,struct dce_i2c_hw * dce_i2c_hw)577 bool dce_i2c_submit_command_hw(
578 	struct resource_pool *pool,
579 	struct ddc *ddc,
580 	struct i2c_command *cmd,
581 	struct dce_i2c_hw *dce_i2c_hw)
582 {
583 	uint8_t index_of_payload = 0;
584 	bool result;
585 
586 	set_speed(dce_i2c_hw, cmd->speed);
587 
588 	result = true;
589 
590 	while (index_of_payload < cmd->number_of_payloads) {
591 		bool mot = (index_of_payload != cmd->number_of_payloads - 1);
592 
593 		struct i2c_payload *payload = cmd->payloads + index_of_payload;
594 
595 		if (!dce_i2c_hw_engine_submit_payload(
596 				dce_i2c_hw, payload, mot, cmd->speed)) {
597 			result = false;
598 			break;
599 		}
600 
601 		++index_of_payload;
602 	}
603 
604 	pool->i2c_hw_buffer_in_use = false;
605 
606 	release_engine(dce_i2c_hw);
607 	dal_ddc_close(dce_i2c_hw->ddc);
608 
609 	dce_i2c_hw->ddc = NULL;
610 
611 	return result;
612 }
613 
dce_i2c_hw_construct(struct dce_i2c_hw * dce_i2c_hw,struct dc_context * ctx,uint32_t engine_id,const struct dce_i2c_registers * regs,const struct dce_i2c_shift * shifts,const struct dce_i2c_mask * masks)614 void dce_i2c_hw_construct(
615 	struct dce_i2c_hw *dce_i2c_hw,
616 	struct dc_context *ctx,
617 	uint32_t engine_id,
618 	const struct dce_i2c_registers *regs,
619 	const struct dce_i2c_shift *shifts,
620 	const struct dce_i2c_mask *masks)
621 {
622 	dce_i2c_hw->ctx = ctx;
623 	dce_i2c_hw->engine_id = engine_id;
624 	dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
625 	dce_i2c_hw->regs = regs;
626 	dce_i2c_hw->shifts = shifts;
627 	dce_i2c_hw->masks = masks;
628 	dce_i2c_hw->buffer_used_bytes = 0;
629 	dce_i2c_hw->transaction_count = 0;
630 	dce_i2c_hw->engine_keep_power_up_count = 1;
631 	dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED;
632 	dce_i2c_hw->send_reset_length = 0;
633 	dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
634 	dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE;
635 }
636 
dce100_i2c_hw_construct(struct dce_i2c_hw * dce_i2c_hw,struct dc_context * ctx,uint32_t engine_id,const struct dce_i2c_registers * regs,const struct dce_i2c_shift * shifts,const struct dce_i2c_mask * masks)637 void dce100_i2c_hw_construct(
638 	struct dce_i2c_hw *dce_i2c_hw,
639 	struct dc_context *ctx,
640 	uint32_t engine_id,
641 	const struct dce_i2c_registers *regs,
642 	const struct dce_i2c_shift *shifts,
643 	const struct dce_i2c_mask *masks)
644 {
645 	dce_i2c_hw_construct(dce_i2c_hw,
646 			ctx,
647 			engine_id,
648 			regs,
649 			shifts,
650 			masks);
651 	dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE100;
652 }
653 
dce112_i2c_hw_construct(struct dce_i2c_hw * dce_i2c_hw,struct dc_context * ctx,uint32_t engine_id,const struct dce_i2c_registers * regs,const struct dce_i2c_shift * shifts,const struct dce_i2c_mask * masks)654 void dce112_i2c_hw_construct(
655 	struct dce_i2c_hw *dce_i2c_hw,
656 	struct dc_context *ctx,
657 	uint32_t engine_id,
658 	const struct dce_i2c_registers *regs,
659 	const struct dce_i2c_shift *shifts,
660 	const struct dce_i2c_mask *masks)
661 {
662 	dce100_i2c_hw_construct(dce_i2c_hw,
663 			ctx,
664 			engine_id,
665 			regs,
666 			shifts,
667 			masks);
668 	dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED_100KHZ;
669 }
670 
dcn1_i2c_hw_construct(struct dce_i2c_hw * dce_i2c_hw,struct dc_context * ctx,uint32_t engine_id,const struct dce_i2c_registers * regs,const struct dce_i2c_shift * shifts,const struct dce_i2c_mask * masks)671 void dcn1_i2c_hw_construct(
672 	struct dce_i2c_hw *dce_i2c_hw,
673 	struct dc_context *ctx,
674 	uint32_t engine_id,
675 	const struct dce_i2c_registers *regs,
676 	const struct dce_i2c_shift *shifts,
677 	const struct dce_i2c_mask *masks)
678 {
679 	dce112_i2c_hw_construct(dce_i2c_hw,
680 			ctx,
681 			engine_id,
682 			regs,
683 			shifts,
684 			masks);
685 	dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN;
686 }
687 
dcn2_i2c_hw_construct(struct dce_i2c_hw * dce_i2c_hw,struct dc_context * ctx,uint32_t engine_id,const struct dce_i2c_registers * regs,const struct dce_i2c_shift * shifts,const struct dce_i2c_mask * masks)688 void dcn2_i2c_hw_construct(
689 	struct dce_i2c_hw *dce_i2c_hw,
690 	struct dc_context *ctx,
691 	uint32_t engine_id,
692 	const struct dce_i2c_registers *regs,
693 	const struct dce_i2c_shift *shifts,
694 	const struct dce_i2c_mask *masks)
695 {
696 	dcn1_i2c_hw_construct(dce_i2c_hw,
697 			ctx,
698 			engine_id,
699 			regs,
700 			shifts,
701 			masks);
702 	dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9;
703 	if (ctx->dc->debug.scl_reset_length10)
704 		dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10;
705 }
706