| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
138 static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg) in dccg35_set_dsc_clk_rcg()
169 struct dccg *dccg, in dccg35_set_symclk32_se_rcg()
208 struct dccg *dccg, in dccg35_set_symclk32_le_rcg()
235 struct dccg *dccg, in dccg35_set_physymclk_rcg()
272 struct dccg *dccg, in dccg35_set_symclk_fe_rcg()
319 struct dccg *dccg, in dccg35_set_symclk_be_rcg()
367 static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable) in dccg35_set_dtbclk_p_rcg()
394 static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg) in dccg35_set_dppclk_rcg()
425 struct dccg *dccg, in dccg35_set_dpstreamclk_rcg()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| H A D | dcn401_dccg.c | 41 #define TO_DCN_DCCG(dccg)\ argument
56 static void dcn401_set_dppclk_enable(struct dccg *dccg, in dcn401_set_dppclk_enable()
78 void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg401_update_dpp_dto()
110 struct dccg *dccg) in dccg401_wait_for_dentist_change_done()
121 struct dccg *dccg, in dccg401_get_pixel_rate_div()
159 struct dccg *dccg, in dccg401_set_pixel_rate_div()
214 struct dccg *dccg, in dccg401_set_dtbclk_p_src()
269 struct dccg *dccg, in dccg401_set_physymclk()
352 void dccg401_get_dccg_ref_freq(struct dccg *dccg, in dccg401_get_dccg_ref_freq()
364 static void dccg401_otg_add_pixel(struct dccg *dccg, in dccg401_otg_add_pixel()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
47 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg31_update_dpp_dto()
98 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_enable_dpstreamclk()
130 static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_disable_dpstreamclk()
163 struct dccg *dccg, in dccg31_set_dpstreamclk()
175 struct dccg *dccg, in dccg31_enable_symclk32_se()
228 struct dccg *dccg, in dccg31_disable_symclk32_se()
278 struct dccg *dccg, in dccg31_enable_symclk32_le()
305 struct dccg *dccg, in dccg31_disable_symclk32_le()
329 struct dccg *dccg, in dccg31_set_symclk32_le_root_clock_gating()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq()
99 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, in dccg2_set_fifo_errdet_ovr_en()
108 void dccg2_otg_add_pixel(struct dccg *dccg, in dccg2_otg_add_pixel()
120 void dccg2_otg_drop_pixel(struct dccg *dccg, in dccg2_otg_drop_pixel()
132 void dccg2_init(struct dccg *dccg) in dccg2_init()
148 void dccg2_refclk_setup(struct dccg *dccg) in dccg2_refclk_setup()
157 bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg) in dccg2_is_s0i3_golden_init_wa_done()
164 void dccg2_allow_clock_gating(struct dccg *dccg, bool allow) in dccg2_allow_clock_gating()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
47 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync()
60 struct dccg *dccg, in dccg32_get_pixel_rate_div()
102 struct dccg *dccg, in dccg32_set_pixel_rate_div()
150 struct dccg *dccg, in dccg32_set_dtbclk_p_src()
206 struct dccg *dccg, in dccg32_set_dtbclk_dto()
249 struct dccg *dccg, in dccg32_set_valid_pixel_rate()
264 static void dccg32_get_dccg_ref_freq(struct dccg *dccg, in dccg32_get_dccg_ref_freq()
277 struct dccg *dccg, in dccg32_set_dpstreamclk()
313 static void dccg32_otg_add_pixel(struct dccg *dccg, in dccg32_otg_add_pixel()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 34 #define TO_DCN_DCCG(dccg)\ argument
50 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync()
60 struct dccg *dccg, in dccg314_get_pixel_rate_div()
102 struct dccg *dccg, in dccg314_set_pixel_rate_div()
150 struct dccg *dccg, in dccg314_set_dtbclk_p_src()
207 struct dccg *dccg, in dccg314_set_dtbclk_dto()
251 struct dccg *dccg, in dccg314_set_dpstreamclk()
289 static void dccg314_init(struct dccg *dccg) in dccg314_init()
316 struct dccg *dccg, in dccg314_set_valid_pixel_rate()
331 struct dccg *dccg, in dccg314_dpp_root_clock_control()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto()
111 static void dccg21_init(struct dccg *dccg) in dccg21_init()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
532 struct dccg *dccg) in dcn20_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 193 struct dccg { struct
195 const struct dccg_funcs *funcs; argument
214 void (*update_dpp_dto)(struct dccg *dccg, argument
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 270 struct dccg *dccg = clk_mgr->dccg; in dcn32_update_clocks_update_dtb_dto() local
374 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn32_update_clocks_update_dentist() local
427 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn32_update_clocks_update_dentist() local
1148 struct dccg *dccg) in dcn32_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 881 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream_timing() local
1673 struct dccg *dccg = dc->res_pool->dccg; in dcn20_update_dchubp_dpp() local
2203 struct dccg *dccg = dc->res_pool->dccg; in dcn20_post_unlock_reset_opp() local
2804 struct dccg *dccg = dc->res_pool->dccg; in dcn20_reset_back_end_for_pipe() local
3019 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream() local
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 182 struct dccg *dccg) in dcn201_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 147 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 202 struct dccg *dccg = clk_mgr_internal->dccg; in dcn35_disable_otg_wa() local
258 struct dccg *dccg = clk_mgr->dccg; in dcn35_update_clocks_update_dtb_dto() local
1401 struct dccg *dccg) in dcn35_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 58 #define TO_DCN_DCCG(dccg)\ argument
1255 struct dccg *dccg = dc->res_pool->dccg; in dcn30_get_underflow_debug_data() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1142 struct dccg *dccg = dc->res_pool->dccg; in dce110_disable_stream() local
1848 struct dccg *dccg = dc->res_pool->dccg; in clean_up_dsc_blocks() local
2885 struct clk_mgr *dccg = dc->clk_mgr; in dce110_prepare_bandwidth() local
2899 struct clk_mgr *dccg = dc->clk_mgr; in dce110_optimize_bandwidth() local
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 529 struct dccg *dccg = clk_mgr->dccg; in dcn401_update_clocks_update_dtb_dto() local
1549 struct dccg *dccg) in dcn401_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 704 struct dccg *dccg) in rn_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 524 struct dccg *dccg) in dcn3_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2252 struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg; in hwss_dccg_set_dto_dscclk() local
2873 struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; in hwss_dccg_set_ref_dscclk() local
2943 struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg; in hwss_dccg_update_dpp_dto() local
3150 struct dccg *dccg, int inst, int num_slices_h) in hwss_add_dccg_set_dto_dscclk()
3656 struct dccg *dccg, in hwss_add_dccg_set_ref_dscclk()
3780 struct dccg *dccg, in hwss_add_dccg_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 957 struct dccg *dccg = dc->res_pool->dccg; in dcn401_enable_stream() local
3480 struct dccg *dccg = dc->res_pool->dccg; in dcn401_post_unlock_reset_opp_sequence() local
3589 struct dccg *dccg = dc->res_pool->dccg; in dcn401_update_dchubp_dpp_sequence() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 1027 struct dccg *dccg = dc->res_pool->dccg; in dcn32_update_dsc_on_stream() local
|