| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
46 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg32_get_pixel_rate_div()
101 struct dccg *dccg, in dccg32_set_pixel_rate_div()
149 struct dccg *dccg, in dccg32_set_dtbclk_p_src()
205 struct dccg *dccg, in dccg32_set_dtbclk_dto()
248 struct dccg *dccg, in dccg32_set_valid_pixel_rate()
263 static void dccg32_get_dccg_ref_freq(struct dccg *dccg, in dccg32_get_dccg_ref_freq()
276 struct dccg *dccg, in dccg32_set_dpstreamclk()
312 static void dccg32_otg_add_pixel(struct dccg *dccg, in dccg32_otg_add_pixel()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
532 struct dccg *dccg) in dcn20_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 896 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream_timing() local
1688 struct dccg *dccg = dc->res_pool->dccg; in dcn20_update_dchubp_dpp() local
2218 struct dccg *dccg = dc->res_pool->dccg; in dcn20_post_unlock_reset_opp() local
2819 struct dccg *dccg = dc->res_pool->dccg; in dcn20_reset_back_end_for_pipe() local
3034 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream() local
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 182 struct dccg *dccg) in dcn201_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 704 struct dccg *dccg) in rn_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 524 struct dccg *dccg) in dcn3_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2250 struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg; in hwss_dccg_set_dto_dscclk() local
2871 struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; in hwss_dccg_set_ref_dscclk() local
2941 struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg; in hwss_dccg_update_dpp_dto() local
3148 struct dccg *dccg, int inst, int num_slices_h) in hwss_add_dccg_set_dto_dscclk()
3654 struct dccg *dccg, in hwss_add_dccg_set_ref_dscclk()
3778 struct dccg *dccg, in hwss_add_dccg_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 949 struct dccg *dccg = dc->res_pool->dccg; in dcn401_enable_stream() local
3465 struct dccg *dccg = dc->res_pool->dccg; in dcn401_post_unlock_reset_opp_sequence() local
3574 struct dccg *dccg = dc->res_pool->dccg; in dcn401_update_dchubp_dpp_sequence() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 221 struct dccg *dccg; member
625 struct dccg *dccg; member
631 struct dccg *dccg; member
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 812 struct dccg *dccg = dc->res_pool->dccg; in link_set_dsc_on_stream() local
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 3009 } dccg; member
|