| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
137 static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg) in dccg35_set_dsc_clk_rcg()
168 struct dccg *dccg, in dccg35_set_symclk32_se_rcg()
207 struct dccg *dccg, in dccg35_set_symclk32_le_rcg()
234 struct dccg *dccg, in dccg35_set_physymclk_rcg()
271 struct dccg *dccg, in dccg35_set_symclk_fe_rcg()
318 struct dccg *dccg, in dccg35_set_symclk_be_rcg()
366 static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable) in dccg35_set_dtbclk_p_rcg()
393 static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg) in dccg35_set_dppclk_rcg()
424 struct dccg *dccg, in dccg35_set_dpstreamclk_rcg()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg31_update_dpp_dto()
97 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_enable_dpstreamclk()
129 static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_disable_dpstreamclk()
162 struct dccg *dccg, in dccg31_set_dpstreamclk()
174 struct dccg *dccg, in dccg31_enable_symclk32_se()
227 struct dccg *dccg, in dccg31_disable_symclk32_se()
277 struct dccg *dccg, in dccg31_enable_symclk32_le()
304 struct dccg *dccg, in dccg31_disable_symclk32_le()
328 struct dccg *dccg, in dccg31_set_symclk32_le_root_clock_gating()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
46 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg32_get_pixel_rate_div()
101 struct dccg *dccg, in dccg32_set_pixel_rate_div()
149 struct dccg *dccg, in dccg32_set_dtbclk_p_src()
205 struct dccg *dccg, in dccg32_set_dtbclk_dto()
248 struct dccg *dccg, in dccg32_set_valid_pixel_rate()
263 static void dccg32_get_dccg_ref_freq(struct dccg *dccg, in dccg32_get_dccg_ref_freq()
276 struct dccg *dccg, in dccg32_set_dpstreamclk()
312 static void dccg32_otg_add_pixel(struct dccg *dccg, in dccg32_otg_add_pixel()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 33 #define TO_DCN_DCCG(dccg)\ argument
49 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg314_get_pixel_rate_div()
101 struct dccg *dccg, in dccg314_set_pixel_rate_div()
149 struct dccg *dccg, in dccg314_set_dtbclk_p_src()
206 struct dccg *dccg, in dccg314_set_dtbclk_dto()
250 struct dccg *dccg, in dccg314_set_dpstreamclk()
288 static void dccg314_init(struct dccg *dccg) in dccg314_init()
315 struct dccg *dccg, in dccg314_set_valid_pixel_rate()
330 struct dccg *dccg, in dccg314_dpp_root_clock_control()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq()
99 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, in dccg2_set_fifo_errdet_ovr_en()
108 void dccg2_otg_add_pixel(struct dccg *dccg, in dccg2_otg_add_pixel()
120 void dccg2_otg_drop_pixel(struct dccg *dccg, in dccg2_otg_drop_pixel()
132 void dccg2_init(struct dccg *dccg) in dccg2_init()
170 void dcn_dccg_destroy(struct dccg **dccg) in dcn_dccg_destroy()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
532 struct dccg *dccg) in dcn20_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 888 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream_timing() local
1680 struct dccg *dccg = dc->res_pool->dccg; in dcn20_update_dchubp_dpp() local
2207 struct dccg *dccg = dc->res_pool->dccg; in dcn20_post_unlock_reset_opp() local
2808 struct dccg *dccg = dc->res_pool->dccg; in dcn20_reset_back_end_for_pipe() local
3023 struct dccg *dccg = dc->res_pool->dccg; in dcn20_enable_stream() local
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 182 struct dccg *dccg) in dcn201_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 819 struct dccg *dccg = dc->res_pool->dccg; in dcn35_enable_plane() local
862 struct dccg *dccg = dc->res_pool->dccg; in dcn35_plane_atomic_disable() local
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 704 struct dccg *dccg) in rn_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 524 struct dccg *dccg) in dcn3_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 946 struct dccg *dccg = dc->res_pool->dccg; in dcn401_enable_stream() local
|