1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_HW_SHARED_H__ 27 #define __DAL_HW_SHARED_H__ 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "dc_hw_types.h" 32 33 /****************************************************************************** 34 * Data types shared between different Virtual HW blocks 35 ******************************************************************************/ 36 37 #define MAX_AUDIOS 7 38 39 /** 40 * @MAX_PIPES: 41 * 42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number 43 * to be used inside loops and for determining array sizes. 44 */ 45 #define MAX_PIPES 6 46 #define MAX_PHANTOM_PIPES (MAX_PIPES / 2) 47 48 #define MAX_DPIA 6 49 #define MAX_CONNECTOR 6 50 #define MAX_VIRTUAL_LINKS 4 51 52 #define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS) 53 54 #define MAX_DIG_LINK_ENCODERS 7 55 #define MAX_DWB_PIPES 1 56 #define MAX_HPO_DP2_ENCODERS 4 57 #define MAX_HPO_DP2_LINK_ENCODERS 4 58 59 struct gamma_curve { 60 uint32_t offset; 61 uint32_t segments_num; 62 }; 63 64 struct curve_points { 65 struct fixed31_32 x; 66 struct fixed31_32 y; 67 struct fixed31_32 offset; 68 struct fixed31_32 slope; 69 70 uint32_t custom_float_x; 71 uint32_t custom_float_y; 72 uint32_t custom_float_offset; 73 uint32_t custom_float_slope; 74 }; 75 76 struct curve_points3 { 77 struct curve_points red; 78 struct curve_points green; 79 struct curve_points blue; 80 }; 81 82 struct pwl_result_data { 83 struct fixed31_32 red; 84 struct fixed31_32 green; 85 struct fixed31_32 blue; 86 87 struct fixed31_32 delta_red; 88 struct fixed31_32 delta_green; 89 struct fixed31_32 delta_blue; 90 91 uint32_t red_reg; 92 uint32_t green_reg; 93 uint32_t blue_reg; 94 95 uint32_t delta_red_reg; 96 uint32_t delta_green_reg; 97 uint32_t delta_blue_reg; 98 }; 99 100 struct dc_rgb { 101 uint32_t red; 102 uint32_t green; 103 uint32_t blue; 104 }; 105 106 struct tetrahedral_17x17x17 { 107 struct dc_rgb lut0[1229]; 108 struct dc_rgb lut1[1228]; 109 struct dc_rgb lut2[1228]; 110 struct dc_rgb lut3[1228]; 111 }; 112 struct tetrahedral_9x9x9 { 113 struct dc_rgb lut0[183]; 114 struct dc_rgb lut1[182]; 115 struct dc_rgb lut2[182]; 116 struct dc_rgb lut3[182]; 117 }; 118 119 struct tetrahedral_params { 120 union { 121 struct tetrahedral_17x17x17 tetrahedral_17; 122 struct tetrahedral_9x9x9 tetrahedral_9; 123 }; 124 bool use_tetrahedral_9; 125 bool use_12bits; 126 127 }; 128 129 /* arr_curve_points - regamma regions/segments specification 130 * arr_points - beginning and end point specified separately (only one on DCE) 131 * corner_points - beginning and end point for all 3 colors (DCN) 132 * rgb_resulted - final curve 133 */ 134 struct pwl_params { 135 struct gamma_curve arr_curve_points[34]; 136 union { 137 struct curve_points arr_points[2]; 138 struct curve_points3 corner_points[2]; 139 }; 140 struct pwl_result_data rgb_resulted[256 + 3]; 141 uint32_t hw_points_num; 142 }; 143 144 /* move to dpp 145 * while we are moving functionality out of opp to dpp to align 146 * HW programming to HW IP, we define these struct in hw_shared 147 * so we can still compile while refactoring 148 */ 149 150 enum lb_pixel_depth { 151 /* do not change the values because it is used as bit vector */ 152 LB_PIXEL_DEPTH_18BPP = 1, 153 LB_PIXEL_DEPTH_24BPP = 2, 154 LB_PIXEL_DEPTH_30BPP = 4, 155 LB_PIXEL_DEPTH_36BPP = 8 156 }; 157 158 enum graphics_csc_adjust_type { 159 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, 160 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ 161 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ 162 }; 163 164 enum ipp_degamma_mode { 165 IPP_DEGAMMA_MODE_BYPASS, 166 IPP_DEGAMMA_MODE_HW_sRGB, 167 IPP_DEGAMMA_MODE_HW_xvYCC, 168 IPP_DEGAMMA_MODE_USER_PWL 169 }; 170 171 enum gamcor_mode { 172 GAMCOR_MODE_BYPASS, 173 GAMCOR_MODE_RESERVED_1, 174 GAMCOR_MODE_USER_PWL, 175 GAMCOR_MODE_RESERVED_3 176 }; 177 178 enum ipp_output_format { 179 IPP_OUTPUT_FORMAT_12_BIT_FIX, 180 IPP_OUTPUT_FORMAT_16_BIT_BYPASS, 181 IPP_OUTPUT_FORMAT_FLOAT 182 }; 183 184 enum expansion_mode { 185 EXPANSION_MODE_DYNAMIC, 186 EXPANSION_MODE_ZERO 187 }; 188 189 struct default_adjustment { 190 enum lb_pixel_depth lb_color_depth; 191 enum dc_color_space out_color_space; 192 enum dc_color_space in_color_space; 193 enum dc_color_depth color_depth; 194 enum pixel_format surface_pixel_format; 195 enum graphics_csc_adjust_type csc_adjust_type; 196 bool force_hw_default; 197 }; 198 199 200 struct out_csc_color_matrix { 201 enum dc_color_space color_space; 202 uint16_t regval[12]; 203 }; 204 205 enum gamut_remap_select { 206 GAMUT_REMAP_BYPASS = 0, 207 GAMUT_REMAP_COEFF, 208 GAMUT_REMAP_COMA_COEFF, 209 GAMUT_REMAP_COMB_COEFF 210 }; 211 212 enum opp_regamma { 213 OPP_REGAMMA_BYPASS = 0, 214 OPP_REGAMMA_SRGB, 215 OPP_REGAMMA_XVYCC, 216 OPP_REGAMMA_USER 217 }; 218 219 enum optc_dsc_mode { 220 OPTC_DSC_DISABLED = 0, 221 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ 222 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ 223 }; 224 225 struct dc_bias_and_scale { 226 uint32_t scale_red; 227 uint32_t bias_red; 228 uint32_t scale_green; 229 uint32_t bias_green; 230 uint32_t scale_blue; 231 uint32_t bias_blue; 232 bool bias_and_scale_valid; 233 }; 234 235 enum test_pattern_dyn_range { 236 TEST_PATTERN_DYN_RANGE_VESA = 0, 237 TEST_PATTERN_DYN_RANGE_CEA 238 }; 239 240 enum test_pattern_mode { 241 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, 242 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, 243 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, 244 TEST_PATTERN_MODE_VERTICALBARS, 245 TEST_PATTERN_MODE_HORIZONTALBARS, 246 TEST_PATTERN_MODE_SINGLERAMP_RGB, 247 TEST_PATTERN_MODE_DUALRAMP_RGB, 248 TEST_PATTERN_MODE_XR_BIAS_RGB 249 }; 250 251 enum test_pattern_color_format { 252 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, 253 TEST_PATTERN_COLOR_FORMAT_BPC_8, 254 TEST_PATTERN_COLOR_FORMAT_BPC_10, 255 TEST_PATTERN_COLOR_FORMAT_BPC_12 256 }; 257 258 enum controller_dp_test_pattern { 259 CONTROLLER_DP_TEST_PATTERN_D102 = 0, 260 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, 261 CONTROLLER_DP_TEST_PATTERN_PRBS7, 262 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, 263 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, 264 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, 265 CONTROLLER_DP_TEST_PATTERN_COLORRAMP, 266 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 267 CONTROLLER_DP_TEST_PATTERN_RESERVED_8, 268 CONTROLLER_DP_TEST_PATTERN_RESERVED_9, 269 CONTROLLER_DP_TEST_PATTERN_RESERVED_A, 270 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, 271 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR 272 }; 273 274 enum controller_dp_color_space { 275 CONTROLLER_DP_COLOR_SPACE_RGB, 276 CONTROLLER_DP_COLOR_SPACE_YCBCR601, 277 CONTROLLER_DP_COLOR_SPACE_YCBCR709, 278 CONTROLLER_DP_COLOR_SPACE_UDEFINED 279 }; 280 281 enum dc_lut_mode { 282 LUT_BYPASS, 283 LUT_RAM_A, 284 LUT_RAM_B 285 }; 286 287 /** 288 * speakersToChannels 289 * 290 * @brief 291 * translate speakers to channels 292 * 293 * FL - Front Left 294 * FR - Front Right 295 * RL - Rear Left 296 * RR - Rear Right 297 * RC - Rear Center 298 * FC - Front Center 299 * FLC - Front Left Center 300 * FRC - Front Right Center 301 * RLC - Rear Left Center 302 * RRC - Rear Right Center 303 * LFE - Low Freq Effect 304 * 305 * FC 306 * FLC FRC 307 * FL FR 308 * 309 * LFE 310 * () 311 * 312 * 313 * RL RR 314 * RLC RRC 315 * RC 316 * 317 * ch 8 7 6 5 4 3 2 1 318 * 0b00000011 - - - - - - FR FL 319 * 0b00000111 - - - - - LFE FR FL 320 * 0b00001011 - - - - FC - FR FL 321 * 0b00001111 - - - - FC LFE FR FL 322 * 0b00010011 - - - RC - - FR FL 323 * 0b00010111 - - - RC - LFE FR FL 324 * 0b00011011 - - - RC FC - FR FL 325 * 0b00011111 - - - RC FC LFE FR FL 326 * 0b00110011 - - RR RL - - FR FL 327 * 0b00110111 - - RR RL - LFE FR FL 328 * 0b00111011 - - RR RL FC - FR FL 329 * 0b00111111 - - RR RL FC LFE FR FL 330 * 0b01110011 - RC RR RL - - FR FL 331 * 0b01110111 - RC RR RL - LFE FR FL 332 * 0b01111011 - RC RR RL FC - FR FL 333 * 0b01111111 - RC RR RL FC LFE FR FL 334 * 0b11110011 RRC RLC RR RL - - FR FL 335 * 0b11110111 RRC RLC RR RL - LFE FR FL 336 * 0b11111011 RRC RLC RR RL FC - FR FL 337 * 0b11111111 RRC RLC RR RL FC LFE FR FL 338 * 0b11000011 FRC FLC - - - - FR FL 339 * 0b11000111 FRC FLC - - - LFE FR FL 340 * 0b11001011 FRC FLC - - FC - FR FL 341 * 0b11001111 FRC FLC - - FC LFE FR FL 342 * 0b11010011 FRC FLC - RC - - FR FL 343 * 0b11010111 FRC FLC - RC - LFE FR FL 344 * 0b11011011 FRC FLC - RC FC - FR FL 345 * 0b11011111 FRC FLC - RC FC LFE FR FL 346 * 0b11110011 FRC FLC RR RL - - FR FL 347 * 0b11110111 FRC FLC RR RL - LFE FR FL 348 * 0b11111011 FRC FLC RR RL FC - FR FL 349 * 0b11111111 FRC FLC RR RL FC LFE FR FL 350 * 351 * @param 352 * speakers - speaker information as it comes from CEA audio block 353 */ 354 /* translate speakers to channels */ 355 356 union audio_cea_channels { 357 uint8_t all; 358 struct audio_cea_channels_bits { 359 uint32_t FL:1; 360 uint32_t FR:1; 361 uint32_t LFE:1; 362 uint32_t FC:1; 363 uint32_t RL_RC:1; 364 uint32_t RR:1; 365 uint32_t RC_RLC_FLC:1; 366 uint32_t RRC_FRC:1; 367 } channels; 368 }; 369 370 #endif /* __DAL_HW_SHARED_H__ */ 371