1 /*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dal_asic_id.h"
27 #include "dc_types.h"
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30 #include "dc_state_priv.h"
31 #include "link_service.h"
32
33 #include "dce100/dce_clk_mgr.h"
34 #include "dce110/dce110_clk_mgr.h"
35 #include "dce112/dce112_clk_mgr.h"
36 #include "dce120/dce120_clk_mgr.h"
37 #include "dcn10/rv1_clk_mgr.h"
38 #include "dcn10/rv2_clk_mgr.h"
39 #include "dcn20/dcn20_clk_mgr.h"
40 #include "dcn21/rn_clk_mgr.h"
41 #include "dcn201/dcn201_clk_mgr.h"
42 #include "dcn30/dcn30_clk_mgr.h"
43 #include "dcn301/vg_clk_mgr.h"
44 #include "dcn31/dcn31_clk_mgr.h"
45 #include "dcn314/dcn314_clk_mgr.h"
46 #include "dcn315/dcn315_clk_mgr.h"
47 #include "dcn316/dcn316_clk_mgr.h"
48 #include "dcn32/dcn32_clk_mgr.h"
49 #include "dcn35/dcn35_clk_mgr.h"
50 #include "dcn401/dcn401_clk_mgr.h"
51 #include "dcn42/dcn42_clk_mgr.h"
52 #include "dcn42b/dcn42b_clk_mgr.h"
53 #include "dcn60/dcn60_clk_mgr.h"
54
clk_mgr_helper_get_active_display_cnt(struct dc * dc,struct dc_state * context)55 int clk_mgr_helper_get_active_display_cnt(
56 struct dc *dc,
57 struct dc_state *context)
58 {
59 int i, display_count;
60
61 display_count = 0;
62 for (i = 0; i < context->stream_count; i++) {
63 const struct dc_stream_state *stream = context->streams[i];
64 const struct dc_stream_status *stream_status = &context->stream_status[i];
65
66 /* Don't count SubVP phantom pipes as part of active
67 * display count
68 */
69 if (dc_state_get_stream_subvp_type(context, stream) == SUBVP_PHANTOM)
70 continue;
71
72 if (!stream->dpms_off || dc->is_switch_in_progress_dest || (stream_status && stream_status->plane_count))
73 display_count++;
74 }
75
76 return display_count;
77 }
78
clk_mgr_helper_get_active_plane_cnt(struct dc * dc,struct dc_state * context)79 int clk_mgr_helper_get_active_plane_cnt(
80 struct dc *dc,
81 struct dc_state *context)
82 {
83 (void)dc;
84 int i, total_plane_count;
85
86 total_plane_count = 0;
87 for (i = 0; i < context->stream_count; i++) {
88 const struct dc_stream_status stream_status = context->stream_status[i];
89
90 /*
91 * Sum up plane_count for all streams ( active and virtual ).
92 */
93 total_plane_count += stream_status.plane_count;
94 }
95
96 return total_plane_count;
97 }
98
clk_mgr_exit_optimized_pwr_state(const struct dc * dc,struct clk_mgr * clk_mgr)99 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
100 {
101 struct dc_link *edp_links[MAX_NUM_EDP];
102 struct dc_link *edp_link = NULL;
103 unsigned int edp_num;
104 unsigned int panel_inst;
105
106 dc_get_edp_links(dc, edp_links, &edp_num);
107 if (dc->hwss.exit_optimized_pwr_state)
108 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
109
110 if (edp_num) {
111 for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
112 bool allow_active = false;
113
114 edp_link = edp_links[panel_inst];
115 if (!edp_link->psr_settings.psr_feature_enabled)
116 continue;
117 clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
118 dc->link_srv->edp_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);
119 dc->link_srv->edp_set_replay_allow_active(edp_link, &allow_active, false, false, NULL);
120 }
121 }
122
123 }
124
clk_mgr_optimize_pwr_state(const struct dc * dc,struct clk_mgr * clk_mgr)125 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
126 {
127 struct dc_link *edp_links[MAX_NUM_EDP];
128 struct dc_link *edp_link = NULL;
129 unsigned int edp_num;
130 unsigned int panel_inst;
131
132 dc_get_edp_links(dc, edp_links, &edp_num);
133 if (edp_num) {
134 for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
135 edp_link = edp_links[panel_inst];
136 if (!edp_link->psr_settings.psr_feature_enabled)
137 continue;
138 dc->link_srv->edp_set_psr_allow_active(edp_link,
139 &clk_mgr->psr_allow_active_cache, false, false, NULL);
140 dc->link_srv->edp_set_replay_allow_active(edp_link,
141 &clk_mgr->psr_allow_active_cache, false, false, NULL);
142 }
143 }
144
145 if (dc->hwss.optimize_pwr_state)
146 dc->hwss.optimize_pwr_state(dc, dc->current_state);
147
148 }
149
dc_clk_mgr_create(struct dc_context * ctx,struct pp_smu_funcs * pp_smu,struct dccg * dccg)150 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
151 {
152 struct hw_asic_id asic_id = ctx->asic_id;
153
154 switch (asic_id.chip_family) {
155 case FAMILY_SI:
156 case FAMILY_CI:
157 case FAMILY_KV: {
158 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
159
160 if (clk_mgr == NULL) {
161 BREAK_TO_DEBUGGER();
162 return NULL;
163 }
164 dce_clk_mgr_construct(ctx, clk_mgr);
165 return &clk_mgr->base;
166 }
167 case FAMILY_CZ: {
168 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
169
170 if (clk_mgr == NULL) {
171 BREAK_TO_DEBUGGER();
172 return NULL;
173 }
174 dce110_clk_mgr_construct(ctx, clk_mgr);
175 return &clk_mgr->base;
176 }
177 case FAMILY_VI: {
178 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
179
180 if (clk_mgr == NULL) {
181 BREAK_TO_DEBUGGER();
182 return NULL;
183 }
184 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
185 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
186 dce_clk_mgr_construct(ctx, clk_mgr);
187 return &clk_mgr->base;
188 }
189 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
190 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
191 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
192 dce112_clk_mgr_construct(ctx, clk_mgr);
193 return &clk_mgr->base;
194 }
195 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
196 dce112_clk_mgr_construct(ctx, clk_mgr);
197 return &clk_mgr->base;
198 }
199 return &clk_mgr->base;
200 }
201 case FAMILY_AI: {
202 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
203
204 if (clk_mgr == NULL) {
205 BREAK_TO_DEBUGGER();
206 return NULL;
207 }
208 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
209 dce121_clk_mgr_construct(ctx, clk_mgr);
210 else
211 dce120_clk_mgr_construct(ctx, clk_mgr);
212 return &clk_mgr->base;
213 }
214 #if defined(CONFIG_DRM_AMD_DC_FP)
215 case FAMILY_RV: {
216 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
217
218 if (clk_mgr == NULL) {
219 BREAK_TO_DEBUGGER();
220 return NULL;
221 }
222
223 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
224 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
225 return &clk_mgr->base;
226 }
227
228 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
229 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
230 return &clk_mgr->base;
231 }
232 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
233 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
234 return &clk_mgr->base;
235 }
236 if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
237 ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
238 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
239 return &clk_mgr->base;
240 }
241 return &clk_mgr->base;
242 }
243 case FAMILY_NV: {
244 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
245
246 if (clk_mgr == NULL) {
247 BREAK_TO_DEBUGGER();
248 return NULL;
249 }
250 if (ctx->dce_version == DCN_VERSION_2_01) {
251 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
252 return &clk_mgr->base;
253 }
254 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
255 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
256 return &clk_mgr->base;
257 }
258 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) {
259 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
260 return &clk_mgr->base;
261 }
262 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {
263 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
264 return &clk_mgr->base;
265 }
266 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
267 return &clk_mgr->base;
268 }
269 case FAMILY_VGH:
270 if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev)) {
271 struct clk_mgr_vgh *clk_mgr = kzalloc_obj(*clk_mgr);
272
273 if (clk_mgr == NULL) {
274 BREAK_TO_DEBUGGER();
275 return NULL;
276 }
277 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
278 return &clk_mgr->base.base;
279 }
280 break;
281
282 case FAMILY_YELLOW_CARP: {
283 struct clk_mgr_dcn31 *clk_mgr = kzalloc_obj(*clk_mgr);
284
285 if (clk_mgr == NULL) {
286 BREAK_TO_DEBUGGER();
287 return NULL;
288 }
289
290 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
291 return &clk_mgr->base.base;
292 }
293 break;
294 case AMDGPU_FAMILY_GC_10_3_6: {
295 struct clk_mgr_dcn315 *clk_mgr = kzalloc_obj(*clk_mgr);
296
297 if (clk_mgr == NULL) {
298 BREAK_TO_DEBUGGER();
299 return NULL;
300 }
301
302 dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
303 return &clk_mgr->base.base;
304 }
305 break;
306 case AMDGPU_FAMILY_GC_10_3_7: {
307 struct clk_mgr_dcn316 *clk_mgr = kzalloc_obj(*clk_mgr);
308
309 if (clk_mgr == NULL) {
310 BREAK_TO_DEBUGGER();
311 return NULL;
312 }
313
314 dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
315 return &clk_mgr->base.base;
316 }
317 break;
318 case AMDGPU_FAMILY_GC_11_0_0: {
319 struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);
320
321 if (clk_mgr == NULL) {
322 BREAK_TO_DEBUGGER();
323 return NULL;
324 }
325 dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
326 return &clk_mgr->base;
327 }
328
329 case AMDGPU_FAMILY_GC_11_0_1: {
330 struct clk_mgr_dcn314 *clk_mgr = kzalloc_obj(*clk_mgr);
331
332 if (clk_mgr == NULL) {
333 BREAK_TO_DEBUGGER();
334 return NULL;
335 }
336
337 dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
338 return &clk_mgr->base.base;
339 }
340 break;
341
342 case AMDGPU_FAMILY_GC_11_5_0: {
343 if (ctx->dce_version == DCN_VERSION_4_2B) {
344 struct clk_mgr_dcn42 *clk_mgr = kzalloc_obj(*clk_mgr);
345
346 if (clk_mgr == NULL) {
347 BREAK_TO_DEBUGGER();
348 return NULL;
349 }
350 dcn42b_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
351 return &clk_mgr->base.base;
352 }
353 struct clk_mgr_dcn35 *clk_mgr = kzalloc_obj(*clk_mgr);
354
355 if (clk_mgr == NULL) {
356 BREAK_TO_DEBUGGER();
357 return NULL;
358 }
359 if (ctx->dce_version == DCN_VERSION_3_51)
360 dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
361 else
362 dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
363
364 return &clk_mgr->base.base;
365 }
366 break;
367
368 case AMDGPU_FAMILY_GC_12_0_0: {
369 struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);
370
371 if (clk_mgr == NULL) {
372 BREAK_TO_DEBUGGER();
373 return NULL;
374 }
375
376 return &clk_mgr->base;
377 }
378 break;
379 case AMDGPU_FAMILY_GC_11_5_4: {
380 struct clk_mgr_dcn42 *clk_mgr = kzalloc_obj(*clk_mgr);
381
382 if (clk_mgr == NULL) {
383 BREAK_TO_DEBUGGER();
384 return NULL;
385 }
386
387 dcn42_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
388 return &clk_mgr->base.base;
389 }
390 break;
391 case AMDGPU_FAMILY_GC_13_0_1: {
392 struct clk_mgr_internal *clk_mgr = dcn60_clk_mgr_construct(ctx, dccg);
393
394 if (clk_mgr == NULL) {
395 BREAK_TO_DEBUGGER();
396 return NULL;
397 }
398
399 return &clk_mgr->base;
400 }
401
402 #endif /* CONFIG_DRM_AMD_DC_FP */
403 default:
404 ASSERT(0); /* Unknown Asic */
405 break;
406 }
407
408 return NULL;
409 }
410
dc_destroy_clk_mgr(struct clk_mgr * clk_mgr_base)411 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
412 {
413 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
414
415 #ifdef CONFIG_DRM_AMD_DC_FP
416 switch (clk_mgr_base->ctx->asic_id.chip_family) {
417 case FAMILY_NV:
418 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
419 dcn3_clk_mgr_destroy(clk_mgr);
420 } else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
421 dcn3_clk_mgr_destroy(clk_mgr);
422 }
423 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
424 dcn3_clk_mgr_destroy(clk_mgr);
425 }
426 break;
427
428 case FAMILY_VGH:
429 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev))
430 vg_clk_mgr_destroy(clk_mgr);
431 break;
432
433 case FAMILY_YELLOW_CARP:
434 dcn31_clk_mgr_destroy(clk_mgr);
435 break;
436
437 case AMDGPU_FAMILY_GC_10_3_6:
438 dcn315_clk_mgr_destroy(clk_mgr);
439 break;
440
441 case AMDGPU_FAMILY_GC_10_3_7:
442 dcn316_clk_mgr_destroy(clk_mgr);
443 break;
444
445 case AMDGPU_FAMILY_GC_11_0_0:
446 dcn32_clk_mgr_destroy(clk_mgr);
447 break;
448
449 case AMDGPU_FAMILY_GC_11_0_1:
450 dcn314_clk_mgr_destroy(clk_mgr);
451 break;
452
453 case AMDGPU_FAMILY_GC_11_5_0:
454 if (clk_mgr_base->ctx->dce_version == DCN_VERSION_4_2B) {
455 dcn42_clk_mgr_destroy(clk_mgr);
456 break;
457 }
458 dcn35_clk_mgr_destroy(clk_mgr);
459 break;
460 case AMDGPU_FAMILY_GC_12_0_0:
461 dcn401_clk_mgr_destroy(clk_mgr);
462 break;
463 case AMDGPU_FAMILY_GC_11_5_4:
464 dcn42_clk_mgr_destroy(clk_mgr);
465 break;
466 case AMDGPU_FAMILY_GC_13_0_1:
467 dcn60_clk_mgr_destroy(clk_mgr);
468 break;
469
470 default:
471 break;
472 }
473 #endif /* CONFIG_DRM_AMD_DC_FP */
474
475 kfree(clk_mgr);
476 }
477
478