1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6 * Copyright (c) 2012 Luiz Otavio O Souza.
7 * Copyright (c) 2022 Julien Cassette <julien.cassette@gmail.com>
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/rman.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/gpio.h>
43 #include <sys/proc.h>
44
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
48
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/fdt/fdt_pinctrl.h>
53
54 #include <arm/allwinner/aw_machdep.h>
55 #include <arm/allwinner/allwinner_pinctrl.h>
56 #include <dev/clk/clk.h>
57 #include <dev/hwreset/hwreset.h>
58 #include <dev/regulator/regulator.h>
59
60 #if defined(__aarch64__) || defined(__riscv)
61 #include "opt_soc.h"
62 #endif
63
64 #include "pic_if.h"
65 #include "gpio_if.h"
66
67 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
68 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
69
70 #define AW_GPIO_INTR_CAPS (GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | \
71 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
72
73 #define AW_GPIO_NONE 0
74 #define AW_GPIO_PULLUP 1
75 #define AW_GPIO_PULLDOWN 2
76
77 #define AW_GPIO_INPUT 0
78 #define AW_GPIO_OUTPUT 1
79
80 #define AW_GPIO_DRV_MASK 0x3
81 #define AW_GPIO_PUD_MASK 0x3
82
83 #define AW_PINCTRL 1
84 #define AW_R_PINCTRL 2
85
86 #if defined(__arm__) || defined(__aarch64__)
87 #define IRQ_MEMORY_BARRIER(x) arm_irq_memory_barrier(x)
88 #else
89 #define IRQ_MEMORY_BARRIER(x) fence()
90 #endif
91
92 struct aw_gpio_conf {
93 struct allwinner_padconf *padconf;
94 const char *banks;
95 uint32_t bank_size;
96 uint32_t drv_pin_shift;
97 uint32_t pul_offset;
98 };
99
100 /* Defined in aw_padconf.c */
101 #ifdef SOC_ALLWINNER_A10
102 extern struct allwinner_padconf a10_padconf;
103 struct aw_gpio_conf a10_gpio_conf = {
104 .padconf = &a10_padconf,
105 .banks = "abcdefghi",
106 .bank_size = 0x24,
107 .drv_pin_shift = 1,
108 .pul_offset = 0x1C,
109 };
110 #endif
111
112 /* Defined in a13_padconf.c */
113 #ifdef SOC_ALLWINNER_A13
114 extern struct allwinner_padconf a13_padconf;
115 struct aw_gpio_conf a13_gpio_conf = {
116 .padconf = &a13_padconf,
117 .banks = "bcdefg",
118 .bank_size = 0x24,
119 .drv_pin_shift = 1,
120 .pul_offset = 0x1C,
121 };
122 #endif
123
124 /* Defined in a20_padconf.c */
125 #ifdef SOC_ALLWINNER_A20
126 extern struct allwinner_padconf a20_padconf;
127 struct aw_gpio_conf a20_gpio_conf = {
128 .padconf = &a20_padconf,
129 .banks = "abcdefghi",
130 .bank_size = 0x24,
131 .drv_pin_shift = 1,
132 .pul_offset = 0x1C,
133 };
134 #endif
135
136 /* Defined in a31_padconf.c */
137 #ifdef SOC_ALLWINNER_A31
138 extern struct allwinner_padconf a31_padconf;
139 struct aw_gpio_conf a31_gpio_conf = {
140 .padconf = &a31_padconf,
141 .banks = "abcdefgh",
142 .bank_size = 0x24,
143 .drv_pin_shift = 1,
144 .pul_offset = 0x1C,
145 };
146 #endif
147
148 /* Defined in a31s_padconf.c */
149 #ifdef SOC_ALLWINNER_A31S
150 extern struct allwinner_padconf a31s_padconf;
151 struct aw_gpio_conf a31s_gpio_conf = {
152 .padconf = &a31s_padconf,
153 .banks = "abcdefgh",
154 .bank_size = 0x24,
155 .drv_pin_shift = 1,
156 .pul_offset = 0x1C,
157 };
158 #endif
159
160 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
161 extern struct allwinner_padconf a31_r_padconf;
162 struct aw_gpio_conf a31_r_gpio_conf = {
163 .padconf = &a31_r_padconf,
164 .banks = "lm",
165 .bank_size = 0x24,
166 .drv_pin_shift = 1,
167 .pul_offset = 0x1C,
168 };
169 #endif
170
171 /* Defined in a33_padconf.c */
172 #ifdef SOC_ALLWINNER_A33
173 extern struct allwinner_padconf a33_padconf;
174 struct aw_gpio_conf a33_gpio_conf = {
175 .padconf = &a33_padconf,
176 .banks = "bcdefgh",
177 .bank_size = 0x24,
178 .drv_pin_shift = 1,
179 .pul_offset = 0x1C,
180 };
181 #endif
182
183 /* Defined in h3_padconf.c */
184 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
185 extern struct allwinner_padconf h3_padconf;
186 extern struct allwinner_padconf h3_r_padconf;
187 struct aw_gpio_conf h3_gpio_conf = {
188 .padconf = &h3_padconf,
189 .banks = "acdefg",
190 .bank_size = 0x24,
191 .drv_pin_shift = 1,
192 .pul_offset = 0x1C,
193 };
194 struct aw_gpio_conf h3_r_gpio_conf = {
195 .padconf = &h3_r_padconf,
196 .banks = "l",
197 .bank_size = 0x24,
198 .drv_pin_shift = 1,
199 .pul_offset = 0x1C,
200 };
201 #endif
202
203 /* Defined in a83t_padconf.c */
204 #ifdef SOC_ALLWINNER_A83T
205 extern struct allwinner_padconf a83t_padconf;
206 extern struct allwinner_padconf a83t_r_padconf;
207 struct aw_gpio_conf a83t_gpio_conf = {
208 .padconf = &a83t_padconf,
209 .banks = "bcdefgh",
210 .bank_size = 0x24,
211 .drv_pin_shift = 1,
212 .pul_offset = 0x1C,
213 };
214 struct aw_gpio_conf a83t_r_gpio_conf = {
215 .padconf = &a83t_r_padconf,
216 .banks = "l",
217 .bank_size = 0x24,
218 .drv_pin_shift = 1,
219 .pul_offset = 0x1C,
220 };
221 #endif
222
223 /* Defined in a64_padconf.c */
224 #ifdef SOC_ALLWINNER_A64
225 extern struct allwinner_padconf a64_padconf;
226 extern struct allwinner_padconf a64_r_padconf;
227 struct aw_gpio_conf a64_gpio_conf = {
228 .padconf = &a64_padconf,
229 .banks = "bcdefgh",
230 .bank_size = 0x24,
231 .drv_pin_shift = 1,
232 .pul_offset = 0x1C,
233 };
234 struct aw_gpio_conf a64_r_gpio_conf = {
235 .padconf = &a64_r_padconf,
236 .banks = "l",
237 .bank_size = 0x24,
238 .drv_pin_shift = 1,
239 .pul_offset = 0x1C,
240 };
241 #endif
242
243 /* Defined in d1_padconf.c */
244 #ifdef SOC_ALLWINNER_D1
245 extern struct allwinner_padconf d1_padconf;
246 struct aw_gpio_conf d1_gpio_conf = {
247 .padconf = &d1_padconf,
248 .banks = "bcdefg",
249 .bank_size = 0x30,
250 .drv_pin_shift = 2,
251 .pul_offset = 0x24,
252 };
253 #endif
254
255 /* Defined in h6_padconf.c */
256 #ifdef SOC_ALLWINNER_H6
257 extern struct allwinner_padconf h6_padconf;
258 extern struct allwinner_padconf h6_r_padconf;
259 struct aw_gpio_conf h6_gpio_conf = {
260 .padconf = &h6_padconf,
261 .banks = "cdfgh",
262 .bank_size = 0x24,
263 .drv_pin_shift = 1,
264 .pul_offset = 0x1C,
265 };
266 struct aw_gpio_conf h6_r_gpio_conf = {
267 .padconf = &h6_r_padconf,
268 .banks = "lm",
269 .bank_size = 0x24,
270 .drv_pin_shift = 1,
271 .pul_offset = 0x1C,
272 };
273 #endif
274
275 static struct ofw_compat_data compat_data[] = {
276 #ifdef SOC_ALLWINNER_A10
277 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
278 #endif
279 #ifdef SOC_ALLWINNER_A13
280 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
281 #endif
282 #ifdef SOC_ALLWINNER_A20
283 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
284 #endif
285 #ifdef SOC_ALLWINNER_A31
286 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
287 #endif
288 #ifdef SOC_ALLWINNER_A31S
289 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
290 #endif
291 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
292 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
293 #endif
294 #ifdef SOC_ALLWINNER_A33
295 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
296 #endif
297 #ifdef SOC_ALLWINNER_A83T
298 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf},
299 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_gpio_conf},
300 #endif
301 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
302 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_gpio_conf},
303 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_gpio_conf},
304 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_gpio_conf},
305 #endif
306 #ifdef SOC_ALLWINNER_A64
307 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_gpio_conf},
308 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_gpio_conf},
309 #endif
310 #ifdef SOC_ALLWINNER_D1
311 {"allwinner,sun20i-d1-pinctrl", (uintptr_t)&d1_gpio_conf},
312 #endif
313 #ifdef SOC_ALLWINNER_H6
314 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_gpio_conf},
315 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_gpio_conf},
316 #endif
317 {NULL, 0}
318 };
319
320 struct clk_list {
321 TAILQ_ENTRY(clk_list) next;
322 clk_t clk;
323 };
324
325 struct gpio_irqsrc {
326 struct intr_irqsrc isrc;
327 u_int irq;
328 uint32_t mode;
329 uint32_t pin;
330 uint32_t bank;
331 uint32_t intnum;
332 uint32_t intfunc;
333 uint32_t oldfunc;
334 bool enabled;
335 };
336
337 #define AW_GPIO_MEMRES 0
338 #define AW_GPIO_IRQRES 1
339 #define AW_GPIO_RESSZ 2
340
341 struct aw_gpio_softc {
342 device_t sc_dev;
343 device_t sc_busdev;
344 struct resource * sc_res[AW_GPIO_RESSZ];
345 struct mtx sc_mtx;
346 struct resource * sc_mem_res;
347 struct resource * sc_irq_res;
348 void * sc_intrhand;
349 struct aw_gpio_conf *conf;
350 TAILQ_HEAD(, clk_list) clk_list;
351
352 struct gpio_irqsrc *gpio_pic_irqsrc;
353 int nirqs;
354 };
355
356 static struct resource_spec aw_gpio_res_spec[] = {
357 { SYS_RES_MEMORY, 0, RF_ACTIVE },
358 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
359 { -1, 0, 0 }
360 };
361
362 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
363 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
364 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
365
366 #define AW_GPIO_GP_BASE(_sc, _bank) ((_sc)->conf->bank_size * (_bank))
367
368 #define AW_GPIO_GP_CFG(_sc, _bank, _idx) \
369 (AW_GPIO_GP_BASE(_sc, _bank) + 0x00 + ((_idx) << 2))
370 #define AW_GPIO_GP_DAT(_sc, _bank) \
371 (AW_GPIO_GP_BASE(_sc, _bank) + 0x10)
372 #define AW_GPIO_GP_DRV(_sc, _bank, _idx) \
373 (AW_GPIO_GP_BASE(_sc, _bank) + 0x14 + ((_idx) << 2))
374 #define AW_GPIO_GP_PUL(_sc, _bank, _idx) \
375 (AW_GPIO_GP_BASE(_sc, _bank) + (_sc)->conf->pul_offset + ((_idx) << 2))
376
377 #define AW_GPIO_GP_INT_BASE(_bank) (0x200 + 0x20 * _bank)
378
379 #define AW_GPIO_GP_INT_CFG(_bank, _pin) (AW_GPIO_GP_INT_BASE(_bank) + (0x4 * ((_pin) / 8)))
380 #define AW_GPIO_GP_INT_CTL(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x10)
381 #define AW_GPIO_GP_INT_STA(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x14)
382 #define AW_GPIO_GP_INT_DEB(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x18)
383
384 #define AW_GPIO_INT_EDGE_POSITIVE 0x0
385 #define AW_GPIO_INT_EDGE_NEGATIVE 0x1
386 #define AW_GPIO_INT_LEVEL_HIGH 0x2
387 #define AW_GPIO_INT_LEVEL_LOW 0x3
388 #define AW_GPIO_INT_EDGE_BOTH 0x4
389
390 static char *aw_gpio_parse_function(phandle_t node);
391 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb);
392 static uint32_t aw_gpio_parse_bias(phandle_t node);
393 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
394
395 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
396 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
397 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value);
398 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value);
399
400 static void aw_gpio_intr(void *arg);
401 static void aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc);
402 static void aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc);
403 static void aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc);
404 static int aw_gpio_register_isrcs(struct aw_gpio_softc *sc);
405
406 #define AW_GPIO_WRITE(_sc, _off, _val) \
407 bus_write_4((_sc)->sc_res[AW_GPIO_MEMRES], _off, _val)
408 #define AW_GPIO_READ(_sc, _off) \
409 bus_read_4((_sc)->sc_res[AW_GPIO_MEMRES], _off)
410
411 static uint32_t
aw_gpio_get_function(struct aw_gpio_softc * sc,uint32_t pin)412 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin)
413 {
414 uint32_t bank, func, offset;
415
416 /* Must be called with lock held. */
417 AW_GPIO_LOCK_ASSERT(sc);
418
419 if (pin > sc->conf->padconf->npins)
420 return (0);
421 bank = sc->conf->padconf->pins[pin].port;
422 pin = sc->conf->padconf->pins[pin].pin;
423 offset = ((pin & 0x07) << 2);
424
425 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(sc, bank, pin >> 3));
426
427 return ((func >> offset) & 0xF);
428 }
429
430 static int
aw_gpio_set_function(struct aw_gpio_softc * sc,uint32_t pin,uint32_t f)431 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f)
432 {
433 uint32_t bank, data, offset;
434
435 /* Check if the function exists in the padconf data */
436 if (sc->conf->padconf->pins[pin].functions[f] == NULL)
437 return (EINVAL);
438
439 /* Must be called with lock held. */
440 AW_GPIO_LOCK_ASSERT(sc);
441
442 bank = sc->conf->padconf->pins[pin].port;
443 pin = sc->conf->padconf->pins[pin].pin;
444 offset = ((pin & 0x07) << 2);
445
446 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(sc, bank, pin >> 3));
447 data &= ~(0xF << offset);
448 data |= (f << offset);
449 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(sc, bank, pin >> 3), data);
450
451 return (0);
452 }
453
454 static uint32_t
aw_gpio_get_pud(struct aw_gpio_softc * sc,uint32_t pin)455 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin)
456 {
457 uint32_t bank, offset, val;
458
459 /* Must be called with lock held. */
460 AW_GPIO_LOCK_ASSERT(sc);
461
462 bank = sc->conf->padconf->pins[pin].port;
463 pin = sc->conf->padconf->pins[pin].pin;
464 offset = ((pin & 0x0f) << 1);
465
466 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(sc, bank, pin >> 4));
467
468 return ((val >> offset) & AW_GPIO_PUD_MASK);
469 }
470
471 static void
aw_gpio_set_pud(struct aw_gpio_softc * sc,uint32_t pin,uint32_t state)472 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state)
473 {
474 uint32_t bank, offset, val;
475
476 if (aw_gpio_get_pud(sc, pin) == state)
477 return;
478
479 /* Must be called with lock held. */
480 AW_GPIO_LOCK_ASSERT(sc);
481
482 bank = sc->conf->padconf->pins[pin].port;
483 pin = sc->conf->padconf->pins[pin].pin;
484 offset = ((pin & 0x0f) << 1);
485
486 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(sc, bank, pin >> 4));
487 val &= ~(AW_GPIO_PUD_MASK << offset);
488 val |= (state << offset);
489 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(sc, bank, pin >> 4), val);
490 }
491
492 static uint32_t
aw_gpio_get_drv(struct aw_gpio_softc * sc,uint32_t pin)493 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin)
494 {
495 uint32_t bank, idx, offset, val;
496
497 /* Must be called with lock held. */
498 AW_GPIO_LOCK_ASSERT(sc);
499
500 bank = sc->conf->padconf->pins[pin].port;
501 pin = sc->conf->padconf->pins[pin].pin;
502 offset = (pin << sc->conf->drv_pin_shift) & 0x1F;
503 idx = (pin << sc->conf->drv_pin_shift) >> 5;
504
505 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(sc, bank, idx));
506
507 return ((val >> offset) & AW_GPIO_DRV_MASK);
508 }
509
510 static void
aw_gpio_set_drv(struct aw_gpio_softc * sc,uint32_t pin,uint32_t drive)511 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive)
512 {
513 uint32_t bank, idx, offset, val;
514
515 if (aw_gpio_get_drv(sc, pin) == drive)
516 return;
517
518 /* Must be called with lock held. */
519 AW_GPIO_LOCK_ASSERT(sc);
520
521 bank = sc->conf->padconf->pins[pin].port;
522 pin = sc->conf->padconf->pins[pin].pin;
523 offset = (pin << sc->conf->drv_pin_shift) & 0x1F;
524 idx = (pin << sc->conf->drv_pin_shift) >> 5;
525
526 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(sc, bank, idx));
527 val &= ~(AW_GPIO_DRV_MASK << offset);
528 val |= (drive << offset);
529 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(sc, bank, idx), val);
530 }
531
532 static int
aw_gpio_pin_configure(struct aw_gpio_softc * sc,uint32_t pin,uint32_t flags)533 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags)
534 {
535 u_int val;
536 int err = 0;
537
538 /* Must be called with lock held. */
539 AW_GPIO_LOCK_ASSERT(sc);
540
541 if (pin > sc->conf->padconf->npins)
542 return (EINVAL);
543
544 /* Manage input/output. */
545 if (flags & GPIO_PIN_INPUT) {
546 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
547 } else if ((flags & GPIO_PIN_OUTPUT) &&
548 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) {
549 if (flags & GPIO_PIN_PRESET_LOW) {
550 aw_gpio_pin_set_locked(sc, pin, 0);
551 } else if (flags & GPIO_PIN_PRESET_HIGH) {
552 aw_gpio_pin_set_locked(sc, pin, 1);
553 } else {
554 /* Read the pin and preset output to current state. */
555 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
556 if (err == 0) {
557 aw_gpio_pin_get_locked(sc, pin, &val);
558 aw_gpio_pin_set_locked(sc, pin, val);
559 }
560 }
561 if (err == 0)
562 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT);
563 }
564
565 if (err)
566 return (err);
567
568 /* Manage Pull-up/pull-down. */
569 if (flags & GPIO_PIN_PULLUP)
570 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP);
571 else if (flags & GPIO_PIN_PULLDOWN)
572 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN);
573 else
574 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE);
575
576 return (0);
577 }
578
579 static device_t
aw_gpio_get_bus(device_t dev)580 aw_gpio_get_bus(device_t dev)
581 {
582 struct aw_gpio_softc *sc;
583
584 sc = device_get_softc(dev);
585
586 return (sc->sc_busdev);
587 }
588
589 static int
aw_gpio_pin_max(device_t dev,int * maxpin)590 aw_gpio_pin_max(device_t dev, int *maxpin)
591 {
592 struct aw_gpio_softc *sc;
593
594 sc = device_get_softc(dev);
595
596 *maxpin = sc->conf->padconf->npins - 1;
597 return (0);
598 }
599
600 static int
aw_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)601 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
602 {
603 struct aw_gpio_softc *sc;
604
605 sc = device_get_softc(dev);
606 if (pin >= sc->conf->padconf->npins)
607 return (EINVAL);
608
609 *caps = AW_GPIO_DEFAULT_CAPS;
610 if (sc->conf->padconf->pins[pin].eint_func != 0)
611 *caps |= AW_GPIO_INTR_CAPS;
612
613 return (0);
614 }
615
616 static int
aw_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)617 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
618 {
619 struct aw_gpio_softc *sc;
620 uint32_t func;
621 uint32_t pud;
622
623 sc = device_get_softc(dev);
624 if (pin >= sc->conf->padconf->npins)
625 return (EINVAL);
626
627 AW_GPIO_LOCK(sc);
628 func = aw_gpio_get_function(sc, pin);
629 switch (func) {
630 case AW_GPIO_INPUT:
631 *flags = GPIO_PIN_INPUT;
632 break;
633 case AW_GPIO_OUTPUT:
634 *flags = GPIO_PIN_OUTPUT;
635 break;
636 default:
637 *flags = 0;
638 break;
639 }
640
641 pud = aw_gpio_get_pud(sc, pin);
642 switch (pud) {
643 case AW_GPIO_PULLDOWN:
644 *flags |= GPIO_PIN_PULLDOWN;
645 break;
646 case AW_GPIO_PULLUP:
647 *flags |= GPIO_PIN_PULLUP;
648 break;
649 default:
650 break;
651 }
652
653 AW_GPIO_UNLOCK(sc);
654
655 return (0);
656 }
657
658 static int
aw_gpio_pin_getname(device_t dev,uint32_t pin,char * name)659 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
660 {
661 struct aw_gpio_softc *sc;
662
663 sc = device_get_softc(dev);
664 if (pin >= sc->conf->padconf->npins)
665 return (EINVAL);
666
667 snprintf(name, GPIOMAXNAME - 1, "%s",
668 sc->conf->padconf->pins[pin].name);
669 name[GPIOMAXNAME - 1] = '\0';
670
671 return (0);
672 }
673
674 static int
aw_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)675 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
676 {
677 struct aw_gpio_softc *sc;
678 int err;
679
680 sc = device_get_softc(dev);
681 if (pin > sc->conf->padconf->npins)
682 return (EINVAL);
683
684 AW_GPIO_LOCK(sc);
685 err = aw_gpio_pin_configure(sc, pin, flags);
686 AW_GPIO_UNLOCK(sc);
687
688 return (err);
689 }
690
691 static int
aw_gpio_pin_set_locked(struct aw_gpio_softc * sc,uint32_t pin,unsigned int value)692 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin,
693 unsigned int value)
694 {
695 uint32_t bank, data;
696
697 AW_GPIO_LOCK_ASSERT(sc);
698
699 if (pin > sc->conf->padconf->npins)
700 return (EINVAL);
701
702 bank = sc->conf->padconf->pins[pin].port;
703 pin = sc->conf->padconf->pins[pin].pin;
704
705 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
706 if (value)
707 data |= (1 << pin);
708 else
709 data &= ~(1 << pin);
710 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(sc, bank), data);
711
712 return (0);
713 }
714
715 static int
aw_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)716 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
717 {
718 struct aw_gpio_softc *sc;
719 int ret;
720
721 sc = device_get_softc(dev);
722
723 AW_GPIO_LOCK(sc);
724 ret = aw_gpio_pin_set_locked(sc, pin, value);
725 AW_GPIO_UNLOCK(sc);
726
727 return (ret);
728 }
729
730 static int
aw_gpio_pin_get_locked(struct aw_gpio_softc * sc,uint32_t pin,unsigned int * val)731 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin,
732 unsigned int *val)
733 {
734 uint32_t bank, reg_data;
735 int32_t func;
736 int err;
737
738 AW_GPIO_LOCK_ASSERT(sc);
739
740 if (pin > sc->conf->padconf->npins)
741 return (EINVAL);
742
743 func = aw_gpio_get_function(sc, pin);
744 if (func == sc->conf->padconf->pins[pin].eint_func) { /* "pl_eintX */
745 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
746 if (err != 0)
747 return (err);
748 }
749
750 bank = sc->conf->padconf->pins[pin].port;
751 pin = sc->conf->padconf->pins[pin].pin;
752
753 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
754 *val = (reg_data & (1 << pin)) ? 1 : 0;
755
756 if (func == sc->conf->padconf->pins[pin].eint_func)
757 (void)aw_gpio_set_function(sc, pin, func);
758
759 return (0);
760 }
761
762 static char *
aw_gpio_parse_function(phandle_t node)763 aw_gpio_parse_function(phandle_t node)
764 {
765 char *function;
766
767 if (OF_getprop_alloc(node, "function",
768 (void **)&function) != -1)
769 return (function);
770 if (OF_getprop_alloc(node, "allwinner,function",
771 (void **)&function) != -1)
772 return (function);
773
774 return (NULL);
775 }
776
777 static const char **
aw_gpio_parse_pins(phandle_t node,int * pins_nb)778 aw_gpio_parse_pins(phandle_t node, int *pins_nb)
779 {
780 const char **pinlist;
781
782 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist);
783 if (*pins_nb > 0)
784 return (pinlist);
785
786 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins",
787 &pinlist);
788 if (*pins_nb > 0)
789 return (pinlist);
790
791 return (NULL);
792 }
793
794 static uint32_t
aw_gpio_parse_bias(phandle_t node)795 aw_gpio_parse_bias(phandle_t node)
796 {
797 uint32_t bias;
798
799 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1)
800 return (bias);
801 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1)
802 return (bias);
803 if (OF_hasprop(node, "bias-disable"))
804 return (AW_GPIO_NONE);
805 if (OF_hasprop(node, "bias-pull-up"))
806 return (AW_GPIO_PULLUP);
807 if (OF_hasprop(node, "bias-pull-down"))
808 return (AW_GPIO_PULLDOWN);
809
810 return (AW_GPIO_NONE);
811 }
812
813 static int
aw_gpio_parse_drive_strength(phandle_t node,uint32_t * drive)814 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
815 {
816 uint32_t drive_str;
817
818 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1)
819 return (0);
820 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1)
821 return (0);
822 if (OF_getencprop(node, "drive-strength", &drive_str,
823 sizeof(drive_str)) != -1) {
824 *drive = (drive_str / 10) - 1;
825 return (0);
826 }
827
828 return (1);
829 }
830
831 static int
aw_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * val)832 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
833 {
834 struct aw_gpio_softc *sc;
835 int ret;
836
837 sc = device_get_softc(dev);
838
839 AW_GPIO_LOCK(sc);
840 ret = aw_gpio_pin_get_locked(sc, pin, val);
841 AW_GPIO_UNLOCK(sc);
842
843 return (ret);
844 }
845
846 static int
aw_gpio_pin_toggle(device_t dev,uint32_t pin)847 aw_gpio_pin_toggle(device_t dev, uint32_t pin)
848 {
849 struct aw_gpio_softc *sc;
850 uint32_t bank, data;
851
852 sc = device_get_softc(dev);
853 if (pin > sc->conf->padconf->npins)
854 return (EINVAL);
855
856 bank = sc->conf->padconf->pins[pin].port;
857 pin = sc->conf->padconf->pins[pin].pin;
858
859 AW_GPIO_LOCK(sc);
860 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
861 if (data & (1 << pin))
862 data &= ~(1 << pin);
863 else
864 data |= (1 << pin);
865 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(sc, bank), data);
866 AW_GPIO_UNLOCK(sc);
867
868 return (0);
869 }
870
871 static int
aw_gpio_pin_access_32(device_t dev,uint32_t first_pin,uint32_t clear_pins,uint32_t change_pins,uint32_t * orig_pins)872 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
873 uint32_t change_pins, uint32_t *orig_pins)
874 {
875 struct aw_gpio_softc *sc;
876 uint32_t bank, data, pin;
877
878 sc = device_get_softc(dev);
879 if (first_pin > sc->conf->padconf->npins)
880 return (EINVAL);
881
882 /*
883 * We require that first_pin refers to the first pin in a bank, because
884 * this API is not about convenience, it's for making a set of pins
885 * change simultaneously (required) with reasonably high performance
886 * (desired); we need to do a read-modify-write on a single register.
887 */
888 bank = sc->conf->padconf->pins[first_pin].port;
889 pin = sc->conf->padconf->pins[first_pin].pin;
890 if (pin != 0)
891 return (EINVAL);
892
893 AW_GPIO_LOCK(sc);
894 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
895 if ((clear_pins | change_pins) != 0)
896 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(sc, bank),
897 (data & ~clear_pins) ^ change_pins);
898 AW_GPIO_UNLOCK(sc);
899
900 if (orig_pins != NULL)
901 *orig_pins = data;
902
903 return (0);
904 }
905
906 static int
aw_gpio_pin_config_32(device_t dev,uint32_t first_pin,uint32_t num_pins,uint32_t * pin_flags)907 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
908 uint32_t *pin_flags)
909 {
910 struct aw_gpio_softc *sc;
911 uint32_t pin;
912 int err;
913
914 sc = device_get_softc(dev);
915 if (first_pin > sc->conf->padconf->npins)
916 return (EINVAL);
917
918 if (sc->conf->padconf->pins[first_pin].pin != 0)
919 return (EINVAL);
920
921 /*
922 * The configuration for a bank of pins is scattered among several
923 * registers; we cannot g'tee to simultaneously change the state of all
924 * the pins in the flags array. So just loop through the array
925 * configuring each pin for now. If there was a strong need, it might
926 * be possible to support some limited simultaneous config, such as
927 * adjacent groups of 8 pins that line up the same as the config regs.
928 */
929 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
930 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
931 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]);
932 }
933
934 return (err);
935 }
936
937 static int
aw_gpio_map_gpios(device_t bus,phandle_t dev,phandle_t gparent,int gcells,pcell_t * gpios,uint32_t * pin,uint32_t * flags)938 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
939 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
940 {
941 struct aw_gpio_softc *sc;
942 int i;
943
944 sc = device_get_softc(bus);
945
946 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
947 for (i = 0; i < sc->conf->padconf->npins; i++)
948 if (sc->conf->padconf->pins[i].port == gpios[0] &&
949 sc->conf->padconf->pins[i].pin == gpios[1]) {
950 *pin = i;
951 break;
952 }
953 *flags = gpios[gcells - 1];
954
955 return (0);
956 }
957
958 static int
aw_find_pinnum_by_name(struct aw_gpio_softc * sc,const char * pinname)959 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname)
960 {
961 int i;
962
963 for (i = 0; i < sc->conf->padconf->npins; i++)
964 if (!strcmp(pinname, sc->conf->padconf->pins[i].name))
965 return i;
966
967 return (-1);
968 }
969
970 static int
aw_find_pin_func(struct aw_gpio_softc * sc,int pin,const char * func)971 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func)
972 {
973 int i;
974
975 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
976 if (sc->conf->padconf->pins[pin].functions[i] &&
977 !strcmp(func, sc->conf->padconf->pins[pin].functions[i]))
978 return (i);
979
980 return (-1);
981 }
982
983 static int
aw_fdt_configure_pins(device_t dev,phandle_t cfgxref)984 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
985 {
986 struct aw_gpio_softc *sc;
987 phandle_t node;
988 const char **pinlist = NULL;
989 char *pin_function = NULL;
990 uint32_t pin_drive, pin_pull;
991 int pins_nb, pin_num, pin_func, i, ret;
992 bool set_drive;
993
994 sc = device_get_softc(dev);
995 node = OF_node_from_xref(cfgxref);
996 ret = 0;
997 set_drive = false;
998
999 /* Getting all prop for configuring pins */
1000 pinlist = aw_gpio_parse_pins(node, &pins_nb);
1001 if (pinlist == NULL)
1002 return (ENOENT);
1003
1004 pin_function = aw_gpio_parse_function(node);
1005 if (pin_function == NULL) {
1006 ret = ENOENT;
1007 goto out;
1008 }
1009
1010 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0)
1011 set_drive = true;
1012
1013 pin_pull = aw_gpio_parse_bias(node);
1014
1015 /* Configure each pin to the correct function, drive and pull */
1016 for (i = 0; i < pins_nb; i++) {
1017 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
1018 if (pin_num == -1) {
1019 ret = ENOENT;
1020 goto out;
1021 }
1022 pin_func = aw_find_pin_func(sc, pin_num, pin_function);
1023 if (pin_func == -1) {
1024 ret = ENOENT;
1025 goto out;
1026 }
1027
1028 AW_GPIO_LOCK(sc);
1029
1030 if (aw_gpio_get_function(sc, pin_num) != pin_func)
1031 aw_gpio_set_function(sc, pin_num, pin_func);
1032 if (set_drive)
1033 aw_gpio_set_drv(sc, pin_num, pin_drive);
1034 if (pin_pull != AW_GPIO_NONE)
1035 aw_gpio_set_pud(sc, pin_num, pin_pull);
1036
1037 AW_GPIO_UNLOCK(sc);
1038 }
1039
1040 out:
1041 OF_prop_free(pinlist);
1042 OF_prop_free(pin_function);
1043 return (ret);
1044 }
1045
1046 static void
aw_gpio_enable_bank_supply(void * arg)1047 aw_gpio_enable_bank_supply(void *arg)
1048 {
1049 struct aw_gpio_softc *sc = arg;
1050 regulator_t vcc_supply;
1051 char bank_reg_name[16];
1052 int i, nbanks;
1053
1054 nbanks = strlen(sc->conf->banks);
1055 for (i = 0; i < nbanks; i++) {
1056 snprintf(bank_reg_name, sizeof(bank_reg_name), "vcc-p%c-supply",
1057 sc->conf->banks[i]);
1058
1059 if (regulator_get_by_ofw_property(sc->sc_dev, 0, bank_reg_name, &vcc_supply) == 0) {
1060 if (bootverbose)
1061 device_printf(sc->sc_dev,
1062 "Enabling regulator for gpio bank %c\n",
1063 sc->conf->banks[i]);
1064 if (regulator_enable(vcc_supply) != 0) {
1065 device_printf(sc->sc_dev,
1066 "Cannot enable regulator for bank %c\n",
1067 sc->conf->banks[i]);
1068 }
1069 }
1070 }
1071 }
1072
1073 static int
aw_gpio_probe(device_t dev)1074 aw_gpio_probe(device_t dev)
1075 {
1076
1077 if (!ofw_bus_status_okay(dev))
1078 return (ENXIO);
1079
1080 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1081 return (ENXIO);
1082
1083 device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
1084 return (BUS_PROBE_DEFAULT);
1085 }
1086
1087 static int
aw_gpio_attach(device_t dev)1088 aw_gpio_attach(device_t dev)
1089 {
1090 int error;
1091 phandle_t gpio;
1092 struct aw_gpio_softc *sc;
1093 struct clk_list *clkp, *clkp_tmp;
1094 clk_t clk;
1095 hwreset_t rst = NULL;
1096 int off, err, clkret;
1097
1098 sc = device_get_softc(dev);
1099 sc->sc_dev = dev;
1100
1101 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN);
1102
1103 if (bus_alloc_resources(dev, aw_gpio_res_spec, sc->sc_res) != 0) {
1104 device_printf(dev, "cannot allocate device resources\n");
1105 return (ENXIO);
1106 }
1107
1108 if (bus_setup_intr(dev, sc->sc_res[AW_GPIO_IRQRES],
1109 INTR_TYPE_CLK | INTR_MPSAFE, NULL, aw_gpio_intr, sc,
1110 &sc->sc_intrhand)) {
1111 device_printf(dev, "cannot setup interrupt handler\n");
1112 goto fail;
1113 }
1114
1115 /* Find our node. */
1116 gpio = ofw_bus_get_node(sc->sc_dev);
1117 if (!OF_hasprop(gpio, "gpio-controller"))
1118 /* Node is not a GPIO controller. */
1119 goto fail;
1120
1121 /* Use the right pin data for the current SoC */
1122 sc->conf = (struct aw_gpio_conf *)ofw_bus_search_compatible(dev,
1123 compat_data)->ocd_data;
1124
1125 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
1126 error = hwreset_deassert(rst);
1127 if (error != 0) {
1128 device_printf(dev, "cannot de-assert reset\n");
1129 goto fail;
1130 }
1131 }
1132
1133 TAILQ_INIT(&sc->clk_list);
1134 for (off = 0, clkret = 0; clkret == 0; off++) {
1135 clkret = clk_get_by_ofw_index(dev, 0, off, &clk);
1136 if (clkret != 0)
1137 break;
1138 err = clk_enable(clk);
1139 if (err != 0) {
1140 device_printf(dev, "Could not enable clock %s\n",
1141 clk_get_name(clk));
1142 goto fail;
1143 }
1144 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
1145 clkp->clk = clk;
1146 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
1147 }
1148 if (clkret != 0 && clkret != ENOENT) {
1149 device_printf(dev, "Could not find clock at offset %d (%d)\n",
1150 off, clkret);
1151 goto fail;
1152 }
1153
1154 aw_gpio_register_isrcs(sc);
1155 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
1156
1157 sc->sc_busdev = gpiobus_attach_bus(dev);
1158 if (sc->sc_busdev == NULL)
1159 goto fail;
1160
1161 /*
1162 * Register as a pinctrl device
1163 */
1164 fdt_pinctrl_register(dev, "pins");
1165 fdt_pinctrl_configure_tree(dev);
1166 fdt_pinctrl_register(dev, "allwinner,pins");
1167 fdt_pinctrl_configure_tree(dev);
1168
1169 config_intrhook_oneshot(aw_gpio_enable_bank_supply, sc);
1170
1171 return (0);
1172
1173 fail:
1174 if (sc->sc_irq_res)
1175 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
1176 if (sc->sc_mem_res)
1177 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
1178 mtx_destroy(&sc->sc_mtx);
1179
1180 /* Disable clock */
1181 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
1182 err = clk_disable(clkp->clk);
1183 if (err != 0)
1184 device_printf(dev, "Could not disable clock %s\n",
1185 clk_get_name(clkp->clk));
1186 err = clk_release(clkp->clk);
1187 if (err != 0)
1188 device_printf(dev, "Could not release clock %s\n",
1189 clk_get_name(clkp->clk));
1190 TAILQ_REMOVE(&sc->clk_list, clkp, next);
1191 free(clkp, M_DEVBUF);
1192 }
1193
1194 /* Assert resets */
1195 if (rst) {
1196 hwreset_assert(rst);
1197 hwreset_release(rst);
1198 }
1199
1200 return (ENXIO);
1201 }
1202
1203 static int
aw_gpio_detach(device_t dev)1204 aw_gpio_detach(device_t dev)
1205 {
1206
1207 return (EBUSY);
1208 }
1209
1210 static void
aw_gpio_intr(void * arg)1211 aw_gpio_intr(void *arg)
1212 {
1213 struct aw_gpio_softc *sc;
1214 struct intr_irqsrc *isrc;
1215 uint32_t reg;
1216 int irq;
1217
1218 sc = (struct aw_gpio_softc *)arg;
1219
1220 AW_GPIO_LOCK(sc);
1221 for (irq = 0; irq < sc->nirqs; irq++) {
1222 if (!sc->gpio_pic_irqsrc[irq].enabled)
1223 continue;
1224
1225 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank));
1226 if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum)))
1227 continue;
1228
1229 isrc = &sc->gpio_pic_irqsrc[irq].isrc;
1230 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
1231 aw_gpio_pic_disable_intr_locked(sc, isrc);
1232 aw_gpio_pic_post_filter(sc->sc_dev, isrc);
1233 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq);
1234 }
1235 }
1236 AW_GPIO_UNLOCK(sc);
1237 }
1238
1239 /*
1240 * Interrupts support
1241 */
1242
1243 static int
aw_gpio_register_isrcs(struct aw_gpio_softc * sc)1244 aw_gpio_register_isrcs(struct aw_gpio_softc *sc)
1245 {
1246 const char *name;
1247 int nirqs;
1248 int pin;
1249 int err;
1250
1251 name = device_get_nameunit(sc->sc_dev);
1252
1253 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1254 if (sc->conf->padconf->pins[pin].eint_func == 0)
1255 continue;
1256
1257 nirqs++;
1258 }
1259
1260 sc->gpio_pic_irqsrc = malloc(sizeof(*sc->gpio_pic_irqsrc) * nirqs,
1261 M_DEVBUF, M_WAITOK | M_ZERO);
1262 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1263 if (sc->conf->padconf->pins[pin].eint_func == 0)
1264 continue;
1265
1266 sc->gpio_pic_irqsrc[nirqs].pin = pin;
1267 sc->gpio_pic_irqsrc[nirqs].bank = sc->conf->padconf->pins[pin].eint_bank;
1268 sc->gpio_pic_irqsrc[nirqs].intnum = sc->conf->padconf->pins[pin].eint_num;
1269 sc->gpio_pic_irqsrc[nirqs].intfunc = sc->conf->padconf->pins[pin].eint_func;
1270 sc->gpio_pic_irqsrc[nirqs].irq = nirqs;
1271 sc->gpio_pic_irqsrc[nirqs].mode = GPIO_INTR_CONFORM;
1272
1273 err = intr_isrc_register(&sc->gpio_pic_irqsrc[nirqs].isrc,
1274 sc->sc_dev, 0, "%s,%s", name,
1275 sc->conf->padconf->pins[pin].functions[sc->conf->padconf->pins[pin].eint_func]);
1276 if (err) {
1277 device_printf(sc->sc_dev, "intr_isrs_register failed for irq %d\n", nirqs);
1278 }
1279
1280 nirqs++;
1281 }
1282
1283 sc->nirqs = nirqs;
1284
1285 return (0);
1286 }
1287
1288 static void
aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc * sc,struct intr_irqsrc * isrc)1289 aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc)
1290 {
1291 u_int irq;
1292 uint32_t reg;
1293
1294 AW_GPIO_LOCK_ASSERT(sc);
1295 irq = ((struct gpio_irqsrc *)isrc)->irq;
1296 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1297 reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum);
1298 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1299
1300 sc->gpio_pic_irqsrc[irq].enabled = false;
1301 }
1302
1303 static void
aw_gpio_pic_disable_intr(device_t dev,struct intr_irqsrc * isrc)1304 aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1305 {
1306 struct aw_gpio_softc *sc;
1307
1308 sc = device_get_softc(dev);
1309
1310 AW_GPIO_LOCK(sc);
1311 aw_gpio_pic_disable_intr_locked(sc, isrc);
1312 AW_GPIO_UNLOCK(sc);
1313 }
1314
1315 static void
aw_gpio_pic_enable_intr(device_t dev,struct intr_irqsrc * isrc)1316 aw_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1317 {
1318 struct aw_gpio_softc *sc;
1319 u_int irq;
1320 uint32_t reg;
1321
1322 sc = device_get_softc(dev);
1323 irq = ((struct gpio_irqsrc *)isrc)->irq;
1324 AW_GPIO_LOCK(sc);
1325 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1326 reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum;
1327 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1328 AW_GPIO_UNLOCK(sc);
1329
1330 sc->gpio_pic_irqsrc[irq].enabled = true;
1331 }
1332
1333 static int
aw_gpio_pic_map_gpio(struct aw_gpio_softc * sc,struct intr_map_data_gpio * dag,u_int * irqp,u_int * mode)1334 aw_gpio_pic_map_gpio(struct aw_gpio_softc *sc, struct intr_map_data_gpio *dag,
1335 u_int *irqp, u_int *mode)
1336 {
1337 u_int irq;
1338 int pin;
1339
1340 irq = dag->gpio_pin_num;
1341
1342 for (pin = 0; pin < sc->nirqs; pin++)
1343 if (sc->gpio_pic_irqsrc[pin].pin == irq)
1344 break;
1345 if (pin == sc->nirqs) {
1346 device_printf(sc->sc_dev, "Invalid interrupt number %u\n", irq);
1347 return (EINVAL);
1348 }
1349
1350 switch (dag->gpio_intr_mode) {
1351 case GPIO_INTR_LEVEL_LOW:
1352 case GPIO_INTR_LEVEL_HIGH:
1353 case GPIO_INTR_EDGE_RISING:
1354 case GPIO_INTR_EDGE_FALLING:
1355 case GPIO_INTR_EDGE_BOTH:
1356 break;
1357 default:
1358 device_printf(sc->sc_dev, "Unsupported interrupt mode 0x%8x\n",
1359 dag->gpio_intr_mode);
1360 return (EINVAL);
1361 }
1362
1363 *irqp = pin;
1364 if (mode != NULL)
1365 *mode = dag->gpio_intr_mode;
1366
1367 return (0);
1368 }
1369
1370 static int
aw_gpio_pic_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)1371 aw_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1372 struct intr_irqsrc **isrcp)
1373 {
1374 struct aw_gpio_softc *sc;
1375 u_int irq;
1376 int err;
1377
1378 sc = device_get_softc(dev);
1379 switch (data->type) {
1380 case INTR_MAP_DATA_GPIO:
1381 err = aw_gpio_pic_map_gpio(sc,
1382 (struct intr_map_data_gpio *)data,
1383 &irq, NULL);
1384 break;
1385 default:
1386 return (ENOTSUP);
1387 };
1388
1389 if (err == 0)
1390 *isrcp = &sc->gpio_pic_irqsrc[irq].isrc;
1391 return (0);
1392 }
1393
1394 static int
aw_gpio_pic_setup_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1395 aw_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1396 struct resource *res, struct intr_map_data *data)
1397 {
1398 struct aw_gpio_softc *sc;
1399 uint32_t irqcfg;
1400 uint32_t pinidx, reg;
1401 u_int irq, mode;
1402 int err;
1403
1404 sc = device_get_softc(dev);
1405
1406 err = 0;
1407 switch (data->type) {
1408 case INTR_MAP_DATA_GPIO:
1409 err = aw_gpio_pic_map_gpio(sc,
1410 (struct intr_map_data_gpio *)data,
1411 &irq, &mode);
1412 if (err != 0)
1413 return (err);
1414 break;
1415 default:
1416 return (ENOTSUP);
1417 };
1418
1419 pinidx = (sc->gpio_pic_irqsrc[irq].intnum % 8) * 4;
1420
1421 AW_GPIO_LOCK(sc);
1422 switch (mode) {
1423 case GPIO_INTR_LEVEL_LOW:
1424 irqcfg = AW_GPIO_INT_LEVEL_LOW << pinidx;
1425 break;
1426 case GPIO_INTR_LEVEL_HIGH:
1427 irqcfg = AW_GPIO_INT_LEVEL_HIGH << pinidx;
1428 break;
1429 case GPIO_INTR_EDGE_RISING:
1430 irqcfg = AW_GPIO_INT_EDGE_POSITIVE << pinidx;
1431 break;
1432 case GPIO_INTR_EDGE_FALLING:
1433 irqcfg = AW_GPIO_INT_EDGE_NEGATIVE << pinidx;
1434 break;
1435 case GPIO_INTR_EDGE_BOTH:
1436 irqcfg = AW_GPIO_INT_EDGE_BOTH << pinidx;
1437 break;
1438 }
1439
1440 /* Switch the pin to interrupt mode */
1441 sc->gpio_pic_irqsrc[irq].oldfunc = aw_gpio_get_function(sc,
1442 sc->gpio_pic_irqsrc[irq].pin);
1443 aw_gpio_set_function(sc, sc->gpio_pic_irqsrc[irq].pin,
1444 sc->gpio_pic_irqsrc[irq].intfunc);
1445
1446 /* Write interrupt mode */
1447 reg = AW_GPIO_READ(sc,
1448 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1449 sc->gpio_pic_irqsrc[irq].intnum));
1450 reg &= ~(0xF << pinidx);
1451 reg |= irqcfg;
1452 AW_GPIO_WRITE(sc,
1453 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1454 sc->gpio_pic_irqsrc[irq].intnum),
1455 reg);
1456
1457 AW_GPIO_UNLOCK(sc);
1458
1459 return (0);
1460 }
1461
1462 static int
aw_gpio_pic_teardown_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1463 aw_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1464 struct resource *res, struct intr_map_data *data)
1465 {
1466 struct aw_gpio_softc *sc;
1467 struct gpio_irqsrc *gi;
1468
1469 sc = device_get_softc(dev);
1470 gi = (struct gpio_irqsrc *)isrc;
1471
1472 /* Switch back the pin to it's original function */
1473 AW_GPIO_LOCK(sc);
1474 aw_gpio_set_function(sc, gi->pin, gi->oldfunc);
1475 AW_GPIO_UNLOCK(sc);
1476
1477 return (0);
1478 }
1479
1480 static void
aw_gpio_pic_post_filter(device_t dev,struct intr_irqsrc * isrc)1481 aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1482 {
1483 struct aw_gpio_softc *sc;
1484 struct gpio_irqsrc *gi;
1485
1486 sc = device_get_softc(dev);
1487 gi = (struct gpio_irqsrc *)isrc;
1488
1489 IRQ_MEMORY_BARRIER(0);
1490 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1491 }
1492
1493 static void
aw_gpio_pic_post_ithread(device_t dev,struct intr_irqsrc * isrc)1494 aw_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1495 {
1496 struct aw_gpio_softc *sc;
1497 struct gpio_irqsrc *gi;
1498
1499 sc = device_get_softc(dev);
1500 gi = (struct gpio_irqsrc *)isrc;
1501
1502 IRQ_MEMORY_BARRIER(0);
1503 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1504 aw_gpio_pic_enable_intr(dev, isrc);
1505 }
1506
1507 static void
aw_gpio_pic_pre_ithread(device_t dev,struct intr_irqsrc * isrc)1508 aw_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1509 {
1510 struct aw_gpio_softc *sc;
1511
1512 sc = device_get_softc(dev);
1513 aw_gpio_pic_disable_intr_locked(sc, isrc);
1514 }
1515
1516 /*
1517 * OFWBUS Interface
1518 */
1519 static phandle_t
aw_gpio_get_node(device_t dev,device_t bus)1520 aw_gpio_get_node(device_t dev, device_t bus)
1521 {
1522
1523 /* We only have one child, the GPIO bus, which needs our own node. */
1524 return (ofw_bus_get_node(dev));
1525 }
1526
1527 static device_method_t aw_gpio_methods[] = {
1528 /* Device interface */
1529 DEVMETHOD(device_probe, aw_gpio_probe),
1530 DEVMETHOD(device_attach, aw_gpio_attach),
1531 DEVMETHOD(device_detach, aw_gpio_detach),
1532
1533 /* Interrupt controller interface */
1534 DEVMETHOD(pic_disable_intr, aw_gpio_pic_disable_intr),
1535 DEVMETHOD(pic_enable_intr, aw_gpio_pic_enable_intr),
1536 DEVMETHOD(pic_map_intr, aw_gpio_pic_map_intr),
1537 DEVMETHOD(pic_setup_intr, aw_gpio_pic_setup_intr),
1538 DEVMETHOD(pic_teardown_intr, aw_gpio_pic_teardown_intr),
1539 DEVMETHOD(pic_post_filter, aw_gpio_pic_post_filter),
1540 DEVMETHOD(pic_post_ithread, aw_gpio_pic_post_ithread),
1541 DEVMETHOD(pic_pre_ithread, aw_gpio_pic_pre_ithread),
1542
1543 /* GPIO protocol */
1544 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus),
1545 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max),
1546 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname),
1547 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags),
1548 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps),
1549 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags),
1550 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get),
1551 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set),
1552 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle),
1553 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32),
1554 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32),
1555 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios),
1556
1557 /* ofw_bus interface */
1558 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node),
1559
1560 /* fdt_pinctrl interface */
1561 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
1562
1563 DEVMETHOD_END
1564 };
1565
1566 static driver_t aw_gpio_driver = {
1567 "gpio",
1568 aw_gpio_methods,
1569 sizeof(struct aw_gpio_softc),
1570 };
1571
1572 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, 0, 0,
1573 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
1574