1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/string_helpers.h>
28 #include <linux/uaccess.h>
29 #include <media/cec-notifier.h>
30
31 #include "dc.h"
32 #include "amdgpu.h"
33 #include "amdgpu_dm.h"
34 #include "amdgpu_dm_debugfs.h"
35 #include "amdgpu_dm_replay.h"
36 #include "dm_helpers.h"
37 #include "dmub/dmub_srv.h"
38 #include "resource.h"
39 #include "dsc.h"
40 #include "link_hwss.h"
41 #include "dc/dc_dmub_srv.h"
42 #include "link/protocols/link_dp_capability.h"
43 #include "inc/hw/dchubbub.h"
44
45 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
46 #include "amdgpu_dm_psr.h"
47 #endif
48
49 #define MULTIPLIER_TO_LR 270000
50 struct dmub_debugfs_trace_header {
51 uint32_t entry_count;
52 uint32_t reserved[3];
53 };
54
55 struct dmub_debugfs_trace_entry {
56 uint32_t trace_code;
57 uint32_t tick_count;
58 uint32_t param0;
59 uint32_t param1;
60 };
61
62 static const char *const mst_progress_status[] = {
63 "probe",
64 "remote_edid",
65 "allocate_new_payload",
66 "clear_allocated_payload",
67 };
68
69 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
70 *
71 * Function takes in attributes passed to debugfs write entry
72 * and writes into param array.
73 * The user passes max_param_num to identify maximum number of
74 * parameters that could be parsed.
75 *
76 */
parse_write_buffer_into_params(char * wr_buf,uint32_t wr_buf_size,long * param,const char __user * buf,int max_param_num,uint8_t * param_nums)77 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
78 long *param, const char __user *buf,
79 int max_param_num,
80 uint8_t *param_nums)
81 {
82 char *wr_buf_ptr = NULL;
83 uint32_t wr_buf_count = 0;
84 int r;
85 char *sub_str = NULL;
86 const char delimiter[3] = {' ', '\n', '\0'};
87 uint8_t param_index = 0;
88
89 *param_nums = 0;
90
91 wr_buf_ptr = wr_buf;
92
93 /* r is bytes not be copied */
94 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
95 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
96 return -EFAULT;
97 }
98
99 /* check number of parameters. isspace could not differ space and\n */
100 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
101 /* skip space*/
102 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
103 wr_buf_ptr++;
104 wr_buf_count++;
105 }
106
107 if (wr_buf_count == wr_buf_size)
108 break;
109
110 /* skip non-space*/
111 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
112 wr_buf_ptr++;
113 wr_buf_count++;
114 }
115
116 (*param_nums)++;
117
118 if (wr_buf_count == wr_buf_size)
119 break;
120 }
121
122 if (*param_nums > max_param_num)
123 *param_nums = max_param_num;
124
125 wr_buf_ptr = wr_buf; /* reset buf pointer */
126 wr_buf_count = 0; /* number of char already checked */
127
128 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
129 wr_buf_ptr++;
130 wr_buf_count++;
131 }
132
133 while (param_index < *param_nums) {
134 /* after strsep, wr_buf_ptr will be moved to after space */
135 sub_str = strsep(&wr_buf_ptr, delimiter);
136
137 r = kstrtol(sub_str, 16, &(param[param_index]));
138
139 if (r)
140 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
141
142 param_index++;
143 }
144
145 return 0;
146 }
147
148 /* function description
149 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
150 *
151 * valid lane count value: 1, 2, 4
152 * valid link rate value:
153 * 06h = 1.62Gbps per lane
154 * 0Ah = 2.7Gbps per lane
155 * 0Ch = 3.24Gbps per lane
156 * 14h = 5.4Gbps per lane
157 * 1Eh = 8.1Gbps per lane
158 *
159 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
160 *
161 * --- to get dp configuration
162 *
163 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
164 *
165 * It will list current, verified, reported, preferred dp configuration.
166 * current -- for current video mode
167 * verified --- maximum configuration which pass link training
168 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
169 * preferred --- user force settings
170 *
171 * --- set (or force) dp configuration
172 *
173 * echo <lane_count> <link_rate> > link_settings
174 *
175 * for example, to force to 2 lane, 2.7GHz,
176 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
177 *
178 * spread_spectrum could not be changed dynamically.
179 *
180 * in case invalid lane count, link rate are force, no hw programming will be
181 * done. please check link settings after force operation to see if HW get
182 * programming.
183 *
184 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
185 *
186 * check current and preferred settings.
187 *
188 */
dp_link_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)189 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
190 size_t size, loff_t *pos)
191 {
192 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
193 struct dc_link *link = connector->dc_link;
194 char *rd_buf = NULL;
195 char *rd_buf_ptr = NULL;
196 const uint32_t rd_buf_size = 100;
197 uint32_t result = 0;
198 uint8_t str_len = 0;
199 int r;
200
201 if (*pos & 3 || size & 3)
202 return -EINVAL;
203
204 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
205 if (!rd_buf)
206 return 0;
207
208 rd_buf_ptr = rd_buf;
209
210 str_len = strlen("Current: %d 0x%x %d ");
211 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ",
212 link->cur_link_settings.lane_count,
213 link->cur_link_settings.link_rate,
214 link->cur_link_settings.link_spread);
215 rd_buf_ptr += str_len;
216
217 str_len = strlen("Verified: %d 0x%x %d ");
218 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ",
219 link->verified_link_cap.lane_count,
220 link->verified_link_cap.link_rate,
221 link->verified_link_cap.link_spread);
222 rd_buf_ptr += str_len;
223
224 str_len = strlen("Reported: %d 0x%x %d ");
225 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ",
226 link->reported_link_cap.lane_count,
227 link->reported_link_cap.link_rate,
228 link->reported_link_cap.link_spread);
229 rd_buf_ptr += str_len;
230
231 str_len = strlen("Preferred: %d 0x%x %d ");
232 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n",
233 link->preferred_link_setting.lane_count,
234 link->preferred_link_setting.link_rate,
235 link->preferred_link_setting.link_spread);
236
237 while (size) {
238 if (*pos >= rd_buf_size)
239 break;
240
241 r = put_user(*(rd_buf + result), buf);
242 if (r) {
243 kfree(rd_buf);
244 return r; /* r = -EFAULT */
245 }
246
247 buf += 1;
248 size -= 1;
249 *pos += 1;
250 result += 1;
251 }
252
253 kfree(rd_buf);
254 return result;
255 }
256
dp_link_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)257 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
258 size_t size, loff_t *pos)
259 {
260 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
261 struct dc_link *link = connector->dc_link;
262 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
263 struct dc *dc = (struct dc *)link->dc;
264 struct dc_link_settings prefer_link_settings = {0};
265 char *wr_buf = NULL;
266 const uint32_t wr_buf_size = 40;
267 /* 0: lane_count; 1: link_rate */
268 int max_param_num = 2;
269 uint8_t param_nums = 0;
270 long param[2];
271 bool valid_input = true;
272
273 if (size == 0)
274 return -EINVAL;
275
276 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
277 if (!wr_buf)
278 return -ENOSPC;
279
280 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
281 (long *)param, buf,
282 max_param_num,
283 ¶m_nums)) {
284 kfree(wr_buf);
285 return -EINVAL;
286 }
287
288 if (param_nums <= 0) {
289 kfree(wr_buf);
290 DRM_DEBUG_DRIVER("user data not be read\n");
291 return -EINVAL;
292 }
293
294 switch (param[0]) {
295 case LANE_COUNT_ONE:
296 case LANE_COUNT_TWO:
297 case LANE_COUNT_FOUR:
298 break;
299 default:
300 valid_input = false;
301 break;
302 }
303
304 switch (param[1]) {
305 case LINK_RATE_LOW:
306 case LINK_RATE_RATE_2:
307 case LINK_RATE_RATE_3:
308 case LINK_RATE_HIGH:
309 case LINK_RATE_RBR2:
310 case LINK_RATE_RATE_6:
311 case LINK_RATE_HIGH2:
312 case LINK_RATE_HIGH3:
313 case LINK_RATE_UHBR10:
314 case LINK_RATE_UHBR13_5:
315 case LINK_RATE_UHBR20:
316 break;
317 default:
318 valid_input = false;
319 break;
320 }
321
322 if (!valid_input) {
323 kfree(wr_buf);
324 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
325 mutex_lock(&adev->dm.dc_lock);
326 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
327 mutex_unlock(&adev->dm.dc_lock);
328 return size;
329 }
330
331 /* save user force lane_count, link_rate to preferred settings
332 * spread spectrum will not be changed
333 */
334 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
335 prefer_link_settings.use_link_rate_set = false;
336 prefer_link_settings.lane_count = param[0];
337 prefer_link_settings.link_rate = param[1];
338
339 mutex_lock(&adev->dm.dc_lock);
340 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
341 mutex_unlock(&adev->dm.dc_lock);
342
343 kfree(wr_buf);
344 return size;
345 }
346
dp_mst_is_end_device(struct amdgpu_dm_connector * aconnector)347 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
348 {
349 bool is_end_device = false;
350 struct drm_dp_mst_topology_mgr *mgr = NULL;
351 struct drm_dp_mst_port *port = NULL;
352
353 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
354 mgr = &aconnector->mst_root->mst_mgr;
355 port = aconnector->mst_output_port;
356
357 drm_modeset_lock(&mgr->base.lock, NULL);
358 if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
359 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
360 is_end_device = true;
361 drm_modeset_unlock(&mgr->base.lock);
362 }
363
364 return is_end_device;
365 }
366
367 /* Change MST link setting
368 *
369 * valid lane count value: 1, 2, 4
370 * valid link rate value:
371 * 06h = 1.62Gbps per lane
372 * 0Ah = 2.7Gbps per lane
373 * 0Ch = 3.24Gbps per lane
374 * 14h = 5.4Gbps per lane
375 * 1Eh = 8.1Gbps per lane
376 * 3E8h = 10.0Gbps per lane
377 * 546h = 13.5Gbps per lane
378 * 7D0h = 20.0Gbps per lane
379 *
380 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
381 *
382 * for example, to force to 2 lane, 10.0GHz,
383 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
384 *
385 * Valid input will trigger hotplug event to get new link setting applied
386 * Invalid input will trigger training setting reset
387 *
388 * The usage can be referred to link_settings entry
389 *
390 */
dp_mst_link_setting(struct file * f,const char __user * buf,size_t size,loff_t * pos)391 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
392 size_t size, loff_t *pos)
393 {
394 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
395 struct dc_link *link = aconnector->dc_link;
396 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
397 struct dc *dc = (struct dc *)link->dc;
398 struct dc_link_settings prefer_link_settings = {0};
399 char *wr_buf = NULL;
400 const uint32_t wr_buf_size = 40;
401 /* 0: lane_count; 1: link_rate */
402 int max_param_num = 2;
403 uint8_t param_nums = 0;
404 long param[2];
405 bool valid_input = true;
406
407 if (!dp_mst_is_end_device(aconnector))
408 return -EINVAL;
409
410 if (size == 0)
411 return -EINVAL;
412
413 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
414 if (!wr_buf)
415 return -ENOSPC;
416
417 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
418 (long *)param, buf,
419 max_param_num,
420 ¶m_nums)) {
421 kfree(wr_buf);
422 return -EINVAL;
423 }
424
425 if (param_nums <= 0) {
426 kfree(wr_buf);
427 DRM_DEBUG_DRIVER("user data not be read\n");
428 return -EINVAL;
429 }
430
431 switch (param[0]) {
432 case LANE_COUNT_ONE:
433 case LANE_COUNT_TWO:
434 case LANE_COUNT_FOUR:
435 break;
436 default:
437 valid_input = false;
438 break;
439 }
440
441 switch (param[1]) {
442 case LINK_RATE_LOW:
443 case LINK_RATE_HIGH:
444 case LINK_RATE_RBR2:
445 case LINK_RATE_HIGH2:
446 case LINK_RATE_HIGH3:
447 case LINK_RATE_UHBR10:
448 case LINK_RATE_UHBR13_5:
449 case LINK_RATE_UHBR20:
450 break;
451 default:
452 valid_input = false;
453 break;
454 }
455
456 if (!valid_input) {
457 kfree(wr_buf);
458 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
459 mutex_lock(&adev->dm.dc_lock);
460 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
461 mutex_unlock(&adev->dm.dc_lock);
462 return -EINVAL;
463 }
464
465 /* save user force lane_count, link_rate to preferred settings
466 * spread spectrum will not be changed
467 */
468 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
469 prefer_link_settings.use_link_rate_set = false;
470 prefer_link_settings.lane_count = param[0];
471 prefer_link_settings.link_rate = param[1];
472
473 /* skip immediate retrain, and train to new link setting after hotplug event triggered */
474 mutex_lock(&adev->dm.dc_lock);
475 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
476 mutex_unlock(&adev->dm.dc_lock);
477
478 mutex_lock(&aconnector->base.dev->mode_config.mutex);
479 aconnector->base.force = DRM_FORCE_OFF;
480 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
481 drm_kms_helper_hotplug_event(aconnector->base.dev);
482
483 msleep(100);
484
485 mutex_lock(&aconnector->base.dev->mode_config.mutex);
486 aconnector->base.force = DRM_FORCE_UNSPECIFIED;
487 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
488 drm_kms_helper_hotplug_event(aconnector->base.dev);
489
490 kfree(wr_buf);
491 return size;
492 }
493
494 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
495 * post-cursor2 (defined by VESA DP specification)
496 *
497 * valid values
498 * voltage swing: 0,1,2,3
499 * pre-emphasis : 0,1,2,3
500 * post cursor2 : 0,1,2,3
501 *
502 *
503 * how to use this debugfs
504 *
505 * debugfs is located at /sys/kernel/debug/dri/0/DP-x
506 *
507 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
508 *
509 * To figure out which DP-x is the display for DP to be check,
510 * cd DP-x
511 * ls -ll
512 * There should be debugfs file, like link_settings, phy_settings.
513 * cat link_settings
514 * from lane_count, link_rate to figure which DP-x is for display to be worked
515 * on
516 *
517 * To get current DP PHY settings,
518 * cat phy_settings
519 *
520 * To change DP PHY settings,
521 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
522 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
523 * 0,
524 * echo 2 3 0 > phy_settings
525 *
526 * To check if change be applied, get current phy settings by
527 * cat phy_settings
528 *
529 * In case invalid values are set by user, like
530 * echo 1 4 0 > phy_settings
531 *
532 * HW will NOT be programmed by these settings.
533 * cat phy_settings will show the previous valid settings.
534 */
dp_phy_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)535 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
536 size_t size, loff_t *pos)
537 {
538 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
539 struct dc_link *link = connector->dc_link;
540 char *rd_buf = NULL;
541 const uint32_t rd_buf_size = 20;
542 uint32_t result = 0;
543 int r;
544
545 if (*pos & 3 || size & 3)
546 return -EINVAL;
547
548 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
549 if (!rd_buf)
550 return -EINVAL;
551
552 snprintf(rd_buf, rd_buf_size, " %d %d %d\n",
553 link->cur_lane_setting[0].VOLTAGE_SWING,
554 link->cur_lane_setting[0].PRE_EMPHASIS,
555 link->cur_lane_setting[0].POST_CURSOR2);
556
557 while (size) {
558 if (*pos >= rd_buf_size)
559 break;
560
561 r = put_user((*(rd_buf + result)), buf);
562 if (r) {
563 kfree(rd_buf);
564 return r; /* r = -EFAULT */
565 }
566
567 buf += 1;
568 size -= 1;
569 *pos += 1;
570 result += 1;
571 }
572
573 kfree(rd_buf);
574 return result;
575 }
576
dp_lttpr_status_show(struct seq_file * m,void * unused)577 static int dp_lttpr_status_show(struct seq_file *m, void *unused)
578 {
579 struct drm_connector *connector = m->private;
580 struct amdgpu_dm_connector *aconnector =
581 to_amdgpu_dm_connector(connector);
582 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
583
584 if (connector->status != connector_status_connected)
585 return -ENODEV;
586
587 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
588 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
589 caps.phy_repeater_cnt);
590
591 seq_puts(m, "phy repeater mode: ");
592
593 switch (caps.mode) {
594 case DP_PHY_REPEATER_MODE_TRANSPARENT:
595 seq_puts(m, "transparent");
596 break;
597 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
598 seq_puts(m, "non-transparent");
599 break;
600 case 0x00:
601 seq_puts(m, "non lttpr");
602 break;
603 default:
604 seq_printf(m, "read error (raw: 0x%x)", caps.mode);
605 break;
606 }
607
608 seq_puts(m, "\n");
609 return 0;
610 }
611
dp_phy_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)612 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
613 size_t size, loff_t *pos)
614 {
615 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
616 struct dc_link *link = connector->dc_link;
617 struct dc *dc = (struct dc *)link->dc;
618 char *wr_buf = NULL;
619 uint32_t wr_buf_size = 40;
620 long param[3];
621 bool use_prefer_link_setting;
622 struct link_training_settings link_lane_settings = {0};
623 int max_param_num = 3;
624 uint8_t param_nums = 0;
625 int r = 0;
626
627
628 if (size == 0)
629 return -EINVAL;
630
631 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
632 if (!wr_buf)
633 return -ENOSPC;
634
635 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
636 (long *)param, buf,
637 max_param_num,
638 ¶m_nums)) {
639 kfree(wr_buf);
640 return -EINVAL;
641 }
642
643 if (param_nums <= 0) {
644 kfree(wr_buf);
645 DRM_DEBUG_DRIVER("user data not be read\n");
646 return -EINVAL;
647 }
648
649 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
650 (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
651 (param[2] > POST_CURSOR2_MAX_LEVEL)) {
652 kfree(wr_buf);
653 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
654 return size;
655 }
656
657 /* get link settings: lane count, link rate */
658 use_prefer_link_setting =
659 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
660 (link->test_pattern_enabled));
661
662 memset(&link_lane_settings, 0, sizeof(link_lane_settings));
663
664 if (use_prefer_link_setting) {
665 link_lane_settings.link_settings.lane_count =
666 link->preferred_link_setting.lane_count;
667 link_lane_settings.link_settings.link_rate =
668 link->preferred_link_setting.link_rate;
669 link_lane_settings.link_settings.link_spread =
670 link->preferred_link_setting.link_spread;
671 } else {
672 link_lane_settings.link_settings.lane_count =
673 link->cur_link_settings.lane_count;
674 link_lane_settings.link_settings.link_rate =
675 link->cur_link_settings.link_rate;
676 link_lane_settings.link_settings.link_spread =
677 link->cur_link_settings.link_spread;
678 }
679
680 /* apply phy settings from user */
681 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
682 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
683 (enum dc_voltage_swing) (param[0]);
684 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
685 (enum dc_pre_emphasis) (param[1]);
686 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
687 (enum dc_post_cursor2) (param[2]);
688 }
689
690 /* program ASIC registers and DPCD registers */
691 dc_link_set_drive_settings(dc, &link_lane_settings, link);
692
693 kfree(wr_buf);
694 return size;
695 }
696
697 /* function description
698 *
699 * set PHY layer or Link layer test pattern
700 * PHY test pattern is used for PHY SI check.
701 * Link layer test will not affect PHY SI.
702 *
703 * Reset Test Pattern:
704 * 0 = DP_TEST_PATTERN_VIDEO_MODE
705 *
706 * PHY test pattern supported:
707 * 1 = DP_TEST_PATTERN_D102
708 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
709 * 3 = DP_TEST_PATTERN_PRBS7
710 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
711 * 5 = DP_TEST_PATTERN_CP2520_1
712 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
713 * 7 = DP_TEST_PATTERN_CP2520_3
714 *
715 * DP PHY Link Training Patterns
716 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
717 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
718 * a = DP_TEST_PATTERN_TRAINING_PATTERN3
719 * b = DP_TEST_PATTERN_TRAINING_PATTERN4
720 *
721 * DP Link Layer Test pattern
722 * c = DP_TEST_PATTERN_COLOR_SQUARES
723 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
724 * e = DP_TEST_PATTERN_VERTICAL_BARS
725 * f = DP_TEST_PATTERN_HORIZONTAL_BARS
726 * 10= DP_TEST_PATTERN_COLOR_RAMP
727 *
728 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
729 *
730 * --- set test pattern
731 * echo <test pattern #> > test_pattern
732 *
733 * If test pattern # is not supported, NO HW programming will be done.
734 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
735 * for the user pattern. input 10 bytes data are separated by space
736 *
737 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
738 *
739 * --- reset test pattern
740 * echo 0 > test_pattern
741 *
742 * --- HPD detection is disabled when set PHY test pattern
743 *
744 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
745 * is disable. User could unplug DP display from DP connected and plug scope to
746 * check test pattern PHY SI.
747 * If there is need unplug scope and plug DP display back, do steps below:
748 * echo 0 > phy_test_pattern
749 * unplug scope
750 * plug DP display.
751 *
752 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
753 * driver could detect "unplug scope" and "plug DP display"
754 */
dp_phy_test_pattern_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)755 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
756 size_t size, loff_t *pos)
757 {
758 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
759 struct dc_link *link = connector->dc_link;
760 char *wr_buf = NULL;
761 uint32_t wr_buf_size = 100;
762 long param[11] = {0x0};
763 int max_param_num = 11;
764 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
765 bool disable_hpd = false;
766 bool supports_hpd = link->irq_source_hpd != DC_IRQ_SOURCE_INVALID;
767 bool valid_test_pattern = false;
768 uint8_t param_nums = 0;
769 /* init with default 80bit custom pattern */
770 uint8_t custom_pattern[10] = {
771 0x1f, 0x7c, 0xf0, 0xc1, 0x07,
772 0x1f, 0x7c, 0xf0, 0xc1, 0x07
773 };
774 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
775 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
776 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
777 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
778 struct link_training_settings link_training_settings = {0};
779 int i;
780
781 if (size == 0)
782 return -EINVAL;
783
784 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
785 if (!wr_buf)
786 return -ENOSPC;
787
788 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
789 (long *)param, buf,
790 max_param_num,
791 ¶m_nums)) {
792 kfree(wr_buf);
793 return -EINVAL;
794 }
795
796 if (param_nums <= 0) {
797 kfree(wr_buf);
798 DRM_DEBUG_DRIVER("user data not be read\n");
799 return -EINVAL;
800 }
801
802
803 test_pattern = param[0];
804
805 switch (test_pattern) {
806 case DP_TEST_PATTERN_VIDEO_MODE:
807 case DP_TEST_PATTERN_COLOR_SQUARES:
808 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
809 case DP_TEST_PATTERN_VERTICAL_BARS:
810 case DP_TEST_PATTERN_HORIZONTAL_BARS:
811 case DP_TEST_PATTERN_COLOR_RAMP:
812 valid_test_pattern = true;
813 break;
814
815 case DP_TEST_PATTERN_D102:
816 case DP_TEST_PATTERN_SYMBOL_ERROR:
817 case DP_TEST_PATTERN_PRBS7:
818 case DP_TEST_PATTERN_80BIT_CUSTOM:
819 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
820 case DP_TEST_PATTERN_TRAINING_PATTERN4:
821 disable_hpd = true;
822 valid_test_pattern = true;
823 break;
824
825 default:
826 valid_test_pattern = false;
827 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
828 break;
829 }
830
831 if (!valid_test_pattern) {
832 kfree(wr_buf);
833 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
834 return size;
835 }
836
837 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
838 for (i = 0; i < 10; i++) {
839 if ((uint8_t) param[i + 1] != 0x0)
840 break;
841 }
842
843 if (i < 10) {
844 /* not use default value */
845 for (i = 0; i < 10; i++)
846 custom_pattern[i] = (uint8_t) param[i + 1];
847 }
848 }
849
850 /* Usage: set DP physical test pattern using debugfs with normal DP
851 * panel. Then plug out DP panel and connect a scope to measure
852 * For normal video mode and test pattern generated from CRCT,
853 * they are visibile to user. So do not disable HPD.
854 * Video Mode is also set to clear the test pattern, so enable HPD
855 * because it might have been disabled after a test pattern was set.
856 * AUX depends on HPD * sequence dependent, do not move!
857 */
858 if (supports_hpd && !disable_hpd)
859 dc_link_enable_hpd(link);
860
861 prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
862 prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
863 prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
864
865 cur_link_settings.lane_count = link->cur_link_settings.lane_count;
866 cur_link_settings.link_rate = link->cur_link_settings.link_rate;
867 cur_link_settings.link_spread = link->cur_link_settings.link_spread;
868
869 link_training_settings.link_settings = cur_link_settings;
870
871
872 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
873 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
874 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN &&
875 (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
876 prefer_link_settings.link_rate != cur_link_settings.link_rate))
877 link_training_settings.link_settings = prefer_link_settings;
878 }
879
880 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
881 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
882
883 dc_link_dp_set_test_pattern(
884 link,
885 test_pattern,
886 DP_TEST_PATTERN_COLOR_SPACE_RGB,
887 &link_training_settings,
888 custom_pattern,
889 10);
890
891 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
892 * Then plug out DP panel and connect a scope to measure DP PHY signal.
893 * Need disable interrupt to avoid SW driver disable DP output. This is
894 * done after the test pattern is set.
895 */
896 if (valid_test_pattern && supports_hpd && disable_hpd)
897 dc_link_disable_hpd(link);
898
899 kfree(wr_buf);
900
901 return size;
902 }
903
904 /*
905 * Returns the DMCUB tracebuffer contents.
906 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
907 */
dmub_tracebuffer_show(struct seq_file * m,void * data)908 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
909 {
910 struct amdgpu_device *adev = m->private;
911 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
912 struct dmub_fw_meta_info *fw_meta_info = NULL;
913 struct dmub_debugfs_trace_entry *entries;
914 uint8_t *tbuf_base;
915 uint32_t tbuf_size, max_entries, num_entries, first_entry, i;
916
917 if (!fb_info)
918 return 0;
919
920 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
921 if (!tbuf_base)
922 return 0;
923
924 if (adev->dm.dmub_srv)
925 fw_meta_info = &adev->dm.dmub_srv->meta_info;
926
927 tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size :
928 DMUB_TRACE_BUFFER_SIZE;
929 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
930 sizeof(struct dmub_debugfs_trace_entry);
931
932 num_entries =
933 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
934
935 /* DMCUB tracebuffer is a ring. If it rolled over, print a hint that
936 * entries are being overwritten.
937 */
938 if (num_entries > max_entries)
939 seq_printf(m, "...\n");
940
941 first_entry = num_entries % max_entries;
942 num_entries = min(num_entries, max_entries);
943
944 entries = (struct dmub_debugfs_trace_entry
945 *)(tbuf_base +
946 sizeof(struct dmub_debugfs_trace_header));
947
948 /* To print entries chronologically, start from the first entry till the
949 * top of buffer, then from base of buffer to first entry.
950 */
951 for (i = first_entry; i < num_entries; ++i) {
952 struct dmub_debugfs_trace_entry *entry = &entries[i];
953
954 seq_printf(m,
955 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
956 entry->trace_code, entry->tick_count, entry->param0,
957 entry->param1);
958 }
959 for (i = 0; i < first_entry; ++i) {
960 struct dmub_debugfs_trace_entry *entry = &entries[i];
961
962 seq_printf(m,
963 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
964 entry->trace_code, entry->tick_count, entry->param0,
965 entry->param1);
966 }
967
968 return 0;
969 }
970
971 /*
972 * Returns the DMCUB firmware state contents.
973 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
974 */
dmub_fw_state_show(struct seq_file * m,void * data)975 static int dmub_fw_state_show(struct seq_file *m, void *data)
976 {
977 struct amdgpu_device *adev = m->private;
978 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
979 uint8_t *state_base;
980 uint32_t state_size;
981
982 if (!fb_info)
983 return 0;
984
985 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
986 if (!state_base)
987 return 0;
988
989 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
990
991 return seq_write(m, state_base, state_size);
992 }
993
994 /* replay_capability_show() - show eDP panel replay capability
995 *
996 * The read function: replay_capability_show
997 * Shows if sink and driver has Replay capability or not.
998 *
999 * cat /sys/kernel/debug/dri/0/eDP-X/replay_capability
1000 *
1001 * Expected output:
1002 * "Sink support: no\n" - if panel doesn't support Replay
1003 * "Sink support: yes\n" - if panel supports Replay
1004 * "Driver support: no\n" - if driver doesn't support Replay
1005 * "Driver support: yes\n" - if driver supports Replay
1006 */
replay_capability_show(struct seq_file * m,void * data)1007 static int replay_capability_show(struct seq_file *m, void *data)
1008 {
1009 struct drm_connector *connector = m->private;
1010 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1011 struct dc_link *link = aconnector->dc_link;
1012 bool sink_support_replay = false;
1013 bool driver_support_replay = false;
1014
1015 if (!link)
1016 return -ENODEV;
1017
1018 if (link->type == dc_connection_none)
1019 return -ENODEV;
1020
1021 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1022 return -ENODEV;
1023
1024 /* If Replay is already set to support, skip the checks */
1025 if (link->replay_settings.config.replay_supported) {
1026 sink_support_replay = true;
1027 driver_support_replay = true;
1028 } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
1029 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1030 } else {
1031 struct dc *dc = link->ctx->dc;
1032
1033 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1034 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
1035 driver_support_replay =
1036 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
1037 }
1038
1039 seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
1040 seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay));
1041 seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported));
1042
1043 return 0;
1044 }
1045
1046 /* psr_capability_show() - show eDP panel PSR capability
1047 *
1048 * The read function: sink_psr_capability_show
1049 * Shows if sink has PSR capability or not.
1050 * If yes - the PSR version is appended
1051 *
1052 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
1053 *
1054 * Expected output:
1055 * "Sink support: no\n" - if panel doesn't support PSR
1056 * "Sink support: yes [0x01]\n" - if panel supports PSR1
1057 * "Driver support: no\n" - if driver doesn't support PSR
1058 * "Driver support: yes [0x01]\n" - if driver supports PSR1
1059 */
psr_capability_show(struct seq_file * m,void * data)1060 static int psr_capability_show(struct seq_file *m, void *data)
1061 {
1062 struct drm_connector *connector = m->private;
1063 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1064 struct dc_link *link = aconnector->dc_link;
1065
1066 if (!link)
1067 return -ENODEV;
1068
1069 if (link->type == dc_connection_none)
1070 return -ENODEV;
1071
1072 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1073 return -ENODEV;
1074
1075 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
1076 if (link->dpcd_caps.psr_info.psr_version)
1077 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
1078 seq_puts(m, "\n");
1079
1080 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
1081 if (link->psr_settings.psr_version)
1082 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
1083 seq_puts(m, "\n");
1084
1085 return 0;
1086 }
1087
1088 /*
1089 * Returns the current bpc for the crtc.
1090 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1091 */
amdgpu_current_bpc_show(struct seq_file * m,void * data)1092 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1093 {
1094 struct drm_crtc *crtc = m->private;
1095 struct drm_device *dev = crtc->dev;
1096 struct dm_crtc_state *dm_crtc_state = NULL;
1097 int res = -ENODEV;
1098 unsigned int bpc;
1099
1100 mutex_lock(&dev->mode_config.mutex);
1101 drm_modeset_lock(&crtc->mutex, NULL);
1102 if (crtc->state == NULL)
1103 goto unlock;
1104
1105 dm_crtc_state = to_dm_crtc_state(crtc->state);
1106 if (dm_crtc_state->stream == NULL)
1107 goto unlock;
1108
1109 switch (dm_crtc_state->stream->timing.display_color_depth) {
1110 case COLOR_DEPTH_666:
1111 bpc = 6;
1112 break;
1113 case COLOR_DEPTH_888:
1114 bpc = 8;
1115 break;
1116 case COLOR_DEPTH_101010:
1117 bpc = 10;
1118 break;
1119 case COLOR_DEPTH_121212:
1120 bpc = 12;
1121 break;
1122 case COLOR_DEPTH_161616:
1123 bpc = 16;
1124 break;
1125 default:
1126 goto unlock;
1127 }
1128
1129 seq_printf(m, "Current: %u\n", bpc);
1130 res = 0;
1131
1132 unlock:
1133 drm_modeset_unlock(&crtc->mutex);
1134 mutex_unlock(&dev->mode_config.mutex);
1135
1136 return res;
1137 }
1138 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1139
1140 /*
1141 * Returns the current colorspace for the crtc.
1142 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1143 */
amdgpu_current_colorspace_show(struct seq_file * m,void * data)1144 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1145 {
1146 struct drm_crtc *crtc = m->private;
1147 struct drm_device *dev = crtc->dev;
1148 struct dm_crtc_state *dm_crtc_state = NULL;
1149 int res = -ENODEV;
1150
1151 mutex_lock(&dev->mode_config.mutex);
1152 drm_modeset_lock(&crtc->mutex, NULL);
1153 if (crtc->state == NULL)
1154 goto unlock;
1155
1156 dm_crtc_state = to_dm_crtc_state(crtc->state);
1157 if (dm_crtc_state->stream == NULL)
1158 goto unlock;
1159
1160 switch (dm_crtc_state->stream->output_color_space) {
1161 case COLOR_SPACE_SRGB:
1162 seq_puts(m, "sRGB");
1163 break;
1164 case COLOR_SPACE_YCBCR601:
1165 case COLOR_SPACE_YCBCR601_LIMITED:
1166 seq_puts(m, "BT601_YCC");
1167 break;
1168 case COLOR_SPACE_YCBCR709:
1169 case COLOR_SPACE_YCBCR709_LIMITED:
1170 seq_puts(m, "BT709_YCC");
1171 break;
1172 case COLOR_SPACE_ADOBERGB:
1173 seq_puts(m, "opRGB");
1174 break;
1175 case COLOR_SPACE_2020_RGB_FULLRANGE:
1176 seq_puts(m, "BT2020_RGB");
1177 break;
1178 case COLOR_SPACE_2020_YCBCR_LIMITED:
1179 seq_puts(m, "BT2020_YCC");
1180 break;
1181 default:
1182 goto unlock;
1183 }
1184 res = 0;
1185
1186 unlock:
1187 drm_modeset_unlock(&crtc->mutex);
1188 mutex_unlock(&dev->mode_config.mutex);
1189
1190 return res;
1191 }
1192 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1193
1194
1195 /*
1196 * Example usage:
1197 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1198 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1199 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1200 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1201 */
dp_dsc_passthrough_set(struct file * f,const char __user * buf,size_t size,loff_t * pos)1202 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1203 size_t size, loff_t *pos)
1204 {
1205 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1206 char *wr_buf = NULL;
1207 uint32_t wr_buf_size = 42;
1208 int max_param_num = 1;
1209 long param;
1210 uint8_t param_nums = 0;
1211
1212 if (size == 0)
1213 return -EINVAL;
1214
1215 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1216
1217 if (!wr_buf) {
1218 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1219 return -ENOSPC;
1220 }
1221
1222 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1223 ¶m, buf,
1224 max_param_num,
1225 ¶m_nums)) {
1226 kfree(wr_buf);
1227 return -EINVAL;
1228 }
1229
1230 aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1231
1232 kfree(wr_buf);
1233 return 0;
1234 }
1235
1236 /*
1237 * Returns the HDCP capability of the Display (1.4 for now).
1238 *
1239 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1240 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1241 *
1242 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1243 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1244 */
hdcp_sink_capability_show(struct seq_file * m,void * data)1245 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1246 {
1247 struct drm_connector *connector = m->private;
1248 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1249 bool hdcp_cap, hdcp2_cap;
1250
1251 if (connector->status != connector_status_connected)
1252 return -ENODEV;
1253
1254 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
1255
1256 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1257 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1258
1259
1260 if (hdcp_cap)
1261 seq_printf(m, "%s ", "HDCP1.4");
1262 if (hdcp2_cap)
1263 seq_printf(m, "%s ", "HDCP2.2");
1264
1265 if (!hdcp_cap && !hdcp2_cap)
1266 seq_printf(m, "%s ", "None");
1267
1268 seq_puts(m, "\n");
1269
1270 return 0;
1271 }
1272
1273 /*
1274 * Returns whether the connected display is internal and not hotpluggable.
1275 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1276 */
internal_display_show(struct seq_file * m,void * data)1277 static int internal_display_show(struct seq_file *m, void *data)
1278 {
1279 struct drm_connector *connector = m->private;
1280 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1281 struct dc_link *link = aconnector->dc_link;
1282
1283 seq_printf(m, "Internal: %u\n", link->is_internal_display);
1284
1285 return 0;
1286 }
1287
1288 /*
1289 * Returns the number of segments used if ODM Combine mode is enabled.
1290 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
1291 */
odm_combine_segments_show(struct seq_file * m,void * unused)1292 static int odm_combine_segments_show(struct seq_file *m, void *unused)
1293 {
1294 struct drm_connector *connector = m->private;
1295 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1296 struct dc_link *link = aconnector->dc_link;
1297 struct pipe_ctx *pipe_ctx = NULL;
1298 int i, segments = -EOPNOTSUPP;
1299
1300 for (i = 0; i < MAX_PIPES; i++) {
1301 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
1302 if (pipe_ctx->stream &&
1303 pipe_ctx->stream->link == link)
1304 break;
1305 }
1306
1307 if (connector->status != connector_status_connected)
1308 return -ENODEV;
1309
1310 if (pipe_ctx && pipe_ctx->stream_res.tg &&
1311 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
1312 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
1313
1314 seq_printf(m, "%d\n", segments);
1315 return 0;
1316 }
1317
1318 /* function description
1319 *
1320 * generic SDP message access for testing
1321 *
1322 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1323 *
1324 * SDP header
1325 * Hb0 : Secondary-Data Packet ID
1326 * Hb1 : Secondary-Data Packet type
1327 * Hb2 : Secondary-Data-packet-specific header, Byte 0
1328 * Hb3 : Secondary-Data-packet-specific header, Byte 1
1329 *
1330 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1331 */
dp_sdp_message_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1332 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1333 size_t size, loff_t *pos)
1334 {
1335 int r;
1336 uint8_t data[36] = {0};
1337 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1338 struct dm_crtc_state *acrtc_state;
1339 uint32_t write_size = 36;
1340
1341 if (connector->base.status != connector_status_connected)
1342 return -ENODEV;
1343
1344 if (size == 0)
1345 return 0;
1346
1347 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1348
1349 r = copy_from_user(data, buf, write_size);
1350
1351 write_size -= r;
1352
1353 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1354
1355 return write_size;
1356 }
1357
1358 /* function: Read link's DSC & FEC capabilities
1359 *
1360 *
1361 * Access it with the following command (you need to specify
1362 * connector like DP-1):
1363 *
1364 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1365 *
1366 */
dp_dsc_fec_support_show(struct seq_file * m,void * data)1367 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1368 {
1369 struct drm_connector *connector = m->private;
1370 struct drm_modeset_acquire_ctx ctx;
1371 struct drm_device *dev = connector->dev;
1372 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1373 int ret = 0;
1374 bool try_again = false;
1375 bool is_fec_supported = false;
1376 bool is_dsc_supported = false;
1377 struct dpcd_caps dpcd_caps;
1378
1379 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1380 do {
1381 try_again = false;
1382 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1383 if (ret) {
1384 if (ret == -EDEADLK) {
1385 ret = drm_modeset_backoff(&ctx);
1386 if (!ret) {
1387 try_again = true;
1388 continue;
1389 }
1390 }
1391 break;
1392 }
1393 if (connector->status != connector_status_connected) {
1394 ret = -ENODEV;
1395 break;
1396 }
1397 dpcd_caps = aconnector->dc_link->dpcd_caps;
1398 if (aconnector->mst_output_port) {
1399 /* aconnector sets dsc_aux during get_modes call
1400 * if MST connector has it means it can either
1401 * enable DSC on the sink device or on MST branch
1402 * its connected to.
1403 */
1404 if (aconnector->dsc_aux) {
1405 is_fec_supported = true;
1406 is_dsc_supported = true;
1407 }
1408 } else {
1409 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1410 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1411 }
1412 } while (try_again);
1413
1414 drm_modeset_drop_locks(&ctx);
1415 drm_modeset_acquire_fini(&ctx);
1416
1417 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1418 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1419
1420 return ret;
1421 }
1422
1423 /* function: Trigger virtual HPD redetection on connector
1424 *
1425 * This function will perform link rediscovery, link disable
1426 * and enable, and dm connector state update.
1427 *
1428 * Retrigger HPD on an existing connector by echoing 1 into
1429 * its respectful "trigger_hotplug" debugfs entry:
1430 *
1431 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1432 *
1433 * This function can perform HPD unplug:
1434 *
1435 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1436 *
1437 */
trigger_hotplug(struct file * f,const char __user * buf,size_t size,loff_t * pos)1438 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1439 size_t size, loff_t *pos)
1440 {
1441 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1442 struct drm_connector *connector = &aconnector->base;
1443 struct dc_link *link = NULL;
1444 struct drm_device *dev = connector->dev;
1445 struct amdgpu_device *adev = drm_to_adev(dev);
1446 enum dc_connection_type new_connection_type = dc_connection_none;
1447 char *wr_buf = NULL;
1448 uint32_t wr_buf_size = 42;
1449 int max_param_num = 1;
1450 long param[1] = {0};
1451 uint8_t param_nums = 0;
1452 bool ret = false;
1453
1454 if (!aconnector->dc_link)
1455 return -EINVAL;
1456
1457 if (size == 0)
1458 return -EINVAL;
1459
1460 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1461
1462 if (!wr_buf) {
1463 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1464 return -ENOSPC;
1465 }
1466
1467 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1468 (long *)param, buf,
1469 max_param_num,
1470 ¶m_nums)) {
1471 kfree(wr_buf);
1472 return -EINVAL;
1473 }
1474
1475 kfree(wr_buf);
1476
1477 if (param_nums <= 0) {
1478 DRM_DEBUG_DRIVER("user data not be read\n");
1479 return -EINVAL;
1480 }
1481
1482 mutex_lock(&aconnector->hpd_lock);
1483
1484 /* Don't support for mst end device*/
1485 if (aconnector->mst_root) {
1486 mutex_unlock(&aconnector->hpd_lock);
1487 return -EINVAL;
1488 }
1489
1490 if (param[0] == 1) {
1491
1492 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1493 new_connection_type != dc_connection_none)
1494 goto unlock;
1495
1496 mutex_lock(&adev->dm.dc_lock);
1497 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1498 mutex_unlock(&adev->dm.dc_lock);
1499
1500 if (!ret)
1501 goto unlock;
1502
1503 amdgpu_dm_update_connector_after_detect(aconnector);
1504
1505 drm_modeset_lock_all(dev);
1506 dm_restore_drm_connector_state(dev, connector);
1507 drm_modeset_unlock_all(dev);
1508
1509 drm_kms_helper_connector_hotplug_event(connector);
1510 } else if (param[0] == 0) {
1511 if (!aconnector->dc_link)
1512 goto unlock;
1513
1514 link = aconnector->dc_link;
1515
1516 if (link->local_sink) {
1517 dc_sink_release(link->local_sink);
1518 link->local_sink = NULL;
1519 }
1520
1521 link->dpcd_sink_count = 0;
1522 link->type = dc_connection_none;
1523 link->dongle_max_pix_clk = 0;
1524
1525 amdgpu_dm_update_connector_after_detect(aconnector);
1526
1527 /* If the aconnector is the root node in mst topology */
1528 if (aconnector->mst_mgr.mst_state == true)
1529 dc_link_reset_cur_dp_mst_topology(link);
1530
1531 drm_modeset_lock_all(dev);
1532 dm_restore_drm_connector_state(dev, connector);
1533 drm_modeset_unlock_all(dev);
1534
1535 drm_kms_helper_connector_hotplug_event(connector);
1536 }
1537
1538 unlock:
1539 mutex_unlock(&aconnector->hpd_lock);
1540
1541 return size;
1542 }
1543
1544 /* function: read DSC status on the connector
1545 *
1546 * The read function: dp_dsc_clock_en_read
1547 * returns current status of DSC clock on the connector.
1548 * The return is a boolean flag: 1 or 0.
1549 *
1550 * Access it with the following command (you need to specify
1551 * connector like DP-1):
1552 *
1553 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1554 *
1555 * Expected output:
1556 * 1 - means that DSC is currently enabled
1557 * 0 - means that DSC is disabled
1558 */
dp_dsc_clock_en_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1559 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1560 size_t size, loff_t *pos)
1561 {
1562 char *rd_buf = NULL;
1563 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1564 struct display_stream_compressor *dsc;
1565 struct dcn_dsc_state dsc_state = {0};
1566 const uint32_t rd_buf_size = 10;
1567 struct pipe_ctx *pipe_ctx;
1568 ssize_t result = 0;
1569 int i, r, str_len = 10;
1570
1571 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1572
1573 if (!rd_buf)
1574 return -ENOMEM;
1575
1576 for (i = 0; i < MAX_PIPES; i++) {
1577 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1578 if (pipe_ctx->stream &&
1579 pipe_ctx->stream->link == aconnector->dc_link &&
1580 pipe_ctx->stream->sink &&
1581 pipe_ctx->stream->sink == aconnector->dc_sink)
1582 break;
1583 }
1584
1585 dsc = pipe_ctx->stream_res.dsc;
1586 if (dsc)
1587 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1588
1589 snprintf(rd_buf, str_len,
1590 "%d\n",
1591 dsc_state.dsc_clock_en);
1592
1593 while (size) {
1594 if (*pos >= rd_buf_size)
1595 break;
1596
1597 r = put_user(*(rd_buf + result), buf);
1598 if (r) {
1599 kfree(rd_buf);
1600 return r; /* r = -EFAULT */
1601 }
1602
1603 buf += 1;
1604 size -= 1;
1605 *pos += 1;
1606 result += 1;
1607 }
1608
1609 kfree(rd_buf);
1610 return result;
1611 }
1612
1613 /* function: write force DSC on the connector
1614 *
1615 * The write function: dp_dsc_clock_en_write
1616 * enables to force DSC on the connector.
1617 * User can write to either force enable or force disable DSC
1618 * on the next modeset or set it to driver default
1619 *
1620 * Accepted inputs:
1621 * 0 - default DSC enablement policy
1622 * 1 - force enable DSC on the connector
1623 * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1624 *
1625 * Writing DSC settings is done with the following command:
1626 * - To force enable DSC (you need to specify
1627 * connector like DP-1):
1628 *
1629 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1630 *
1631 * - To return to default state set the flag to zero and
1632 * let driver deal with DSC automatically
1633 * (you need to specify connector like DP-1):
1634 *
1635 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1636 *
1637 */
dp_dsc_clock_en_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1638 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1639 size_t size, loff_t *pos)
1640 {
1641 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1642 struct drm_connector *connector = &aconnector->base;
1643 struct drm_device *dev = connector->dev;
1644 struct drm_crtc *crtc = NULL;
1645 struct dm_crtc_state *dm_crtc_state = NULL;
1646 struct pipe_ctx *pipe_ctx;
1647 int i;
1648 char *wr_buf = NULL;
1649 uint32_t wr_buf_size = 42;
1650 int max_param_num = 1;
1651 long param[1] = {0};
1652 uint8_t param_nums = 0;
1653
1654 if (size == 0)
1655 return -EINVAL;
1656
1657 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1658
1659 if (!wr_buf) {
1660 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1661 return -ENOSPC;
1662 }
1663
1664 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1665 (long *)param, buf,
1666 max_param_num,
1667 ¶m_nums)) {
1668 kfree(wr_buf);
1669 return -EINVAL;
1670 }
1671
1672 if (param_nums <= 0) {
1673 DRM_DEBUG_DRIVER("user data not be read\n");
1674 kfree(wr_buf);
1675 return -EINVAL;
1676 }
1677
1678 for (i = 0; i < MAX_PIPES; i++) {
1679 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1680 if (pipe_ctx->stream &&
1681 pipe_ctx->stream->link == aconnector->dc_link &&
1682 pipe_ctx->stream->sink &&
1683 pipe_ctx->stream->sink == aconnector->dc_sink)
1684 break;
1685 }
1686
1687 if (!pipe_ctx->stream)
1688 goto done;
1689
1690 // Get CRTC state
1691 mutex_lock(&dev->mode_config.mutex);
1692 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1693
1694 if (connector->state == NULL)
1695 goto unlock;
1696
1697 crtc = connector->state->crtc;
1698 if (crtc == NULL)
1699 goto unlock;
1700
1701 drm_modeset_lock(&crtc->mutex, NULL);
1702 if (crtc->state == NULL)
1703 goto unlock;
1704
1705 dm_crtc_state = to_dm_crtc_state(crtc->state);
1706 if (dm_crtc_state->stream == NULL)
1707 goto unlock;
1708
1709 if (param[0] == 1)
1710 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1711 else if (param[0] == 2)
1712 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1713 else
1714 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1715
1716 dm_crtc_state->dsc_force_changed = true;
1717
1718 unlock:
1719 if (crtc)
1720 drm_modeset_unlock(&crtc->mutex);
1721 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1722 mutex_unlock(&dev->mode_config.mutex);
1723
1724 done:
1725 kfree(wr_buf);
1726 return size;
1727 }
1728
1729 /* function: read DSC slice width parameter on the connector
1730 *
1731 * The read function: dp_dsc_slice_width_read
1732 * returns dsc slice width used in the current configuration
1733 * The return is an integer: 0 or other positive number
1734 *
1735 * Access the status with the following command:
1736 *
1737 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1738 *
1739 * 0 - means that DSC is disabled
1740 *
1741 * Any other number more than zero represents the
1742 * slice width currently used by DSC in pixels
1743 *
1744 */
dp_dsc_slice_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1745 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1746 size_t size, loff_t *pos)
1747 {
1748 char *rd_buf = NULL;
1749 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1750 struct display_stream_compressor *dsc;
1751 struct dcn_dsc_state dsc_state = {0};
1752 const uint32_t rd_buf_size = 100;
1753 struct pipe_ctx *pipe_ctx;
1754 ssize_t result = 0;
1755 int i, r, str_len = 30;
1756
1757 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1758
1759 if (!rd_buf)
1760 return -ENOMEM;
1761
1762 for (i = 0; i < MAX_PIPES; i++) {
1763 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1764 if (pipe_ctx->stream &&
1765 pipe_ctx->stream->link == aconnector->dc_link &&
1766 pipe_ctx->stream->sink &&
1767 pipe_ctx->stream->sink == aconnector->dc_sink)
1768 break;
1769 }
1770
1771 dsc = pipe_ctx->stream_res.dsc;
1772 if (dsc)
1773 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1774
1775 snprintf(rd_buf, str_len,
1776 "%d\n",
1777 dsc_state.dsc_slice_width);
1778
1779 while (size) {
1780 if (*pos >= rd_buf_size)
1781 break;
1782
1783 r = put_user(*(rd_buf + result), buf);
1784 if (r) {
1785 kfree(rd_buf);
1786 return r; /* r = -EFAULT */
1787 }
1788
1789 buf += 1;
1790 size -= 1;
1791 *pos += 1;
1792 result += 1;
1793 }
1794
1795 kfree(rd_buf);
1796 return result;
1797 }
1798
1799 /* function: write DSC slice width parameter
1800 *
1801 * The write function: dp_dsc_slice_width_write
1802 * overwrites automatically generated DSC configuration
1803 * of slice width.
1804 *
1805 * The user has to write the slice width divisible by the
1806 * picture width.
1807 *
1808 * Also the user has to write width in hexidecimal
1809 * rather than in decimal.
1810 *
1811 * Writing DSC settings is done with the following command:
1812 * - To force overwrite slice width: (example sets to 1920 pixels)
1813 *
1814 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1815 *
1816 * - To stop overwriting and let driver find the optimal size,
1817 * set the width to zero:
1818 *
1819 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1820 *
1821 */
dp_dsc_slice_width_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1822 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1823 size_t size, loff_t *pos)
1824 {
1825 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1826 struct pipe_ctx *pipe_ctx;
1827 struct drm_connector *connector = &aconnector->base;
1828 struct drm_device *dev = connector->dev;
1829 struct drm_crtc *crtc = NULL;
1830 struct dm_crtc_state *dm_crtc_state = NULL;
1831 int i;
1832 char *wr_buf = NULL;
1833 uint32_t wr_buf_size = 42;
1834 int max_param_num = 1;
1835 long param[1] = {0};
1836 uint8_t param_nums = 0;
1837
1838 if (size == 0)
1839 return -EINVAL;
1840
1841 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1842
1843 if (!wr_buf) {
1844 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1845 return -ENOSPC;
1846 }
1847
1848 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1849 (long *)param, buf,
1850 max_param_num,
1851 ¶m_nums)) {
1852 kfree(wr_buf);
1853 return -EINVAL;
1854 }
1855
1856 if (param_nums <= 0) {
1857 DRM_DEBUG_DRIVER("user data not be read\n");
1858 kfree(wr_buf);
1859 return -EINVAL;
1860 }
1861
1862 for (i = 0; i < MAX_PIPES; i++) {
1863 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1864 if (pipe_ctx->stream &&
1865 pipe_ctx->stream->link == aconnector->dc_link &&
1866 pipe_ctx->stream->sink &&
1867 pipe_ctx->stream->sink == aconnector->dc_sink)
1868 break;
1869 }
1870
1871 if (!pipe_ctx->stream)
1872 goto done;
1873
1874 // Safely get CRTC state
1875 mutex_lock(&dev->mode_config.mutex);
1876 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1877
1878 if (connector->state == NULL)
1879 goto unlock;
1880
1881 crtc = connector->state->crtc;
1882 if (crtc == NULL)
1883 goto unlock;
1884
1885 drm_modeset_lock(&crtc->mutex, NULL);
1886 if (crtc->state == NULL)
1887 goto unlock;
1888
1889 dm_crtc_state = to_dm_crtc_state(crtc->state);
1890 if (dm_crtc_state->stream == NULL)
1891 goto unlock;
1892
1893 if (param[0] > 0)
1894 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1895 pipe_ctx->stream->timing.h_addressable,
1896 param[0]);
1897 else
1898 aconnector->dsc_settings.dsc_num_slices_h = 0;
1899
1900 dm_crtc_state->dsc_force_changed = true;
1901
1902 unlock:
1903 if (crtc)
1904 drm_modeset_unlock(&crtc->mutex);
1905 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1906 mutex_unlock(&dev->mode_config.mutex);
1907
1908 done:
1909 kfree(wr_buf);
1910 return size;
1911 }
1912
1913 /* function: read DSC slice height parameter on the connector
1914 *
1915 * The read function: dp_dsc_slice_height_read
1916 * returns dsc slice height used in the current configuration
1917 * The return is an integer: 0 or other positive number
1918 *
1919 * Access the status with the following command:
1920 *
1921 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1922 *
1923 * 0 - means that DSC is disabled
1924 *
1925 * Any other number more than zero represents the
1926 * slice height currently used by DSC in pixels
1927 *
1928 */
dp_dsc_slice_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1929 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1930 size_t size, loff_t *pos)
1931 {
1932 char *rd_buf = NULL;
1933 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1934 struct display_stream_compressor *dsc;
1935 struct dcn_dsc_state dsc_state = {0};
1936 const uint32_t rd_buf_size = 100;
1937 struct pipe_ctx *pipe_ctx;
1938 ssize_t result = 0;
1939 int i, r, str_len = 30;
1940
1941 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1942
1943 if (!rd_buf)
1944 return -ENOMEM;
1945
1946 for (i = 0; i < MAX_PIPES; i++) {
1947 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1948 if (pipe_ctx->stream &&
1949 pipe_ctx->stream->link == aconnector->dc_link &&
1950 pipe_ctx->stream->sink &&
1951 pipe_ctx->stream->sink == aconnector->dc_sink)
1952 break;
1953 }
1954
1955 dsc = pipe_ctx->stream_res.dsc;
1956 if (dsc)
1957 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1958
1959 snprintf(rd_buf, str_len,
1960 "%d\n",
1961 dsc_state.dsc_slice_height);
1962
1963 while (size) {
1964 if (*pos >= rd_buf_size)
1965 break;
1966
1967 r = put_user(*(rd_buf + result), buf);
1968 if (r) {
1969 kfree(rd_buf);
1970 return r; /* r = -EFAULT */
1971 }
1972
1973 buf += 1;
1974 size -= 1;
1975 *pos += 1;
1976 result += 1;
1977 }
1978
1979 kfree(rd_buf);
1980 return result;
1981 }
1982
1983 /* function: write DSC slice height parameter
1984 *
1985 * The write function: dp_dsc_slice_height_write
1986 * overwrites automatically generated DSC configuration
1987 * of slice height.
1988 *
1989 * The user has to write the slice height divisible by the
1990 * picture height.
1991 *
1992 * Also the user has to write height in hexidecimal
1993 * rather than in decimal.
1994 *
1995 * Writing DSC settings is done with the following command:
1996 * - To force overwrite slice height (example sets to 128 pixels):
1997 *
1998 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1999 *
2000 * - To stop overwriting and let driver find the optimal size,
2001 * set the height to zero:
2002 *
2003 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
2004 *
2005 */
dp_dsc_slice_height_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2006 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
2007 size_t size, loff_t *pos)
2008 {
2009 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2010 struct drm_connector *connector = &aconnector->base;
2011 struct drm_device *dev = connector->dev;
2012 struct drm_crtc *crtc = NULL;
2013 struct dm_crtc_state *dm_crtc_state = NULL;
2014 struct pipe_ctx *pipe_ctx;
2015 int i;
2016 char *wr_buf = NULL;
2017 uint32_t wr_buf_size = 42;
2018 int max_param_num = 1;
2019 uint8_t param_nums = 0;
2020 long param[1] = {0};
2021
2022 if (size == 0)
2023 return -EINVAL;
2024
2025 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2026
2027 if (!wr_buf) {
2028 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2029 return -ENOSPC;
2030 }
2031
2032 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2033 (long *)param, buf,
2034 max_param_num,
2035 ¶m_nums)) {
2036 kfree(wr_buf);
2037 return -EINVAL;
2038 }
2039
2040 if (param_nums <= 0) {
2041 DRM_DEBUG_DRIVER("user data not be read\n");
2042 kfree(wr_buf);
2043 return -EINVAL;
2044 }
2045
2046 for (i = 0; i < MAX_PIPES; i++) {
2047 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2048 if (pipe_ctx->stream &&
2049 pipe_ctx->stream->link == aconnector->dc_link &&
2050 pipe_ctx->stream->sink &&
2051 pipe_ctx->stream->sink == aconnector->dc_sink)
2052 break;
2053 }
2054
2055 if (!pipe_ctx->stream)
2056 goto done;
2057
2058 // Get CRTC state
2059 mutex_lock(&dev->mode_config.mutex);
2060 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2061
2062 if (connector->state == NULL)
2063 goto unlock;
2064
2065 crtc = connector->state->crtc;
2066 if (crtc == NULL)
2067 goto unlock;
2068
2069 drm_modeset_lock(&crtc->mutex, NULL);
2070 if (crtc->state == NULL)
2071 goto unlock;
2072
2073 dm_crtc_state = to_dm_crtc_state(crtc->state);
2074 if (dm_crtc_state->stream == NULL)
2075 goto unlock;
2076
2077 if (param[0] > 0)
2078 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
2079 pipe_ctx->stream->timing.v_addressable,
2080 param[0]);
2081 else
2082 aconnector->dsc_settings.dsc_num_slices_v = 0;
2083
2084 dm_crtc_state->dsc_force_changed = true;
2085
2086 unlock:
2087 if (crtc)
2088 drm_modeset_unlock(&crtc->mutex);
2089 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2090 mutex_unlock(&dev->mode_config.mutex);
2091
2092 done:
2093 kfree(wr_buf);
2094 return size;
2095 }
2096
2097 /* function: read DSC target rate on the connector in bits per pixel
2098 *
2099 * The read function: dp_dsc_bits_per_pixel_read
2100 * returns target rate of compression in bits per pixel
2101 * The return is an integer: 0 or other positive integer
2102 *
2103 * Access it with the following command:
2104 *
2105 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2106 *
2107 * 0 - means that DSC is disabled
2108 */
dp_dsc_bits_per_pixel_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2109 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
2110 size_t size, loff_t *pos)
2111 {
2112 char *rd_buf = NULL;
2113 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2114 struct display_stream_compressor *dsc;
2115 struct dcn_dsc_state dsc_state = {0};
2116 const uint32_t rd_buf_size = 100;
2117 struct pipe_ctx *pipe_ctx;
2118 ssize_t result = 0;
2119 int i, r, str_len = 30;
2120
2121 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2122
2123 if (!rd_buf)
2124 return -ENOMEM;
2125
2126 for (i = 0; i < MAX_PIPES; i++) {
2127 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2128 if (pipe_ctx->stream &&
2129 pipe_ctx->stream->link == aconnector->dc_link &&
2130 pipe_ctx->stream->sink &&
2131 pipe_ctx->stream->sink == aconnector->dc_sink)
2132 break;
2133 }
2134
2135 dsc = pipe_ctx->stream_res.dsc;
2136 if (dsc)
2137 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2138
2139 snprintf(rd_buf, str_len,
2140 "%d\n",
2141 dsc_state.dsc_bits_per_pixel);
2142
2143 while (size) {
2144 if (*pos >= rd_buf_size)
2145 break;
2146
2147 r = put_user(*(rd_buf + result), buf);
2148 if (r) {
2149 kfree(rd_buf);
2150 return r; /* r = -EFAULT */
2151 }
2152
2153 buf += 1;
2154 size -= 1;
2155 *pos += 1;
2156 result += 1;
2157 }
2158
2159 kfree(rd_buf);
2160 return result;
2161 }
2162
2163 /* function: write DSC target rate in bits per pixel
2164 *
2165 * The write function: dp_dsc_bits_per_pixel_write
2166 * overwrites automatically generated DSC configuration
2167 * of DSC target bit rate.
2168 *
2169 * Also the user has to write bpp in hexidecimal
2170 * rather than in decimal.
2171 *
2172 * Writing DSC settings is done with the following command:
2173 * - To force overwrite rate (example sets to 256 bpp x 1/16):
2174 *
2175 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2176 *
2177 * - To stop overwriting and let driver find the optimal rate,
2178 * set the rate to zero:
2179 *
2180 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2181 *
2182 */
dp_dsc_bits_per_pixel_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2183 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2184 size_t size, loff_t *pos)
2185 {
2186 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2187 struct drm_connector *connector = &aconnector->base;
2188 struct drm_device *dev = connector->dev;
2189 struct drm_crtc *crtc = NULL;
2190 struct dm_crtc_state *dm_crtc_state = NULL;
2191 struct pipe_ctx *pipe_ctx;
2192 int i;
2193 char *wr_buf = NULL;
2194 uint32_t wr_buf_size = 42;
2195 int max_param_num = 1;
2196 uint8_t param_nums = 0;
2197 long param[1] = {0};
2198
2199 if (size == 0)
2200 return -EINVAL;
2201
2202 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2203
2204 if (!wr_buf) {
2205 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2206 return -ENOSPC;
2207 }
2208
2209 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2210 (long *)param, buf,
2211 max_param_num,
2212 ¶m_nums)) {
2213 kfree(wr_buf);
2214 return -EINVAL;
2215 }
2216
2217 if (param_nums <= 0) {
2218 DRM_DEBUG_DRIVER("user data not be read\n");
2219 kfree(wr_buf);
2220 return -EINVAL;
2221 }
2222
2223 for (i = 0; i < MAX_PIPES; i++) {
2224 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2225 if (pipe_ctx->stream &&
2226 pipe_ctx->stream->link == aconnector->dc_link &&
2227 pipe_ctx->stream->sink &&
2228 pipe_ctx->stream->sink == aconnector->dc_sink)
2229 break;
2230 }
2231
2232 if (!pipe_ctx->stream)
2233 goto done;
2234
2235 // Get CRTC state
2236 mutex_lock(&dev->mode_config.mutex);
2237 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2238
2239 if (connector->state == NULL)
2240 goto unlock;
2241
2242 crtc = connector->state->crtc;
2243 if (crtc == NULL)
2244 goto unlock;
2245
2246 drm_modeset_lock(&crtc->mutex, NULL);
2247 if (crtc->state == NULL)
2248 goto unlock;
2249
2250 dm_crtc_state = to_dm_crtc_state(crtc->state);
2251 if (dm_crtc_state->stream == NULL)
2252 goto unlock;
2253
2254 aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2255
2256 dm_crtc_state->dsc_force_changed = true;
2257
2258 unlock:
2259 if (crtc)
2260 drm_modeset_unlock(&crtc->mutex);
2261 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2262 mutex_unlock(&dev->mode_config.mutex);
2263
2264 done:
2265 kfree(wr_buf);
2266 return size;
2267 }
2268
2269 /* function: read DSC picture width parameter on the connector
2270 *
2271 * The read function: dp_dsc_pic_width_read
2272 * returns dsc picture width used in the current configuration
2273 * It is the same as h_addressable of the current
2274 * display's timing
2275 * The return is an integer: 0 or other positive integer
2276 * If 0 then DSC is disabled.
2277 *
2278 * Access it with the following command:
2279 *
2280 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2281 *
2282 * 0 - means that DSC is disabled
2283 */
dp_dsc_pic_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2284 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2285 size_t size, loff_t *pos)
2286 {
2287 char *rd_buf = NULL;
2288 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2289 struct display_stream_compressor *dsc;
2290 struct dcn_dsc_state dsc_state = {0};
2291 const uint32_t rd_buf_size = 100;
2292 struct pipe_ctx *pipe_ctx;
2293 ssize_t result = 0;
2294 int i, r, str_len = 30;
2295
2296 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2297
2298 if (!rd_buf)
2299 return -ENOMEM;
2300
2301 for (i = 0; i < MAX_PIPES; i++) {
2302 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2303 if (pipe_ctx->stream &&
2304 pipe_ctx->stream->link == aconnector->dc_link &&
2305 pipe_ctx->stream->sink &&
2306 pipe_ctx->stream->sink == aconnector->dc_sink)
2307 break;
2308 }
2309
2310 dsc = pipe_ctx->stream_res.dsc;
2311 if (dsc)
2312 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2313
2314 snprintf(rd_buf, str_len,
2315 "%d\n",
2316 dsc_state.dsc_pic_width);
2317
2318 while (size) {
2319 if (*pos >= rd_buf_size)
2320 break;
2321
2322 r = put_user(*(rd_buf + result), buf);
2323 if (r) {
2324 kfree(rd_buf);
2325 return r; /* r = -EFAULT */
2326 }
2327
2328 buf += 1;
2329 size -= 1;
2330 *pos += 1;
2331 result += 1;
2332 }
2333
2334 kfree(rd_buf);
2335 return result;
2336 }
2337
dp_dsc_pic_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2338 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2339 size_t size, loff_t *pos)
2340 {
2341 char *rd_buf = NULL;
2342 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2343 struct display_stream_compressor *dsc;
2344 struct dcn_dsc_state dsc_state = {0};
2345 const uint32_t rd_buf_size = 100;
2346 struct pipe_ctx *pipe_ctx;
2347 ssize_t result = 0;
2348 int i, r, str_len = 30;
2349
2350 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2351
2352 if (!rd_buf)
2353 return -ENOMEM;
2354
2355 for (i = 0; i < MAX_PIPES; i++) {
2356 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2357 if (pipe_ctx->stream &&
2358 pipe_ctx->stream->link == aconnector->dc_link &&
2359 pipe_ctx->stream->sink &&
2360 pipe_ctx->stream->sink == aconnector->dc_sink)
2361 break;
2362 }
2363
2364 dsc = pipe_ctx->stream_res.dsc;
2365 if (dsc)
2366 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2367
2368 snprintf(rd_buf, str_len,
2369 "%d\n",
2370 dsc_state.dsc_pic_height);
2371
2372 while (size) {
2373 if (*pos >= rd_buf_size)
2374 break;
2375
2376 r = put_user(*(rd_buf + result), buf);
2377 if (r) {
2378 kfree(rd_buf);
2379 return r; /* r = -EFAULT */
2380 }
2381
2382 buf += 1;
2383 size -= 1;
2384 *pos += 1;
2385 result += 1;
2386 }
2387
2388 kfree(rd_buf);
2389 return result;
2390 }
2391
2392 /* function: read DSC chunk size parameter on the connector
2393 *
2394 * The read function: dp_dsc_chunk_size_read
2395 * returns dsc chunk size set in the current configuration
2396 * The value is calculated automatically by DSC code
2397 * and depends on slice parameters and bpp target rate
2398 * The return is an integer: 0 or other positive integer
2399 * If 0 then DSC is disabled.
2400 *
2401 * Access it with the following command:
2402 *
2403 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2404 *
2405 * 0 - means that DSC is disabled
2406 */
dp_dsc_chunk_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2407 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2408 size_t size, loff_t *pos)
2409 {
2410 char *rd_buf = NULL;
2411 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2412 struct display_stream_compressor *dsc;
2413 struct dcn_dsc_state dsc_state = {0};
2414 const uint32_t rd_buf_size = 100;
2415 struct pipe_ctx *pipe_ctx;
2416 ssize_t result = 0;
2417 int i, r, str_len = 30;
2418
2419 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2420
2421 if (!rd_buf)
2422 return -ENOMEM;
2423
2424 for (i = 0; i < MAX_PIPES; i++) {
2425 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2426 if (pipe_ctx->stream &&
2427 pipe_ctx->stream->link == aconnector->dc_link &&
2428 pipe_ctx->stream->sink &&
2429 pipe_ctx->stream->sink == aconnector->dc_sink)
2430 break;
2431 }
2432
2433 dsc = pipe_ctx->stream_res.dsc;
2434 if (dsc)
2435 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2436
2437 snprintf(rd_buf, str_len,
2438 "%d\n",
2439 dsc_state.dsc_chunk_size);
2440
2441 while (size) {
2442 if (*pos >= rd_buf_size)
2443 break;
2444
2445 r = put_user(*(rd_buf + result), buf);
2446 if (r) {
2447 kfree(rd_buf);
2448 return r; /* r = -EFAULT */
2449 }
2450
2451 buf += 1;
2452 size -= 1;
2453 *pos += 1;
2454 result += 1;
2455 }
2456
2457 kfree(rd_buf);
2458 return result;
2459 }
2460
2461 /* function: read DSC slice bpg offset on the connector
2462 *
2463 * The read function: dp_dsc_slice_bpg_offset_read
2464 * returns dsc bpg slice offset set in the current configuration
2465 * The value is calculated automatically by DSC code
2466 * and depends on slice parameters and bpp target rate
2467 * The return is an integer: 0 or other positive integer
2468 * If 0 then DSC is disabled.
2469 *
2470 * Access it with the following command:
2471 *
2472 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2473 *
2474 * 0 - means that DSC is disabled
2475 */
dp_dsc_slice_bpg_offset_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2476 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2477 size_t size, loff_t *pos)
2478 {
2479 char *rd_buf = NULL;
2480 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2481 struct display_stream_compressor *dsc;
2482 struct dcn_dsc_state dsc_state = {0};
2483 const uint32_t rd_buf_size = 100;
2484 struct pipe_ctx *pipe_ctx;
2485 ssize_t result = 0;
2486 int i, r, str_len = 30;
2487
2488 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2489
2490 if (!rd_buf)
2491 return -ENOMEM;
2492
2493 for (i = 0; i < MAX_PIPES; i++) {
2494 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2495 if (pipe_ctx->stream &&
2496 pipe_ctx->stream->link == aconnector->dc_link &&
2497 pipe_ctx->stream->sink &&
2498 pipe_ctx->stream->sink == aconnector->dc_sink)
2499 break;
2500 }
2501
2502 dsc = pipe_ctx->stream_res.dsc;
2503 if (dsc)
2504 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2505
2506 snprintf(rd_buf, str_len,
2507 "%d\n",
2508 dsc_state.dsc_slice_bpg_offset);
2509
2510 while (size) {
2511 if (*pos >= rd_buf_size)
2512 break;
2513
2514 r = put_user(*(rd_buf + result), buf);
2515 if (r) {
2516 kfree(rd_buf);
2517 return r; /* r = -EFAULT */
2518 }
2519
2520 buf += 1;
2521 size -= 1;
2522 *pos += 1;
2523 result += 1;
2524 }
2525
2526 kfree(rd_buf);
2527 return result;
2528 }
2529
2530
2531 /*
2532 * function description: Read max_requested_bpc property from the connector
2533 *
2534 * Access it with the following command:
2535 *
2536 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2537 *
2538 */
dp_max_bpc_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2539 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2540 size_t size, loff_t *pos)
2541 {
2542 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2543 struct drm_connector *connector = &aconnector->base;
2544 struct drm_device *dev = connector->dev;
2545 struct dm_connector_state *state;
2546 ssize_t result = 0;
2547 char *rd_buf = NULL;
2548 char *rd_buf_ptr = NULL;
2549 const uint32_t rd_buf_size = 10;
2550 int r;
2551
2552 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2553
2554 if (!rd_buf)
2555 return -ENOMEM;
2556
2557 mutex_lock(&dev->mode_config.mutex);
2558 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2559
2560 if (connector->state == NULL)
2561 goto unlock;
2562
2563 state = to_dm_connector_state(connector->state);
2564
2565 rd_buf_ptr = rd_buf;
2566 snprintf(rd_buf_ptr, rd_buf_size,
2567 "%u\n",
2568 state->base.max_requested_bpc);
2569
2570 while (size) {
2571 if (*pos >= rd_buf_size)
2572 break;
2573
2574 r = put_user(*(rd_buf + result), buf);
2575 if (r) {
2576 result = r; /* r = -EFAULT */
2577 goto unlock;
2578 }
2579 buf += 1;
2580 size -= 1;
2581 *pos += 1;
2582 result += 1;
2583 }
2584 unlock:
2585 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2586 mutex_unlock(&dev->mode_config.mutex);
2587 kfree(rd_buf);
2588 return result;
2589 }
2590
2591
2592 /*
2593 * function description: Set max_requested_bpc property on the connector
2594 *
2595 * This function will not force the input BPC on connector, it will only
2596 * change the max value. This is equivalent to setting max_bpc through
2597 * xrandr.
2598 *
2599 * The BPC value written must be >= 6 and <= 16. Values outside of this
2600 * range will result in errors.
2601 *
2602 * BPC values:
2603 * 0x6 - 6 BPC
2604 * 0x8 - 8 BPC
2605 * 0xa - 10 BPC
2606 * 0xc - 12 BPC
2607 * 0x10 - 16 BPC
2608 *
2609 * Write the max_bpc in the following way:
2610 *
2611 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2612 *
2613 */
dp_max_bpc_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2614 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2615 size_t size, loff_t *pos)
2616 {
2617 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2618 struct drm_connector *connector = &aconnector->base;
2619 struct dm_connector_state *state;
2620 struct drm_device *dev = connector->dev;
2621 char *wr_buf = NULL;
2622 uint32_t wr_buf_size = 42;
2623 int max_param_num = 1;
2624 long param[1] = {0};
2625 uint8_t param_nums = 0;
2626
2627 if (size == 0)
2628 return -EINVAL;
2629
2630 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2631
2632 if (!wr_buf) {
2633 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2634 return -ENOSPC;
2635 }
2636
2637 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2638 (long *)param, buf,
2639 max_param_num,
2640 ¶m_nums)) {
2641 kfree(wr_buf);
2642 return -EINVAL;
2643 }
2644
2645 if (param_nums <= 0) {
2646 DRM_DEBUG_DRIVER("user data not be read\n");
2647 kfree(wr_buf);
2648 return -EINVAL;
2649 }
2650
2651 if (param[0] < 6 || param[0] > 16) {
2652 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2653 kfree(wr_buf);
2654 return -EINVAL;
2655 }
2656
2657 mutex_lock(&dev->mode_config.mutex);
2658 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2659
2660 if (connector->state == NULL)
2661 goto unlock;
2662
2663 state = to_dm_connector_state(connector->state);
2664 state->base.max_requested_bpc = param[0];
2665 unlock:
2666 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2667 mutex_unlock(&dev->mode_config.mutex);
2668
2669 kfree(wr_buf);
2670 return size;
2671 }
2672
2673 /*
2674 * IPS status. Read only.
2675 *
2676 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
2677 */
ips_status_show(struct seq_file * m,void * unused)2678 static int ips_status_show(struct seq_file *m, void *unused)
2679 {
2680 struct amdgpu_device *adev = m->private;
2681 struct dc *dc = adev->dm.dc;
2682 struct dc_dmub_srv *dc_dmub_srv;
2683
2684 seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
2685 seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);
2686
2687 if (adev->dm.idle_workqueue) {
2688 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
2689 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
2690 }
2691
2692 dc_dmub_srv = dc->ctx->dmub_srv;
2693 if (dc_dmub_srv && dc_dmub_srv->dmub) {
2694 uint32_t rcg_count, ips1_count, ips2_count;
2695 volatile const struct dmub_shared_state_ips_fw *ips_fw =
2696 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
2697 rcg_count = ips_fw->rcg_entry_count;
2698 ips1_count = ips_fw->ips1_entry_count;
2699 ips2_count = ips_fw->ips2_entry_count;
2700 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n",
2701 rcg_count,
2702 ips1_count,
2703 ips2_count);
2704 rcg_count = ips_fw->rcg_exit_count;
2705 ips1_count = ips_fw->ips1_exit_count;
2706 ips2_count = ips_fw->ips2_exit_count;
2707 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u",
2708 rcg_count,
2709 ips1_count,
2710 ips2_count);
2711 seq_puts(m, "\n");
2712 }
2713 return 0;
2714 }
2715
2716 /*
2717 * IPS residency information from DMUB service. Read only.
2718 *
2719 * For time-window (segment) measurement:
2720 * 1) echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl
2721 * 2) sleep <seconds>
2722 * 3) echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl
2723 * 4) cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency
2724 */
ips_residency_show(struct seq_file * m,void * unused)2725 static int ips_residency_show(struct seq_file *m, void *unused)
2726 {
2727 struct amdgpu_device *adev = m->private;
2728 struct dc *dc = adev->dm.dc;
2729 uint8_t panel_inst = 0;
2730 enum ips_residency_mode mode;
2731 struct dmub_ips_residency_info info;
2732
2733 mutex_lock(&adev->dm.dc_lock);
2734
2735 mode = IPS_RESIDENCY__IPS1_RCG;
2736 if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) {
2737 seq_printf(m, "ISP query failed\n");
2738 } else {
2739 unsigned int pct, frac;
2740 pct = info.residency_millipercent / 1000;
2741 frac = info.residency_millipercent % 1000;
2742
2743 seq_printf(m, "IPS residency: %u.%03u%% \n", pct, frac);
2744 seq_printf(m, " entry_counter: %u\n", info.entry_counter);
2745 seq_printf(m, " total_time_us: %llu\n",
2746 (unsigned long long)info.total_time_us);
2747 seq_printf(m, " total_inactive_time_us: %llu\n",
2748 (unsigned long long)info.total_inactive_time_us);
2749 }
2750 mutex_unlock(&adev->dm.dc_lock);
2751 return 0;
2752 }
2753
ips_residency_cntl_get(void * data,u64 * val)2754 static int ips_residency_cntl_get(void *data, u64 *val)
2755 {
2756 *val = 0;
2757 return 0;
2758 }
2759
ips_residency_cntl_set(void * data,u64 val)2760 static int ips_residency_cntl_set(void *data, u64 val)
2761 {
2762 struct amdgpu_device *adev = data;
2763 struct dc *dc = adev->dm.dc;
2764 uint8_t panel_inst = 0;
2765 int ret = 0;
2766
2767 mutex_lock(&adev->dm.dc_lock);
2768 if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val))
2769 ret = -EIO;
2770 mutex_unlock(&adev->dm.dc_lock);
2771
2772 return ret;
2773 }
2774
2775 /*
2776 * Backlight at this moment. Read only.
2777 * As written to display, taking ABM and backlight lut into account.
2778 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2779 *
2780 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2781 */
current_backlight_show(struct seq_file * m,void * unused)2782 static int current_backlight_show(struct seq_file *m, void *unused)
2783 {
2784 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2785 struct dc_link *link = aconnector->dc_link;
2786 unsigned int backlight;
2787
2788 backlight = dc_link_get_backlight_level(link);
2789 seq_printf(m, "0x%x\n", backlight);
2790
2791 return 0;
2792 }
2793
2794 /*
2795 * Backlight value that is being approached. Read only.
2796 * As written to display, taking ABM and backlight lut into account.
2797 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2798 *
2799 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2800 */
target_backlight_show(struct seq_file * m,void * unused)2801 static int target_backlight_show(struct seq_file *m, void *unused)
2802 {
2803 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2804 struct dc_link *link = aconnector->dc_link;
2805 unsigned int backlight;
2806
2807 backlight = dc_link_get_target_backlight_pwm(link);
2808 seq_printf(m, "0x%x\n", backlight);
2809
2810 return 0;
2811 }
2812
2813 /*
2814 * function description: Determine if the connector is mst connector
2815 *
2816 * This function helps to determine whether a connector is a mst connector.
2817 * - "root" stands for the root connector of the topology
2818 * - "branch" stands for branch device of the topology
2819 * - "end" stands for leaf node connector of the topology
2820 * - "no" stands for the connector is not a device of a mst topology
2821 * Access it with the following command:
2822 *
2823 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2824 *
2825 */
dp_is_mst_connector_show(struct seq_file * m,void * unused)2826 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2827 {
2828 struct drm_connector *connector = m->private;
2829 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2830 struct drm_dp_mst_topology_mgr *mgr = NULL;
2831 struct drm_dp_mst_port *port = NULL;
2832 char *role = NULL;
2833
2834 mutex_lock(&aconnector->hpd_lock);
2835
2836 if (aconnector->mst_mgr.mst_state) {
2837 role = "root";
2838 } else if (aconnector->mst_root &&
2839 aconnector->mst_root->mst_mgr.mst_state) {
2840
2841 role = "end";
2842
2843 mgr = &aconnector->mst_root->mst_mgr;
2844 port = aconnector->mst_output_port;
2845
2846 drm_modeset_lock(&mgr->base.lock, NULL);
2847 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2848 port->mcs)
2849 role = "branch";
2850 drm_modeset_unlock(&mgr->base.lock);
2851
2852 } else {
2853 role = "no";
2854 }
2855
2856 seq_printf(m, "%s\n", role);
2857
2858 mutex_unlock(&aconnector->hpd_lock);
2859
2860 return 0;
2861 }
2862
2863 /*
2864 * function description: Read out the mst progress status
2865 *
2866 * This function helps to determine the mst progress status of
2867 * a mst connector.
2868 *
2869 * Access it with the following command:
2870 *
2871 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2872 *
2873 */
dp_mst_progress_status_show(struct seq_file * m,void * unused)2874 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2875 {
2876 struct drm_connector *connector = m->private;
2877 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2878 struct amdgpu_device *adev = drm_to_adev(connector->dev);
2879 int i;
2880
2881 mutex_lock(&aconnector->hpd_lock);
2882 mutex_lock(&adev->dm.dc_lock);
2883
2884 if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2885 seq_puts(m, "disabled\n");
2886 } else {
2887 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2888 seq_printf(m, "%s:%s\n",
2889 mst_progress_status[i],
2890 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2891 }
2892
2893 mutex_unlock(&adev->dm.dc_lock);
2894 mutex_unlock(&aconnector->hpd_lock);
2895
2896 return 0;
2897 }
2898
2899 /*
2900 * Reports whether the connected display is a USB4 DPIA tunneled display
2901 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2902 */
is_dpia_link_show(struct seq_file * m,void * data)2903 static int is_dpia_link_show(struct seq_file *m, void *data)
2904 {
2905 struct drm_connector *connector = m->private;
2906 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2907 struct dc_link *link = aconnector->dc_link;
2908
2909 if (connector->status != connector_status_connected)
2910 return -ENODEV;
2911
2912 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2913 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2914
2915 return 0;
2916 }
2917
2918 /**
2919 * hdmi_cec_state_show - Read out the HDMI-CEC feature status
2920 * @m: sequence file.
2921 * @data: unused.
2922 *
2923 * Return 0 on success
2924 */
hdmi_cec_state_show(struct seq_file * m,void * data)2925 static int hdmi_cec_state_show(struct seq_file *m, void *data)
2926 {
2927 struct drm_connector *connector = m->private;
2928 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2929
2930 seq_printf(m, "%s:%d\n", connector->name, connector->base.id);
2931 seq_printf(m, "HDMI-CEC status: %d\n", aconnector->notifier ? 1 : 0);
2932
2933 return 0;
2934 }
2935
2936 /**
2937 * hdmi_cec_state_write - Enable/Disable HDMI-CEC feature from driver side
2938 * @f: file structure.
2939 * @buf: userspace buffer. set to '1' to enable; '0' to disable cec feature.
2940 * @size: size of buffer from userpsace.
2941 * @pos: unused.
2942 *
2943 * Return size on success, error code on failure
2944 */
hdmi_cec_state_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2945 static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf,
2946 size_t size, loff_t *pos)
2947 {
2948 int ret;
2949 bool enable;
2950 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2951 struct drm_device *ddev = aconnector->base.dev;
2952
2953 if (size == 0)
2954 return -EINVAL;
2955
2956 ret = kstrtobool_from_user(buf, size, &enable);
2957 if (ret) {
2958 drm_dbg_driver(ddev, "invalid user data !\n");
2959 return ret;
2960 }
2961
2962 if (enable) {
2963 if (aconnector->notifier)
2964 return -EINVAL;
2965 ret = amdgpu_dm_initialize_hdmi_connector(aconnector);
2966 if (ret)
2967 return ret;
2968 hdmi_cec_set_edid(aconnector);
2969 } else {
2970 if (!aconnector->notifier)
2971 return -EINVAL;
2972 cec_notifier_conn_unregister(aconnector->notifier);
2973 aconnector->notifier = NULL;
2974 }
2975
2976 return size;
2977 }
2978
2979 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2980 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2981 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2982 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2983 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2984 DEFINE_SHOW_ATTRIBUTE(internal_display);
2985 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
2986 DEFINE_SHOW_ATTRIBUTE(replay_capability);
2987 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2988 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2989 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2990 DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2991 DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state);
2992
2993 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2994 .owner = THIS_MODULE,
2995 .read = dp_dsc_clock_en_read,
2996 .write = dp_dsc_clock_en_write,
2997 .llseek = default_llseek
2998 };
2999
3000 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
3001 .owner = THIS_MODULE,
3002 .read = dp_dsc_slice_width_read,
3003 .write = dp_dsc_slice_width_write,
3004 .llseek = default_llseek
3005 };
3006
3007 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
3008 .owner = THIS_MODULE,
3009 .read = dp_dsc_slice_height_read,
3010 .write = dp_dsc_slice_height_write,
3011 .llseek = default_llseek
3012 };
3013
3014 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
3015 .owner = THIS_MODULE,
3016 .read = dp_dsc_bits_per_pixel_read,
3017 .write = dp_dsc_bits_per_pixel_write,
3018 .llseek = default_llseek
3019 };
3020
3021 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
3022 .owner = THIS_MODULE,
3023 .read = dp_dsc_pic_width_read,
3024 .llseek = default_llseek
3025 };
3026
3027 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
3028 .owner = THIS_MODULE,
3029 .read = dp_dsc_pic_height_read,
3030 .llseek = default_llseek
3031 };
3032
3033 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
3034 .owner = THIS_MODULE,
3035 .read = dp_dsc_chunk_size_read,
3036 .llseek = default_llseek
3037 };
3038
3039 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
3040 .owner = THIS_MODULE,
3041 .read = dp_dsc_slice_bpg_offset_read,
3042 .llseek = default_llseek
3043 };
3044
3045 static const struct file_operations trigger_hotplug_debugfs_fops = {
3046 .owner = THIS_MODULE,
3047 .write = trigger_hotplug,
3048 .llseek = default_llseek
3049 };
3050
3051 static const struct file_operations dp_link_settings_debugfs_fops = {
3052 .owner = THIS_MODULE,
3053 .read = dp_link_settings_read,
3054 .write = dp_link_settings_write,
3055 .llseek = default_llseek
3056 };
3057
3058 static const struct file_operations dp_phy_settings_debugfs_fop = {
3059 .owner = THIS_MODULE,
3060 .read = dp_phy_settings_read,
3061 .write = dp_phy_settings_write,
3062 .llseek = default_llseek
3063 };
3064
3065 static const struct file_operations dp_phy_test_pattern_fops = {
3066 .owner = THIS_MODULE,
3067 .write = dp_phy_test_pattern_debugfs_write,
3068 .llseek = default_llseek
3069 };
3070
3071 static const struct file_operations sdp_message_fops = {
3072 .owner = THIS_MODULE,
3073 .write = dp_sdp_message_debugfs_write,
3074 .llseek = default_llseek
3075 };
3076
3077 static const struct file_operations dp_max_bpc_debugfs_fops = {
3078 .owner = THIS_MODULE,
3079 .read = dp_max_bpc_read,
3080 .write = dp_max_bpc_write,
3081 .llseek = default_llseek
3082 };
3083
3084 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
3085 .owner = THIS_MODULE,
3086 .write = dp_dsc_passthrough_set,
3087 .llseek = default_llseek
3088 };
3089
3090 static const struct file_operations dp_mst_link_settings_debugfs_fops = {
3091 .owner = THIS_MODULE,
3092 .write = dp_mst_link_setting,
3093 .llseek = default_llseek
3094 };
3095
3096 static const struct {
3097 char *name;
3098 const struct file_operations *fops;
3099 } dp_debugfs_entries[] = {
3100 {"link_settings", &dp_link_settings_debugfs_fops},
3101 {"phy_settings", &dp_phy_settings_debugfs_fop},
3102 {"lttpr_status", &dp_lttpr_status_fops},
3103 {"test_pattern", &dp_phy_test_pattern_fops},
3104 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3105 {"sdp_message", &sdp_message_fops},
3106 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
3107 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
3108 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
3109 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
3110 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
3111 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
3112 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
3113 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
3114 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
3115 {"max_bpc", &dp_max_bpc_debugfs_fops},
3116 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
3117 {"is_mst_connector", &dp_is_mst_connector_fops},
3118 {"mst_progress_status", &dp_mst_progress_status_fops},
3119 {"is_dpia_link", &is_dpia_link_fops},
3120 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
3121 };
3122
3123 static const struct {
3124 char *name;
3125 const struct file_operations *fops;
3126 } hdmi_debugfs_entries[] = {
3127 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3128 {"hdmi_cec_state", &hdmi_cec_state_fops}
3129 };
3130
3131 /*
3132 * Force YUV420 output if available from the given mode
3133 */
force_yuv420_output_set(void * data,u64 val)3134 static int force_yuv420_output_set(void *data, u64 val)
3135 {
3136 struct amdgpu_dm_connector *connector = data;
3137
3138 connector->force_yuv420_output = (bool)val;
3139
3140 return 0;
3141 }
3142
3143 /*
3144 * Check if YUV420 is forced when available from the given mode
3145 */
force_yuv420_output_get(void * data,u64 * val)3146 static int force_yuv420_output_get(void *data, u64 *val)
3147 {
3148 struct amdgpu_dm_connector *connector = data;
3149
3150 *val = connector->force_yuv420_output;
3151
3152 return 0;
3153 }
3154
3155 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
3156 force_yuv420_output_set, "%llu\n");
3157
3158 /*
3159 * Read Replay state
3160 */
replay_get_state(void * data,u64 * val)3161 static int replay_get_state(void *data, u64 *val)
3162 {
3163 struct amdgpu_dm_connector *connector = data;
3164 struct dc_link *link = connector->dc_link;
3165 uint64_t state = REPLAY_STATE_INVALID;
3166
3167 dc_link_get_replay_state(link, &state);
3168
3169 *val = state;
3170
3171 return 0;
3172 }
3173
3174 /*
3175 * Start / Stop capture Replay residency
3176 */
replay_set_residency(void * data,u64 val)3177 static int replay_set_residency(void *data, u64 val)
3178 {
3179 struct amdgpu_dm_connector *connector = data;
3180 struct dc_link *link = connector->dc_link;
3181 bool is_start = (val != 0);
3182 u32 residency = 0;
3183
3184 link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
3185 return 0;
3186 }
3187
3188 /*
3189 * Read Replay residency
3190 */
replay_get_residency(void * data,u64 * val)3191 static int replay_get_residency(void *data, u64 *val)
3192 {
3193 struct amdgpu_dm_connector *connector = data;
3194 struct dc_link *link = connector->dc_link;
3195 u32 residency = 0;
3196
3197 link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
3198 *val = (u64)residency;
3199
3200 return 0;
3201 }
3202
3203 /*
3204 * Read PSR state
3205 */
psr_get(void * data,u64 * val)3206 static int psr_get(void *data, u64 *val)
3207 {
3208 struct amdgpu_dm_connector *connector = data;
3209 struct dc_link *link = connector->dc_link;
3210 enum dc_psr_state state = PSR_STATE0;
3211
3212 dc_link_get_psr_state(link, &state);
3213
3214 *val = state;
3215
3216 return 0;
3217 }
3218
3219 /*
3220 * Read PSR state residency
3221 */
psr_read_residency(void * data,u64 * val)3222 static int psr_read_residency(void *data, u64 *val)
3223 {
3224 struct amdgpu_dm_connector *connector = data;
3225 struct dc_link *link = connector->dc_link;
3226 u32 residency = 0;
3227
3228 link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
3229
3230 *val = (u64)residency;
3231
3232 return 0;
3233 }
3234
3235 /* read allow_edp_hotplug_detection */
allow_edp_hotplug_detection_get(void * data,u64 * val)3236 static int allow_edp_hotplug_detection_get(void *data, u64 *val)
3237 {
3238 struct amdgpu_dm_connector *aconnector = data;
3239 struct drm_connector *connector = &aconnector->base;
3240 struct drm_device *dev = connector->dev;
3241 struct amdgpu_device *adev = drm_to_adev(dev);
3242
3243 *val = adev->dm.dc->config.allow_edp_hotplug_detection;
3244
3245 return 0;
3246 }
3247
3248 /* set allow_edp_hotplug_detection */
allow_edp_hotplug_detection_set(void * data,u64 val)3249 static int allow_edp_hotplug_detection_set(void *data, u64 val)
3250 {
3251 struct amdgpu_dm_connector *aconnector = data;
3252 struct drm_connector *connector = &aconnector->base;
3253 struct drm_device *dev = connector->dev;
3254 struct amdgpu_device *adev = drm_to_adev(dev);
3255
3256 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
3257
3258 return 0;
3259 }
3260
3261 /* check if kernel disallow eDP enter psr state
3262 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3263 * 0: allow edp enter psr; 1: disallow
3264 */
disallow_edp_enter_psr_get(void * data,u64 * val)3265 static int disallow_edp_enter_psr_get(void *data, u64 *val)
3266 {
3267 struct amdgpu_dm_connector *aconnector = data;
3268
3269 *val = (u64) aconnector->disallow_edp_enter_psr;
3270 return 0;
3271 }
3272
3273 /* set kernel disallow eDP enter psr state
3274 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3275 * 0: allow edp enter psr; 1: disallow
3276 *
3277 * usage: test app read crc from PSR eDP rx.
3278 *
3279 * during kernel boot up, kernel write dpcd 0x170 = 5.
3280 * this notify eDP rx psr enable and let rx check crc.
3281 * rx fw will start checking crc for rx internal logic.
3282 * crc read count within dpcd 0x246 is not updated and
3283 * value is 0. when eDP tx driver wants to read rx crc
3284 * from dpcd 0x246, 0x270, read count 0 lead tx driver
3285 * timeout.
3286 *
3287 * to avoid this, we add this debugfs to let test app to disbable
3288 * rx crc checking for rx internal logic. then test app can read
3289 * non-zero crc read count.
3290 *
3291 * expected app sequence is as below:
3292 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3293 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3294 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3295 * without dpcd 0x170 = 5.
3296 * 4. read crc from rx dpcd 0x270, 0x246, etc.
3297 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
3298 * this will let eDP back to normal with psr setup dpcd 0x170 = 5.
3299 */
disallow_edp_enter_psr_set(void * data,u64 val)3300 static int disallow_edp_enter_psr_set(void *data, u64 val)
3301 {
3302 struct amdgpu_dm_connector *aconnector = data;
3303
3304 aconnector->disallow_edp_enter_psr = val ? true : false;
3305 return 0;
3306 }
3307
dmub_trace_mask_set(void * data,u64 val)3308 static int dmub_trace_mask_set(void *data, u64 val)
3309 {
3310 struct amdgpu_device *adev = data;
3311 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3312 enum dmub_gpint_command cmd;
3313 u64 mask = 0xffff;
3314 u8 shift = 0;
3315 u32 res;
3316 int i;
3317
3318 if (!srv->fw_version)
3319 return -EINVAL;
3320
3321 for (i = 0; i < 4; i++) {
3322 res = (val & mask) >> shift;
3323
3324 switch (i) {
3325 case 0:
3326 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;
3327 break;
3328 case 1:
3329 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;
3330 break;
3331 case 2:
3332 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;
3333 break;
3334 case 3:
3335 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;
3336 break;
3337 }
3338
3339 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
3340 return -EIO;
3341
3342 usleep_range(100, 1000);
3343
3344 mask <<= 16;
3345 shift += 16;
3346 }
3347
3348 return 0;
3349 }
3350
dmub_trace_mask_show(void * data,u64 * val)3351 static int dmub_trace_mask_show(void *data, u64 *val)
3352 {
3353 enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;
3354 struct amdgpu_device *adev = data;
3355 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3356 u8 shift = 0;
3357 u64 raw = 0;
3358 u64 res = 0;
3359 int i = 0;
3360
3361 if (!srv->fw_version)
3362 return -EINVAL;
3363
3364 while (i < 4) {
3365 uint32_t response;
3366
3367 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
3368 return -EIO;
3369
3370 raw = response;
3371 usleep_range(100, 1000);
3372
3373 cmd++;
3374 res |= (raw << shift);
3375 shift += 16;
3376 i++;
3377 }
3378
3379 *val = res;
3380
3381 return 0;
3382 }
3383
3384 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,
3385 dmub_trace_mask_set, "0x%llx\n");
3386
3387 /*
3388 * Set dmcub trace event IRQ enable or disable.
3389 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3390 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3391 */
dmcub_trace_event_state_set(void * data,u64 val)3392 static int dmcub_trace_event_state_set(void *data, u64 val)
3393 {
3394 struct amdgpu_device *adev = data;
3395
3396 if (val == 1 || val == 0) {
3397 dc_dmub_trace_event_control(adev->dm.dc, val);
3398 adev->dm.dmcub_trace_event_en = (bool)val;
3399 } else
3400 return 0;
3401
3402 return 0;
3403 }
3404
3405 /*
3406 * The interface doesn't need get function, so it will return the
3407 * value of zero
3408 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3409 */
dmcub_trace_event_state_get(void * data,u64 * val)3410 static int dmcub_trace_event_state_get(void *data, u64 *val)
3411 {
3412 struct amdgpu_device *adev = data;
3413
3414 *val = adev->dm.dmcub_trace_event_en;
3415 return 0;
3416 }
3417
3418 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
3419 dmcub_trace_event_state_set, "%llu\n");
3420
3421 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n");
3422 DEFINE_DEBUGFS_ATTRIBUTE(replay_residency_fops, replay_get_residency, replay_set_residency,
3423 "%llu\n");
3424 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
3425 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
3426 "%llu\n");
3427
3428 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
3429 allow_edp_hotplug_detection_get,
3430 allow_edp_hotplug_detection_set, "%llu\n");
3431
3432 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
3433 disallow_edp_enter_psr_get,
3434 disallow_edp_enter_psr_set, "%llu\n");
3435
3436 DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get,
3437 ips_residency_cntl_set, "%llu\n");
3438 DEFINE_SHOW_ATTRIBUTE(current_backlight);
3439 DEFINE_SHOW_ATTRIBUTE(target_backlight);
3440 DEFINE_SHOW_ATTRIBUTE(ips_status);
3441 DEFINE_SHOW_ATTRIBUTE(ips_residency);
3442
3443 static const struct {
3444 char *name;
3445 const struct file_operations *fops;
3446 } connector_debugfs_entries[] = {
3447 {"force_yuv420_output", &force_yuv420_output_fops},
3448 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
3449 {"internal_display", &internal_display_fops},
3450 {"odm_combine_segments", &odm_combine_segments_fops}
3451 };
3452
3453 /*
3454 * Returns supported customized link rates by this eDP panel.
3455 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3456 */
edp_ilr_show(struct seq_file * m,void * unused)3457 static int edp_ilr_show(struct seq_file *m, void *unused)
3458 {
3459 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3460 struct dc_link *link = aconnector->dc_link;
3461 uint8_t supported_link_rates[16];
3462 uint32_t link_rate_in_khz;
3463 uint32_t entry = 0;
3464 uint8_t dpcd_rev;
3465
3466 memset(supported_link_rates, 0, sizeof(supported_link_rates));
3467 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3468 supported_link_rates, sizeof(supported_link_rates));
3469
3470 dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3471
3472 if (dpcd_rev >= DP_DPCD_REV_13 &&
3473 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3474
3475 for (entry = 0; entry < 16; entry += 2) {
3476 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3477 supported_link_rates[entry]) * 200;
3478 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3479 }
3480 } else {
3481 seq_puts(m, "ILR is not supported by this eDP panel.\n");
3482 }
3483
3484 return 0;
3485 }
3486
3487 /*
3488 * Set supported customized link rate to eDP panel.
3489 *
3490 * echo <lane_count> <link_rate option> > ilr_setting
3491 *
3492 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3493 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3494 * to set 4 lanes and 2.16 GHz
3495 */
edp_ilr_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)3496 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3497 size_t size, loff_t *pos)
3498 {
3499 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3500 struct dc_link *link = connector->dc_link;
3501 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3502 struct dc *dc = (struct dc *)link->dc;
3503 struct dc_link_settings prefer_link_settings;
3504 char *wr_buf = NULL;
3505 const uint32_t wr_buf_size = 40;
3506 /* 0: lane_count; 1: link_rate */
3507 int max_param_num = 2;
3508 uint8_t param_nums = 0;
3509 long param[2];
3510 bool valid_input = true;
3511 uint8_t supported_link_rates[16] = {0};
3512 uint32_t entry = 0;
3513 uint32_t link_rate_in_khz = 0;
3514 uint8_t dpcd_rev = 0;
3515
3516 if (size == 0)
3517 return -EINVAL;
3518
3519 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3520 if (!wr_buf)
3521 return -ENOMEM;
3522
3523 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3524 (long *)param, buf,
3525 max_param_num,
3526 ¶m_nums)) {
3527 kfree(wr_buf);
3528 return -EINVAL;
3529 }
3530
3531 if (param_nums <= 0) {
3532 kfree(wr_buf);
3533 return -EINVAL;
3534 }
3535
3536 switch (param[0]) {
3537 case LANE_COUNT_ONE:
3538 case LANE_COUNT_TWO:
3539 case LANE_COUNT_FOUR:
3540 break;
3541 default:
3542 valid_input = false;
3543 break;
3544 }
3545
3546 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3547 valid_input = false;
3548
3549 if (!valid_input) {
3550 kfree(wr_buf);
3551 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3552 prefer_link_settings.use_link_rate_set = false;
3553 mutex_lock(&adev->dm.dc_lock);
3554 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
3555 mutex_unlock(&adev->dm.dc_lock);
3556 return size;
3557 }
3558
3559 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3560 supported_link_rates, sizeof(supported_link_rates)))
3561 return -EINVAL;
3562
3563 dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3564 if (dpcd_rev < DP_DPCD_REV_13 ||
3565 (supported_link_rates[entry + 1] == 0 && supported_link_rates[entry] == 0)) {
3566 return size;
3567 }
3568
3569 entry = param[1] * 2;
3570 link_rate_in_khz = (supported_link_rates[entry + 1] * 0x100 +
3571 supported_link_rates[entry]) * 200;
3572
3573 /* save user force lane_count, link_rate to preferred settings
3574 * spread spectrum will not be changed
3575 */
3576 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3577 prefer_link_settings.lane_count = param[0];
3578 prefer_link_settings.use_link_rate_set = true;
3579 prefer_link_settings.link_rate_set = param[1];
3580 prefer_link_settings.link_rate = link_rate_in_khz / MULTIPLIER_TO_LR;
3581
3582 mutex_lock(&adev->dm.dc_lock);
3583 dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3584 NULL, link, false);
3585 mutex_unlock(&adev->dm.dc_lock);
3586
3587 kfree(wr_buf);
3588 return size;
3589 }
3590
edp_ilr_open(struct inode * inode,struct file * file)3591 static int edp_ilr_open(struct inode *inode, struct file *file)
3592 {
3593 return single_open(file, edp_ilr_show, inode->i_private);
3594 }
3595
3596 static const struct file_operations edp_ilr_debugfs_fops = {
3597 .owner = THIS_MODULE,
3598 .open = edp_ilr_open,
3599 .read = seq_read,
3600 .llseek = seq_lseek,
3601 .release = single_release,
3602 .write = edp_ilr_write
3603 };
3604
connector_debugfs_init(struct amdgpu_dm_connector * connector)3605 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3606 {
3607 int i;
3608 struct dentry *dir = connector->base.debugfs_entry;
3609
3610 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3611 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3612 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3613 debugfs_create_file(dp_debugfs_entries[i].name,
3614 0644, dir, connector,
3615 dp_debugfs_entries[i].fops);
3616 }
3617 }
3618 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3619 debugfs_create_file("replay_capability", 0444, dir, connector,
3620 &replay_capability_fops);
3621 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops);
3622 debugfs_create_file_unsafe("replay_residency", 0444, dir,
3623 connector, &replay_residency_fops);
3624 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3625 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3626 debugfs_create_file_unsafe("psr_residency", 0444, dir,
3627 connector, &psr_residency_fops);
3628 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3629 ¤t_backlight_fops);
3630 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3631 &target_backlight_fops);
3632 debugfs_create_file("ilr_setting", 0644, dir, connector,
3633 &edp_ilr_debugfs_fops);
3634 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3635 &allow_edp_hotplug_detection_fops);
3636 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
3637 &disallow_edp_enter_psr_fops);
3638 }
3639
3640 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3641 debugfs_create_file(connector_debugfs_entries[i].name,
3642 0644, dir, connector,
3643 connector_debugfs_entries[i].fops);
3644 }
3645
3646 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3647 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3648 debugfs_create_file(hdmi_debugfs_entries[i].name,
3649 0644, dir, connector,
3650 hdmi_debugfs_entries[i].fops);
3651 }
3652 }
3653 }
3654
3655 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3656 /*
3657 * Set crc window coordinate x start
3658 */
crc_win_x_start_set(void * data,u64 val)3659 static int crc_win_x_start_set(void *data, u64 val)
3660 {
3661 struct drm_crtc *crtc = data;
3662 struct drm_device *drm_dev = crtc->dev;
3663 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3664
3665 spin_lock_irq(&drm_dev->event_lock);
3666 acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val;
3667 acrtc->dm_irq_params.window_param[0].update_win = false;
3668 spin_unlock_irq(&drm_dev->event_lock);
3669
3670 return 0;
3671 }
3672
3673 /*
3674 * Get crc window coordinate x start
3675 */
crc_win_x_start_get(void * data,u64 * val)3676 static int crc_win_x_start_get(void *data, u64 *val)
3677 {
3678 struct drm_crtc *crtc = data;
3679 struct drm_device *drm_dev = crtc->dev;
3680 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3681
3682 spin_lock_irq(&drm_dev->event_lock);
3683 *val = acrtc->dm_irq_params.window_param[0].x_start;
3684 spin_unlock_irq(&drm_dev->event_lock);
3685
3686 return 0;
3687 }
3688
3689 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3690 crc_win_x_start_set, "%llu\n");
3691
3692
3693 /*
3694 * Set crc window coordinate y start
3695 */
crc_win_y_start_set(void * data,u64 val)3696 static int crc_win_y_start_set(void *data, u64 val)
3697 {
3698 struct drm_crtc *crtc = data;
3699 struct drm_device *drm_dev = crtc->dev;
3700 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3701
3702 spin_lock_irq(&drm_dev->event_lock);
3703 acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val;
3704 acrtc->dm_irq_params.window_param[0].update_win = false;
3705 spin_unlock_irq(&drm_dev->event_lock);
3706
3707 return 0;
3708 }
3709
3710 /*
3711 * Get crc window coordinate y start
3712 */
crc_win_y_start_get(void * data,u64 * val)3713 static int crc_win_y_start_get(void *data, u64 *val)
3714 {
3715 struct drm_crtc *crtc = data;
3716 struct drm_device *drm_dev = crtc->dev;
3717 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3718
3719 spin_lock_irq(&drm_dev->event_lock);
3720 *val = acrtc->dm_irq_params.window_param[0].y_start;
3721 spin_unlock_irq(&drm_dev->event_lock);
3722
3723 return 0;
3724 }
3725
3726 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3727 crc_win_y_start_set, "%llu\n");
3728
3729 /*
3730 * Set crc window coordinate x end
3731 */
crc_win_x_end_set(void * data,u64 val)3732 static int crc_win_x_end_set(void *data, u64 val)
3733 {
3734 struct drm_crtc *crtc = data;
3735 struct drm_device *drm_dev = crtc->dev;
3736 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3737
3738 spin_lock_irq(&drm_dev->event_lock);
3739 acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val;
3740 acrtc->dm_irq_params.window_param[0].update_win = false;
3741 spin_unlock_irq(&drm_dev->event_lock);
3742
3743 return 0;
3744 }
3745
3746 /*
3747 * Get crc window coordinate x end
3748 */
crc_win_x_end_get(void * data,u64 * val)3749 static int crc_win_x_end_get(void *data, u64 *val)
3750 {
3751 struct drm_crtc *crtc = data;
3752 struct drm_device *drm_dev = crtc->dev;
3753 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3754
3755 spin_lock_irq(&drm_dev->event_lock);
3756 *val = acrtc->dm_irq_params.window_param[0].x_end;
3757 spin_unlock_irq(&drm_dev->event_lock);
3758
3759 return 0;
3760 }
3761
3762 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3763 crc_win_x_end_set, "%llu\n");
3764
3765 /*
3766 * Set crc window coordinate y end
3767 */
crc_win_y_end_set(void * data,u64 val)3768 static int crc_win_y_end_set(void *data, u64 val)
3769 {
3770 struct drm_crtc *crtc = data;
3771 struct drm_device *drm_dev = crtc->dev;
3772 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3773
3774 spin_lock_irq(&drm_dev->event_lock);
3775 acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val;
3776 acrtc->dm_irq_params.window_param[0].update_win = false;
3777 spin_unlock_irq(&drm_dev->event_lock);
3778
3779 return 0;
3780 }
3781
3782 /*
3783 * Get crc window coordinate y end
3784 */
crc_win_y_end_get(void * data,u64 * val)3785 static int crc_win_y_end_get(void *data, u64 *val)
3786 {
3787 struct drm_crtc *crtc = data;
3788 struct drm_device *drm_dev = crtc->dev;
3789 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3790
3791 spin_lock_irq(&drm_dev->event_lock);
3792 *val = acrtc->dm_irq_params.window_param[0].y_end;
3793 spin_unlock_irq(&drm_dev->event_lock);
3794
3795 return 0;
3796 }
3797
3798 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3799 crc_win_y_end_set, "%llu\n");
3800 /*
3801 * Trigger to commit crc window
3802 */
crc_win_update_set(void * data,u64 val)3803 static int crc_win_update_set(void *data, u64 val)
3804 {
3805 struct drm_crtc *crtc = data;
3806 struct amdgpu_crtc *acrtc;
3807 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3808
3809 if (val) {
3810 acrtc = to_amdgpu_crtc(crtc);
3811 mutex_lock(&adev->dm.dc_lock);
3812 /* PSR may write to OTG CRC window control register,
3813 * so close it before starting secure_display.
3814 */
3815 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true);
3816
3817 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3818
3819 acrtc->dm_irq_params.window_param[0].enable = true;
3820 acrtc->dm_irq_params.window_param[0].update_win = true;
3821 acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0;
3822 acrtc->dm_irq_params.crc_window_activated = true;
3823
3824 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3825 mutex_unlock(&adev->dm.dc_lock);
3826 }
3827
3828 return 0;
3829 }
3830
3831 /*
3832 * Get crc window update flag
3833 */
crc_win_update_get(void * data,u64 * val)3834 static int crc_win_update_get(void *data, u64 *val)
3835 {
3836 *val = 0;
3837 return 0;
3838 }
3839
3840 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3841 crc_win_update_set, "%llu\n");
3842
3843 /*
3844 * Trigger to set crc polynomial mode
3845 * 0: 16-bit CRC, 1: 32-bit CRC
3846 * only accepts 0 or 1 for supported hwip versions
3847 */
crc_poly_mode_set(void * data,u64 val)3848 static int crc_poly_mode_set(void *data, u64 val)
3849 {
3850 struct drm_crtc *crtc = data;
3851 struct amdgpu_crtc *acrtc;
3852 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3853
3854 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) &&
3855 (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1)) &&
3856 (val < 2)) {
3857 acrtc = to_amdgpu_crtc(crtc);
3858 mutex_lock(&adev->dm.dc_lock);
3859 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3860 acrtc->dm_irq_params.crc_poly_mode = val;
3861 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3862 mutex_unlock(&adev->dm.dc_lock);
3863 }
3864
3865 return 0;
3866 }
3867
3868 /*
3869 * Get crc polynomial mode (0: 16-bit CRC, 1: 32-bit CRC)
3870 */
crc_poly_mode_get(void * data,u64 * val)3871 static int crc_poly_mode_get(void *data, u64 *val)
3872 {
3873 struct drm_crtc *crtc = data;
3874 struct drm_device *drm_dev = crtc->dev;
3875 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3876
3877 spin_lock_irq(&drm_dev->event_lock);
3878 *val = acrtc->dm_irq_params.crc_poly_mode;
3879 spin_unlock_irq(&drm_dev->event_lock);
3880
3881 return 0;
3882 }
3883
3884 DEFINE_DEBUGFS_ATTRIBUTE(crc_poly_mode_fops, crc_poly_mode_get,
3885 crc_poly_mode_set, "%llu\n");
3886 #endif
crtc_debugfs_init(struct drm_crtc * crtc)3887 void crtc_debugfs_init(struct drm_crtc *crtc)
3888 {
3889 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3890 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3891
3892 if (!dir)
3893 return;
3894
3895 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3896 &crc_win_x_start_fops);
3897 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3898 &crc_win_y_start_fops);
3899 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3900 &crc_win_x_end_fops);
3901 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3902 &crc_win_y_end_fops);
3903 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3904 &crc_win_update_fops);
3905 debugfs_create_file_unsafe("crc_poly_mode", 0644, dir, crtc,
3906 &crc_poly_mode_fops);
3907 dput(dir);
3908 #endif
3909 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3910 crtc, &amdgpu_current_bpc_fops);
3911 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
3912 crtc, &amdgpu_current_colorspace_fops);
3913 }
3914
3915 /*
3916 * Writes DTN log state to the user supplied buffer.
3917 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3918 */
dtn_log_read(struct file * f,char __user * buf,size_t size,loff_t * pos)3919 static ssize_t dtn_log_read(
3920 struct file *f,
3921 char __user *buf,
3922 size_t size,
3923 loff_t *pos)
3924 {
3925 struct amdgpu_device *adev = file_inode(f)->i_private;
3926 struct dc *dc = adev->dm.dc;
3927 struct dc_log_buffer_ctx log_ctx = { 0 };
3928 ssize_t result = 0;
3929
3930 if (!buf || !size)
3931 return -EINVAL;
3932
3933 if (!dc->hwss.log_hw_state)
3934 return 0;
3935
3936 dc->hwss.log_hw_state(dc, &log_ctx);
3937
3938 if (*pos < log_ctx.pos) {
3939 size_t to_copy = log_ctx.pos - *pos;
3940
3941 to_copy = min(to_copy, size);
3942
3943 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3944 *pos += to_copy;
3945 result = to_copy;
3946 }
3947 }
3948
3949 kfree(log_ctx.buf);
3950
3951 return result;
3952 }
3953
3954 /*
3955 * Writes DTN log state to dmesg when triggered via a write.
3956 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3957 */
dtn_log_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)3958 static ssize_t dtn_log_write(
3959 struct file *f,
3960 const char __user *buf,
3961 size_t size,
3962 loff_t *pos)
3963 {
3964 struct amdgpu_device *adev = file_inode(f)->i_private;
3965 struct dc *dc = adev->dm.dc;
3966
3967 /* Write triggers log output via dmesg. */
3968 if (size == 0)
3969 return 0;
3970
3971 if (dc->hwss.log_hw_state)
3972 dc->hwss.log_hw_state(dc, NULL);
3973
3974 return size;
3975 }
3976
mst_topo_show(struct seq_file * m,void * unused)3977 static int mst_topo_show(struct seq_file *m, void *unused)
3978 {
3979 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3980 struct drm_device *dev = adev_to_drm(adev);
3981 struct drm_connector *connector;
3982 struct drm_connector_list_iter conn_iter;
3983 struct amdgpu_dm_connector *aconnector;
3984
3985 drm_connector_list_iter_begin(dev, &conn_iter);
3986 drm_for_each_connector_iter(connector, &conn_iter) {
3987 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3988 continue;
3989
3990 aconnector = to_amdgpu_dm_connector(connector);
3991
3992 /* Ensure we're only dumping the topology of a root mst node */
3993 if (!aconnector->mst_mgr.mst_state)
3994 continue;
3995
3996 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3997 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3998 }
3999 drm_connector_list_iter_end(&conn_iter);
4000
4001 return 0;
4002 }
4003
4004 /*
4005 * Sets trigger hpd for MST topologies.
4006 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
4007 * All topologies will be disconnected if val of 0 is set .
4008 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4009 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4010 */
trigger_hpd_mst_set(void * data,u64 val)4011 static int trigger_hpd_mst_set(void *data, u64 val)
4012 {
4013 struct amdgpu_device *adev = data;
4014 struct drm_device *dev = adev_to_drm(adev);
4015 struct drm_connector_list_iter iter;
4016 struct amdgpu_dm_connector *aconnector;
4017 struct drm_connector *connector;
4018 struct dc_link *link = NULL;
4019 int ret;
4020
4021 if (val == 1) {
4022 drm_connector_list_iter_begin(dev, &iter);
4023 drm_for_each_connector_iter(connector, &iter) {
4024 aconnector = to_amdgpu_dm_connector(connector);
4025 if (aconnector->dc_link->type == dc_connection_mst_branch &&
4026 aconnector->mst_mgr.aux) {
4027 mutex_lock(&adev->dm.dc_lock);
4028 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4029 mutex_unlock(&adev->dm.dc_lock);
4030
4031 if (!ret)
4032 DRM_ERROR("DM_MST: Failed to detect dc link!");
4033
4034 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
4035 if (ret < 0)
4036 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
4037 }
4038 }
4039 } else if (val == 0) {
4040 drm_connector_list_iter_begin(dev, &iter);
4041 drm_for_each_connector_iter(connector, &iter) {
4042 aconnector = to_amdgpu_dm_connector(connector);
4043 if (!aconnector->dc_link)
4044 continue;
4045
4046 if (!aconnector->mst_root)
4047 continue;
4048
4049 link = aconnector->dc_link;
4050 dc_link_dp_receiver_power_ctrl(link, false);
4051 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
4052 link->mst_stream_alloc_table.stream_count = 0;
4053 memset(link->mst_stream_alloc_table.stream_allocations, 0,
4054 sizeof(link->mst_stream_alloc_table.stream_allocations));
4055 }
4056 } else {
4057 return 0;
4058 }
4059 drm_kms_helper_hotplug_event(dev);
4060
4061 return 0;
4062 }
4063
4064 /*
4065 * The interface doesn't need get function, so it will return the
4066 * value of zero
4067 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4068 */
trigger_hpd_mst_get(void * data,u64 * val)4069 static int trigger_hpd_mst_get(void *data, u64 *val)
4070 {
4071 *val = 0;
4072 return 0;
4073 }
4074
4075 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
4076 trigger_hpd_mst_set, "%llu\n");
4077
4078
4079 /*
4080 * Sets the force_timing_sync debug option from the given string.
4081 * All connected displays will be force synchronized immediately.
4082 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
4083 */
force_timing_sync_set(void * data,u64 val)4084 static int force_timing_sync_set(void *data, u64 val)
4085 {
4086 struct amdgpu_device *adev = data;
4087
4088 adev->dm.force_timing_sync = (bool)val;
4089
4090 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
4091
4092 return 0;
4093 }
4094
4095 /*
4096 * Gets the force_timing_sync debug option value into the given buffer.
4097 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
4098 */
force_timing_sync_get(void * data,u64 * val)4099 static int force_timing_sync_get(void *data, u64 *val)
4100 {
4101 struct amdgpu_device *adev = data;
4102
4103 *val = adev->dm.force_timing_sync;
4104
4105 return 0;
4106 }
4107
4108 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
4109 force_timing_sync_set, "%llu\n");
4110
4111
4112 /*
4113 * Disables all HPD and HPD RX interrupt handling in the
4114 * driver when set to 1. Default is 0.
4115 */
disable_hpd_set(void * data,u64 val)4116 static int disable_hpd_set(void *data, u64 val)
4117 {
4118 struct amdgpu_device *adev = data;
4119
4120 adev->dm.disable_hpd_irq = (bool)val;
4121
4122 return 0;
4123 }
4124
4125
4126 /*
4127 * Returns 1 if HPD and HPRX interrupt handling is disabled,
4128 * 0 otherwise.
4129 */
disable_hpd_get(void * data,u64 * val)4130 static int disable_hpd_get(void *data, u64 *val)
4131 {
4132 struct amdgpu_device *adev = data;
4133
4134 *val = adev->dm.disable_hpd_irq;
4135
4136 return 0;
4137 }
4138
4139 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
4140 disable_hpd_set, "%llu\n");
4141
4142 /*
4143 * Prints hardware capabilities. These are used for IGT testing.
4144 */
capabilities_show(struct seq_file * m,void * unused)4145 static int capabilities_show(struct seq_file *m, void *unused)
4146 {
4147 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4148 struct dc *dc = adev->dm.dc;
4149 bool mall_supported = dc->caps.mall_size_total;
4150 bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
4151 unsigned int mall_in_use = false;
4152 unsigned int subvp_in_use = false;
4153
4154 struct hubbub *hubbub = dc->res_pool->hubbub;
4155
4156 if (hubbub && hubbub->funcs->get_mall_en)
4157 hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
4158
4159 if (dc->cap_funcs.get_subvp_en)
4160 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
4161
4162 seq_printf(m, "mall supported: %s, enabled: %s\n",
4163 mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
4164 seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
4165 subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no");
4166
4167 return 0;
4168 }
4169
4170 DEFINE_SHOW_ATTRIBUTE(capabilities);
4171
4172 /*
4173 * Temporary w/a to force sst sequence in M42D DP2 mst receiver
4174 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
4175 */
dp_force_sst_set(void * data,u64 val)4176 static int dp_force_sst_set(void *data, u64 val)
4177 {
4178 struct amdgpu_device *adev = data;
4179
4180 adev->dm.dc->debug.set_mst_en_for_sst = val;
4181
4182 return 0;
4183 }
4184
dp_force_sst_get(void * data,u64 * val)4185 static int dp_force_sst_get(void *data, u64 *val)
4186 {
4187 struct amdgpu_device *adev = data;
4188
4189 *val = adev->dm.dc->debug.set_mst_en_for_sst;
4190
4191 return 0;
4192 }
4193 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
4194 dp_force_sst_set, "%llu\n");
4195
4196 /*
4197 * Force DP2 sequence without VESA certified cable.
4198 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
4199 */
dp_ignore_cable_id_set(void * data,u64 val)4200 static int dp_ignore_cable_id_set(void *data, u64 val)
4201 {
4202 struct amdgpu_device *adev = data;
4203
4204 adev->dm.dc->debug.ignore_cable_id = val;
4205
4206 return 0;
4207 }
4208
dp_ignore_cable_id_get(void * data,u64 * val)4209 static int dp_ignore_cable_id_get(void *data, u64 *val)
4210 {
4211 struct amdgpu_device *adev = data;
4212
4213 *val = adev->dm.dc->debug.ignore_cable_id;
4214
4215 return 0;
4216 }
4217 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
4218 dp_ignore_cable_id_set, "%llu\n");
4219
4220 /*
4221 * Sets the DC visual confirm debug option from the given string.
4222 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
4223 */
visual_confirm_set(void * data,u64 val)4224 static int visual_confirm_set(void *data, u64 val)
4225 {
4226 struct amdgpu_device *adev = data;
4227
4228 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
4229
4230 return 0;
4231 }
4232
4233 /*
4234 * Reads the DC visual confirm debug option value into the given buffer.
4235 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
4236 */
visual_confirm_get(void * data,u64 * val)4237 static int visual_confirm_get(void *data, u64 *val)
4238 {
4239 struct amdgpu_device *adev = data;
4240
4241 *val = adev->dm.dc->debug.visual_confirm;
4242
4243 return 0;
4244 }
4245
4246 DEFINE_SHOW_ATTRIBUTE(mst_topo);
4247 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
4248 visual_confirm_set, "%llu\n");
4249
4250
4251 /*
4252 * Sets the DC skip_detection_link_training debug option from the given string.
4253 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
4254 */
skip_detection_link_training_set(void * data,u64 val)4255 static int skip_detection_link_training_set(void *data, u64 val)
4256 {
4257 struct amdgpu_device *adev = data;
4258
4259 if (val == 0)
4260 adev->dm.dc->debug.skip_detection_link_training = false;
4261 else
4262 adev->dm.dc->debug.skip_detection_link_training = true;
4263
4264 return 0;
4265 }
4266
4267 /*
4268 * Reads the DC skip_detection_link_training debug option value into the given buffer.
4269 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
4270 */
skip_detection_link_training_get(void * data,u64 * val)4271 static int skip_detection_link_training_get(void *data, u64 *val)
4272 {
4273 struct amdgpu_device *adev = data;
4274
4275 *val = adev->dm.dc->debug.skip_detection_link_training;
4276
4277 return 0;
4278 }
4279
4280 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
4281 skip_detection_link_training_get,
4282 skip_detection_link_training_set, "%llu\n");
4283
4284 /*
4285 * Dumps the DCC_EN bit for each pipe.
4286 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
4287 */
dcc_en_bits_read(struct file * f,char __user * buf,size_t size,loff_t * pos)4288 static ssize_t dcc_en_bits_read(
4289 struct file *f,
4290 char __user *buf,
4291 size_t size,
4292 loff_t *pos)
4293 {
4294 struct amdgpu_device *adev = file_inode(f)->i_private;
4295 struct dc *dc = adev->dm.dc;
4296 char *rd_buf = NULL;
4297 const uint32_t rd_buf_size = 32;
4298 uint32_t result = 0;
4299 int offset = 0;
4300 int num_pipes = dc->res_pool->pipe_count;
4301 int *dcc_en_bits;
4302 int i, r;
4303
4304 dcc_en_bits = kzalloc_objs(int, num_pipes);
4305 if (!dcc_en_bits)
4306 return -ENOMEM;
4307
4308 if (!dc->hwss.get_dcc_en_bits) {
4309 kfree(dcc_en_bits);
4310 return 0;
4311 }
4312
4313 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
4314
4315 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
4316 if (!rd_buf) {
4317 kfree(dcc_en_bits);
4318 return -ENOMEM;
4319 }
4320
4321 for (i = 0; i < num_pipes; i++)
4322 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
4323 "%d ", dcc_en_bits[i]);
4324 rd_buf[strlen(rd_buf)] = '\n';
4325
4326 kfree(dcc_en_bits);
4327
4328 while (size) {
4329 if (*pos >= rd_buf_size)
4330 break;
4331 r = put_user(*(rd_buf + result), buf);
4332 if (r) {
4333 kfree(rd_buf);
4334 return r; /* r = -EFAULT */
4335 }
4336 buf += 1;
4337 size -= 1;
4338 *pos += 1;
4339 result += 1;
4340 }
4341
4342 kfree(rd_buf);
4343 return result;
4344 }
4345
dtn_debugfs_init(struct amdgpu_device * adev)4346 void dtn_debugfs_init(struct amdgpu_device *adev)
4347 {
4348 static const struct file_operations dtn_log_fops = {
4349 .owner = THIS_MODULE,
4350 .read = dtn_log_read,
4351 .write = dtn_log_write,
4352 .llseek = default_llseek
4353 };
4354 static const struct file_operations dcc_en_bits_fops = {
4355 .owner = THIS_MODULE,
4356 .read = dcc_en_bits_read,
4357 .llseek = default_llseek
4358 };
4359
4360 struct drm_minor *minor = adev_to_drm(adev)->primary;
4361 struct dentry *root = minor->debugfs_root;
4362
4363 debugfs_create_file("amdgpu_mst_topology", 0444, root,
4364 adev, &mst_topo_fops);
4365 debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
4366 adev, &capabilities_fops);
4367 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
4368 &dtn_log_fops);
4369 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
4370 &dp_set_mst_en_for_sst_ops);
4371 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
4372 &dp_ignore_cable_id_ops);
4373
4374 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
4375 &visual_confirm_fops);
4376
4377 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
4378 &skip_detection_link_training_fops);
4379
4380 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
4381 adev, &dmub_tracebuffer_fops);
4382
4383 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
4384 adev, &dmub_fw_state_fops);
4385
4386 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
4387 adev, &force_timing_sync_ops);
4388
4389 debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root,
4390 adev, &dmub_trace_mask_fops);
4391
4392 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
4393 adev, &dmcub_trace_event_state_fops);
4394
4395 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
4396 adev, &trigger_hpd_mst_ops);
4397
4398 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
4399 &dcc_en_bits_fops);
4400
4401 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
4402 &disable_hpd_ops);
4403
4404 if (adev->dm.dc->caps.ips_support) {
4405 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
4406 &ips_status_fops);
4407
4408 debugfs_create_file_unsafe("amdgpu_dm_ips_residency_cntl", 0644, root, adev,
4409 &ips_residency_cntl_fops);
4410
4411 debugfs_create_file_unsafe("amdgpu_dm_ips_residency", 0644, root, adev,
4412 &ips_residency_fops);
4413 }
4414 }
4415