xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c (revision 3ef7acec975bde28ab9cef92af76be8fc2ce684d)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
5  * Copyright (C) 2013 Red Hat
6  * Author: Rob Clark <robdclark@gmail.com>
7  */
8 
9 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
10 #include <linux/sort.h>
11 #include <linux/debugfs.h>
12 #include <linux/ktime.h>
13 #include <linux/bits.h>
14 
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_blend.h>
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_flip_work.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_mode.h>
21 #include <drm/drm_probe_helper.h>
22 #include <drm/drm_rect.h>
23 #include <drm/drm_vblank.h>
24 #include <drm/drm_self_refresh_helper.h>
25 
26 #include "dpu_kms.h"
27 #include "dpu_hw_lm.h"
28 #include "dpu_hw_ctl.h"
29 #include "dpu_hw_dspp.h"
30 #include "dpu_crtc.h"
31 #include "dpu_plane.h"
32 #include "dpu_encoder.h"
33 #include "dpu_vbif.h"
34 #include "dpu_core_perf.h"
35 #include "dpu_trace.h"
36 
37 /* layer mixer index on dpu_crtc */
38 #define LEFT_MIXER 0
39 #define RIGHT_MIXER 1
40 
41 /* timeout in ms waiting for frame done */
42 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS	60
43 
44 #define	CONVERT_S3_15(val) \
45 	(((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))
46 
_dpu_crtc_get_kms(struct drm_crtc * crtc)47 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
48 {
49 	struct msm_drm_private *priv = crtc->dev->dev_private;
50 
51 	return to_dpu_kms(priv->kms);
52 }
53 
get_encoder_from_crtc(struct drm_crtc * crtc)54 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
55 {
56 	struct drm_device *dev = crtc->dev;
57 	struct drm_encoder *encoder;
58 
59 	drm_for_each_encoder(encoder, dev)
60 		if (encoder->crtc == crtc)
61 			return encoder;
62 
63 	return NULL;
64 }
65 
dpu_crtc_parse_crc_source(const char * src_name)66 static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name)
67 {
68 	if (!src_name ||
69 	    !strcmp(src_name, "none"))
70 		return DPU_CRTC_CRC_SOURCE_NONE;
71 	if (!strcmp(src_name, "auto") ||
72 	    !strcmp(src_name, "lm"))
73 		return DPU_CRTC_CRC_SOURCE_LAYER_MIXER;
74 	if (!strcmp(src_name, "encoder"))
75 		return DPU_CRTC_CRC_SOURCE_ENCODER;
76 
77 	return DPU_CRTC_CRC_SOURCE_INVALID;
78 }
79 
dpu_crtc_verify_crc_source(struct drm_crtc * crtc,const char * src_name,size_t * values_cnt)80 static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc,
81 		const char *src_name, size_t *values_cnt)
82 {
83 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
84 	struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
85 
86 	if (source < 0) {
87 		DRM_DEBUG_DRIVER("Invalid source %s for CRTC%d\n", src_name, crtc->index);
88 		return -EINVAL;
89 	}
90 
91 	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) {
92 		*values_cnt = crtc_state->num_mixers;
93 	} else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) {
94 		struct drm_encoder *drm_enc;
95 
96 		*values_cnt = 0;
97 
98 		drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
99 			*values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc);
100 	}
101 
102 	return 0;
103 }
104 
dpu_crtc_setup_lm_misr(struct dpu_crtc_state * crtc_state)105 static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
106 {
107 	struct dpu_crtc_mixer *m;
108 	int i;
109 
110 	for (i = 0; i < crtc_state->num_mixers; ++i) {
111 		m = &crtc_state->mixers[i];
112 
113 		if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
114 			continue;
115 
116 		/* Calculate MISR over 1 frame */
117 		m->hw_lm->ops.setup_misr(m->hw_lm);
118 	}
119 }
120 
dpu_crtc_setup_encoder_misr(struct drm_crtc * crtc)121 static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc)
122 {
123 	struct drm_encoder *drm_enc;
124 
125 	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
126 		dpu_encoder_setup_misr(drm_enc);
127 }
128 
dpu_crtc_set_crc_source(struct drm_crtc * crtc,const char * src_name)129 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
130 {
131 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
132 	enum dpu_crtc_crc_source current_source;
133 	struct dpu_crtc_state *crtc_state;
134 	struct drm_device *drm_dev = crtc->dev;
135 
136 	bool was_enabled;
137 	bool enable = false;
138 	int ret = 0;
139 
140 	if (source < 0) {
141 		DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index);
142 		return -EINVAL;
143 	}
144 
145 	ret = drm_modeset_lock(&crtc->mutex, NULL);
146 
147 	if (ret)
148 		return ret;
149 
150 	enable = (source != DPU_CRTC_CRC_SOURCE_NONE);
151 	crtc_state = to_dpu_crtc_state(crtc->state);
152 
153 	spin_lock_irq(&drm_dev->event_lock);
154 	current_source = crtc_state->crc_source;
155 	spin_unlock_irq(&drm_dev->event_lock);
156 
157 	was_enabled = (current_source != DPU_CRTC_CRC_SOURCE_NONE);
158 
159 	if (!was_enabled && enable) {
160 		ret = drm_crtc_vblank_get(crtc);
161 
162 		if (ret)
163 			goto cleanup;
164 
165 	} else if (was_enabled && !enable) {
166 		drm_crtc_vblank_put(crtc);
167 	}
168 
169 	spin_lock_irq(&drm_dev->event_lock);
170 	crtc_state->crc_source = source;
171 	spin_unlock_irq(&drm_dev->event_lock);
172 
173 	crtc_state->crc_frame_skip_count = 0;
174 
175 	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
176 		dpu_crtc_setup_lm_misr(crtc_state);
177 	else if (source == DPU_CRTC_CRC_SOURCE_ENCODER)
178 		dpu_crtc_setup_encoder_misr(crtc);
179 	else
180 		ret = -EINVAL;
181 
182 cleanup:
183 	drm_modeset_unlock(&crtc->mutex);
184 
185 	return ret;
186 }
187 
dpu_crtc_get_vblank_counter(struct drm_crtc * crtc)188 static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
189 {
190 	struct drm_encoder *encoder = get_encoder_from_crtc(crtc);
191 	if (!encoder) {
192 		DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
193 		return 0;
194 	}
195 
196 	return dpu_encoder_get_vsync_count(encoder);
197 }
198 
dpu_crtc_get_lm_crc(struct drm_crtc * crtc,struct dpu_crtc_state * crtc_state)199 static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
200 		struct dpu_crtc_state *crtc_state)
201 {
202 	struct dpu_crtc_mixer *m;
203 	u32 crcs[CRTC_DUAL_MIXERS];
204 
205 	int rc = 0;
206 	int i;
207 
208 	BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers));
209 
210 	for (i = 0; i < crtc_state->num_mixers; ++i) {
211 
212 		m = &crtc_state->mixers[i];
213 
214 		if (!m->hw_lm || !m->hw_lm->ops.collect_misr)
215 			continue;
216 
217 		rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]);
218 
219 		if (rc) {
220 			if (rc != -ENODATA)
221 				DRM_DEBUG_DRIVER("MISR read failed\n");
222 			return rc;
223 		}
224 	}
225 
226 	return drm_crtc_add_crc_entry(crtc, true,
227 			drm_crtc_accurate_vblank_count(crtc), crcs);
228 }
229 
dpu_crtc_get_encoder_crc(struct drm_crtc * crtc)230 static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc)
231 {
232 	struct drm_encoder *drm_enc;
233 	int rc, pos = 0;
234 	u32 crcs[INTF_MAX];
235 
236 	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) {
237 		rc = dpu_encoder_get_crc(drm_enc, crcs, pos);
238 		if (rc < 0) {
239 			if (rc != -ENODATA)
240 				DRM_DEBUG_DRIVER("MISR read failed\n");
241 
242 			return rc;
243 		}
244 
245 		pos += rc;
246 	}
247 
248 	return drm_crtc_add_crc_entry(crtc, true,
249 			drm_crtc_accurate_vblank_count(crtc), crcs);
250 }
251 
dpu_crtc_get_crc(struct drm_crtc * crtc)252 static int dpu_crtc_get_crc(struct drm_crtc *crtc)
253 {
254 	struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
255 
256 	/* Skip first 2 frames in case of "uncooked" CRCs */
257 	if (crtc_state->crc_frame_skip_count < 2) {
258 		crtc_state->crc_frame_skip_count++;
259 		return 0;
260 	}
261 
262 	if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
263 		return dpu_crtc_get_lm_crc(crtc, crtc_state);
264 	else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER)
265 		return dpu_crtc_get_encoder_crc(crtc);
266 
267 	return -EINVAL;
268 }
269 
dpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)270 static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
271 					   bool in_vblank_irq,
272 					   int *vpos, int *hpos,
273 					   ktime_t *stime, ktime_t *etime,
274 					   const struct drm_display_mode *mode)
275 {
276 	unsigned int pipe = crtc->index;
277 	struct drm_encoder *encoder;
278 	int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
279 
280 	encoder = get_encoder_from_crtc(crtc);
281 	if (!encoder) {
282 		DRM_ERROR("no encoder found for crtc %d\n", pipe);
283 		return false;
284 	}
285 
286 	vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
287 	vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
288 
289 	/*
290 	 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
291 	 * the end of VFP. Translate the porch values relative to the line
292 	 * counter positions.
293 	 */
294 
295 	vactive_start = vsw + vbp + 1;
296 	vactive_end = vactive_start + mode->crtc_vdisplay;
297 
298 	/* last scan line before VSYNC */
299 	vfp_end = mode->crtc_vtotal;
300 
301 	if (stime)
302 		*stime = ktime_get();
303 
304 	line = dpu_encoder_get_linecount(encoder);
305 
306 	if (line < vactive_start)
307 		line -= vactive_start;
308 	else if (line > vactive_end)
309 		line = line - vfp_end - vactive_start;
310 	else
311 		line -= vactive_start;
312 
313 	*vpos = line;
314 	*hpos = 0;
315 
316 	if (etime)
317 		*etime = ktime_get();
318 
319 	return true;
320 }
321 
_dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer * mixer,struct dpu_plane_state * pstate,const struct msm_format * format)322 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
323 		struct dpu_plane_state *pstate, const struct msm_format *format)
324 {
325 	struct dpu_hw_mixer *lm = mixer->hw_lm;
326 	uint32_t blend_op;
327 	uint32_t fg_alpha, bg_alpha;
328 
329 	fg_alpha = pstate->base.alpha >> 8;
330 	bg_alpha = 0xff - fg_alpha;
331 
332 	/* default to opaque blending */
333 	if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
334 	    !format->alpha_enable) {
335 		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
336 			DPU_BLEND_BG_ALPHA_BG_CONST;
337 	} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
338 		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
339 			DPU_BLEND_BG_ALPHA_FG_PIXEL;
340 		if (fg_alpha != 0xff) {
341 			bg_alpha = fg_alpha;
342 			blend_op |= DPU_BLEND_BG_MOD_ALPHA |
343 				    DPU_BLEND_BG_INV_MOD_ALPHA;
344 		} else {
345 			blend_op |= DPU_BLEND_BG_INV_ALPHA;
346 		}
347 	} else {
348 		/* coverage blending */
349 		blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
350 			DPU_BLEND_BG_ALPHA_FG_PIXEL;
351 		if (fg_alpha != 0xff) {
352 			bg_alpha = fg_alpha;
353 			blend_op |= DPU_BLEND_FG_MOD_ALPHA |
354 				    DPU_BLEND_FG_INV_MOD_ALPHA |
355 				    DPU_BLEND_BG_MOD_ALPHA |
356 				    DPU_BLEND_BG_INV_MOD_ALPHA;
357 		} else {
358 			blend_op |= DPU_BLEND_BG_INV_ALPHA;
359 		}
360 	}
361 
362 	lm->ops.setup_blend_config(lm, pstate->stage,
363 				fg_alpha, bg_alpha, blend_op);
364 
365 	DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
366 		  &format->pixel_format, format->alpha_enable, blend_op);
367 }
368 
_dpu_crtc_program_lm_output_roi(struct drm_crtc * crtc)369 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
370 {
371 	struct dpu_crtc_state *crtc_state;
372 	int lm_idx, lm_horiz_position;
373 
374 	crtc_state = to_dpu_crtc_state(crtc->state);
375 
376 	lm_horiz_position = 0;
377 	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
378 		const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
379 		struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
380 		struct dpu_hw_mixer_cfg cfg;
381 
382 		if (!lm_roi || !drm_rect_visible(lm_roi))
383 			continue;
384 
385 		cfg.out_width = drm_rect_width(lm_roi);
386 		cfg.out_height = drm_rect_height(lm_roi);
387 		cfg.right_mixer = lm_horiz_position++;
388 		cfg.flags = 0;
389 		hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
390 	}
391 }
392 
_dpu_crtc_blend_setup_pipe(struct drm_crtc * crtc,struct drm_plane * plane,struct dpu_crtc_mixer * mixer,u32 num_mixers,enum dpu_stage stage,const struct msm_format * format,uint64_t modifier,struct dpu_sw_pipe * pipe,unsigned int stage_idx,struct dpu_hw_stage_cfg * stage_cfg)393 static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
394 				       struct drm_plane *plane,
395 				       struct dpu_crtc_mixer *mixer,
396 				       u32 num_mixers,
397 				       enum dpu_stage stage,
398 				       const struct msm_format *format,
399 				       uint64_t modifier,
400 				       struct dpu_sw_pipe *pipe,
401 				       unsigned int stage_idx,
402 				       struct dpu_hw_stage_cfg *stage_cfg
403 				      )
404 {
405 	uint32_t lm_idx;
406 	enum dpu_sspp sspp_idx;
407 	struct drm_plane_state *state;
408 
409 	sspp_idx = pipe->sspp->idx;
410 
411 	state = plane->state;
412 
413 	trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
414 				   state, to_dpu_plane_state(state), stage_idx,
415 				   format->pixel_format,
416 				   modifier);
417 
418 	DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
419 			 crtc->base.id,
420 			 stage,
421 			 plane->base.id,
422 			 sspp_idx - SSPP_NONE,
423 			 state->fb ? state->fb->base.id : -1,
424 			 pipe->multirect_index);
425 
426 	stage_cfg->stage[stage][stage_idx] = sspp_idx;
427 	stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;
428 
429 	/* blend config update */
430 	for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
431 		mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);
432 }
433 
_dpu_crtc_blend_setup_mixer(struct drm_crtc * crtc,struct dpu_crtc * dpu_crtc,struct dpu_crtc_mixer * mixer,struct dpu_hw_stage_cfg * stage_cfg)434 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
435 	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
436 	struct dpu_hw_stage_cfg *stage_cfg)
437 {
438 	struct drm_plane *plane;
439 	struct drm_framebuffer *fb;
440 	struct drm_plane_state *state;
441 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
442 	struct dpu_plane_state *pstate = NULL;
443 	const struct msm_format *format;
444 	struct dpu_hw_ctl *ctl = mixer->lm_ctl;
445 
446 	uint32_t lm_idx;
447 	bool bg_alpha_enable = false;
448 	DECLARE_BITMAP(fetch_active, SSPP_MAX);
449 
450 	memset(fetch_active, 0, sizeof(fetch_active));
451 	drm_atomic_crtc_for_each_plane(plane, crtc) {
452 		state = plane->state;
453 		if (!state)
454 			continue;
455 
456 		if (!state->visible)
457 			continue;
458 
459 		pstate = to_dpu_plane_state(state);
460 		fb = state->fb;
461 
462 		format = msm_framebuffer_format(pstate->base.fb);
463 
464 		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
465 			bg_alpha_enable = true;
466 
467 		set_bit(pstate->pipe.sspp->idx, fetch_active);
468 		_dpu_crtc_blend_setup_pipe(crtc, plane,
469 					   mixer, cstate->num_mixers,
470 					   pstate->stage,
471 					   format, fb ? fb->modifier : 0,
472 					   &pstate->pipe, 0, stage_cfg);
473 
474 		if (pstate->r_pipe.sspp) {
475 			set_bit(pstate->r_pipe.sspp->idx, fetch_active);
476 			_dpu_crtc_blend_setup_pipe(crtc, plane,
477 						   mixer, cstate->num_mixers,
478 						   pstate->stage,
479 						   format, fb ? fb->modifier : 0,
480 						   &pstate->r_pipe, 1, stage_cfg);
481 		}
482 
483 		/* blend config update */
484 		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
485 			_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
486 
487 			if (bg_alpha_enable && !format->alpha_enable)
488 				mixer[lm_idx].mixer_op_mode = 0;
489 			else
490 				mixer[lm_idx].mixer_op_mode |=
491 						1 << pstate->stage;
492 		}
493 	}
494 
495 	if (ctl->ops.set_active_pipes)
496 		ctl->ops.set_active_pipes(ctl, fetch_active);
497 
498 	_dpu_crtc_program_lm_output_roi(crtc);
499 }
500 
501 /**
502  * _dpu_crtc_blend_setup - configure crtc mixers
503  * @crtc: Pointer to drm crtc structure
504  */
_dpu_crtc_blend_setup(struct drm_crtc * crtc)505 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
506 {
507 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
508 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
509 	struct dpu_crtc_mixer *mixer = cstate->mixers;
510 	struct dpu_hw_ctl *ctl;
511 	struct dpu_hw_mixer *lm;
512 	struct dpu_hw_stage_cfg stage_cfg;
513 	int i;
514 
515 	DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
516 
517 	for (i = 0; i < cstate->num_mixers; i++) {
518 		mixer[i].mixer_op_mode = 0;
519 		if (mixer[i].lm_ctl->ops.clear_all_blendstages)
520 			mixer[i].lm_ctl->ops.clear_all_blendstages(
521 					mixer[i].lm_ctl);
522 	}
523 
524 	/* initialize stage cfg */
525 	memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
526 
527 	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
528 
529 	for (i = 0; i < cstate->num_mixers; i++) {
530 		ctl = mixer[i].lm_ctl;
531 		lm = mixer[i].hw_lm;
532 
533 		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
534 
535 		/* stage config flush mask */
536 		ctl->ops.update_pending_flush_mixer(ctl,
537 			mixer[i].hw_lm->idx);
538 
539 		DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n",
540 			mixer[i].hw_lm->idx - LM_0,
541 			mixer[i].mixer_op_mode,
542 			ctl->idx - CTL_0);
543 
544 		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
545 			&stage_cfg);
546 	}
547 }
548 
549 /**
550  *  _dpu_crtc_complete_flip - signal pending page_flip events
551  * Any pending vblank events are added to the vblank_event_list
552  * so that the next vblank interrupt shall signal them.
553  * However PAGE_FLIP events are not handled through the vblank_event_list.
554  * This API signals any pending PAGE_FLIP events requested through
555  * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event.
556  * @crtc: Pointer to drm crtc structure
557  */
_dpu_crtc_complete_flip(struct drm_crtc * crtc)558 static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
559 {
560 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
561 	struct drm_device *dev = crtc->dev;
562 	unsigned long flags;
563 
564 	spin_lock_irqsave(&dev->event_lock, flags);
565 	if (dpu_crtc->event) {
566 		DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name,
567 			      dpu_crtc->event);
568 		trace_dpu_crtc_complete_flip(DRMID(crtc));
569 		drm_crtc_send_vblank_event(crtc, dpu_crtc->event);
570 		dpu_crtc->event = NULL;
571 	}
572 	spin_unlock_irqrestore(&dev->event_lock, flags);
573 }
574 
575 /**
576  * dpu_crtc_get_intf_mode - get interface mode of the given crtc
577  * @crtc: Pointert to crtc
578  */
dpu_crtc_get_intf_mode(struct drm_crtc * crtc)579 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
580 {
581 	struct drm_encoder *encoder;
582 
583 	/*
584 	 * TODO: This function is called from dpu debugfs and as part of atomic
585 	 * check. When called from debugfs, the crtc->mutex must be held to
586 	 * read crtc->state. However reading crtc->state from atomic check isn't
587 	 * allowed (unless you have a good reason, a big comment, and a deep
588 	 * understanding of how the atomic/modeset locks work (<- and this is
589 	 * probably not possible)). So we'll keep the WARN_ON here for now, but
590 	 * really we need to figure out a better way to track our operating mode
591 	 */
592 	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
593 
594 	/* TODO: Returns the first INTF_MODE, could there be multiple values? */
595 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
596 		return dpu_encoder_get_intf_mode(encoder);
597 
598 	return INTF_MODE_NONE;
599 }
600 
601 /**
602  * dpu_crtc_vblank_callback - called on vblank irq, issues completion events
603  * @crtc: Pointer to drm crtc object
604  */
dpu_crtc_vblank_callback(struct drm_crtc * crtc)605 void dpu_crtc_vblank_callback(struct drm_crtc *crtc)
606 {
607 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
608 
609 	/* keep statistics on vblank callback - with auto reset via debugfs */
610 	if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
611 		dpu_crtc->vblank_cb_time = ktime_get();
612 	else
613 		dpu_crtc->vblank_cb_count++;
614 
615 	dpu_crtc_get_crc(crtc);
616 
617 	drm_crtc_handle_vblank(crtc);
618 	trace_dpu_crtc_vblank_cb(DRMID(crtc));
619 }
620 
dpu_crtc_frame_event_work(struct kthread_work * work)621 static void dpu_crtc_frame_event_work(struct kthread_work *work)
622 {
623 	struct dpu_crtc_frame_event *fevent = container_of(work,
624 			struct dpu_crtc_frame_event, work);
625 	struct drm_crtc *crtc = fevent->crtc;
626 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
627 	unsigned long flags;
628 	bool frame_done = false;
629 
630 	DPU_ATRACE_BEGIN("crtc_frame_event");
631 
632 	DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
633 			ktime_to_ns(fevent->ts));
634 
635 	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
636 				| DPU_ENCODER_FRAME_EVENT_ERROR
637 				| DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
638 
639 		if (atomic_read(&dpu_crtc->frame_pending) < 1) {
640 			/* ignore vblank when not pending */
641 		} else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) {
642 			/* release bandwidth and other resources */
643 			trace_dpu_crtc_frame_event_done(DRMID(crtc),
644 							fevent->event);
645 			dpu_core_perf_crtc_release_bw(crtc);
646 		} else {
647 			trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
648 								fevent->event);
649 		}
650 
651 		if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
652 					| DPU_ENCODER_FRAME_EVENT_ERROR))
653 			frame_done = true;
654 	}
655 
656 	if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)
657 		DPU_ERROR("crtc%d ts:%lld received panel dead event\n",
658 				crtc->base.id, ktime_to_ns(fevent->ts));
659 
660 	if (frame_done)
661 		complete_all(&dpu_crtc->frame_done_comp);
662 
663 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
664 	list_add_tail(&fevent->list, &dpu_crtc->frame_event_list);
665 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
666 	DPU_ATRACE_END("crtc_frame_event");
667 }
668 
669 /**
670  * dpu_crtc_frame_event_cb - crtc frame event callback API
671  * @crtc: Pointer to crtc
672  * @event: Event to process
673  *
674  * Encoder may call this for different events from different context - IRQ,
675  * user thread, commit_thread, etc. Each event should be carefully reviewed and
676  * should be processed in proper task context to avoid schedulin delay or
677  * properly manage the irq context's bottom half processing.
678  */
dpu_crtc_frame_event_cb(struct drm_crtc * crtc,u32 event)679 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event)
680 {
681 	struct dpu_crtc *dpu_crtc;
682 	struct msm_drm_private *priv;
683 	struct dpu_crtc_frame_event *fevent;
684 	unsigned long flags;
685 	u32 crtc_id;
686 
687 	/* Nothing to do on idle event */
688 	if (event & DPU_ENCODER_FRAME_EVENT_IDLE)
689 		return;
690 
691 	dpu_crtc = to_dpu_crtc(crtc);
692 	priv = crtc->dev->dev_private;
693 	crtc_id = drm_crtc_index(crtc);
694 
695 	trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
696 
697 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
698 	fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list,
699 			struct dpu_crtc_frame_event, list);
700 	if (fevent)
701 		list_del_init(&fevent->list);
702 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
703 
704 	if (!fevent) {
705 		DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event);
706 		return;
707 	}
708 
709 	fevent->event = event;
710 	fevent->crtc = crtc;
711 	fevent->ts = ktime_get();
712 	kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work);
713 }
714 
715 /**
716  * dpu_crtc_complete_commit - callback signalling completion of current commit
717  * @crtc: Pointer to drm crtc object
718  */
dpu_crtc_complete_commit(struct drm_crtc * crtc)719 void dpu_crtc_complete_commit(struct drm_crtc *crtc)
720 {
721 	trace_dpu_crtc_complete_commit(DRMID(crtc));
722 	dpu_core_perf_crtc_update(crtc, 0);
723 	_dpu_crtc_complete_flip(crtc);
724 }
725 
_dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc * crtc,struct drm_crtc_state * state)726 static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
727 		struct drm_crtc_state *state)
728 {
729 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
730 	struct drm_display_mode *adj_mode = &state->adjusted_mode;
731 	u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
732 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
733 	int i;
734 
735 	/* if we cannot merge 2 LMs (no 3d mux) better to fail earlier
736 	 * before even checking the width after the split
737 	 */
738 	if (!dpu_kms->catalog->caps->has_3d_merge &&
739 	    adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
740 		return -E2BIG;
741 
742 	for (i = 0; i < cstate->num_mixers; i++) {
743 		struct drm_rect *r = &cstate->lm_bounds[i];
744 		r->x1 = crtc_split_width * i;
745 		r->y1 = 0;
746 		r->x2 = r->x1 + crtc_split_width;
747 		r->y2 = adj_mode->vdisplay;
748 
749 		trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
750 
751 		if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width)
752 			return -E2BIG;
753 	}
754 
755 	return 0;
756 }
757 
_dpu_crtc_get_pcc_coeff(struct drm_crtc_state * state,struct dpu_hw_pcc_cfg * cfg)758 static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state,
759 		struct dpu_hw_pcc_cfg *cfg)
760 {
761 	struct drm_color_ctm *ctm;
762 
763 	memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg));
764 
765 	ctm = (struct drm_color_ctm *)state->ctm->data;
766 
767 	if (!ctm)
768 		return;
769 
770 	cfg->r.r = CONVERT_S3_15(ctm->matrix[0]);
771 	cfg->g.r = CONVERT_S3_15(ctm->matrix[1]);
772 	cfg->b.r = CONVERT_S3_15(ctm->matrix[2]);
773 
774 	cfg->r.g = CONVERT_S3_15(ctm->matrix[3]);
775 	cfg->g.g = CONVERT_S3_15(ctm->matrix[4]);
776 	cfg->b.g = CONVERT_S3_15(ctm->matrix[5]);
777 
778 	cfg->r.b = CONVERT_S3_15(ctm->matrix[6]);
779 	cfg->g.b = CONVERT_S3_15(ctm->matrix[7]);
780 	cfg->b.b = CONVERT_S3_15(ctm->matrix[8]);
781 }
782 
_dpu_crtc_setup_cp_blocks(struct drm_crtc * crtc)783 static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
784 {
785 	struct drm_crtc_state *state = crtc->state;
786 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
787 	struct dpu_crtc_mixer *mixer = cstate->mixers;
788 	struct dpu_hw_pcc_cfg cfg;
789 	struct dpu_hw_ctl *ctl;
790 	struct dpu_hw_dspp *dspp;
791 	int i;
792 
793 
794 	if (!state->color_mgmt_changed && !drm_atomic_crtc_needs_modeset(state))
795 		return;
796 
797 	for (i = 0; i < cstate->num_mixers; i++) {
798 		ctl = mixer[i].lm_ctl;
799 		dspp = mixer[i].hw_dspp;
800 
801 		if (!dspp || !dspp->ops.setup_pcc)
802 			continue;
803 
804 		if (!state->ctm) {
805 			dspp->ops.setup_pcc(dspp, NULL);
806 		} else {
807 			_dpu_crtc_get_pcc_coeff(state, &cfg);
808 			dspp->ops.setup_pcc(dspp, &cfg);
809 		}
810 
811 		/* stage config flush mask */
812 		ctl->ops.update_pending_flush_dspp(ctl,
813 			mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
814 	}
815 }
816 
dpu_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)817 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
818 		struct drm_atomic_state *state)
819 {
820 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
821 	struct drm_encoder *encoder;
822 
823 	if (!crtc->state->enable) {
824 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
825 				crtc->base.id, crtc->state->enable);
826 		return;
827 	}
828 
829 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
830 
831 	_dpu_crtc_check_and_setup_lm_bounds(crtc, crtc->state);
832 
833 	/* encoder will trigger pending mask now */
834 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
835 		dpu_encoder_trigger_kickoff_pending(encoder);
836 
837 	/*
838 	 * If no mixers have been allocated in dpu_crtc_atomic_check(),
839 	 * it means we are trying to flush a CRTC whose state is disabled:
840 	 * nothing else needs to be done.
841 	 */
842 	if (unlikely(!cstate->num_mixers))
843 		return;
844 
845 	_dpu_crtc_blend_setup(crtc);
846 
847 	_dpu_crtc_setup_cp_blocks(crtc);
848 
849 	/*
850 	 * PP_DONE irq is only used by command mode for now.
851 	 * It is better to request pending before FLUSH and START trigger
852 	 * to make sure no pp_done irq missed.
853 	 * This is safe because no pp_done will happen before SW trigger
854 	 * in command mode.
855 	 */
856 }
857 
dpu_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)858 static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
859 		struct drm_atomic_state *state)
860 {
861 	struct dpu_crtc *dpu_crtc;
862 	struct drm_device *dev;
863 	struct drm_plane *plane;
864 	struct msm_drm_private *priv;
865 	unsigned long flags;
866 	struct dpu_crtc_state *cstate;
867 
868 	if (!crtc->state->enable) {
869 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
870 				crtc->base.id, crtc->state->enable);
871 		return;
872 	}
873 
874 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
875 
876 	dpu_crtc = to_dpu_crtc(crtc);
877 	cstate = to_dpu_crtc_state(crtc->state);
878 	dev = crtc->dev;
879 	priv = dev->dev_private;
880 
881 	if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
882 		DPU_ERROR("invalid crtc index[%d]\n", crtc->index);
883 		return;
884 	}
885 
886 	WARN_ON(dpu_crtc->event);
887 	spin_lock_irqsave(&dev->event_lock, flags);
888 	dpu_crtc->event = crtc->state->event;
889 	crtc->state->event = NULL;
890 	spin_unlock_irqrestore(&dev->event_lock, flags);
891 
892 	/*
893 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
894 	 * it means we are trying to flush a CRTC whose state is disabled:
895 	 * nothing else needs to be done.
896 	 */
897 	if (unlikely(!cstate->num_mixers))
898 		return;
899 
900 	/* update performance setting before crtc kickoff */
901 	dpu_core_perf_crtc_update(crtc, 1);
902 
903 	/*
904 	 * Final plane updates: Give each plane a chance to complete all
905 	 *                      required writes/flushing before crtc's "flush
906 	 *                      everything" call below.
907 	 */
908 	drm_atomic_crtc_for_each_plane(plane, crtc) {
909 		if (dpu_crtc->smmu_state.transition_error)
910 			dpu_plane_set_error(plane, true);
911 		dpu_plane_flush(plane);
912 	}
913 
914 	/* Kickoff will be scheduled by outer layer */
915 }
916 
917 /**
918  * dpu_crtc_destroy_state - state destroy hook
919  * @crtc: drm CRTC
920  * @state: CRTC state object to release
921  */
dpu_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)922 static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
923 		struct drm_crtc_state *state)
924 {
925 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
926 
927 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
928 
929 	__drm_atomic_helper_crtc_destroy_state(state);
930 
931 	kfree(cstate);
932 }
933 
_dpu_crtc_wait_for_frame_done(struct drm_crtc * crtc)934 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
935 {
936 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
937 	int ret, rc = 0;
938 
939 	if (!atomic_read(&dpu_crtc->frame_pending)) {
940 		DRM_DEBUG_ATOMIC("no frames pending\n");
941 		return 0;
942 	}
943 
944 	DPU_ATRACE_BEGIN("frame done completion wait");
945 	ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp,
946 			msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS));
947 	if (!ret) {
948 		DRM_ERROR("frame done wait timed out, ret:%d\n", ret);
949 		rc = -ETIMEDOUT;
950 	}
951 	DPU_ATRACE_END("frame done completion wait");
952 
953 	return rc;
954 }
955 
956 /**
957  * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc
958  * @crtc: Pointer to drm crtc object
959  */
dpu_crtc_commit_kickoff(struct drm_crtc * crtc)960 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
961 {
962 	struct drm_encoder *encoder;
963 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
964 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
965 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
966 
967 	/*
968 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
969 	 * it means we are trying to start a CRTC whose state is disabled:
970 	 * nothing else needs to be done.
971 	 */
972 	if (unlikely(!cstate->num_mixers))
973 		return;
974 
975 	DPU_ATRACE_BEGIN("crtc_commit");
976 
977 	drm_for_each_encoder_mask(encoder, crtc->dev,
978 			crtc->state->encoder_mask) {
979 		if (!dpu_encoder_is_valid_for_commit(encoder)) {
980 			DRM_DEBUG_ATOMIC("invalid FB not kicking off crtc\n");
981 			goto end;
982 		}
983 	}
984 	/*
985 	 * Encoder will flush/start now, unless it has a tx pending. If so, it
986 	 * may delay and flush at an irq event (e.g. ppdone)
987 	 */
988 	drm_for_each_encoder_mask(encoder, crtc->dev,
989 				  crtc->state->encoder_mask)
990 		dpu_encoder_prepare_for_kickoff(encoder);
991 
992 	if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
993 		/* acquire bandwidth and other resources */
994 		DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
995 	} else
996 		DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
997 
998 	dpu_crtc->play_count++;
999 
1000 	dpu_vbif_clear_errors(dpu_kms);
1001 
1002 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
1003 		dpu_encoder_kickoff(encoder);
1004 
1005 	reinit_completion(&dpu_crtc->frame_done_comp);
1006 
1007 end:
1008 	DPU_ATRACE_END("crtc_commit");
1009 }
1010 
dpu_crtc_reset(struct drm_crtc * crtc)1011 static void dpu_crtc_reset(struct drm_crtc *crtc)
1012 {
1013 	struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
1014 
1015 	if (crtc->state)
1016 		dpu_crtc_destroy_state(crtc, crtc->state);
1017 
1018 	if (cstate)
1019 		__drm_atomic_helper_crtc_reset(crtc, &cstate->base);
1020 	else
1021 		__drm_atomic_helper_crtc_reset(crtc, NULL);
1022 }
1023 
1024 /**
1025  * dpu_crtc_duplicate_state - state duplicate hook
1026  * @crtc: Pointer to drm crtc structure
1027  */
dpu_crtc_duplicate_state(struct drm_crtc * crtc)1028 static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
1029 {
1030 	struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state);
1031 
1032 	cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
1033 	if (!cstate) {
1034 		DPU_ERROR("failed to allocate state\n");
1035 		return NULL;
1036 	}
1037 
1038 	/* duplicate base helper */
1039 	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
1040 
1041 	return &cstate->base;
1042 }
1043 
dpu_crtc_atomic_print_state(struct drm_printer * p,const struct drm_crtc_state * state)1044 static void dpu_crtc_atomic_print_state(struct drm_printer *p,
1045 					const struct drm_crtc_state *state)
1046 {
1047 	const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
1048 	int i;
1049 
1050 	for (i = 0; i < cstate->num_mixers; i++) {
1051 		drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0);
1052 		drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0);
1053 		if (cstate->mixers[i].hw_dspp)
1054 			drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0);
1055 	}
1056 }
1057 
dpu_crtc_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)1058 static void dpu_crtc_disable(struct drm_crtc *crtc,
1059 			     struct drm_atomic_state *state)
1060 {
1061 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1062 									      crtc);
1063 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1064 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
1065 	struct drm_encoder *encoder;
1066 	unsigned long flags;
1067 	bool release_bandwidth = false;
1068 
1069 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
1070 
1071 	/* If disable is triggered while in self refresh mode,
1072 	 * reset the encoder software state so that in enable
1073 	 * it won't trigger a warn while assigning crtc.
1074 	 */
1075 	if (old_crtc_state->self_refresh_active) {
1076 		drm_for_each_encoder_mask(encoder, crtc->dev,
1077 					old_crtc_state->encoder_mask) {
1078 			dpu_encoder_assign_crtc(encoder, NULL);
1079 		}
1080 		return;
1081 	}
1082 
1083 	/* Disable/save vblank irq handling */
1084 	drm_crtc_vblank_off(crtc);
1085 
1086 	drm_for_each_encoder_mask(encoder, crtc->dev,
1087 				  old_crtc_state->encoder_mask) {
1088 		/* in video mode, we hold an extra bandwidth reference
1089 		 * as we cannot drop bandwidth at frame-done if any
1090 		 * crtc is being used in video mode.
1091 		 */
1092 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1093 			release_bandwidth = true;
1094 
1095 		/*
1096 		 * If disable is triggered during psr active(e.g: screen dim in PSR),
1097 		 * we will need encoder->crtc connection to process the device sleep &
1098 		 * preserve it during psr sequence.
1099 		 */
1100 		if (!crtc->state->self_refresh_active)
1101 			dpu_encoder_assign_crtc(encoder, NULL);
1102 	}
1103 
1104 	/* wait for frame_event_done completion */
1105 	if (_dpu_crtc_wait_for_frame_done(crtc))
1106 		DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
1107 				crtc->base.id,
1108 				atomic_read(&dpu_crtc->frame_pending));
1109 
1110 	trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
1111 	dpu_crtc->enabled = false;
1112 
1113 	if (atomic_read(&dpu_crtc->frame_pending)) {
1114 		trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
1115 				     atomic_read(&dpu_crtc->frame_pending));
1116 		if (release_bandwidth)
1117 			dpu_core_perf_crtc_release_bw(crtc);
1118 		atomic_set(&dpu_crtc->frame_pending, 0);
1119 	}
1120 
1121 	dpu_core_perf_crtc_update(crtc, 0);
1122 
1123 	/* disable clk & bw control until clk & bw properties are set */
1124 	cstate->bw_control = false;
1125 	cstate->bw_split_vote = false;
1126 
1127 	if (crtc->state->event && !crtc->state->active) {
1128 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
1129 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
1130 		crtc->state->event = NULL;
1131 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1132 	}
1133 
1134 	pm_runtime_put_sync(crtc->dev->dev);
1135 }
1136 
dpu_crtc_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1137 static void dpu_crtc_enable(struct drm_crtc *crtc,
1138 		struct drm_atomic_state *state)
1139 {
1140 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1141 	struct drm_encoder *encoder;
1142 	bool request_bandwidth = false;
1143 	struct drm_crtc_state *old_crtc_state;
1144 
1145 	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1146 
1147 	pm_runtime_get_sync(crtc->dev->dev);
1148 
1149 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
1150 
1151 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
1152 		/* in video mode, we hold an extra bandwidth reference
1153 		 * as we cannot drop bandwidth at frame-done if any
1154 		 * crtc is being used in video mode.
1155 		 */
1156 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1157 			request_bandwidth = true;
1158 	}
1159 
1160 	if (request_bandwidth)
1161 		atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1162 
1163 	trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
1164 	dpu_crtc->enabled = true;
1165 
1166 	if (!old_crtc_state->self_refresh_active) {
1167 		drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
1168 			dpu_encoder_assign_crtc(encoder, crtc);
1169 	}
1170 
1171 	/* Enable/restore vblank irq handling */
1172 	drm_crtc_vblank_on(crtc);
1173 }
1174 
dpu_crtc_needs_dirtyfb(struct drm_crtc_state * cstate)1175 static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
1176 {
1177 	struct drm_crtc *crtc = cstate->crtc;
1178 	struct drm_encoder *encoder;
1179 
1180 	if (cstate->self_refresh_active)
1181 		return true;
1182 
1183 	drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) {
1184 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) {
1185 			return true;
1186 		}
1187 	}
1188 
1189 	return false;
1190 }
1191 
dpu_crtc_reassign_planes(struct drm_crtc * crtc,struct drm_crtc_state * crtc_state)1192 static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
1193 {
1194 	int total_planes = crtc->dev->mode_config.num_total_plane;
1195 	struct drm_atomic_state *state = crtc_state->state;
1196 	struct dpu_global_state *global_state;
1197 	struct drm_plane_state **states;
1198 	struct drm_plane *plane;
1199 	int ret;
1200 
1201 	global_state = dpu_kms_get_global_state(crtc_state->state);
1202 	if (IS_ERR(global_state))
1203 		return PTR_ERR(global_state);
1204 
1205 	dpu_rm_release_all_sspp(global_state, crtc);
1206 
1207 	if (!crtc_state->enable)
1208 		return 0;
1209 
1210 	states = kcalloc(total_planes, sizeof(*states), GFP_KERNEL);
1211 	if (!states)
1212 		return -ENOMEM;
1213 
1214 	drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1215 		struct drm_plane_state *plane_state =
1216 			drm_atomic_get_plane_state(state, plane);
1217 
1218 		if (IS_ERR(plane_state)) {
1219 			ret = PTR_ERR(plane_state);
1220 			goto done;
1221 		}
1222 
1223 		states[plane_state->normalized_zpos] = plane_state;
1224 	}
1225 
1226 	ret = dpu_assign_plane_resources(global_state, state, crtc, states, total_planes);
1227 
1228 done:
1229 	kfree(states);
1230 	return ret;
1231 }
1232 
dpu_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1233 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
1234 		struct drm_atomic_state *state)
1235 {
1236 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1237 									  crtc);
1238 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1239 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
1240 
1241 	const struct drm_plane_state *pstate;
1242 	struct drm_plane *plane;
1243 
1244 	int rc = 0;
1245 
1246 	bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
1247 
1248 	if (dpu_use_virtual_planes &&
1249 	    (crtc_state->planes_changed || crtc_state->zpos_changed)) {
1250 		rc = dpu_crtc_reassign_planes(crtc, crtc_state);
1251 		if (rc < 0)
1252 			return rc;
1253 	}
1254 
1255 	if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) {
1256 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
1257 				crtc->base.id, crtc_state->enable,
1258 				crtc_state->active);
1259 		memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
1260 		return 0;
1261 	}
1262 
1263 	DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
1264 
1265 	/* force a full mode set if active state changed */
1266 	if (crtc_state->active_changed)
1267 		crtc_state->mode_changed = true;
1268 
1269 	if (cstate->num_mixers) {
1270 		rc = _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc_state);
1271 		if (rc)
1272 			return rc;
1273 	}
1274 
1275 	/* FIXME: move this to dpu_plane_atomic_check? */
1276 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
1277 		struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
1278 
1279 		if (IS_ERR_OR_NULL(pstate)) {
1280 			rc = PTR_ERR(pstate);
1281 			DPU_ERROR("%s: failed to get plane%d state, %d\n",
1282 					dpu_crtc->name, plane->base.id, rc);
1283 			return rc;
1284 		}
1285 
1286 		if (!pstate->visible)
1287 			continue;
1288 
1289 		dpu_pstate->needs_dirtyfb = needs_dirtyfb;
1290 	}
1291 
1292 	atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1293 
1294 	rc = dpu_core_perf_crtc_check(crtc, crtc_state);
1295 	if (rc) {
1296 		DPU_ERROR("crtc%d failed performance check %d\n",
1297 				crtc->base.id, rc);
1298 		return rc;
1299 	}
1300 
1301 	return 0;
1302 }
1303 
dpu_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)1304 static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
1305 						const struct drm_display_mode *mode)
1306 {
1307 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
1308 
1309 	/* if there is no 3d_mux block we cannot merge LMs so we cannot
1310 	 * split the large layer into 2 LMs, filter out such modes
1311 	 */
1312 	if (!dpu_kms->catalog->caps->has_3d_merge &&
1313 	    mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
1314 		return MODE_BAD_HVALUE;
1315 	/*
1316 	 * max crtc width is equal to the max mixer width * 2 and max height is 4K
1317 	 */
1318 	return drm_mode_validate_size(mode,
1319 				      2 * dpu_kms->catalog->caps->max_mixer_width,
1320 				      4096);
1321 }
1322 
1323 /**
1324  * dpu_crtc_vblank - enable or disable vblanks for this crtc
1325  * @crtc: Pointer to drm crtc object
1326  * @en: true to enable vblanks, false to disable
1327  */
dpu_crtc_vblank(struct drm_crtc * crtc,bool en)1328 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
1329 {
1330 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1331 	struct drm_encoder *enc;
1332 
1333 	trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
1334 
1335 	/*
1336 	 * Normally we would iterate through encoder_mask in crtc state to find
1337 	 * attached encoders. In this case, we might be disabling vblank _after_
1338 	 * encoder_mask has been cleared.
1339 	 *
1340 	 * Instead, we "assign" a crtc to the encoder in enable and clear it in
1341 	 * disable (which is also after encoder_mask is cleared). So instead of
1342 	 * using encoder mask, we'll ask the encoder to toggle itself iff it's
1343 	 * currently assigned to our crtc.
1344 	 *
1345 	 * Note also that this function cannot be called while crtc is disabled
1346 	 * since we use drm_crtc_vblank_on/off. So we don't need to worry
1347 	 * about the assigned crtcs being inconsistent with the current state
1348 	 * (which means no need to worry about modeset locks).
1349 	 */
1350 	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
1351 		trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en,
1352 					     dpu_crtc);
1353 
1354 		dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en);
1355 	}
1356 
1357 	return 0;
1358 }
1359 
1360 #ifdef CONFIG_DEBUG_FS
_dpu_debugfs_status_show(struct seq_file * s,void * data)1361 static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
1362 {
1363 	struct dpu_crtc *dpu_crtc;
1364 	struct dpu_plane_state *pstate = NULL;
1365 	struct dpu_crtc_mixer *m;
1366 
1367 	struct drm_crtc *crtc;
1368 	struct drm_plane *plane;
1369 	struct drm_display_mode *mode;
1370 	struct drm_framebuffer *fb;
1371 	struct drm_plane_state *state;
1372 	struct dpu_crtc_state *cstate;
1373 
1374 	int i, out_width;
1375 
1376 	dpu_crtc = s->private;
1377 	crtc = &dpu_crtc->base;
1378 
1379 	drm_modeset_lock_all(crtc->dev);
1380 	cstate = to_dpu_crtc_state(crtc->state);
1381 
1382 	mode = &crtc->state->adjusted_mode;
1383 	out_width = mode->hdisplay / cstate->num_mixers;
1384 
1385 	seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
1386 				mode->hdisplay, mode->vdisplay);
1387 
1388 	seq_puts(s, "\n");
1389 
1390 	for (i = 0; i < cstate->num_mixers; ++i) {
1391 		m = &cstate->mixers[i];
1392 		seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
1393 			m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
1394 			out_width, mode->vdisplay);
1395 	}
1396 
1397 	seq_puts(s, "\n");
1398 
1399 	drm_atomic_crtc_for_each_plane(plane, crtc) {
1400 		pstate = to_dpu_plane_state(plane->state);
1401 		state = plane->state;
1402 
1403 		if (!pstate || !state)
1404 			continue;
1405 
1406 		seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
1407 			pstate->stage);
1408 
1409 		if (plane->state->fb) {
1410 			fb = plane->state->fb;
1411 
1412 			seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
1413 				fb->base.id, (char *) &fb->format->format,
1414 				fb->width, fb->height);
1415 			for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
1416 				seq_printf(s, "cpp[%d]:%u ",
1417 						i, fb->format->cpp[i]);
1418 			seq_puts(s, "\n\t");
1419 
1420 			seq_printf(s, "modifier:%8llu ", fb->modifier);
1421 			seq_puts(s, "\n");
1422 
1423 			seq_puts(s, "\t");
1424 			for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
1425 				seq_printf(s, "pitches[%d]:%8u ", i,
1426 							fb->pitches[i]);
1427 			seq_puts(s, "\n");
1428 
1429 			seq_puts(s, "\t");
1430 			for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
1431 				seq_printf(s, "offsets[%d]:%8u ", i,
1432 							fb->offsets[i]);
1433 			seq_puts(s, "\n");
1434 		}
1435 
1436 		seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
1437 			state->src_x, state->src_y, state->src_w, state->src_h);
1438 
1439 		seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
1440 			state->crtc_x, state->crtc_y, state->crtc_w,
1441 			state->crtc_h);
1442 		seq_printf(s, "\tsspp[0]:%s\n",
1443 			   pstate->pipe.sspp->cap->name);
1444 		seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
1445 			pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
1446 		if (pstate->r_pipe.sspp) {
1447 			seq_printf(s, "\tsspp[1]:%s\n",
1448 				   pstate->r_pipe.sspp->cap->name);
1449 			seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
1450 				   pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
1451 		}
1452 
1453 		seq_puts(s, "\n");
1454 	}
1455 	if (dpu_crtc->vblank_cb_count) {
1456 		ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time);
1457 		s64 diff_ms = ktime_to_ms(diff);
1458 		s64 fps = diff_ms ? div_s64(
1459 				dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0;
1460 
1461 		seq_printf(s,
1462 			"vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
1463 				fps, dpu_crtc->vblank_cb_count,
1464 				ktime_to_ms(diff), dpu_crtc->play_count);
1465 
1466 		/* reset time & count for next measurement */
1467 		dpu_crtc->vblank_cb_count = 0;
1468 		dpu_crtc->vblank_cb_time = ktime_set(0, 0);
1469 	}
1470 
1471 	drm_modeset_unlock_all(crtc->dev);
1472 
1473 	return 0;
1474 }
1475 
1476 DEFINE_SHOW_ATTRIBUTE(_dpu_debugfs_status);
1477 
dpu_crtc_debugfs_state_show(struct seq_file * s,void * v)1478 static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
1479 {
1480 	struct drm_crtc *crtc = s->private;
1481 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1482 
1483 	seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
1484 	seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
1485 	seq_printf(s, "core_clk_rate: %llu\n",
1486 			dpu_crtc->cur_perf.core_clk_rate);
1487 	seq_printf(s, "bw_ctl: %llu\n", dpu_crtc->cur_perf.bw_ctl);
1488 	seq_printf(s, "max_per_pipe_ib: %llu\n",
1489 				dpu_crtc->cur_perf.max_per_pipe_ib);
1490 
1491 	return 0;
1492 }
1493 DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state);
1494 
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)1495 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1496 {
1497 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1498 
1499 	debugfs_create_file("status", 0400,
1500 			crtc->debugfs_entry,
1501 			dpu_crtc, &_dpu_debugfs_status_fops);
1502 	debugfs_create_file("state", 0600,
1503 			crtc->debugfs_entry,
1504 			&dpu_crtc->base,
1505 			&dpu_crtc_debugfs_state_fops);
1506 
1507 	return 0;
1508 }
1509 #else
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)1510 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1511 {
1512 	return 0;
1513 }
1514 #endif /* CONFIG_DEBUG_FS */
1515 
dpu_crtc_late_register(struct drm_crtc * crtc)1516 static int dpu_crtc_late_register(struct drm_crtc *crtc)
1517 {
1518 	return _dpu_crtc_init_debugfs(crtc);
1519 }
1520 
1521 static const struct drm_crtc_funcs dpu_crtc_funcs = {
1522 	.set_config = drm_atomic_helper_set_config,
1523 	.page_flip = drm_atomic_helper_page_flip,
1524 	.reset = dpu_crtc_reset,
1525 	.atomic_duplicate_state = dpu_crtc_duplicate_state,
1526 	.atomic_destroy_state = dpu_crtc_destroy_state,
1527 	.atomic_print_state = dpu_crtc_atomic_print_state,
1528 	.late_register = dpu_crtc_late_register,
1529 	.verify_crc_source = dpu_crtc_verify_crc_source,
1530 	.set_crc_source = dpu_crtc_set_crc_source,
1531 	.enable_vblank  = msm_crtc_enable_vblank,
1532 	.disable_vblank = msm_crtc_disable_vblank,
1533 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1534 	.get_vblank_counter = dpu_crtc_get_vblank_counter,
1535 };
1536 
1537 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
1538 	.atomic_disable = dpu_crtc_disable,
1539 	.atomic_enable = dpu_crtc_enable,
1540 	.atomic_check = dpu_crtc_atomic_check,
1541 	.atomic_begin = dpu_crtc_atomic_begin,
1542 	.atomic_flush = dpu_crtc_atomic_flush,
1543 	.mode_valid = dpu_crtc_mode_valid,
1544 	.get_scanout_position = dpu_crtc_get_scanout_position,
1545 };
1546 
1547 /**
1548  * dpu_crtc_init - create a new crtc object
1549  * @dev: dpu device
1550  * @plane: base plane
1551  * @cursor: cursor plane
1552  * @return: new crtc object or error
1553  *
1554  * initialize CRTC
1555  */
dpu_crtc_init(struct drm_device * dev,struct drm_plane * plane,struct drm_plane * cursor)1556 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
1557 				struct drm_plane *cursor)
1558 {
1559 	struct msm_drm_private *priv = dev->dev_private;
1560 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1561 	struct drm_crtc *crtc = NULL;
1562 	struct dpu_crtc *dpu_crtc;
1563 	int i, ret;
1564 
1565 	dpu_crtc = drmm_crtc_alloc_with_planes(dev, struct dpu_crtc, base,
1566 					       plane, cursor,
1567 					       &dpu_crtc_funcs,
1568 					       NULL);
1569 
1570 	if (IS_ERR(dpu_crtc))
1571 		return ERR_CAST(dpu_crtc);
1572 
1573 	crtc = &dpu_crtc->base;
1574 	crtc->dev = dev;
1575 
1576 	spin_lock_init(&dpu_crtc->spin_lock);
1577 	atomic_set(&dpu_crtc->frame_pending, 0);
1578 
1579 	init_completion(&dpu_crtc->frame_done_comp);
1580 
1581 	INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
1582 
1583 	for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
1584 		INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
1585 		list_add(&dpu_crtc->frame_events[i].list,
1586 				&dpu_crtc->frame_event_list);
1587 		kthread_init_work(&dpu_crtc->frame_events[i].work,
1588 				dpu_crtc_frame_event_work);
1589 	}
1590 
1591 	drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
1592 
1593 	if (dpu_kms->catalog->dspp_count)
1594 		drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
1595 
1596 	/* save user friendly CRTC name for later */
1597 	snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
1598 
1599 	/* initialize event handling */
1600 	spin_lock_init(&dpu_crtc->event_lock);
1601 
1602 	ret = drm_self_refresh_helper_init(crtc);
1603 	if (ret) {
1604 		DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
1605 			crtc->name, ret);
1606 		return ERR_PTR(ret);
1607 	}
1608 
1609 	DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
1610 	return crtc;
1611 }
1612