1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 10 #include <linux/sort.h> 11 #include <linux/debugfs.h> 12 #include <linux/ktime.h> 13 #include <linux/bits.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_blend.h> 17 #include <drm/drm_crtc.h> 18 #include <drm/drm_flip_work.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_mode.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_rect.h> 23 #include <drm/drm_vblank.h> 24 #include <drm/drm_self_refresh_helper.h> 25 26 #include "dpu_kms.h" 27 #include "dpu_hw_lm.h" 28 #include "dpu_hw_ctl.h" 29 #include "dpu_hw_dspp.h" 30 #include "dpu_crtc.h" 31 #include "dpu_plane.h" 32 #include "dpu_encoder.h" 33 #include "dpu_vbif.h" 34 #include "dpu_core_perf.h" 35 #include "dpu_trace.h" 36 37 /* layer mixer index on dpu_crtc */ 38 #define LEFT_MIXER 0 39 #define RIGHT_MIXER 1 40 41 /* timeout in ms waiting for frame done */ 42 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS 60 43 44 #define CONVERT_S3_15(val) \ 45 (((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0)) 46 47 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) 48 { 49 struct msm_drm_private *priv = crtc->dev->dev_private; 50 51 return to_dpu_kms(priv->kms); 52 } 53 54 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) 55 { 56 struct drm_device *dev = crtc->dev; 57 struct drm_encoder *encoder; 58 59 drm_for_each_encoder(encoder, dev) 60 if (encoder->crtc == crtc) 61 return encoder; 62 63 return NULL; 64 } 65 66 static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name) 67 { 68 if (!src_name || 69 !strcmp(src_name, "none")) 70 return DPU_CRTC_CRC_SOURCE_NONE; 71 if (!strcmp(src_name, "auto") || 72 !strcmp(src_name, "lm")) 73 return DPU_CRTC_CRC_SOURCE_LAYER_MIXER; 74 if (!strcmp(src_name, "encoder")) 75 return DPU_CRTC_CRC_SOURCE_ENCODER; 76 77 return DPU_CRTC_CRC_SOURCE_INVALID; 78 } 79 80 static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc, 81 const char *src_name, size_t *values_cnt) 82 { 83 enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name); 84 struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state); 85 86 if (source < 0) { 87 DRM_DEBUG_DRIVER("Invalid source %s for CRTC%d\n", src_name, crtc->index); 88 return -EINVAL; 89 } 90 91 if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) { 92 *values_cnt = crtc_state->num_mixers; 93 } else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) { 94 struct drm_encoder *drm_enc; 95 96 *values_cnt = 0; 97 98 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) 99 *values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc); 100 } 101 102 return 0; 103 } 104 105 static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state) 106 { 107 struct dpu_crtc_mixer *m; 108 int i; 109 110 for (i = 0; i < crtc_state->num_mixers; ++i) { 111 m = &crtc_state->mixers[i]; 112 113 if (!m->hw_lm || !m->hw_lm->ops.setup_misr) 114 continue; 115 116 /* Calculate MISR over 1 frame */ 117 m->hw_lm->ops.setup_misr(m->hw_lm); 118 } 119 } 120 121 static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc) 122 { 123 struct drm_encoder *drm_enc; 124 125 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) 126 dpu_encoder_setup_misr(drm_enc); 127 } 128 129 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 130 { 131 enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name); 132 enum dpu_crtc_crc_source current_source; 133 struct dpu_crtc_state *crtc_state; 134 struct drm_device *drm_dev = crtc->dev; 135 136 bool was_enabled; 137 bool enable = false; 138 int ret = 0; 139 140 if (source < 0) { 141 DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index); 142 return -EINVAL; 143 } 144 145 ret = drm_modeset_lock(&crtc->mutex, NULL); 146 147 if (ret) 148 return ret; 149 150 enable = (source != DPU_CRTC_CRC_SOURCE_NONE); 151 crtc_state = to_dpu_crtc_state(crtc->state); 152 153 spin_lock_irq(&drm_dev->event_lock); 154 current_source = crtc_state->crc_source; 155 spin_unlock_irq(&drm_dev->event_lock); 156 157 was_enabled = (current_source != DPU_CRTC_CRC_SOURCE_NONE); 158 159 if (!was_enabled && enable) { 160 ret = drm_crtc_vblank_get(crtc); 161 162 if (ret) 163 goto cleanup; 164 165 } else if (was_enabled && !enable) { 166 drm_crtc_vblank_put(crtc); 167 } 168 169 spin_lock_irq(&drm_dev->event_lock); 170 crtc_state->crc_source = source; 171 spin_unlock_irq(&drm_dev->event_lock); 172 173 crtc_state->crc_frame_skip_count = 0; 174 175 if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) 176 dpu_crtc_setup_lm_misr(crtc_state); 177 else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) 178 dpu_crtc_setup_encoder_misr(crtc); 179 else 180 ret = -EINVAL; 181 182 cleanup: 183 drm_modeset_unlock(&crtc->mutex); 184 185 return ret; 186 } 187 188 static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc) 189 { 190 struct drm_encoder *encoder = get_encoder_from_crtc(crtc); 191 if (!encoder) { 192 DRM_ERROR("no encoder found for crtc %d\n", crtc->index); 193 return 0; 194 } 195 196 return dpu_encoder_get_vsync_count(encoder); 197 } 198 199 static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, 200 struct dpu_crtc_state *crtc_state) 201 { 202 struct dpu_crtc_mixer *m; 203 u32 crcs[CRTC_DUAL_MIXERS]; 204 205 int rc = 0; 206 int i; 207 208 BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers)); 209 210 for (i = 0; i < crtc_state->num_mixers; ++i) { 211 212 m = &crtc_state->mixers[i]; 213 214 if (!m->hw_lm || !m->hw_lm->ops.collect_misr) 215 continue; 216 217 rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]); 218 219 if (rc) { 220 if (rc != -ENODATA) 221 DRM_DEBUG_DRIVER("MISR read failed\n"); 222 return rc; 223 } 224 } 225 226 return drm_crtc_add_crc_entry(crtc, true, 227 drm_crtc_accurate_vblank_count(crtc), crcs); 228 } 229 230 static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc) 231 { 232 struct drm_encoder *drm_enc; 233 int rc, pos = 0; 234 u32 crcs[INTF_MAX]; 235 236 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) { 237 rc = dpu_encoder_get_crc(drm_enc, crcs, pos); 238 if (rc < 0) { 239 if (rc != -ENODATA) 240 DRM_DEBUG_DRIVER("MISR read failed\n"); 241 242 return rc; 243 } 244 245 pos += rc; 246 } 247 248 return drm_crtc_add_crc_entry(crtc, true, 249 drm_crtc_accurate_vblank_count(crtc), crcs); 250 } 251 252 static int dpu_crtc_get_crc(struct drm_crtc *crtc) 253 { 254 struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state); 255 256 /* Skip first 2 frames in case of "uncooked" CRCs */ 257 if (crtc_state->crc_frame_skip_count < 2) { 258 crtc_state->crc_frame_skip_count++; 259 return 0; 260 } 261 262 if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) 263 return dpu_crtc_get_lm_crc(crtc, crtc_state); 264 else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER) 265 return dpu_crtc_get_encoder_crc(crtc); 266 267 return -EINVAL; 268 } 269 270 static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, 271 bool in_vblank_irq, 272 int *vpos, int *hpos, 273 ktime_t *stime, ktime_t *etime, 274 const struct drm_display_mode *mode) 275 { 276 unsigned int pipe = crtc->index; 277 struct drm_encoder *encoder; 278 int line, vsw, vbp, vactive_start, vactive_end, vfp_end; 279 280 encoder = get_encoder_from_crtc(crtc); 281 if (!encoder) { 282 DRM_ERROR("no encoder found for crtc %d\n", pipe); 283 return false; 284 } 285 286 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; 287 vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 288 289 /* 290 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at 291 * the end of VFP. Translate the porch values relative to the line 292 * counter positions. 293 */ 294 295 vactive_start = vsw + vbp + 1; 296 vactive_end = vactive_start + mode->crtc_vdisplay; 297 298 /* last scan line before VSYNC */ 299 vfp_end = mode->crtc_vtotal; 300 301 if (stime) 302 *stime = ktime_get(); 303 304 line = dpu_encoder_get_linecount(encoder); 305 306 if (line < vactive_start) 307 line -= vactive_start; 308 else if (line > vactive_end) 309 line = line - vfp_end - vactive_start; 310 else 311 line -= vactive_start; 312 313 *vpos = line; 314 *hpos = 0; 315 316 if (etime) 317 *etime = ktime_get(); 318 319 return true; 320 } 321 322 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 323 struct dpu_plane_state *pstate, const struct msm_format *format) 324 { 325 struct dpu_hw_mixer *lm = mixer->hw_lm; 326 uint32_t blend_op; 327 uint32_t fg_alpha, bg_alpha; 328 329 fg_alpha = pstate->base.alpha >> 8; 330 bg_alpha = 0xff - fg_alpha; 331 332 /* default to opaque blending */ 333 if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || 334 !format->alpha_enable) { 335 blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 336 DPU_BLEND_BG_ALPHA_BG_CONST; 337 } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 338 blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 339 DPU_BLEND_BG_ALPHA_FG_PIXEL; 340 if (fg_alpha != 0xff) { 341 bg_alpha = fg_alpha; 342 blend_op |= DPU_BLEND_BG_MOD_ALPHA | 343 DPU_BLEND_BG_INV_MOD_ALPHA; 344 } else { 345 blend_op |= DPU_BLEND_BG_INV_ALPHA; 346 } 347 } else { 348 /* coverage blending */ 349 blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | 350 DPU_BLEND_BG_ALPHA_FG_PIXEL; 351 if (fg_alpha != 0xff) { 352 bg_alpha = fg_alpha; 353 blend_op |= DPU_BLEND_FG_MOD_ALPHA | 354 DPU_BLEND_FG_INV_MOD_ALPHA | 355 DPU_BLEND_BG_MOD_ALPHA | 356 DPU_BLEND_BG_INV_MOD_ALPHA; 357 } else { 358 blend_op |= DPU_BLEND_BG_INV_ALPHA; 359 } 360 } 361 362 lm->ops.setup_blend_config(lm, pstate->stage, 363 fg_alpha, bg_alpha, blend_op); 364 365 DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n", 366 &format->pixel_format, format->alpha_enable, blend_op); 367 } 368 369 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 370 { 371 struct dpu_crtc_state *crtc_state; 372 int lm_idx, lm_horiz_position; 373 374 crtc_state = to_dpu_crtc_state(crtc->state); 375 376 lm_horiz_position = 0; 377 for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { 378 const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; 379 struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; 380 struct dpu_hw_mixer_cfg cfg; 381 382 if (!lm_roi || !drm_rect_visible(lm_roi)) 383 continue; 384 385 cfg.out_width = drm_rect_width(lm_roi); 386 cfg.out_height = drm_rect_height(lm_roi); 387 cfg.right_mixer = lm_horiz_position++; 388 cfg.flags = 0; 389 hw_lm->ops.setup_mixer_out(hw_lm, &cfg); 390 } 391 } 392 393 static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, 394 struct drm_plane *plane, 395 struct dpu_crtc_mixer *mixer, 396 u32 num_mixers, 397 enum dpu_stage stage, 398 const struct msm_format *format, 399 uint64_t modifier, 400 struct dpu_sw_pipe *pipe, 401 unsigned int stage_idx, 402 struct dpu_hw_stage_cfg *stage_cfg 403 ) 404 { 405 uint32_t lm_idx; 406 enum dpu_sspp sspp_idx; 407 struct drm_plane_state *state; 408 409 sspp_idx = pipe->sspp->idx; 410 411 state = plane->state; 412 413 trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), 414 state, to_dpu_plane_state(state), stage_idx, 415 format->pixel_format, 416 modifier); 417 418 DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n", 419 crtc->base.id, 420 stage, 421 plane->base.id, 422 sspp_idx - SSPP_NONE, 423 state->fb ? state->fb->base.id : -1, 424 pipe->multirect_index); 425 426 stage_cfg->stage[stage][stage_idx] = sspp_idx; 427 stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; 428 429 /* blend config update */ 430 for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) 431 mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx); 432 } 433 434 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 435 struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer, 436 struct dpu_hw_stage_cfg *stage_cfg) 437 { 438 struct drm_plane *plane; 439 struct drm_framebuffer *fb; 440 struct drm_plane_state *state; 441 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 442 struct dpu_plane_state *pstate = NULL; 443 const struct msm_format *format; 444 struct dpu_hw_ctl *ctl = mixer->lm_ctl; 445 446 uint32_t lm_idx; 447 bool bg_alpha_enable = false; 448 DECLARE_BITMAP(fetch_active, SSPP_MAX); 449 450 memset(fetch_active, 0, sizeof(fetch_active)); 451 drm_atomic_crtc_for_each_plane(plane, crtc) { 452 state = plane->state; 453 if (!state) 454 continue; 455 456 if (!state->visible) 457 continue; 458 459 pstate = to_dpu_plane_state(state); 460 fb = state->fb; 461 462 format = msm_framebuffer_format(pstate->base.fb); 463 464 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 465 bg_alpha_enable = true; 466 467 set_bit(pstate->pipe.sspp->idx, fetch_active); 468 _dpu_crtc_blend_setup_pipe(crtc, plane, 469 mixer, cstate->num_mixers, 470 pstate->stage, 471 format, fb ? fb->modifier : 0, 472 &pstate->pipe, 0, stage_cfg); 473 474 if (pstate->r_pipe.sspp) { 475 set_bit(pstate->r_pipe.sspp->idx, fetch_active); 476 _dpu_crtc_blend_setup_pipe(crtc, plane, 477 mixer, cstate->num_mixers, 478 pstate->stage, 479 format, fb ? fb->modifier : 0, 480 &pstate->r_pipe, 1, stage_cfg); 481 } 482 483 /* blend config update */ 484 for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { 485 _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); 486 487 if (bg_alpha_enable && !format->alpha_enable) 488 mixer[lm_idx].mixer_op_mode = 0; 489 else 490 mixer[lm_idx].mixer_op_mode |= 491 1 << pstate->stage; 492 } 493 } 494 495 if (ctl->ops.set_active_pipes) 496 ctl->ops.set_active_pipes(ctl, fetch_active); 497 498 _dpu_crtc_program_lm_output_roi(crtc); 499 } 500 501 /** 502 * _dpu_crtc_blend_setup - configure crtc mixers 503 * @crtc: Pointer to drm crtc structure 504 */ 505 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 506 { 507 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 508 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 509 struct dpu_crtc_mixer *mixer = cstate->mixers; 510 struct dpu_hw_ctl *ctl; 511 struct dpu_hw_mixer *lm; 512 struct dpu_hw_stage_cfg stage_cfg; 513 int i; 514 515 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); 516 517 for (i = 0; i < cstate->num_mixers; i++) { 518 mixer[i].mixer_op_mode = 0; 519 if (mixer[i].lm_ctl->ops.clear_all_blendstages) 520 mixer[i].lm_ctl->ops.clear_all_blendstages( 521 mixer[i].lm_ctl); 522 } 523 524 /* initialize stage cfg */ 525 memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); 526 527 _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); 528 529 for (i = 0; i < cstate->num_mixers; i++) { 530 ctl = mixer[i].lm_ctl; 531 lm = mixer[i].hw_lm; 532 533 lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); 534 535 /* stage config flush mask */ 536 ctl->ops.update_pending_flush_mixer(ctl, 537 mixer[i].hw_lm->idx); 538 539 DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n", 540 mixer[i].hw_lm->idx - LM_0, 541 mixer[i].mixer_op_mode, 542 ctl->idx - CTL_0); 543 544 ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, 545 &stage_cfg); 546 } 547 } 548 549 /** 550 * _dpu_crtc_complete_flip - signal pending page_flip events 551 * Any pending vblank events are added to the vblank_event_list 552 * so that the next vblank interrupt shall signal them. 553 * However PAGE_FLIP events are not handled through the vblank_event_list. 554 * This API signals any pending PAGE_FLIP events requested through 555 * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event. 556 * @crtc: Pointer to drm crtc structure 557 */ 558 static void _dpu_crtc_complete_flip(struct drm_crtc *crtc) 559 { 560 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 561 struct drm_device *dev = crtc->dev; 562 unsigned long flags; 563 564 spin_lock_irqsave(&dev->event_lock, flags); 565 if (dpu_crtc->event) { 566 DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 567 dpu_crtc->event); 568 trace_dpu_crtc_complete_flip(DRMID(crtc)); 569 drm_crtc_send_vblank_event(crtc, dpu_crtc->event); 570 dpu_crtc->event = NULL; 571 } 572 spin_unlock_irqrestore(&dev->event_lock, flags); 573 } 574 575 /** 576 * dpu_crtc_get_intf_mode - get interface mode of the given crtc 577 * @crtc: Pointert to crtc 578 */ 579 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 580 { 581 struct drm_encoder *encoder; 582 583 /* 584 * TODO: This function is called from dpu debugfs and as part of atomic 585 * check. When called from debugfs, the crtc->mutex must be held to 586 * read crtc->state. However reading crtc->state from atomic check isn't 587 * allowed (unless you have a good reason, a big comment, and a deep 588 * understanding of how the atomic/modeset locks work (<- and this is 589 * probably not possible)). So we'll keep the WARN_ON here for now, but 590 * really we need to figure out a better way to track our operating mode 591 */ 592 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 593 594 /* TODO: Returns the first INTF_MODE, could there be multiple values? */ 595 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 596 return dpu_encoder_get_intf_mode(encoder); 597 598 return INTF_MODE_NONE; 599 } 600 601 /** 602 * dpu_crtc_vblank_callback - called on vblank irq, issues completion events 603 * @crtc: Pointer to drm crtc object 604 */ 605 void dpu_crtc_vblank_callback(struct drm_crtc *crtc) 606 { 607 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 608 609 /* keep statistics on vblank callback - with auto reset via debugfs */ 610 if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0) 611 dpu_crtc->vblank_cb_time = ktime_get(); 612 else 613 dpu_crtc->vblank_cb_count++; 614 615 dpu_crtc_get_crc(crtc); 616 617 drm_crtc_handle_vblank(crtc); 618 trace_dpu_crtc_vblank_cb(DRMID(crtc)); 619 } 620 621 static void dpu_crtc_frame_event_work(struct kthread_work *work) 622 { 623 struct dpu_crtc_frame_event *fevent = container_of(work, 624 struct dpu_crtc_frame_event, work); 625 struct drm_crtc *crtc = fevent->crtc; 626 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 627 unsigned long flags; 628 bool frame_done = false; 629 630 DPU_ATRACE_BEGIN("crtc_frame_event"); 631 632 DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, 633 ktime_to_ns(fevent->ts)); 634 635 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 636 | DPU_ENCODER_FRAME_EVENT_ERROR 637 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 638 639 if (atomic_read(&dpu_crtc->frame_pending) < 1) { 640 /* ignore vblank when not pending */ 641 } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) { 642 /* release bandwidth and other resources */ 643 trace_dpu_crtc_frame_event_done(DRMID(crtc), 644 fevent->event); 645 dpu_core_perf_crtc_release_bw(crtc); 646 } else { 647 trace_dpu_crtc_frame_event_more_pending(DRMID(crtc), 648 fevent->event); 649 } 650 651 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 652 | DPU_ENCODER_FRAME_EVENT_ERROR)) 653 frame_done = true; 654 } 655 656 if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD) 657 DPU_ERROR("crtc%d ts:%lld received panel dead event\n", 658 crtc->base.id, ktime_to_ns(fevent->ts)); 659 660 if (frame_done) 661 complete_all(&dpu_crtc->frame_done_comp); 662 663 spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 664 list_add_tail(&fevent->list, &dpu_crtc->frame_event_list); 665 spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 666 DPU_ATRACE_END("crtc_frame_event"); 667 } 668 669 /** 670 * dpu_crtc_frame_event_cb - crtc frame event callback API 671 * @crtc: Pointer to crtc 672 * @event: Event to process 673 * 674 * Encoder may call this for different events from different context - IRQ, 675 * user thread, commit_thread, etc. Each event should be carefully reviewed and 676 * should be processed in proper task context to avoid schedulin delay or 677 * properly manage the irq context's bottom half processing. 678 */ 679 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event) 680 { 681 struct dpu_crtc *dpu_crtc; 682 struct msm_drm_private *priv; 683 struct dpu_crtc_frame_event *fevent; 684 unsigned long flags; 685 u32 crtc_id; 686 687 /* Nothing to do on idle event */ 688 if (event & DPU_ENCODER_FRAME_EVENT_IDLE) 689 return; 690 691 dpu_crtc = to_dpu_crtc(crtc); 692 priv = crtc->dev->dev_private; 693 crtc_id = drm_crtc_index(crtc); 694 695 trace_dpu_crtc_frame_event_cb(DRMID(crtc), event); 696 697 spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 698 fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list, 699 struct dpu_crtc_frame_event, list); 700 if (fevent) 701 list_del_init(&fevent->list); 702 spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 703 704 if (!fevent) { 705 DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event); 706 return; 707 } 708 709 fevent->event = event; 710 fevent->crtc = crtc; 711 fevent->ts = ktime_get(); 712 kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work); 713 } 714 715 /** 716 * dpu_crtc_complete_commit - callback signalling completion of current commit 717 * @crtc: Pointer to drm crtc object 718 */ 719 void dpu_crtc_complete_commit(struct drm_crtc *crtc) 720 { 721 trace_dpu_crtc_complete_commit(DRMID(crtc)); 722 dpu_core_perf_crtc_update(crtc, 0); 723 _dpu_crtc_complete_flip(crtc); 724 } 725 726 static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc, 727 struct drm_crtc_state *state) 728 { 729 struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 730 struct drm_display_mode *adj_mode = &state->adjusted_mode; 731 u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers; 732 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 733 int i; 734 735 /* if we cannot merge 2 LMs (no 3d mux) better to fail earlier 736 * before even checking the width after the split 737 */ 738 if (!dpu_kms->catalog->caps->has_3d_merge && 739 adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) 740 return -E2BIG; 741 742 for (i = 0; i < cstate->num_mixers; i++) { 743 struct drm_rect *r = &cstate->lm_bounds[i]; 744 r->x1 = crtc_split_width * i; 745 r->y1 = 0; 746 r->x2 = r->x1 + crtc_split_width; 747 r->y2 = adj_mode->vdisplay; 748 749 trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); 750 751 if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width) 752 return -E2BIG; 753 } 754 755 return 0; 756 } 757 758 static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state, 759 struct dpu_hw_pcc_cfg *cfg) 760 { 761 struct drm_color_ctm *ctm; 762 763 memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg)); 764 765 ctm = (struct drm_color_ctm *)state->ctm->data; 766 767 if (!ctm) 768 return; 769 770 cfg->r.r = CONVERT_S3_15(ctm->matrix[0]); 771 cfg->g.r = CONVERT_S3_15(ctm->matrix[1]); 772 cfg->b.r = CONVERT_S3_15(ctm->matrix[2]); 773 774 cfg->r.g = CONVERT_S3_15(ctm->matrix[3]); 775 cfg->g.g = CONVERT_S3_15(ctm->matrix[4]); 776 cfg->b.g = CONVERT_S3_15(ctm->matrix[5]); 777 778 cfg->r.b = CONVERT_S3_15(ctm->matrix[6]); 779 cfg->g.b = CONVERT_S3_15(ctm->matrix[7]); 780 cfg->b.b = CONVERT_S3_15(ctm->matrix[8]); 781 } 782 783 static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) 784 { 785 struct drm_crtc_state *state = crtc->state; 786 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 787 struct dpu_crtc_mixer *mixer = cstate->mixers; 788 struct dpu_hw_pcc_cfg cfg; 789 struct dpu_hw_ctl *ctl; 790 struct dpu_hw_dspp *dspp; 791 int i; 792 793 794 if (!state->color_mgmt_changed && !drm_atomic_crtc_needs_modeset(state)) 795 return; 796 797 for (i = 0; i < cstate->num_mixers; i++) { 798 ctl = mixer[i].lm_ctl; 799 dspp = mixer[i].hw_dspp; 800 801 if (!dspp || !dspp->ops.setup_pcc) 802 continue; 803 804 if (!state->ctm) { 805 dspp->ops.setup_pcc(dspp, NULL); 806 } else { 807 _dpu_crtc_get_pcc_coeff(state, &cfg); 808 dspp->ops.setup_pcc(dspp, &cfg); 809 } 810 811 /* stage config flush mask */ 812 ctl->ops.update_pending_flush_dspp(ctl, 813 mixer[i].hw_dspp->idx, DPU_DSPP_PCC); 814 } 815 } 816 817 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, 818 struct drm_atomic_state *state) 819 { 820 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 821 struct drm_encoder *encoder; 822 823 if (!crtc->state->enable) { 824 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n", 825 crtc->base.id, crtc->state->enable); 826 return; 827 } 828 829 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); 830 831 _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc->state); 832 833 /* encoder will trigger pending mask now */ 834 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 835 dpu_encoder_trigger_kickoff_pending(encoder); 836 837 /* 838 * If no mixers have been allocated in dpu_crtc_atomic_check(), 839 * it means we are trying to flush a CRTC whose state is disabled: 840 * nothing else needs to be done. 841 */ 842 if (unlikely(!cstate->num_mixers)) 843 return; 844 845 _dpu_crtc_blend_setup(crtc); 846 847 _dpu_crtc_setup_cp_blocks(crtc); 848 849 /* 850 * PP_DONE irq is only used by command mode for now. 851 * It is better to request pending before FLUSH and START trigger 852 * to make sure no pp_done irq missed. 853 * This is safe because no pp_done will happen before SW trigger 854 * in command mode. 855 */ 856 } 857 858 static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, 859 struct drm_atomic_state *state) 860 { 861 struct dpu_crtc *dpu_crtc; 862 struct drm_device *dev; 863 struct drm_plane *plane; 864 struct msm_drm_private *priv; 865 unsigned long flags; 866 struct dpu_crtc_state *cstate; 867 868 if (!crtc->state->enable) { 869 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n", 870 crtc->base.id, crtc->state->enable); 871 return; 872 } 873 874 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); 875 876 dpu_crtc = to_dpu_crtc(crtc); 877 cstate = to_dpu_crtc_state(crtc->state); 878 dev = crtc->dev; 879 priv = dev->dev_private; 880 881 if (crtc->index >= ARRAY_SIZE(priv->event_thread)) { 882 DPU_ERROR("invalid crtc index[%d]\n", crtc->index); 883 return; 884 } 885 886 WARN_ON(dpu_crtc->event); 887 spin_lock_irqsave(&dev->event_lock, flags); 888 dpu_crtc->event = crtc->state->event; 889 crtc->state->event = NULL; 890 spin_unlock_irqrestore(&dev->event_lock, flags); 891 892 /* 893 * If no mixers has been allocated in dpu_crtc_atomic_check(), 894 * it means we are trying to flush a CRTC whose state is disabled: 895 * nothing else needs to be done. 896 */ 897 if (unlikely(!cstate->num_mixers)) 898 return; 899 900 /* update performance setting before crtc kickoff */ 901 dpu_core_perf_crtc_update(crtc, 1); 902 903 /* 904 * Final plane updates: Give each plane a chance to complete all 905 * required writes/flushing before crtc's "flush 906 * everything" call below. 907 */ 908 drm_atomic_crtc_for_each_plane(plane, crtc) { 909 if (dpu_crtc->smmu_state.transition_error) 910 dpu_plane_set_error(plane, true); 911 dpu_plane_flush(plane); 912 } 913 914 /* Kickoff will be scheduled by outer layer */ 915 } 916 917 /** 918 * dpu_crtc_destroy_state - state destroy hook 919 * @crtc: drm CRTC 920 * @state: CRTC state object to release 921 */ 922 static void dpu_crtc_destroy_state(struct drm_crtc *crtc, 923 struct drm_crtc_state *state) 924 { 925 struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 926 927 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); 928 929 __drm_atomic_helper_crtc_destroy_state(state); 930 931 kfree(cstate); 932 } 933 934 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) 935 { 936 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 937 int ret, rc = 0; 938 939 if (!atomic_read(&dpu_crtc->frame_pending)) { 940 DRM_DEBUG_ATOMIC("no frames pending\n"); 941 return 0; 942 } 943 944 DPU_ATRACE_BEGIN("frame done completion wait"); 945 ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp, 946 msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS)); 947 if (!ret) { 948 DRM_ERROR("frame done wait timed out, ret:%d\n", ret); 949 rc = -ETIMEDOUT; 950 } 951 DPU_ATRACE_END("frame done completion wait"); 952 953 return rc; 954 } 955 956 static int dpu_crtc_kickoff_clone_mode(struct drm_crtc *crtc) 957 { 958 struct drm_encoder *encoder; 959 struct drm_encoder *rt_encoder = NULL, *wb_encoder = NULL; 960 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 961 962 /* Find encoder for real time display */ 963 drm_for_each_encoder_mask(encoder, crtc->dev, 964 crtc->state->encoder_mask) { 965 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) 966 wb_encoder = encoder; 967 else 968 rt_encoder = encoder; 969 } 970 971 if (!rt_encoder || !wb_encoder) { 972 DRM_DEBUG_ATOMIC("real time or wb encoder not found\n"); 973 return -EINVAL; 974 } 975 976 dpu_encoder_prepare_for_kickoff(wb_encoder); 977 dpu_encoder_prepare_for_kickoff(rt_encoder); 978 979 dpu_vbif_clear_errors(dpu_kms); 980 981 /* 982 * Kickoff real time encoder last as it's the encoder that 983 * will do the flush 984 */ 985 dpu_encoder_kickoff(wb_encoder); 986 dpu_encoder_kickoff(rt_encoder); 987 988 /* Don't start frame done timers until the kickoffs have finished */ 989 dpu_encoder_start_frame_done_timer(wb_encoder); 990 dpu_encoder_start_frame_done_timer(rt_encoder); 991 992 return 0; 993 } 994 995 /** 996 * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc 997 * @crtc: Pointer to drm crtc object 998 */ 999 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) 1000 { 1001 struct drm_encoder *encoder; 1002 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1003 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 1004 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 1005 1006 /* 1007 * If no mixers has been allocated in dpu_crtc_atomic_check(), 1008 * it means we are trying to start a CRTC whose state is disabled: 1009 * nothing else needs to be done. 1010 */ 1011 if (unlikely(!cstate->num_mixers)) 1012 return; 1013 1014 DPU_ATRACE_BEGIN("crtc_commit"); 1015 1016 drm_for_each_encoder_mask(encoder, crtc->dev, 1017 crtc->state->encoder_mask) { 1018 if (!dpu_encoder_is_valid_for_commit(encoder)) { 1019 DRM_DEBUG_ATOMIC("invalid FB not kicking off crtc\n"); 1020 goto end; 1021 } 1022 } 1023 1024 if (drm_crtc_in_clone_mode(crtc->state)) { 1025 if (dpu_crtc_kickoff_clone_mode(crtc)) 1026 goto end; 1027 } else { 1028 /* 1029 * Encoder will flush/start now, unless it has a tx pending. 1030 * If so, it may delay and flush at an irq event (e.g. ppdone) 1031 */ 1032 drm_for_each_encoder_mask(encoder, crtc->dev, 1033 crtc->state->encoder_mask) 1034 dpu_encoder_prepare_for_kickoff(encoder); 1035 1036 dpu_vbif_clear_errors(dpu_kms); 1037 1038 drm_for_each_encoder_mask(encoder, crtc->dev, 1039 crtc->state->encoder_mask) { 1040 dpu_encoder_kickoff(encoder); 1041 dpu_encoder_start_frame_done_timer(encoder); 1042 } 1043 } 1044 1045 if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { 1046 /* acquire bandwidth and other resources */ 1047 DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id); 1048 } else 1049 DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id); 1050 1051 dpu_crtc->play_count++; 1052 1053 reinit_completion(&dpu_crtc->frame_done_comp); 1054 1055 end: 1056 DPU_ATRACE_END("crtc_commit"); 1057 } 1058 1059 static void dpu_crtc_reset(struct drm_crtc *crtc) 1060 { 1061 struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); 1062 1063 if (crtc->state) 1064 dpu_crtc_destroy_state(crtc, crtc->state); 1065 1066 if (cstate) 1067 __drm_atomic_helper_crtc_reset(crtc, &cstate->base); 1068 else 1069 __drm_atomic_helper_crtc_reset(crtc, NULL); 1070 } 1071 1072 /** 1073 * dpu_crtc_duplicate_state - state duplicate hook 1074 * @crtc: Pointer to drm crtc structure 1075 */ 1076 static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) 1077 { 1078 struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state); 1079 1080 cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL); 1081 if (!cstate) { 1082 DPU_ERROR("failed to allocate state\n"); 1083 return NULL; 1084 } 1085 1086 /* duplicate base helper */ 1087 __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); 1088 1089 return &cstate->base; 1090 } 1091 1092 static void dpu_crtc_atomic_print_state(struct drm_printer *p, 1093 const struct drm_crtc_state *state) 1094 { 1095 const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 1096 int i; 1097 1098 for (i = 0; i < cstate->num_mixers; i++) { 1099 drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0); 1100 drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0); 1101 if (cstate->mixers[i].hw_dspp) 1102 drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0); 1103 } 1104 } 1105 1106 static void dpu_crtc_disable(struct drm_crtc *crtc, 1107 struct drm_atomic_state *state) 1108 { 1109 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1110 crtc); 1111 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1112 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 1113 struct drm_encoder *encoder; 1114 unsigned long flags; 1115 bool release_bandwidth = false; 1116 1117 DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 1118 1119 /* If disable is triggered while in self refresh mode, 1120 * reset the encoder software state so that in enable 1121 * it won't trigger a warn while assigning crtc. 1122 */ 1123 if (old_crtc_state->self_refresh_active) { 1124 drm_for_each_encoder_mask(encoder, crtc->dev, 1125 old_crtc_state->encoder_mask) { 1126 dpu_encoder_assign_crtc(encoder, NULL); 1127 } 1128 return; 1129 } 1130 1131 /* Disable/save vblank irq handling */ 1132 drm_crtc_vblank_off(crtc); 1133 1134 drm_for_each_encoder_mask(encoder, crtc->dev, 1135 old_crtc_state->encoder_mask) { 1136 /* in video mode, we hold an extra bandwidth reference 1137 * as we cannot drop bandwidth at frame-done if any 1138 * crtc is being used in video mode. 1139 */ 1140 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO) 1141 release_bandwidth = true; 1142 1143 /* 1144 * If disable is triggered during psr active(e.g: screen dim in PSR), 1145 * we will need encoder->crtc connection to process the device sleep & 1146 * preserve it during psr sequence. 1147 */ 1148 if (!crtc->state->self_refresh_active) 1149 dpu_encoder_assign_crtc(encoder, NULL); 1150 } 1151 1152 /* wait for frame_event_done completion */ 1153 if (_dpu_crtc_wait_for_frame_done(crtc)) 1154 DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 1155 crtc->base.id, 1156 atomic_read(&dpu_crtc->frame_pending)); 1157 1158 trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc); 1159 dpu_crtc->enabled = false; 1160 1161 if (atomic_read(&dpu_crtc->frame_pending)) { 1162 trace_dpu_crtc_disable_frame_pending(DRMID(crtc), 1163 atomic_read(&dpu_crtc->frame_pending)); 1164 if (release_bandwidth) 1165 dpu_core_perf_crtc_release_bw(crtc); 1166 atomic_set(&dpu_crtc->frame_pending, 0); 1167 } 1168 1169 dpu_core_perf_crtc_update(crtc, 0); 1170 1171 /* disable clk & bw control until clk & bw properties are set */ 1172 cstate->bw_control = false; 1173 cstate->bw_split_vote = false; 1174 1175 if (crtc->state->event && !crtc->state->active) { 1176 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1177 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1178 crtc->state->event = NULL; 1179 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1180 } 1181 1182 pm_runtime_put_sync(crtc->dev->dev); 1183 } 1184 1185 static void dpu_crtc_enable(struct drm_crtc *crtc, 1186 struct drm_atomic_state *state) 1187 { 1188 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1189 struct drm_encoder *encoder; 1190 bool request_bandwidth = false; 1191 struct drm_crtc_state *old_crtc_state; 1192 1193 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 1194 1195 pm_runtime_get_sync(crtc->dev->dev); 1196 1197 DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 1198 1199 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { 1200 /* in video mode, we hold an extra bandwidth reference 1201 * as we cannot drop bandwidth at frame-done if any 1202 * crtc is being used in video mode. 1203 */ 1204 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO) 1205 request_bandwidth = true; 1206 } 1207 1208 if (request_bandwidth) 1209 atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); 1210 1211 trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); 1212 dpu_crtc->enabled = true; 1213 1214 if (!old_crtc_state->self_refresh_active) { 1215 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 1216 dpu_encoder_assign_crtc(encoder, crtc); 1217 } 1218 1219 /* Enable/restore vblank irq handling */ 1220 drm_crtc_vblank_on(crtc); 1221 } 1222 1223 static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) 1224 { 1225 struct drm_crtc *crtc = cstate->crtc; 1226 struct drm_encoder *encoder; 1227 1228 if (cstate->self_refresh_active) 1229 return true; 1230 1231 drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) { 1232 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) { 1233 return true; 1234 } 1235 } 1236 1237 return false; 1238 } 1239 1240 static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 1241 { 1242 int total_planes = crtc->dev->mode_config.num_total_plane; 1243 struct drm_atomic_state *state = crtc_state->state; 1244 struct dpu_global_state *global_state; 1245 struct drm_plane_state **states; 1246 struct drm_plane *plane; 1247 int ret; 1248 1249 global_state = dpu_kms_get_global_state(crtc_state->state); 1250 if (IS_ERR(global_state)) 1251 return PTR_ERR(global_state); 1252 1253 dpu_rm_release_all_sspp(global_state, crtc); 1254 1255 if (!crtc_state->enable) 1256 return 0; 1257 1258 states = kcalloc(total_planes, sizeof(*states), GFP_KERNEL); 1259 if (!states) 1260 return -ENOMEM; 1261 1262 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1263 struct drm_plane_state *plane_state = 1264 drm_atomic_get_plane_state(state, plane); 1265 1266 if (IS_ERR(plane_state)) { 1267 ret = PTR_ERR(plane_state); 1268 goto done; 1269 } 1270 1271 states[plane_state->normalized_zpos] = plane_state; 1272 } 1273 1274 ret = dpu_assign_plane_resources(global_state, state, crtc, states, total_planes); 1275 1276 done: 1277 kfree(states); 1278 return ret; 1279 } 1280 1281 #define MAX_CHANNELS_PER_CRTC 2 1282 #define MAX_HDISPLAY_SPLIT 1080 1283 1284 static struct msm_display_topology dpu_crtc_get_topology( 1285 struct drm_crtc *crtc, 1286 struct dpu_kms *dpu_kms, 1287 struct drm_crtc_state *crtc_state) 1288 { 1289 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1290 struct msm_display_topology topology = {0}; 1291 struct drm_encoder *drm_enc; 1292 1293 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) 1294 dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, 1295 &crtc_state->adjusted_mode); 1296 1297 topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state); 1298 1299 /* 1300 * Datapath topology selection 1301 * 1302 * Dual display 1303 * 2 LM, 2 INTF ( Split display using 2 interfaces) 1304 * 1305 * Single display 1306 * 1 LM, 1 INTF 1307 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 1308 * 1309 * If DSC is enabled, use 2 LMs for 2:2:1 topology 1310 * 1311 * Add dspps to the reservation requirements if ctm is requested 1312 * 1313 * Only hardcode num_lm to 2 for cases where num_intf == 2 and CWB is not 1314 * enabled. This is because in cases where CWB is enabled, num_intf will 1315 * count both the WB and real-time phys encoders. 1316 * 1317 * For non-DSC CWB usecases, have the num_lm be decided by the 1318 * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. 1319 */ 1320 1321 if (topology.num_intf == 2 && !topology.cwb_enabled) 1322 topology.num_lm = 2; 1323 else if (topology.num_dsc == 2) 1324 topology.num_lm = 2; 1325 else if (dpu_kms->catalog->caps->has_3d_merge) 1326 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 1327 else 1328 topology.num_lm = 1; 1329 1330 if (crtc_state->ctm) 1331 topology.num_dspp = topology.num_lm; 1332 1333 return topology; 1334 } 1335 1336 static int dpu_crtc_assign_resources(struct drm_crtc *crtc, 1337 struct drm_crtc_state *crtc_state) 1338 { 1339 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; 1340 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC]; 1341 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC]; 1342 int i, num_lm, num_ctl, num_dspp; 1343 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 1344 struct dpu_global_state *global_state; 1345 struct dpu_crtc_state *cstate; 1346 struct msm_display_topology topology; 1347 int ret; 1348 1349 /* 1350 * Release and Allocate resources on every modeset 1351 */ 1352 global_state = dpu_kms_get_global_state(crtc_state->state); 1353 if (IS_ERR(global_state)) 1354 return PTR_ERR(global_state); 1355 1356 dpu_rm_release(global_state, crtc); 1357 1358 if (!crtc_state->enable) 1359 return 0; 1360 1361 topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state); 1362 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 1363 crtc_state->crtc, &topology); 1364 if (ret) 1365 return ret; 1366 1367 cstate = to_dpu_crtc_state(crtc_state); 1368 1369 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1370 crtc_state->crtc, 1371 DPU_HW_BLK_CTL, hw_ctl, 1372 ARRAY_SIZE(hw_ctl)); 1373 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1374 crtc_state->crtc, 1375 DPU_HW_BLK_LM, hw_lm, 1376 ARRAY_SIZE(hw_lm)); 1377 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1378 crtc_state->crtc, 1379 DPU_HW_BLK_DSPP, hw_dspp, 1380 ARRAY_SIZE(hw_dspp)); 1381 1382 for (i = 0; i < num_lm; i++) { 1383 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 1384 1385 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 1386 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 1387 if (i < num_dspp) 1388 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); 1389 } 1390 1391 cstate->num_mixers = num_lm; 1392 1393 return 0; 1394 } 1395 1396 /** 1397 * dpu_crtc_check_mode_changed: check if full modeset is required 1398 * @old_crtc_state: Previous CRTC state 1399 * @new_crtc_state: Corresponding CRTC state to be checked 1400 * 1401 * Check if the changes in the object properties demand full mode set. 1402 */ 1403 int dpu_crtc_check_mode_changed(struct drm_crtc_state *old_crtc_state, 1404 struct drm_crtc_state *new_crtc_state) 1405 { 1406 struct drm_encoder *drm_enc; 1407 struct drm_crtc *crtc = new_crtc_state->crtc; 1408 bool clone_mode_enabled = drm_crtc_in_clone_mode(old_crtc_state); 1409 bool clone_mode_requested = drm_crtc_in_clone_mode(new_crtc_state); 1410 1411 DRM_DEBUG_ATOMIC("%d\n", crtc->base.id); 1412 1413 /* there might be cases where encoder needs a modeset too */ 1414 drm_for_each_encoder_mask(drm_enc, crtc->dev, new_crtc_state->encoder_mask) { 1415 if (dpu_encoder_needs_modeset(drm_enc, new_crtc_state->state)) 1416 new_crtc_state->mode_changed = true; 1417 } 1418 1419 if ((clone_mode_requested && !clone_mode_enabled) || 1420 (!clone_mode_requested && clone_mode_enabled)) 1421 new_crtc_state->mode_changed = true; 1422 1423 return 0; 1424 } 1425 1426 static int dpu_crtc_atomic_check(struct drm_crtc *crtc, 1427 struct drm_atomic_state *state) 1428 { 1429 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1430 crtc); 1431 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1432 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); 1433 1434 const struct drm_plane_state *pstate; 1435 struct drm_plane *plane; 1436 1437 int rc = 0; 1438 1439 bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); 1440 1441 /* don't reallocate resources if only ACTIVE has beeen changed */ 1442 if (crtc_state->mode_changed || crtc_state->connectors_changed) { 1443 rc = dpu_crtc_assign_resources(crtc, crtc_state); 1444 if (rc < 0) 1445 return rc; 1446 } 1447 1448 if (dpu_use_virtual_planes && 1449 (crtc_state->planes_changed || crtc_state->zpos_changed)) { 1450 rc = dpu_crtc_reassign_planes(crtc, crtc_state); 1451 if (rc < 0) 1452 return rc; 1453 } 1454 1455 if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { 1456 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", 1457 crtc->base.id, crtc_state->enable, 1458 crtc_state->active); 1459 memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); 1460 return 0; 1461 } 1462 1463 DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name); 1464 1465 if (cstate->num_mixers) { 1466 rc = _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc_state); 1467 if (rc) 1468 return rc; 1469 } 1470 1471 /* FIXME: move this to dpu_plane_atomic_check? */ 1472 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { 1473 struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); 1474 1475 if (IS_ERR_OR_NULL(pstate)) { 1476 rc = PTR_ERR(pstate); 1477 DPU_ERROR("%s: failed to get plane%d state, %d\n", 1478 dpu_crtc->name, plane->base.id, rc); 1479 return rc; 1480 } 1481 1482 if (!pstate->visible) 1483 continue; 1484 1485 dpu_pstate->needs_dirtyfb = needs_dirtyfb; 1486 } 1487 1488 atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); 1489 1490 rc = dpu_core_perf_crtc_check(crtc, crtc_state); 1491 if (rc) { 1492 DPU_ERROR("crtc%d failed performance check %d\n", 1493 crtc->base.id, rc); 1494 return rc; 1495 } 1496 1497 return 0; 1498 } 1499 1500 static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc, 1501 const struct drm_display_mode *mode) 1502 { 1503 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 1504 1505 /* if there is no 3d_mux block we cannot merge LMs so we cannot 1506 * split the large layer into 2 LMs, filter out such modes 1507 */ 1508 if (!dpu_kms->catalog->caps->has_3d_merge && 1509 mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) 1510 return MODE_BAD_HVALUE; 1511 /* 1512 * max crtc width is equal to the max mixer width * 2 and max height is 4K 1513 */ 1514 return drm_mode_validate_size(mode, 1515 2 * dpu_kms->catalog->caps->max_mixer_width, 1516 4096); 1517 } 1518 1519 /** 1520 * dpu_crtc_vblank - enable or disable vblanks for this crtc 1521 * @crtc: Pointer to drm crtc object 1522 * @en: true to enable vblanks, false to disable 1523 */ 1524 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 1525 { 1526 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1527 struct drm_encoder *enc; 1528 1529 trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); 1530 1531 /* 1532 * Normally we would iterate through encoder_mask in crtc state to find 1533 * attached encoders. In this case, we might be disabling vblank _after_ 1534 * encoder_mask has been cleared. 1535 * 1536 * Instead, we "assign" a crtc to the encoder in enable and clear it in 1537 * disable (which is also after encoder_mask is cleared). So instead of 1538 * using encoder mask, we'll ask the encoder to toggle itself iff it's 1539 * currently assigned to our crtc. 1540 * 1541 * Note also that this function cannot be called while crtc is disabled 1542 * since we use drm_crtc_vblank_on/off. So we don't need to worry 1543 * about the assigned crtcs being inconsistent with the current state 1544 * (which means no need to worry about modeset locks). 1545 */ 1546 list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { 1547 trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en, 1548 dpu_crtc); 1549 1550 dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en); 1551 } 1552 1553 return 0; 1554 } 1555 1556 #ifdef CONFIG_DEBUG_FS 1557 static int _dpu_debugfs_status_show(struct seq_file *s, void *data) 1558 { 1559 struct dpu_crtc *dpu_crtc; 1560 struct dpu_plane_state *pstate = NULL; 1561 struct dpu_crtc_mixer *m; 1562 1563 struct drm_crtc *crtc; 1564 struct drm_plane *plane; 1565 struct drm_display_mode *mode; 1566 struct drm_framebuffer *fb; 1567 struct drm_plane_state *state; 1568 struct dpu_crtc_state *cstate; 1569 1570 int i, out_width; 1571 1572 dpu_crtc = s->private; 1573 crtc = &dpu_crtc->base; 1574 1575 drm_modeset_lock_all(crtc->dev); 1576 cstate = to_dpu_crtc_state(crtc->state); 1577 1578 mode = &crtc->state->adjusted_mode; 1579 out_width = mode->hdisplay / cstate->num_mixers; 1580 1581 seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, 1582 mode->hdisplay, mode->vdisplay); 1583 1584 seq_puts(s, "\n"); 1585 1586 for (i = 0; i < cstate->num_mixers; ++i) { 1587 m = &cstate->mixers[i]; 1588 seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", 1589 m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, 1590 out_width, mode->vdisplay); 1591 } 1592 1593 seq_puts(s, "\n"); 1594 1595 drm_atomic_crtc_for_each_plane(plane, crtc) { 1596 pstate = to_dpu_plane_state(plane->state); 1597 state = plane->state; 1598 1599 if (!pstate || !state) 1600 continue; 1601 1602 seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, 1603 pstate->stage); 1604 1605 if (plane->state->fb) { 1606 fb = plane->state->fb; 1607 1608 seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ", 1609 fb->base.id, (char *) &fb->format->format, 1610 fb->width, fb->height); 1611 for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i) 1612 seq_printf(s, "cpp[%d]:%u ", 1613 i, fb->format->cpp[i]); 1614 seq_puts(s, "\n\t"); 1615 1616 seq_printf(s, "modifier:%8llu ", fb->modifier); 1617 seq_puts(s, "\n"); 1618 1619 seq_puts(s, "\t"); 1620 for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) 1621 seq_printf(s, "pitches[%d]:%8u ", i, 1622 fb->pitches[i]); 1623 seq_puts(s, "\n"); 1624 1625 seq_puts(s, "\t"); 1626 for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) 1627 seq_printf(s, "offsets[%d]:%8u ", i, 1628 fb->offsets[i]); 1629 seq_puts(s, "\n"); 1630 } 1631 1632 seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", 1633 state->src_x, state->src_y, state->src_w, state->src_h); 1634 1635 seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", 1636 state->crtc_x, state->crtc_y, state->crtc_w, 1637 state->crtc_h); 1638 seq_printf(s, "\tsspp[0]:%s\n", 1639 pstate->pipe.sspp->cap->name); 1640 seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", 1641 pstate->pipe.multirect_mode, pstate->pipe.multirect_index); 1642 if (pstate->r_pipe.sspp) { 1643 seq_printf(s, "\tsspp[1]:%s\n", 1644 pstate->r_pipe.sspp->cap->name); 1645 seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", 1646 pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); 1647 } 1648 1649 seq_puts(s, "\n"); 1650 } 1651 if (dpu_crtc->vblank_cb_count) { 1652 ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time); 1653 s64 diff_ms = ktime_to_ms(diff); 1654 s64 fps = diff_ms ? div_s64( 1655 dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0; 1656 1657 seq_printf(s, 1658 "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", 1659 fps, dpu_crtc->vblank_cb_count, 1660 ktime_to_ms(diff), dpu_crtc->play_count); 1661 1662 /* reset time & count for next measurement */ 1663 dpu_crtc->vblank_cb_count = 0; 1664 dpu_crtc->vblank_cb_time = ktime_set(0, 0); 1665 } 1666 1667 drm_modeset_unlock_all(crtc->dev); 1668 1669 return 0; 1670 } 1671 1672 DEFINE_SHOW_ATTRIBUTE(_dpu_debugfs_status); 1673 1674 static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) 1675 { 1676 struct drm_crtc *crtc = s->private; 1677 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1678 1679 seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); 1680 seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); 1681 seq_printf(s, "core_clk_rate: %llu\n", 1682 dpu_crtc->cur_perf.core_clk_rate); 1683 seq_printf(s, "bw_ctl: %uk\n", 1684 (u32)DIV_ROUND_UP_ULL(dpu_crtc->cur_perf.bw_ctl, 1000)); 1685 seq_printf(s, "max_per_pipe_ib: %u\n", 1686 dpu_crtc->cur_perf.max_per_pipe_ib); 1687 1688 return 0; 1689 } 1690 DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state); 1691 1692 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 1693 { 1694 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1695 1696 debugfs_create_file("status", 0400, 1697 crtc->debugfs_entry, 1698 dpu_crtc, &_dpu_debugfs_status_fops); 1699 debugfs_create_file("state", 0600, 1700 crtc->debugfs_entry, 1701 &dpu_crtc->base, 1702 &dpu_crtc_debugfs_state_fops); 1703 1704 return 0; 1705 } 1706 #else 1707 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 1708 { 1709 return 0; 1710 } 1711 #endif /* CONFIG_DEBUG_FS */ 1712 1713 static int dpu_crtc_late_register(struct drm_crtc *crtc) 1714 { 1715 return _dpu_crtc_init_debugfs(crtc); 1716 } 1717 1718 static const struct drm_crtc_funcs dpu_crtc_funcs = { 1719 .set_config = drm_atomic_helper_set_config, 1720 .page_flip = drm_atomic_helper_page_flip, 1721 .reset = dpu_crtc_reset, 1722 .atomic_duplicate_state = dpu_crtc_duplicate_state, 1723 .atomic_destroy_state = dpu_crtc_destroy_state, 1724 .atomic_print_state = dpu_crtc_atomic_print_state, 1725 .late_register = dpu_crtc_late_register, 1726 .verify_crc_source = dpu_crtc_verify_crc_source, 1727 .set_crc_source = dpu_crtc_set_crc_source, 1728 .enable_vblank = msm_crtc_enable_vblank, 1729 .disable_vblank = msm_crtc_disable_vblank, 1730 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1731 .get_vblank_counter = dpu_crtc_get_vblank_counter, 1732 }; 1733 1734 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { 1735 .atomic_disable = dpu_crtc_disable, 1736 .atomic_enable = dpu_crtc_enable, 1737 .atomic_check = dpu_crtc_atomic_check, 1738 .atomic_begin = dpu_crtc_atomic_begin, 1739 .atomic_flush = dpu_crtc_atomic_flush, 1740 .mode_valid = dpu_crtc_mode_valid, 1741 .get_scanout_position = dpu_crtc_get_scanout_position, 1742 }; 1743 1744 /** 1745 * dpu_crtc_init - create a new crtc object 1746 * @dev: dpu device 1747 * @plane: base plane 1748 * @cursor: cursor plane 1749 * @return: new crtc object or error 1750 * 1751 * initialize CRTC 1752 */ 1753 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 1754 struct drm_plane *cursor) 1755 { 1756 struct msm_drm_private *priv = dev->dev_private; 1757 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1758 struct drm_crtc *crtc = NULL; 1759 struct dpu_crtc *dpu_crtc; 1760 int i, ret; 1761 1762 dpu_crtc = drmm_crtc_alloc_with_planes(dev, struct dpu_crtc, base, 1763 plane, cursor, 1764 &dpu_crtc_funcs, 1765 NULL); 1766 1767 if (IS_ERR(dpu_crtc)) 1768 return ERR_CAST(dpu_crtc); 1769 1770 crtc = &dpu_crtc->base; 1771 crtc->dev = dev; 1772 1773 spin_lock_init(&dpu_crtc->spin_lock); 1774 atomic_set(&dpu_crtc->frame_pending, 0); 1775 1776 init_completion(&dpu_crtc->frame_done_comp); 1777 1778 INIT_LIST_HEAD(&dpu_crtc->frame_event_list); 1779 1780 for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) { 1781 INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list); 1782 list_add(&dpu_crtc->frame_events[i].list, 1783 &dpu_crtc->frame_event_list); 1784 kthread_init_work(&dpu_crtc->frame_events[i].work, 1785 dpu_crtc_frame_event_work); 1786 } 1787 1788 drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); 1789 1790 if (dpu_kms->catalog->dspp_count) 1791 drm_crtc_enable_color_mgmt(crtc, 0, true, 0); 1792 1793 /* save user friendly CRTC name for later */ 1794 snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); 1795 1796 /* initialize event handling */ 1797 spin_lock_init(&dpu_crtc->event_lock); 1798 1799 ret = drm_self_refresh_helper_init(crtc); 1800 if (ret) { 1801 DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n", 1802 crtc->name, ret); 1803 return ERR_PTR(ret); 1804 } 1805 1806 DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name); 1807 return crtc; 1808 } 1809