1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014 QLogic Corporation
24 * The contents of this file are subject to the terms of the
25 * QLogic End User License (the "License").
26 * You may not use this file except in compliance with the License.
27 *
28 * You can obtain a copy of the License at
29 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
30 * QLogic_End_User_Software_License.txt
31 * See the License for the specific language governing permissions
32 * and limitations under the License.
33 */
34
35 /*
36 * Copyright (c) 2002, 2011, Oracle and/or its affiliates. All rights reserved.
37 */
38
39 #ifndef BNXE_H
40 #define BNXE_H
41
42 #include <sys/types.h>
43 #include <sys/stream.h>
44 #include <sys/stropts.h>
45 #include <sys/errno.h>
46 #include <sys/cred.h>
47 #include <sys/poll.h>
48 #include <sys/modctl.h>
49 #include <sys/mac.h>
50 #include <sys/mac_provider.h>
51 #include <sys/stat.h>
52 #include <sys/ddi.h>
53 #include <sys/sunddi.h>
54 #include <sys/sunndi.h>
55 #include <sys/ddifm.h>
56 #include <sys/fm/protocol.h>
57 #include <sys/fm/util.h>
58 #include <sys/fm/io/ddi.h>
59 #include <sys/pattr.h>
60 #include <sys/sysmacros.h>
61 #include <sys/ethernet.h>
62 //#include <sys/vlan.h>
63 #include <sys/strsun.h>
64 #include <sys/ksynch.h>
65 #include <sys/kstat.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #include <netinet/udp.h>
69 #include <netinet/tcp.h>
70 #include <inet/common.h>
71 #include <inet/ip.h>
72 #include <inet/ip_if.h>
73 #include <sys/strsubr.h>
74 #include <sys/pci.h>
75 #include <sys/gld.h>
76
77 /*
78 * This really ticks me off! We use 'u' for naming unions
79 * within structures. Why is 'u' a reserved word!?!?!?
80 * http://bugs.opensolaris.org/view_bug.do?bug_id=4340073
81 * This undef has been moved to bnxe_debug.h.
82 */
83 //#undef u
84
85 #include "version.h"
86 #include "debug.h"
87 #include "bcmtype.h"
88 #include "lm_defs.h"
89 #include "listq.h"
90 #include "lm5710.h"
91 #include "lm.h"
92 #include "bd_chain.h"
93 #if !defined(__SunOS_MDB)
94 #include "command.h"
95 #endif
96 #include "bnxe_binding.h"
97 #if !defined(DBG) && !defined(__SunOS_MDB)
98 #include "bnxe_debug.h" /* wasn't included by debug.h */
99 #endif
100
101 #ifndef VLAN_TAGSZ
102 #define VLAN_TAGSZ 4
103 #endif
104
105 #define BNXE_RINGS
106 #define RSS_ID_NONE -1
107
108 #define USER_OPTION_CKSUM_NONE 0x0
109 #define USER_OPTION_CKSUM_L3 0x1
110 #define USER_OPTION_CKSUM_L3_L4 0x2
111 #define USER_OPTION_CKSUM_DEFAULT USER_OPTION_CKSUM_L3_L4
112
113 #define USER_OPTION_MTU_MIN 60
114 #define USER_OPTION_MTU_MAX 9216
115 #define USER_OPTION_MTU_DEFAULT 1500
116
117 #define USER_OPTION_NUM_RINGS_MIN 0
118 #define USER_OPTION_NUM_RINGS_MAX MAX_RSS_CHAINS
119 #define USER_OPTION_NUM_RINGS_DEFAULT_MF 1
120 #define USER_OPTION_NUM_RINGS_DEFAULT_SF 4
121 #define USER_OPTION_NUM_RINGS_DEFAULT 0
122
123 #define USER_OPTION_RX_RING_GROUPS_MIN 1
124 #define USER_OPTION_RX_RING_GROUPS_MAX 1
125 #define USER_OPTION_RX_RING_GROUPS_DEFAULT 1
126
127 #define USER_OPTION_BDS_MIN 1
128 #define USER_OPTION_BDS_MAX 32767
129 #define USER_OPTION_RX_BDS_DEFAULT 1024
130 #define USER_OPTION_TX_BDS_DEFAULT 1024
131 #define USER_OPTION_MF_BDS_DIVISOR 4
132
133 #define USER_OPTION_INTR_COALESCE_MIN 10 /* usecs */
134 #define USER_OPTION_INTR_COALESCE_MAX 1000
135 #define USER_OPTION_INTR_COALESCE_RX_DEFAULT 20
136 #define USER_OPTION_INTR_COALESCE_TX_DEFAULT 40
137
138 #define USER_OPTION_TX_MAX_FREE_DEFAULT 32
139 #define USER_OPTION_RX_MAX_FREE_DEFAULT 32
140
141 //#define USER_OPTION_RX_DCOPY_THRESH_DEFAULT 0xffffffff
142 #define USER_OPTION_RX_DCOPY_THRESH_DEFAULT 128
143
144 //#define USER_OPTION_TX_DCOPY_THRESH_DEFAULT 0
145 #define USER_OPTION_TX_DCOPY_THRESH_DEFAULT 512
146
147 //#define BNXE_IP_MAXLEN 65535
148 #define BNXE_IP_MAXLEN 32768 /* 32768 = PAGESIZE * (BNXE_MAX_DMA_FRAGS_PER_PKT - 2 ) */
149 #define BNXE_OPTION_LEN 80 /* room for IP/TCP options (max 40 bytes each) */
150 #define BNXE_PKTHDR_LEN (sizeof(struct ether_vlan_header) + sizeof(struct ip) + sizeof(struct tcphdr) + BNXE_OPTION_LEN)
151 #define BNXE_LSO_MAXLEN (BNXE_IP_MAXLEN + sizeof(struct ether_vlan_header) - BNXE_PKTHDR_LEN) /* maximum payload */
152
153 #define BNXE_MAGIC 0x0feedead
154 #define BNXE_MEM_CHECK_LEN 16
155 #define BNXE_STR_SIZE 32
156
157 #define BNXEF_NAME "bnxef"
158
159 #define BNXE_FCOE(dev) ((um_device_t *)(dev))->do_fcoe
160
161 #ifdef __sparc
162 #define BNXE_DMA_ALIGNMENT 0x2000UL
163 #else
164 #define BNXE_DMA_ALIGNMENT 0x1000UL
165 #endif
166
167 /*
168 * Adding a two byte offset to the receive buffer aligns the IP header on a
169 * 16 byte boundary and it would put the TCP payload (assuming a 20 byte IP
170 * header and 20 byte TCP header) on an 8 byte boundary.
171 */
172 #define BNXE_DMA_RX_OFFSET 2
173
174 /*
175 * The following two defines are used for defining limits on Tx packets.
176 * BNXE_MAX_DMA_HANDLES_PER_PKT is the maximum number of DMA handles that are
177 * pre-allocated for every Tx buffer descriptor. These DMA handles are used
178 * for mapping each mblk in the chain when not double copying the packet data
179 * into the copy buffer. BNXE_MAX_DMA_FRAGS_PER_PKT is based on the hardware
180 * and represents the maximum number of fragments an outgoing packet can have.
181 * Note that a single DMA handle can be comprised of multiple fragments which
182 * is very likely with LSO.
183 *
184 * As seen below BNXE_MAX_DMA_FRAGS_PER_PKT is set to 10. The actual firmware
185 * limit is 13 but 10 is chosen specifically for the case of LSO packets that
186 * are broken up across a long mblk chain. The firmware utilizes a sliding
187 * window on a packet's assigned buffer descriptors for LSO. The window is 10
188 * bds and each window (i.e. bds 1-10, 2-11, 3-12, etc), except the window
189 * containing the last bd, must contains at least MSS bytes. There are 'rare'
190 * cases where a packet sent down by the stack will not satisfy this window
191 * size requirement. Therefore, setting the frag limit to 10 results in any
192 * long chained packet (i.e. greater than 10 mblks), the trailing mblks will
193 * get double copied into a single copy buffer and will be pointed to by the
194 * last bd. This simple change will ensure the sliding window requirement is
195 * always satisfied. Note, LSO packets with long mblk chains are a rare
196 * occurance (nicdrv test01 can trigger it).
197 */
198 #define BNXE_MAX_DMA_HANDLES_PER_PKT 11 /* go easy on DMA resources */
199 #define BNXE_MAX_DMA_FRAGS_PER_PKT 10 /* set BNXE_IP_MAXLEN above accordingly */
200 #define BNXE_MAX_DMA_SGLLEN 20 /* for partial dma mapping */
201
202 #define BNXE_PDWM_THRESHOLD 8
203
204 #define BNXE_TX_RESOURCES_NO_CREDIT 0x01
205 #define BNXE_TX_RESOURCES_NO_DESC 0x02
206 #define BNXE_TX_RESOURCES_NO_DRV_DMA_RES 0x04 /* Out of Tx DMA handles */
207 #define BNXE_TX_RESOURCES_NO_OS_DMA_RES 0x08 /* Unable to allocate DMA resources. (e.g. bind error) */
208 #define BNXE_TX_RESOURCES_TOO_MANY_FRAGS 0x10
209
210 #define BNXE_TX_GOODXMIT 0
211 #define BNXE_TX_LINKDOWN 1
212 #define BNXE_TX_DEFERPKT 2
213 #define BNXE_TX_HDWRFULL 3
214 #define BNXE_TX_PKTERROR 4
215
216 #define BNXE_ROUTE_RING_NONE 0
217 #define BNXE_ROUTE_RING_TCPUDP 1
218 #define BNXE_ROUTE_RING_DEST_MAC 2
219 #define BNXE_ROUTE_RING_MSG_PRIO 3
220
221 #undef BNXE_DEBUG_DMA_LIST
222
223 extern ddi_device_acc_attr_t bnxeAccessAttribBAR;
224 extern ddi_device_acc_attr_t bnxeAccessAttribBUF;
225
226 typedef struct _BnxeDevParams
227 {
228 u32_t fw_ver;
229
230 u32_t mtu[LM_CLI_IDX_MAX];
231
232 u32_t routeTxRingPolicy;
233 u32_t numRings; /* number of rings */
234 u32_t numRxDesc[LM_CLI_IDX_MAX]; /* number of RX descriptors */
235 u32_t numTxDesc[LM_CLI_IDX_MAX]; /* number of TX descriptors */
236 u32_t maxRxFree; /* max free allowed before posting back */
237 u32_t maxTxFree; /* max free allowed before posting back */
238
239 boolean_t intrCoalesce;
240 u32_t intrRxPerSec;
241 u32_t intrTxPerSec;
242 boolean_t disableMsix;
243
244 boolean_t l2_fw_flow_ctrl;
245 boolean_t autogreeenEnable;
246
247 u32_t rxCopyThreshold;
248 u32_t txCopyThreshold;
249
250 lm_rx_mask_t rx_filter_mask[LM_CLI_IDX_MAX];
251
252 int checksum;
253 lm_offload_t enabled_oflds;
254
255 boolean_t lsoEnable;
256
257 boolean_t logEnable;
258
259 boolean_t fcoeEnable;
260
261 boolean_t linkRemoteFaultDetect;
262
263 lm_status_t lastIndLink;
264 lm_medium_t lastIndMedium;
265
266 uint32_t debug_level;
267 } BnxeDevParams;
268
269
270 typedef struct _BnxeLinkCfg
271 {
272 boolean_t link_autoneg;
273 boolean_t param_20000fdx;
274 boolean_t param_10000fdx;
275 boolean_t param_2500fdx;
276 boolean_t param_1000fdx;
277 boolean_t param_100fdx;
278 boolean_t param_100hdx;
279 boolean_t param_10fdx;
280 boolean_t param_10hdx;
281 boolean_t param_txpause;
282 boolean_t param_rxpause;
283 } BnxeLinkCfg;
284
285
286 typedef struct _BnxePhyCfg
287 {
288 BnxeLinkCfg lnkcfg;
289 boolean_t flow_autoneg;
290 u32_t supported[ELINK_LINK_CONFIG_SIZE];
291 u32_t phy_cfg_size;
292 } BnxePhyCfg;
293
294
295 typedef struct _BnxeProps
296 {
297 u32_t link_speed;
298 boolean_t link_duplex;
299 boolean_t link_txpause;
300 boolean_t link_rxpause;
301 time_t uptime;
302 } BnxeProps;
303
304
305 typedef struct _BnxeMemBlock
306 {
307 d_list_entry_t link;
308 u32_t size;
309 void * pBuf;
310 char fileName[128];
311 u32_t fileLine;
312 } BnxeMemBlock;
313
314
315 typedef struct _BnxeMemDma
316 {
317 d_list_entry_t link;
318 u32_t size;
319 void * pDmaVirt;
320 ddi_dma_handle_t dmaHandle;
321 ddi_acc_handle_t dmaAccHandle;
322 lm_address_t physAddr;
323 char fileName[128];
324 u32_t fileLine;
325 } BnxeMemDma;
326
327
328 typedef struct _BnxeMemRegion
329 {
330 d_list_entry_t link;
331 lm_address_t baseAddr;
332 u32_t regNumber;
333 offset_t offset;
334 u32_t size;
335 ddi_acc_handle_t regAccess;
336 caddr_t pRegAddr;
337 } BnxeMemRegion;
338
339
340 typedef struct _um_txpacket_t
341 {
342 lm_packet_t lm_pkt; /* must be the first entry */
343 lm_pkt_tx_info_t tx_info;
344
345 mblk_t * pMblk;
346
347 ddi_dma_handle_t cbDmaHandle; /* cb = copy buffer */
348 ddi_acc_handle_t cbDmaAccHandle;
349 caddr_t pCbBuf;
350 lm_address_t cbPhysAddr;
351
352 u32_t cbLength;
353 u32_t num_handles; /* number of handles used for pkt */
354 ddi_dma_handle_t dmaHandles[BNXE_MAX_DMA_HANDLES_PER_PKT];
355
356 lm_frag_list_t frag_list;
357 lm_frag_t frag_list_buffer[BNXE_MAX_DMA_FRAGS_PER_PKT];
358 } um_txpacket_t;
359
360
361 typedef struct _TxQueue
362 {
363 void * pUM; /* backpointer to um_device_t */
364 u32_t idx; /* this ring's index */
365
366 mac_ring_handle_t ringHandle;
367
368 u32_t desc_cnt; /* number of Tx descriptors */
369
370 u32_t txFailed;
371 u32_t txDiscards;
372 u32_t txRecycle;
373 u32_t txCopied;
374 u32_t txBlocked;
375 u32_t txWait;
376 u32_t txLowWater;
377
378 u32_t thresh_pdwm; /* low resource water marks */
379
380 kmutex_t txMutex;
381
382 s_list_t sentTxQ; /* bds that have been sent and are ready to be freed */
383
384 kmutex_t freeTxDescMutex;
385 s_list_t freeTxDescQ; /* bds that are free for use */
386
387 s_list_t waitTxDescQ; /* bds that are setup and waiting for tx (lock w/ tx mutex) */
388
389 u32_t noTxCredits;
390 } TxQueue;
391
392
393 typedef struct _um_rxpacket_t
394 {
395 lm_packet_t lm_pkt; /* must be first entry */
396 lm_pkt_rx_info_t rx_info;
397 u32_t hash_value;
398
399 frtn_t freeRtn;
400 void * pUM; /* backpointer to um_device_t for free routine */
401 int idx; /* chain index used by the free routine */
402
403 u32_t signature;
404
405 ddi_dma_handle_t dmaHandle;
406 ddi_acc_handle_t dmaAccHandle;
407 } um_rxpacket_t;
408
409
410 typedef struct _RxQueue
411 {
412 void * pUM; /* backpointer to um_device_t */
413 u32_t idx; /* this ring's index */
414
415 mac_ring_handle_t ringHandle;
416 uint64_t genNumber; /* set by mac and passed up in mac_ring_rx */
417
418 volatile u32_t inPollMode;
419 u8_t intrDisableCnt;
420 u8_t intrEnableCnt;
421 u8_t pollCnt;
422
423 u32_t rxDiscards;
424 u32_t rxCopied;
425 u32_t rxLowWater;
426 u32_t rxBufUpInStack;
427
428 kmutex_t rxMutex;
429
430 kmutex_t doneRxMutex;
431 s_list_t doneRxQ; /* free bds that are ready to be posted */
432
433 s_list_t waitRxQ; /* packet waiting to be sent up */
434 } RxQueue;
435
436
437 typedef struct _RxQueueGroup
438 {
439 void * pUM; /* backpointer to um_device_t */
440 u32_t idx; /* this group's index */
441 mac_group_handle_t groupHandle;
442 } RxQueueGroup;
443
444
445 typedef struct _KstatRingMap
446 {
447 u32_t idx; /* ring index */
448 void * pUM; /* reference back to um_device_t */
449 } KstatRingMap;
450
451
452 typedef struct _BnxeFcoeState
453 {
454 lm_fcoe_state_t lm_fcoe;
455 } BnxeFcoeState;
456
457
458 typedef struct _BnxeClientStats
459 {
460 u32_t initWqeTx;
461 u32_t initWqeTxErr;
462 u32_t initCqeRx;
463 u32_t initCqeRxErr;
464 u32_t offloadConnWqeTx;
465 u32_t offloadConnWqeTxErr;
466 u32_t offloadConnCqeRx;
467 u32_t offloadConnCqeRxErr;
468 u32_t enableConnWqeTx;
469 u32_t enableConnWqeTxErr;
470 u32_t enableConnCqeRx;
471 u32_t enableConnCqeRxErr;
472 u32_t disableConnWqeTx;
473 u32_t disableConnWqeTxErr;
474 u32_t disableConnCqeRx;
475 u32_t disableConnCqeRxErr;
476 u32_t destroyConnWqeTx;
477 u32_t destroyConnWqeTxErr;
478 u32_t destroyConnCqeRx;
479 u32_t destroyConnCqeRxErr;
480 u32_t destroyWqeTx;
481 u32_t destroyWqeTxErr;
482 u32_t destroyCqeRx;
483 u32_t destroyCqeRxErr;
484 u32_t compRequestCqeRx;
485 u32_t compRequestCqeRxErr;
486 u32_t statWqeTx;
487 u32_t statWqeTxErr;
488 u32_t statCqeRx;
489 u32_t statCqeRxErr;
490 } BnxeClientStats;
491
492
493 typedef struct _BnxeFcoeData
494 {
495 dev_info_t * pDev;
496 BnxeBinding bind;
497 BnxeClientStats stats;
498 BnxeWwnInfo wwn;
499 } BnxeFcoeData;
500
501
502 typedef struct _BnxeIntrBlock
503 {
504 int intrCount;
505 int intrCapability;
506 u32_t intrPriority;
507 u32_t intrHandleBlockSize;
508 ddi_intr_handle_t * pIntrHandleBlockAlloc;
509 ddi_intr_handle_t * pIntrHandleBlock;
510 } BnxeIntrBlock;
511
512
513 typedef struct _BnxeWorkQueueInstance
514 {
515 void * pUM;
516
517 char taskqName[BNXE_STR_SIZE];
518 ddi_taskq_t * pTaskq;
519 kmutex_t workQueueMutex;
520 s_list_t workQueue;
521
522 u32_t workItemQueued;
523 u32_t workItemError;
524 u32_t workItemComplete;
525 u32_t highWater;
526 } BnxeWorkQueueInstance;
527
528
529 typedef struct _BnxeWorkQueues
530 {
531 BnxeWorkQueueInstance instq; /* instant, single thread serialized */
532 BnxeWorkQueueInstance delayq; /* delayed, multi thread not serialized */
533 } BnxeWorkQueues;
534
535
536 /* the following are used against the clientState variable in um_device_t */
537
538 #define CLIENT_FLG_DEVI 0x001
539 #define CLIENT_FLG_BIND 0x002
540 #define CLIENT_FLG_HW 0x004
541
542 #define CLIENT_DEVI(pUM, client) \
543 ((pUM)->clientState[(client)] & CLIENT_FLG_DEVI)
544
545 #define CLIENT_HW(pUM, client) \
546 ((pUM)->clientState[(client)] & CLIENT_FLG_HW)
547
548 #define CLIENT_BOUND(pUM, client) \
549 (((client) == LM_CLI_IDX_NDIS) ? \
550 ((pUM)->clientState[(client)] & CLIENT_FLG_HW) : \
551 ((pUM)->clientState[(client)] & CLIENT_FLG_BIND))
552
553 #define CLIENT_DEVI_SET(pUM, client) \
554 ((pUM)->clientState[(client)] |= CLIENT_FLG_DEVI)
555
556 #define CLIENT_DEVI_RESET(pUM, client) \
557 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_DEVI)
558
559 #define CLIENT_BIND_SET(pUM, client) \
560 ((pUM)->clientState[(client)] |= CLIENT_FLG_BIND)
561
562 #define CLIENT_BIND_RESET(pUM, client) \
563 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_BIND)
564
565 #define CLIENT_HW_SET(pUM, client) \
566 ((pUM)->clientState[(client)] |= CLIENT_FLG_HW)
567
568 #define CLIENT_HW_RESET(pUM, client) \
569 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_HW)
570
571
572 typedef struct _um_device
573 {
574 lm_device_t lm_dev; /* must be the first element */
575
576 u32_t magic;
577 dev_info_t * pDev;
578
579 u32_t hwInitDone;
580 u32_t chipStarted;
581 u32_t clientState[LM_CLI_IDX_MAX];
582
583 d_list_t memBlockList;
584 d_list_t memDmaList;
585 d_list_t memRegionList;
586 #ifdef BNXE_DEBUG_DMA_LIST
587 d_list_t memDmaListSaved;
588 #endif
589
590 int instance;
591 char devName[BNXE_STR_SIZE];
592 char version[BNXE_STR_SIZE];
593 char versionLM[BNXE_STR_SIZE];
594 char versionFW[BNXE_STR_SIZE];
595 char versionBC[BNXE_STR_SIZE];
596 char chipName[BNXE_STR_SIZE];
597 char chipID[BNXE_STR_SIZE];
598 char intrAlloc[BNXE_STR_SIZE];
599 char bus_dev_func[BNXE_STR_SIZE];
600 char vendor_device[BNXE_STR_SIZE];
601
602 volatile u32_t plumbed;
603
604 ddi_acc_handle_t pPciCfg;
605
606 kmutex_t intrMutex[MAX_RSS_CHAINS + 1];
607 kmutex_t intrFlipMutex[MAX_RSS_CHAINS + 1];
608 kmutex_t sbMutex[MAX_RSS_CHAINS + 1];
609 kmutex_t ethConMutex;
610 kmutex_t mcpMutex;
611 kmutex_t phyMutex;
612 kmutex_t indMutex;
613 kmutex_t cidMutex;
614 kmutex_t spqMutex; /* slow path queue lock */
615 kmutex_t spReqMutex; /* slow path request manager lock */
616 kmutex_t rrReqMutex; /* ramrod request */
617 kmutex_t islesCtrlMutex;
618 kmutex_t toeMutex;
619 kmutex_t memMutex;
620 kmutex_t offloadMutex;
621 kmutex_t hwInitMutex;
622 kmutex_t gldMutex;
623 krwlock_t gldTxMutex;
624
625 kmutex_t timerMutex;
626 volatile u32_t timerEnabled;
627 timeout_id_t timerID;
628
629 BnxeWorkQueues workqs;
630
631 BnxeMemDma * statusBlocks[MAX_RSS_CHAINS + 1];
632 volatile u32_t intrEnabled;
633 u64_t intrFired;
634 /* the arrays below = LM_SB_CNT() + 1 = 17 */
635 u64_t intrSbCnt[MAX_RSS_CHAINS + 1];
636 u64_t intrSbNoChangeCnt[MAX_RSS_CHAINS + 1];
637 u64_t intrSbPollCnt[MAX_RSS_CHAINS + 1];
638 u64_t intrSbPollNoChangeCnt[MAX_RSS_CHAINS + 1];
639
640 int intrType;
641 u32_t intrPriority;
642 BnxeIntrBlock defIntr;
643 BnxeIntrBlock rssIntr;
644 BnxeIntrBlock fcoeIntr;
645
646 BnxeDevParams devParams;
647 mac_handle_t pMac;
648 mac_resource_handle_t macRxResourceHandles[MAX_ETH_REG_CONS];
649 u8_t gldMac[ETHERNET_ADDRESS_SIZE];
650
651 d_list_t mcast_l2;
652 d_list_t mcast_fcoe;
653
654 u32_t ucastTableLen; /* number of ucast addrs in the table */
655 #ifndef LM_MAX_UC_TABLE_SIZE
656 #define LM_MAX_UC_TABLE_SIZE 1 /* for now, fix needed to support multiple ucast addr */
657 #endif
658
659 TxQueue txq[MAX_ETH_CONS];
660 RxQueue rxq[MAX_ETH_CONS];
661 RxQueueGroup rxqGroup[USER_OPTION_RX_RING_GROUPS_MAX];
662 u32_t rxBufSignature[LM_CLI_IDX_MAX];
663 u32_t txMsgPullUp;
664
665 BnxeProps props;
666 BnxePhyCfg hwinit; /* gathered by BnxeCfgInit */
667 BnxePhyCfg curcfg; /* initialized from hwinit by BnxeCfgReset */
668 BnxeLinkCfg remote;
669 u32_t phyInitialized;
670
671 kstat_t * kstats;
672 kstat_t * kstatsLink;
673 kstat_t * kstatsIntr;
674 kstat_t * kstatsL2Chip;
675 kstat_t * kstatsL2Driver;
676 kstat_t * kstatsL2Stats;
677 kstat_t * kstatsFcoe;
678 kstat_t * kstatsDcbx;
679 kstat_t * kstats_rxq[MAX_ETH_CONS];
680 KstatRingMap kstats_rxq_map[MAX_ETH_CONS];
681 kstat_t * kstats_txq[MAX_ETH_CONS];
682 KstatRingMap kstats_txq_map[MAX_ETH_CONS];
683 kmutex_t kstatMutex;
684
685 int fmCapabilities; /* FMA capabilities */
686
687 boolean_t do_fcoe;
688 BnxeFcoeData fcoe;
689 iscsi_info_block_hdr_t iscsiInfo;
690
691 } um_device_t;
692
693
694 /* mioc[ack|nak] return values from ioctl subroutines */
695 enum ioc_reply
696 {
697 IOC_INVAL = -1, /* bad, NAK with EINVAL */
698 IOC_DONE, /* OK, reply sent */
699 IOC_ACK, /* OK, just send ACK */
700 IOC_REPLY, /* OK, just send reply */
701 IOC_RESTART_ACK, /* OK, restart & ACK */
702 IOC_RESTART_REPLY /* OK, restart & reply */
703 };
704
705
706 #define BNXE_IOC_BASE ('X' << 8)
707 /* IOCTLs for get/set lldp and dcbx params */
708 #define GIOCBNXELLDP (BNXE_IOC_BASE + 0)
709 #define GIOCBNXEDCBX (BNXE_IOC_BASE + 1)
710 #define SIOCBNXEDCBX (BNXE_IOC_BASE + 2)
711 /* IOCTLs for edebug and firmware upgrade */
712 #define GIOCBNXEREG (BNXE_IOC_BASE + 3)
713 #define SIOCBNXEREG (BNXE_IOC_BASE + 4)
714 #define GIOCBNXENVRM (BNXE_IOC_BASE + 5)
715 #define SIOCBNXENVRM (BNXE_IOC_BASE + 6)
716 #define GIOCBNXEPCI (BNXE_IOC_BASE + 7)
717 #define GIOCBNXESTATS (BNXE_IOC_BASE + 8)
718
719 struct bnxe_reg_data
720 {
721 u32_t offset;
722 u32_t value;
723 };
724
725 struct bnxe_nvram_data
726 {
727 u32_t offset;
728 u32_t num_of_u32;
729 u32_t value[1]; /* variable */
730 };
731
732
733 /* bnxe_cfg.c */
734 void BnxeCfgInit(um_device_t * pUM);
735 void BnxeCfgReset(um_device_t * pUM);
736
737 /* bnxe_mm.c */
738 void BnxeInitBdCnts(um_device_t * pUM,
739 int cli_idx);
740
741 /* bnxe_gld.c */
742 boolean_t BnxeGldInit(um_device_t * pUM);
743 boolean_t BnxeGldFini(um_device_t * pUM);
744 void BnxeGldLink(um_device_t * pUM,
745 link_state_t state);
746
747 /* bnxe_hw.c */
748 boolean_t BnxeEstablishHwConn(um_device_t * pUM,
749 int cid);
750 int BnxeHwStartFCOE(um_device_t * pUM);
751 int BnxeHwStartL2(um_device_t * pUM);
752 int BnxeHwStartCore(um_device_t * pUM);
753 void BnxeHwStopFCOE(um_device_t * pUM);
754 void BnxeHwStopL2(um_device_t * pUM);
755 void BnxeHwStopCore(um_device_t * pUM);
756 void BnxeUpdatePhy(um_device_t * pUM);
757 int BnxeMacAddress(um_device_t * pUM,
758 int cliIdx,
759 boolean_t flag,
760 const uint8_t * pMacAddr);
761 int BnxeMulticast(um_device_t * pUM,
762 int cliIdx,
763 boolean_t flag,
764 const uint8_t * pMcastAddr,
765 boolean_t hwSet);
766 int BnxeRxMask(um_device_t * pUM,
767 int cliIdx,
768 lm_rx_mask_t mask);
769 int BnxeHwResume(um_device_t * pUM);
770 int BnxeHwSuspend(um_device_t * pUM);
771 #if (DEVO_REV > 3)
772 int BnxeHwQuiesce(um_device_t * pUM);
773 #endif
774
775 /* bnxe_intr.c */
776 void BnxeIntrIguSbEnable(um_device_t * pUM,
777 u32_t idx,
778 boolean_t fromISR);
779 void BnxeIntrIguSbDisable(um_device_t * pUM,
780 u32_t idx,
781 boolean_t fromISR);
782 void BnxePollRxRing(um_device_t * pUM,
783 u32_t idx,
784 boolean_t * pPktsRxed,
785 boolean_t * pPktsTxed);
786 void BnxePollRxRingFCOE(um_device_t * pUM);
787 int BnxeIntrEnable(um_device_t * pUM);
788 void BnxeIntrDisable(um_device_t * pUM);
789 boolean_t BnxeIntrInit(um_device_t * pUM);
790 void BnxeIntrFini(um_device_t * pUM);
791
792 /* bnxe_kstat.c */
793 boolean_t BnxeKstatInit(um_device_t * pUM);
794 void BnxeKstatFini(um_device_t * pUM);
795
796 /* bnxe_rr.c */
797 int BnxeRouteTxRing(um_device_t * pUM,
798 mblk_t * pMblk);
799
800 /* bnxe_rx.c */
801 boolean_t BnxeWaitForPacketsFromClient(um_device_t * pUM,
802 int cliIdx);
803 mblk_t * BnxeRxRingProcess(um_device_t * pUM,
804 int idx,
805 boolean_t polling,
806 int numBytes);
807 void BnxeRxPktsAbort(um_device_t * pUM,
808 int cliIdx);
809 int BnxeRxPktsInitPostBuffers(um_device_t * pUM,
810 int cliIdx);
811 int BnxeRxPktsInit(um_device_t * pUM,
812 int cliIdx);
813 void BnxeRxPktsFini(um_device_t * pUM,
814 int cliIdx);
815
816 /* bnxe_tx.c */
817 void BnxeTxPktsReclaim(um_device_t * pUM,
818 int idx,
819 s_list_t * pPktList);
820 void BnxeTxRingProcess(um_device_t * pUM,
821 int idx);
822 int BnxeTxSendMblk(um_device_t * pUM,
823 int idx,
824 mblk_t * pMblk,
825 u32_t flags,
826 u16_t vlan_tag);
827 void BnxeTxPktsAbort(um_device_t * pUM,
828 int cliIdx);
829 int BnxeTxPktsInit(um_device_t * pUM,
830 int cliIdx);
831 void BnxeTxPktsFini(um_device_t * pUM,
832 int cliIdx);
833
834 /* bnxe_timer.c */
835 void BnxeTimerStart(um_device_t * pUM);
836 void BnxeTimerStop(um_device_t * pUM);
837
838 /* bnxe_workq.c */
839 boolean_t BnxeWorkQueueInit(um_device_t * pUM);
840 void BnxeWorkQueueWaitAndDestroy(um_device_t * pUM);
841 void BnxeWorkQueueStartPending(um_device_t * pUM);
842 boolean_t BnxeWorkQueueAdd(um_device_t * pUM,
843 void (*pWorkCbk)(um_device_t *, void *, u32_t),
844 void * pWorkData,
845 u32_t workDataLen);
846 boolean_t BnxeWorkQueueAddNoCopy(um_device_t * pUM,
847 void (*pWorkCbk)(um_device_t *, void *),
848 void * pWorkData);
849 boolean_t BnxeWorkQueueAddGeneric(um_device_t * pUM,
850 void (*pWorkCbkGeneric)(um_device_t *));
851 boolean_t BnxeWorkQueueAddDelay(um_device_t * pUM,
852 void (*pWorkCbk)(um_device_t *, void *, u32_t),
853 void * pWorkData,
854 u32_t workDataLen,
855 u32_t delayMs);
856 boolean_t BnxeWorkQueueAddDelayNoCopy(um_device_t * pUM,
857 void (*pWorkCbk)(um_device_t *, void *),
858 void * pWorkData,
859 u32_t delayMs);
860 boolean_t BnxeWorkQueueAddDelayGeneric(um_device_t * pUM,
861 void (*pWorkCbkGeneric)(um_device_t *),
862 u32_t delayMs);
863
864 /* bnxe_fcoe.c */
865 boolean_t BnxeFcoeInitCqe(um_device_t * pUM,
866 struct fcoe_kcqe * kcqe);
867 boolean_t BnxeFcoeOffloadConnCqe(um_device_t * pUM,
868 BnxeFcoeState * pFcoeState,
869 struct fcoe_kcqe * kcqe);
870 boolean_t BnxeFcoeEnableConnCqe(um_device_t * pUM,
871 BnxeFcoeState * pFcoeState,
872 struct fcoe_kcqe * kcqe);
873 boolean_t BnxeFcoeDisableConnCqe(um_device_t * pUM,
874 BnxeFcoeState * pFcoeState,
875 struct fcoe_kcqe * kcqe);
876 boolean_t BnxeFcoeDestroyConnCqe(um_device_t * pUM,
877 BnxeFcoeState * pFcoeState,
878 struct fcoe_kcqe * kcqe);
879 boolean_t BnxeFcoeDestroyCqe(um_device_t * pUM,
880 struct fcoe_kcqe * kcqe);
881 boolean_t BnxeFcoeStatCqe(um_device_t * pUM,
882 struct fcoe_kcqe * kcqe);
883 boolean_t BnxeFcoeCompRequestCqe(um_device_t * pUM,
884 struct fcoe_kcqe * kcqes,
885 u32_t num_kcqes);
886 boolean_t BnxeFcoePrvCtl(dev_info_t * pDev,
887 int cmd,
888 void * pData,
889 int dataLen);
890 mblk_t * BnxeFcoePrvTx(dev_info_t * pDev,
891 mblk_t * pMblk,
892 u32_t flags,
893 u16_t vlan_tag);
894 boolean_t BnxeFcoePrvPoll(dev_info_t * pDev);
895 boolean_t BnxeFcoePrvSendWqes(dev_info_t * pDev,
896 void * wqes[],
897 int wqeCnt);
898 boolean_t BnxeFcoePrvMapMailboxq(dev_info_t * pDev,
899 u32_t cid,
900 void ** ppMap,
901 ddi_acc_handle_t * pAccHandle);
902 boolean_t BnxeFcoePrvUnmapMailboxq(dev_info_t * pDev,
903 u32_t cid,
904 void * pMap,
905 ddi_acc_handle_t accHandle);
906 int BnxeFcoeInit(um_device_t * pUM);
907 int BnxeFcoeFini(um_device_t * pUM);
908 void BnxeFcoeStartStop(um_device_t * pUM);
909
910 /* bnxe_main.c */
911 u8_t BnxeInstance(void * pDev);
912 char * BnxeDevName(void * pDev);
913 boolean_t BnxeProtoSupport(um_device_t * pUM, int proto);
914 boolean_t BnxeProtoFcoeAfex(um_device_t * pUM);
915 int BnxeCheckAccHandle(ddi_acc_handle_t handle);
916 int BnxeCheckDmaHandle(ddi_dma_handle_t handle);
917 void BnxeFmErrorReport(um_device_t * pUM, char * detail);
918
919 extern kmutex_t bnxeLoaderMutex;
920 extern u32_t bnxeNumPlumbed;
921
922 extern BnxeLinkCfg bnxeLinkCfg;
923
924 /* undefine this to help with dtrace analysis */
925 #define BNXE_LOCKS_INLINE
926
927 #ifdef BNXE_LOCKS_INLINE
928
929 #define BNXE_LOCK_ENTER_INTR(pUM, idx) mutex_enter(&(pUM)->intrMutex[(idx)])
930 #define BNXE_LOCK_EXIT_INTR(pUM, idx) mutex_exit(&(pUM)->intrMutex[(idx)])
931 #define BNXE_LOCK_ENTER_INTR_FLIP(pUM, idx) mutex_enter(&(pUM)->intrFlipMutex[(idx)])
932 #define BNXE_LOCK_EXIT_INTR_FLIP(pUM, idx) mutex_exit(&(pUM)->intrFlipMutex[(idx)])
933 #define BNXE_LOCK_ENTER_TX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].txMutex)
934 #define BNXE_LOCK_EXIT_TX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].txMutex)
935 #define BNXE_LOCK_ENTER_FREETX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].freeTxDescMutex)
936 #define BNXE_LOCK_EXIT_FREETX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].freeTxDescMutex)
937 #define BNXE_LOCK_ENTER_RX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].rxMutex)
938 #define BNXE_LOCK_EXIT_RX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].rxMutex)
939 #define BNXE_LOCK_ENTER_DONERX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].doneRxMutex)
940 #define BNXE_LOCK_EXIT_DONERX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].doneRxMutex)
941 #define BNXE_LOCK_ENTER_SB(pUM, idx) mutex_enter(&(pUM)->sbMutex[(idx)])
942 #define BNXE_LOCK_EXIT_SB(pUM, idx) mutex_exit(&(pUM)->sbMutex[(idx)])
943 #define BNXE_LOCK_ENTER_ETH_CON(pUM) mutex_enter(&(pUM)->ethConMutex)
944 #define BNXE_LOCK_EXIT_ETH_CON(pUM) mutex_exit(&(pUM)->ethConMutex)
945 #define BNXE_LOCK_ENTER_MCP(pUM) mutex_enter(&(pUM)->mcpMutex)
946 #define BNXE_LOCK_EXIT_MCP(pUM) mutex_exit(&(pUM)->mcpMutex)
947 #define BNXE_LOCK_ENTER_PHY(pUM) mutex_enter(&(pUM)->phyMutex)
948 #define BNXE_LOCK_EXIT_PHY(pUM) mutex_exit(&(pUM)->phyMutex)
949 #define BNXE_LOCK_ENTER_IND(pUM) mutex_enter(&(pUM)->indMutex)
950 #define BNXE_LOCK_EXIT_IND(pUM) mutex_exit(&(pUM)->indMutex)
951 #define BNXE_LOCK_ENTER_CID(pUM) mutex_enter(&(pUM)->cidMutex)
952 #define BNXE_LOCK_EXIT_CID(pUM) mutex_exit(&(pUM)->cidMutex)
953 #define BNXE_LOCK_ENTER_SPQ(pUM) mutex_enter(&(pUM)->spqMutex)
954 #define BNXE_LOCK_EXIT_SPQ(pUM) mutex_exit(&(pUM)->spqMutex)
955 #define BNXE_LOCK_ENTER_SPREQ(pUM) mutex_enter(&(pUM)->spReqMutex)
956 #define BNXE_LOCK_EXIT_SPREQ(pUM) mutex_exit(&(pUM)->spReqMutex)
957 #define BNXE_LOCK_ENTER_RRREQ(pUM) mutex_enter(&(pUM)->rrReqMutex)
958 #define BNXE_LOCK_EXIT_RRREQ(pUM) mutex_exit(&(pUM)->rrReqMutex)
959 #define BNXE_LOCK_ENTER_ISLES_CONTROL(pUM) mutex_enter(&(pUM)->islesCtrlMutex)
960 #define BNXE_LOCK_EXIT_ISLES_CONTROL(pUM) mutex_exit(&(pUM)->islesCtrlMutex)
961 #define BNXE_LOCK_ENTER_TOE(pUM) mutex_enter(&(pUM)->toeMutex)
962 #define BNXE_LOCK_EXIT_TOE(pUM) mutex_exit(&(pUM)->toeMutex)
963 #define BNXE_LOCK_ENTER_MEM(pUM) mutex_enter(&(pUM)->memMutex)
964 #define BNXE_LOCK_EXIT_MEM(pUM) mutex_exit(&(pUM)->memMutex)
965 #define BNXE_LOCK_ENTER_OFFLOAD(pUM) mutex_enter(&(pUM)->offloadMutex)
966 #define BNXE_LOCK_EXIT_OFFLOAD(pUM) mutex_exit(&(pUM)->offloadMutex)
967 #define BNXE_LOCK_ENTER_HWINIT(pUM) mutex_enter(&(pUM)->hwInitMutex)
968 #define BNXE_LOCK_EXIT_HWINIT(pUM) mutex_exit(&(pUM)->hwInitMutex)
969 #define BNXE_LOCK_ENTER_GLD(pUM) mutex_enter(&(pUM)->gldMutex)
970 #define BNXE_LOCK_EXIT_GLD(pUM) mutex_exit(&(pUM)->gldMutex)
971 #define BNXE_LOCK_ENTER_GLDTX(pUM, rw) rw_enter(&(pUM)->gldTxMutex, (rw))
972 #define BNXE_LOCK_EXIT_GLDTX(pUM) rw_exit(&(pUM)->gldTxMutex)
973 #define BNXE_LOCK_ENTER_TIMER(pUM) mutex_enter(&(pUM)->timerMutex)
974 #define BNXE_LOCK_EXIT_TIMER(pUM) mutex_exit(&(pUM)->timerMutex)
975 #define BNXE_LOCK_ENTER_STATS(pUM) mutex_enter(&(pUM)->kstatMutex)
976 #define BNXE_LOCK_EXIT_STATS(pUM) mutex_exit(&(pUM)->kstatMutex)
977
978 #else /* not BNXE_LOCKS_INLINE */
979
980 void BNXE_LOCK_ENTER_INTR(um_device_t * pUM, int idx);
981 void BNXE_LOCK_EXIT_INTR(um_device_t * pUM, int idx);
982 void BNXE_LOCK_ENTER_INTR_FLIP(um_device_t * pUM, int idx);
983 void BNXE_LOCK_EXIT_INTR_FLIP(um_device_t * pUM, int idx);
984 void BNXE_LOCK_ENTER_TX(um_device_t * pUM, int idx);
985 void BNXE_LOCK_EXIT_TX(um_device_t * pUM, int idx);
986 void BNXE_LOCK_ENTER_FREETX(um_device_t * pUM, int idx);
987 void BNXE_LOCK_EXIT_FREETX(um_device_t * pUM, int idx);
988 void BNXE_LOCK_ENTER_RX(um_device_t * pUM, int idx);
989 void BNXE_LOCK_EXIT_RX(um_device_t * pUM, int idx);
990 void BNXE_LOCK_ENTER_DONERX(um_device_t * pUM, int idx);
991 void BNXE_LOCK_EXIT_DONERX(um_device_t * pUM, int idx);
992 void BNXE_LOCK_ENTER_SB(um_device_t * pUM, int idx);
993 void BNXE_LOCK_EXIT_SB(um_device_t * pUM, int idx);
994 void BNXE_LOCK_ENTER_ETH_CON(um_device_t * pUM);
995 void BNXE_LOCK_EXIT_ETH_CON(um_device_t * pUM);
996 void BNXE_LOCK_ENTER_MCP(um_device_t * pUM);
997 void BNXE_LOCK_EXIT_MCP(um_device_t * pUM);
998 void BNXE_LOCK_ENTER_PHY(um_device_t * pUM);
999 void BNXE_LOCK_EXIT_PHY(um_device_t * pUM);
1000 void BNXE_LOCK_ENTER_IND(um_device_t * pUM);
1001 void BNXE_LOCK_EXIT_IND(um_device_t * pUM);
1002 void BNXE_LOCK_ENTER_CID(um_device_t * pUM);
1003 void BNXE_LOCK_EXIT_CID(um_device_t * pUM);
1004 void BNXE_LOCK_ENTER_SPQ(um_device_t * pUM);
1005 void BNXE_LOCK_EXIT_SPQ(um_device_t * pUM);
1006 void BNXE_LOCK_ENTER_SPREQ(um_device_t * pUM);
1007 void BNXE_LOCK_EXIT_SPREQ(um_device_t * pUM);
1008 void BNXE_LOCK_ENTER_RRREQ(um_device_t * pUM);
1009 void BNXE_LOCK_EXIT_RRREQ(um_device_t * pUM);
1010 void BNXE_LOCK_ENTER_ISLES_CONTROL(um_device_t * pUM);
1011 void BNXE_LOCK_EXIT_ISLES_CONTROL(um_device_t * pUM);
1012 void BNXE_LOCK_ENTER_MEM(um_device_t * pUM);
1013 void BNXE_LOCK_EXIT_MEM(um_device_t * pUM);
1014 void BNXE_LOCK_ENTER_GLD(um_device_t * pUM);
1015 void BNXE_LOCK_EXIT_GLD(um_device_t * pUM);
1016 void BNXE_LOCK_ENTER_GLDTX(um_device_t * pUM, krw_t rw);
1017 void BNXE_LOCK_EXIT_GLDTX(um_device_t * pUM);
1018 void BNXE_LOCK_ENTER_TIMER(um_device_t * pUM);
1019 void BNXE_LOCK_EXIT_TIMER(um_device_t * pUM);
1020 void BNXE_LOCK_ENTER_STATS(um_device_t * pUM);
1021 void BNXE_LOCK_EXIT_STATS(um_device_t * pUM);
1022
1023 #endif /* BNXE_LOCKS_INLINE */
1024
1025 #define CATC_TRIGGER(lmdev, data) { \
1026 REG_WR((lmdev), 0x2000, (data)); \
1027 }
1028 #define CATC_TRIGGER_START(lmdev) CATC_TRIGGER((lmdev), 0xcafecafe)
1029
1030 void BnxeDumpMem(um_device_t * pUM,
1031 char * pTag,
1032 u8_t * pMem,
1033 u32_t len);
1034 void BnxeDumpPkt(um_device_t * pUM,
1035 char * pTag,
1036 mblk_t * pMblk,
1037 boolean_t contents);
1038
1039 /* XXX yuck (beware return strings lengths with kstat and mdb) */
1040
BnxeIsClientBound(um_device_t * pUM)1041 inline boolean_t BnxeIsClientBound(um_device_t * pUM)
1042 {
1043 return (CLIENT_HW(pUM, LM_CLI_IDX_NDIS) ||
1044 CLIENT_BOUND(pUM, LM_CLI_IDX_FCOE));
1045 }
1046
BnxeClientsHw(um_device_t * pUM)1047 inline char * BnxeClientsHw(um_device_t * pUM)
1048 {
1049 if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS) &&
1050 CLIENT_HW(pUM, LM_CLI_IDX_FCOE)) { return "L2,FCoE"; }
1051 else if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS)) { return "L2"; }
1052 else if (CLIENT_HW(pUM, LM_CLI_IDX_FCOE)) { return "FCoE"; }
1053 else { return "None"; }
1054 }
1055
BnxeClientsDevi(um_device_t * pUM)1056 inline char * BnxeClientsDevi(um_device_t * pUM)
1057 {
1058 if (CLIENT_DEVI(pUM, LM_CLI_IDX_FCOE)) { return "FCoE"; }
1059 else { return "None"; }
1060 }
1061
BnxeClientsBound(um_device_t * pUM)1062 inline char * BnxeClientsBound(um_device_t * pUM)
1063 {
1064 if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS) &&
1065 CLIENT_BOUND(pUM, LM_CLI_IDX_FCOE)) { return "L2,FCoE"; }
1066 else if (CLIENT_HW(pUM, LM_CLI_IDX_NDIS)) { return "L2"; }
1067 else if (CLIENT_BOUND(pUM, LM_CLI_IDX_FCOE)) { return "FCoE"; }
1068 else { return "None"; }
1069 }
1070
1071 #endif /* BNXE_H */
1072
1073