1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2016 The FreeBSD Foundation
5 * Copyright (c) 2019 Colin Percival
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33
34 #include <machine/bus.h>
35
36 #include <dev/pci/pcireg.h>
37
38 #include <dev/uart/uart.h>
39 #include <dev/uart/uart_bus.h>
40 #include <dev/uart/uart_cpu.h>
41 #include <dev/uart/uart_cpu_acpi.h>
42
43 #include <contrib/dev/acpica/include/acpi.h>
44 #include <contrib/dev/acpica/include/accommon.h>
45 #include <contrib/dev/acpica/include/actables.h>
46
47 static struct acpi_uart_compat_data *
uart_cpu_acpi_scan(uint8_t interface_type)48 uart_cpu_acpi_scan(uint8_t interface_type)
49 {
50 struct acpi_uart_compat_data **cd, *curcd;
51 int i;
52
53 SET_FOREACH(cd, uart_acpi_class_and_device_set) {
54 curcd = *cd;
55 for (i = 0; curcd[i].cd_hid != NULL; i++) {
56 if (curcd[i].cd_port_subtype == interface_type)
57 return (&curcd[i]);
58 }
59 }
60
61 SET_FOREACH(cd, uart_acpi_class_set) {
62 curcd = *cd;
63 for (i = 0; curcd[i].cd_hid != NULL; i++) {
64 if (curcd[i].cd_port_subtype == interface_type)
65 return (&curcd[i]);
66 }
67 }
68
69 return (NULL);
70 }
71
72 static int
uart_cpu_acpi_init_devinfo(struct uart_devinfo * di,struct uart_class * class,ACPI_GENERIC_ADDRESS * addr)73 uart_cpu_acpi_init_devinfo(struct uart_devinfo *di, struct uart_class *class,
74 ACPI_GENERIC_ADDRESS *addr)
75 {
76 /* Fill in some fixed details. */
77 di->bas.chan = 0;
78 di->bas.rclk = 0;
79 di->databits = 8;
80 di->stopbits = 1;
81 di->parity = UART_PARITY_NONE;
82 di->ops = uart_getops(class);
83
84 /* Fill in details from SPCR table. */
85 switch (addr->SpaceId) {
86 case 0:
87 di->bas.bst = uart_bus_space_mem;
88 break;
89 case 1:
90 di->bas.bst = uart_bus_space_io;
91 break;
92 default:
93 printf("UART in unrecognized address space: %d!\n",
94 (int)addr->SpaceId);
95 return (ENXIO);
96 }
97 switch (addr->AccessWidth) {
98 case 0: /* EFI_ACPI_6_0_UNDEFINED */
99 /* FALLTHROUGH */
100 case 1: /* EFI_ACPI_6_0_BYTE */
101 di->bas.regiowidth = 1;
102 break;
103 case 2: /* EFI_ACPI_6_0_WORD */
104 di->bas.regiowidth = 2;
105 break;
106 case 3: /* EFI_ACPI_6_0_DWORD */
107 di->bas.regiowidth = 4;
108 break;
109 case 4: /* EFI_ACPI_6_0_QWORD */
110 di->bas.regiowidth = 8;
111 break;
112 default:
113 printf("UART unsupported access width: %d!\n",
114 (int)addr->AccessWidth);
115 return (ENXIO);
116 }
117 switch (addr->BitWidth) {
118 case 0:
119 /* FALLTHROUGH */
120 case 8:
121 di->bas.regshft = 0;
122 break;
123 case 16:
124 di->bas.regshft = 1;
125 break;
126 case 32:
127 di->bas.regshft = 2;
128 break;
129 case 64:
130 di->bas.regshft = 3;
131 break;
132 default:
133 printf("UART unsupported bit width: %d!\n",
134 (int)addr->BitWidth);
135 return (ENXIO);
136 }
137
138 return (0);
139 }
140
141 static int
uart_cpu_acpi_spcr(int devtype,struct uart_devinfo * di)142 uart_cpu_acpi_spcr(int devtype, struct uart_devinfo *di)
143 {
144 vm_paddr_t spcr_physaddr;
145 ACPI_TABLE_SPCR *spcr;
146 struct acpi_uart_compat_data *cd;
147 struct uart_class *class;
148 int error = ENXIO;
149
150 /* Look for the SPCR table. */
151 spcr_physaddr = acpi_find_table(ACPI_SIG_SPCR);
152 if (spcr_physaddr == 0)
153 return (error);
154 spcr = acpi_map_table(spcr_physaddr, ACPI_SIG_SPCR);
155 if (spcr == NULL) {
156 printf("Unable to map the SPCR table!\n");
157 return (error);
158 }
159
160 /* Search for information about this SPCR interface type. */
161 cd = uart_cpu_acpi_scan(spcr->InterfaceType);
162 if (cd == NULL)
163 goto out;
164 class = cd->cd_class;
165
166 error = uart_cpu_acpi_init_devinfo(di, class, &spcr->SerialPort);
167 if (error != 0)
168 goto out;
169
170 /*
171 * SPCR Rev 4 and newer allow a precise baudrate to be passed in for
172 * things like 1.5M or 2.0M. If we have that, then use that value,
173 * otherwise try to decode the older enumeration.
174 */
175 if (spcr->Header.Revision >= 4 && spcr->PreciseBaudrate != 0) {
176 di->baudrate = spcr->PreciseBaudrate;
177 } else {
178 switch (spcr->BaudRate) {
179 case 0:
180 /* Special value; means "keep current value unchanged". */
181 di->baudrate = 0;
182 break;
183 case 3:
184 di->baudrate = 9600;
185 break;
186 case 4:
187 di->baudrate = 19200;
188 break;
189 case 6:
190 di->baudrate = 57600;
191 break;
192 case 7:
193 di->baudrate = 115200;
194 break;
195 default:
196 printf("SPCR has reserved BaudRate value: %d!\n",
197 (int)spcr->BaudRate);
198 goto out;
199 }
200 }
201
202 /*
203 * Rev 3 and newer can specify a rclk, use it if it's there. It's
204 * defined to be 0 when it's not known, and we've initialized rclk to 0
205 * in uart_cpu_acpi_init_devinfo, so we don't have to test for it.
206 */
207 if (spcr->Header.Revision >= 3)
208 di->bas.rclk = spcr->UartClkFreq;
209
210 /*
211 * If no rclk is set, then we will assume the BIOS has configured the
212 * hardware at the stated baudrate, so we can use it to guess the rclk
213 * relatively accurately, so make a note for later.
214 */
215 if (di->bas.rclk == 0)
216 di->bas.rclk_guess = 1;
217
218 if (spcr->PciVendorId != PCIV_INVALID &&
219 spcr->PciDeviceId != PCIV_INVALID) {
220 di->pci_info.vendor = spcr->PciVendorId;
221 di->pci_info.device = spcr->PciDeviceId;
222 }
223
224 /* Apply device tweaks. */
225 if ((cd->cd_quirks & UART_F_IGNORE_SPCR_REGSHFT) ==
226 UART_F_IGNORE_SPCR_REGSHFT) {
227 di->bas.regshft = cd->cd_regshft;
228 }
229
230 /* Create a bus space handle. */
231 error = bus_space_map(di->bas.bst, spcr->SerialPort.Address,
232 uart_getrange(class), 0, &di->bas.bsh);
233
234 out:
235 acpi_unmap_table(spcr);
236 return (error);
237 }
238
239 static int
uart_cpu_acpi_dbg2(struct uart_devinfo * di)240 uart_cpu_acpi_dbg2(struct uart_devinfo *di)
241 {
242 vm_paddr_t dbg2_physaddr;
243 ACPI_TABLE_DBG2 *dbg2;
244 ACPI_DBG2_DEVICE *dbg2_dev;
245 ACPI_GENERIC_ADDRESS *base_address;
246 struct acpi_uart_compat_data *cd;
247 struct uart_class *class;
248 int error;
249 bool found;
250
251 /* Look for the DBG2 table. */
252 dbg2_physaddr = acpi_find_table(ACPI_SIG_DBG2);
253 if (dbg2_physaddr == 0)
254 return (ENXIO);
255
256 dbg2 = acpi_map_table(dbg2_physaddr, ACPI_SIG_DBG2);
257 if (dbg2 == NULL) {
258 printf("Unable to map the DBG2 table!\n");
259 return (ENXIO);
260 }
261
262 error = ENXIO;
263
264 dbg2_dev = (ACPI_DBG2_DEVICE *)((uintptr_t)dbg2 + dbg2->InfoOffset);
265 found = false;
266 while ((uintptr_t)dbg2_dev + dbg2_dev->Length <=
267 (uintptr_t)dbg2 + dbg2->Header.Length) {
268 if (dbg2_dev->PortType != ACPI_DBG2_SERIAL_PORT)
269 goto next;
270
271 /* XXX: Too restrictive? */
272 if (dbg2_dev->RegisterCount != 1)
273 goto next;
274
275 cd = uart_cpu_acpi_scan(dbg2_dev->PortSubtype);
276 if (cd == NULL)
277 goto next;
278
279 class = cd->cd_class;
280 base_address = (ACPI_GENERIC_ADDRESS *)
281 ((uintptr_t)dbg2_dev + dbg2_dev->BaseAddressOffset);
282
283 error = uart_cpu_acpi_init_devinfo(di, class, base_address);
284 if (error == 0) {
285 found = true;
286 break;
287 }
288
289 next:
290 dbg2_dev = (ACPI_DBG2_DEVICE *)
291 ((uintptr_t)dbg2_dev + dbg2_dev->Length);
292 }
293 if (!found)
294 goto out;
295
296 /* XXX: Find the correct value */
297 di->baudrate = 115200;
298
299 /* Apply device tweaks. */
300 if ((cd->cd_quirks & UART_F_IGNORE_SPCR_REGSHFT) ==
301 UART_F_IGNORE_SPCR_REGSHFT) {
302 di->bas.regshft = cd->cd_regshft;
303 }
304
305 /* Create a bus space handle. */
306 error = bus_space_map(di->bas.bst, base_address->Address,
307 uart_getrange(class), 0, &di->bas.bsh);
308
309 out:
310 acpi_unmap_table(dbg2);
311 return (error);
312 }
313
314 int
uart_cpu_acpi_setup(int devtype,struct uart_devinfo * di)315 uart_cpu_acpi_setup(int devtype, struct uart_devinfo *di)
316 {
317 char *cp;
318
319 switch(devtype) {
320 case UART_DEV_CONSOLE:
321 return (uart_cpu_acpi_spcr(devtype, di));
322 case UART_DEV_DBGPORT:
323 /* Use the Debug Port Table 2 (DBG2) to find a debug uart */
324 cp = kern_getenv("hw.acpi.enable_dbg2");
325 if (cp != NULL && strcasecmp(cp, "yes") == 0)
326 return (uart_cpu_acpi_dbg2(di));
327 break;
328 }
329 return (ENXIO);
330 }
331