Searched defs:ctrl_regs (Results 1 – 9 of 9) sorted by relevance
16 struct ctrl_regs { struct17 u32 tmr_ctrl; /* Timer control register */18 u32 tmr_tevent; /* Timestamp event register */19 u32 tmr_temask; /* Timer event mask register */20 u32 tmr_pevent; /* Timestamp event register */21 u32 tmr_pemask; /* Timer event mask register */22 u32 tmr_stat; /* Timestamp status register */23 u32 tmr_cnt_h; /* Timer counter high register */24 u32 tmr_cnt_l; /* Timer counter low register */25 u32 tmr_add; /* Timer drift compensation addend register */[all …]
90 static u32 snet_read32_word(struct snet_ctrl_regs __iomem *ctrl_regs, u16 word_idx) in snet_read32_word()95 static u32 snet_read_ctrl(struct snet_ctrl_regs __iomem *ctrl_regs) in snet_read_ctrl()100 static void snet_write_ctrl(struct snet_ctrl_regs __iomem *ctrl_regs, u32 val) in snet_write_ctrl()105 static void snet_write_op(struct snet_ctrl_regs __iomem *ctrl_regs, u32 val) in snet_write_op()110 static int snet_wait_for_dpu_completion(struct snet_ctrl_regs __iomem *ctrl_regs) in snet_wait_for_dpu_completion()
627 const struct msa_control_regs ctrl_regs = { in msa_get() local658 struct msa_control_regs ctrl_regs; in msa_set() local
52 void __iomem *ctrl_regs; member
72 u8 ctrl_regs[RMI_F30_CTRL_REGS_MAX_SIZE]; member
206 struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; in ath10k_ce_src_ring_dmax_set() local220 struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; in ath10k_ce_src_ring_byte_swap_set() local234 struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; in ath10k_ce_dest_ring_byte_swap_set() local
265 uint64_t *counter_regs, *ctrl_regs; in xen_amd_pmu_emulate() local
245 u8 ctrl_regs[REGS_END]; member
1432 static inline void __iomem *ctrl_regs(struct mmp_path *path) in ctrl_regs() function