1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale MXS LRADC ADC driver
4 *
5 * Copyright (c) 2012 DENX Software Engineering, GmbH.
6 * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
7 *
8 * Authors:
9 * Marek Vasut <marex@denx.de>
10 * Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
11 */
12
13 #include <linux/completion.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/mfd/core.h>
18 #include <linux/mfd/mxs-lradc.h>
19 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/sysfs.h>
23
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/sysfs.h>
30
31 /*
32 * Make this runtime configurable if necessary. Currently, if the buffered mode
33 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
34 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
35 * seconds. The result is that the samples arrive every 500mS.
36 */
37 #define LRADC_DELAY_TIMER_PER 200
38 #define LRADC_DELAY_TIMER_LOOP 5
39
40 #define VREF_MV_BASE 1850
41
42 static const char *mx23_lradc_adc_irq_names[] = {
43 "mxs-lradc-channel0",
44 "mxs-lradc-channel1",
45 "mxs-lradc-channel2",
46 "mxs-lradc-channel3",
47 "mxs-lradc-channel4",
48 "mxs-lradc-channel5",
49 };
50
51 static const char *mx28_lradc_adc_irq_names[] = {
52 "mxs-lradc-thresh0",
53 "mxs-lradc-thresh1",
54 "mxs-lradc-channel0",
55 "mxs-lradc-channel1",
56 "mxs-lradc-channel2",
57 "mxs-lradc-channel3",
58 "mxs-lradc-channel4",
59 "mxs-lradc-channel5",
60 "mxs-lradc-button0",
61 "mxs-lradc-button1",
62 };
63
64 static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
65 [IMX23_LRADC] = {
66 VREF_MV_BASE, /* CH0 */
67 VREF_MV_BASE, /* CH1 */
68 VREF_MV_BASE, /* CH2 */
69 VREF_MV_BASE, /* CH3 */
70 VREF_MV_BASE, /* CH4 */
71 VREF_MV_BASE, /* CH5 */
72 VREF_MV_BASE * 2, /* CH6 VDDIO */
73 VREF_MV_BASE * 4, /* CH7 VBATT */
74 VREF_MV_BASE, /* CH8 Temp sense 0 */
75 VREF_MV_BASE, /* CH9 Temp sense 1 */
76 VREF_MV_BASE, /* CH10 */
77 VREF_MV_BASE, /* CH11 */
78 VREF_MV_BASE, /* CH12 USB_DP */
79 VREF_MV_BASE, /* CH13 USB_DN */
80 VREF_MV_BASE, /* CH14 VBG */
81 VREF_MV_BASE * 4, /* CH15 VDD5V */
82 },
83 [IMX28_LRADC] = {
84 VREF_MV_BASE, /* CH0 */
85 VREF_MV_BASE, /* CH1 */
86 VREF_MV_BASE, /* CH2 */
87 VREF_MV_BASE, /* CH3 */
88 VREF_MV_BASE, /* CH4 */
89 VREF_MV_BASE, /* CH5 */
90 VREF_MV_BASE, /* CH6 */
91 VREF_MV_BASE * 4, /* CH7 VBATT */
92 VREF_MV_BASE, /* CH8 Temp sense 0 */
93 VREF_MV_BASE, /* CH9 Temp sense 1 */
94 VREF_MV_BASE * 2, /* CH10 VDDIO */
95 VREF_MV_BASE, /* CH11 VTH */
96 VREF_MV_BASE * 2, /* CH12 VDDA */
97 VREF_MV_BASE, /* CH13 VDDD */
98 VREF_MV_BASE, /* CH14 VBG */
99 VREF_MV_BASE * 4, /* CH15 VDD5V */
100 },
101 };
102
103 enum mxs_lradc_divbytwo {
104 MXS_LRADC_DIV_DISABLED = 0,
105 MXS_LRADC_DIV_ENABLED,
106 };
107
108 struct mxs_lradc_scale {
109 unsigned int integer;
110 unsigned int nano;
111 };
112
113 struct mxs_lradc_adc {
114 struct mxs_lradc *lradc;
115 struct device *dev;
116
117 void __iomem *base;
118 /* Maximum of 8 channels + 8 byte ts */
119 u32 buffer[10] __aligned(8);
120 struct iio_trigger *trig;
121 struct completion completion;
122 spinlock_t lock;
123
124 const u32 *vref_mv;
125 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
126 unsigned long is_divided;
127 };
128
129
130 /* Raw I/O operations */
mxs_lradc_adc_read_single(struct iio_dev * iio_dev,int chan,int * val)131 static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
132 int *val)
133 {
134 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
135 struct mxs_lradc *lradc = adc->lradc;
136 int ret;
137
138 /*
139 * See if there is no buffered operation in progress. If there is simply
140 * bail out. This can be improved to support both buffered and raw IO at
141 * the same time, yet the code becomes horribly complicated. Therefore I
142 * applied KISS principle here.
143 */
144 if (!iio_device_claim_direct(iio_dev))
145 return -EBUSY;
146
147 reinit_completion(&adc->completion);
148
149 /*
150 * No buffered operation in progress, map the channel and trigger it.
151 * Virtual channel 0 is always used here as the others are always not
152 * used if doing raw sampling.
153 */
154 if (lradc->soc == IMX28_LRADC)
155 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
156 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
157 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
158
159 /* Enable / disable the divider per requirement */
160 if (test_bit(chan, &adc->is_divided))
161 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
162 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
163 else
164 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
165 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
166
167 /* Clean the slot's previous content, then set new one. */
168 writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
169 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
170 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
171
172 writel(0, adc->base + LRADC_CH(0));
173
174 /* Enable the IRQ and start sampling the channel. */
175 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
176 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
177 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
178
179 /* Wait for completion on the channel, 1 second max. */
180 ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
181 if (!ret)
182 ret = -ETIMEDOUT;
183 if (ret < 0)
184 goto err;
185
186 /* Read the data. */
187 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
188 ret = IIO_VAL_INT;
189
190 err:
191 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
192 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
193
194 iio_device_release_direct(iio_dev);
195
196 return ret;
197 }
198
mxs_lradc_adc_read_temp(struct iio_dev * iio_dev,int * val)199 static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
200 {
201 int ret, min, max;
202
203 ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
204 if (ret != IIO_VAL_INT)
205 return ret;
206
207 ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
208 if (ret != IIO_VAL_INT)
209 return ret;
210
211 *val = max - min;
212
213 return IIO_VAL_INT;
214 }
215
mxs_lradc_adc_read_raw(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long m)216 static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
217 const struct iio_chan_spec *chan,
218 int *val, int *val2, long m)
219 {
220 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
221
222 switch (m) {
223 case IIO_CHAN_INFO_RAW:
224 if (chan->type == IIO_TEMP)
225 return mxs_lradc_adc_read_temp(iio_dev, val);
226
227 return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
228
229 case IIO_CHAN_INFO_SCALE:
230 if (chan->type == IIO_TEMP) {
231 /*
232 * From the datasheet, we have to multiply by 1.012 and
233 * divide by 4
234 */
235 *val = 0;
236 *val2 = 253000;
237 return IIO_VAL_INT_PLUS_MICRO;
238 }
239
240 *val = adc->vref_mv[chan->channel];
241 *val2 = chan->scan_type.realbits -
242 test_bit(chan->channel, &adc->is_divided);
243 return IIO_VAL_FRACTIONAL_LOG2;
244
245 case IIO_CHAN_INFO_OFFSET:
246 if (chan->type == IIO_TEMP) {
247 /*
248 * The calculated value from the ADC is in Kelvin, we
249 * want Celsius for hwmon so the offset is -273.15
250 * The offset is applied before scaling so it is
251 * actually -213.15 * 4 / 1.012 = -1079.644268
252 */
253 *val = -1079;
254 *val2 = 644268;
255
256 return IIO_VAL_INT_PLUS_MICRO;
257 }
258
259 return -EINVAL;
260
261 default:
262 break;
263 }
264
265 return -EINVAL;
266 }
267
mxs_lradc_adc_write_raw(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,int val,int val2,long m)268 static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
269 const struct iio_chan_spec *chan,
270 int val, int val2, long m)
271 {
272 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
273 struct mxs_lradc_scale *scale_avail =
274 adc->scale_avail[chan->channel];
275 int ret;
276
277 if (!iio_device_claim_direct(iio_dev))
278 return -EBUSY;
279
280 switch (m) {
281 case IIO_CHAN_INFO_SCALE:
282 ret = -EINVAL;
283 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
284 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
285 /* divider by two disabled */
286 clear_bit(chan->channel, &adc->is_divided);
287 ret = 0;
288 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
289 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
290 /* divider by two enabled */
291 set_bit(chan->channel, &adc->is_divided);
292 ret = 0;
293 }
294
295 break;
296 default:
297 ret = -EINVAL;
298 break;
299 }
300
301 iio_device_release_direct(iio_dev);
302
303 return ret;
304 }
305
mxs_lradc_adc_write_raw_get_fmt(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,long m)306 static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
307 const struct iio_chan_spec *chan,
308 long m)
309 {
310 return IIO_VAL_INT_PLUS_NANO;
311 }
312
mxs_lradc_adc_show_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)313 static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
314 struct device_attribute *attr,
315 char *buf)
316 {
317 struct iio_dev *iio = dev_to_iio_dev(dev);
318 struct mxs_lradc_adc *adc = iio_priv(iio);
319 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
320 int i, ch, len = 0;
321
322 ch = iio_attr->address;
323 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
324 len += sprintf(buf + len, "%u.%09u ",
325 adc->scale_avail[ch][i].integer,
326 adc->scale_avail[ch][i].nano);
327
328 len += sprintf(buf + len, "\n");
329
330 return len;
331 }
332
333 #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
334 IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
335 mxs_lradc_adc_show_scale_avail, NULL, ch)
336
337 static SHOW_SCALE_AVAILABLE_ATTR(0);
338 static SHOW_SCALE_AVAILABLE_ATTR(1);
339 static SHOW_SCALE_AVAILABLE_ATTR(2);
340 static SHOW_SCALE_AVAILABLE_ATTR(3);
341 static SHOW_SCALE_AVAILABLE_ATTR(4);
342 static SHOW_SCALE_AVAILABLE_ATTR(5);
343 static SHOW_SCALE_AVAILABLE_ATTR(6);
344 static SHOW_SCALE_AVAILABLE_ATTR(7);
345 static SHOW_SCALE_AVAILABLE_ATTR(10);
346 static SHOW_SCALE_AVAILABLE_ATTR(11);
347 static SHOW_SCALE_AVAILABLE_ATTR(12);
348 static SHOW_SCALE_AVAILABLE_ATTR(13);
349 static SHOW_SCALE_AVAILABLE_ATTR(14);
350 static SHOW_SCALE_AVAILABLE_ATTR(15);
351
352 static struct attribute *mxs_lradc_adc_attributes[] = {
353 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
354 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
355 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
356 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
357 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
358 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
359 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
360 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
361 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
362 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
363 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
364 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
365 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
366 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
367 NULL
368 };
369
370 static const struct attribute_group mxs_lradc_adc_attribute_group = {
371 .attrs = mxs_lradc_adc_attributes,
372 };
373
374 static const struct iio_info mxs_lradc_adc_iio_info = {
375 .read_raw = mxs_lradc_adc_read_raw,
376 .write_raw = mxs_lradc_adc_write_raw,
377 .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
378 .attrs = &mxs_lradc_adc_attribute_group,
379 };
380
381 /* IRQ Handling */
mxs_lradc_adc_handle_irq(int irq,void * data)382 static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
383 {
384 struct iio_dev *iio = data;
385 struct mxs_lradc_adc *adc = iio_priv(iio);
386 struct mxs_lradc *lradc = adc->lradc;
387 unsigned long reg = readl(adc->base + LRADC_CTRL1);
388 unsigned long flags;
389
390 if (!(reg & mxs_lradc_irq_mask(lradc)))
391 return IRQ_NONE;
392
393 if (iio_buffer_enabled(iio)) {
394 if (reg & lradc->buffer_vchans) {
395 spin_lock_irqsave(&adc->lock, flags);
396 iio_trigger_poll(iio->trig);
397 spin_unlock_irqrestore(&adc->lock, flags);
398 }
399 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
400 complete(&adc->completion);
401 }
402
403 writel(reg & mxs_lradc_irq_mask(lradc),
404 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
405
406 return IRQ_HANDLED;
407 }
408
409
410 /* Trigger handling */
mxs_lradc_adc_trigger_handler(int irq,void * p)411 static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
412 {
413 struct iio_poll_func *pf = p;
414 struct iio_dev *iio = pf->indio_dev;
415 struct mxs_lradc_adc *adc = iio_priv(iio);
416 const u32 chan_value = LRADC_CH_ACCUMULATE |
417 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
418 unsigned int i, j = 0;
419
420 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
421 adc->buffer[j] = readl(adc->base + LRADC_CH(j));
422 writel(chan_value, adc->base + LRADC_CH(j));
423 adc->buffer[j] &= LRADC_CH_VALUE_MASK;
424 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
425 j++;
426 }
427
428 iio_push_to_buffers_with_ts(iio, adc->buffer, sizeof(adc->buffer),
429 pf->timestamp);
430
431 iio_trigger_notify_done(iio->trig);
432
433 return IRQ_HANDLED;
434 }
435
mxs_lradc_adc_configure_trigger(struct iio_trigger * trig,bool state)436 static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
437 {
438 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
439 struct mxs_lradc_adc *adc = iio_priv(iio);
440 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
441
442 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
443
444 return 0;
445 }
446
447 static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
448 .set_trigger_state = &mxs_lradc_adc_configure_trigger,
449 };
450
mxs_lradc_adc_trigger_init(struct iio_dev * iio)451 static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
452 {
453 int ret;
454 struct iio_trigger *trig;
455 struct mxs_lradc_adc *adc = iio_priv(iio);
456
457 trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
458 iio_device_id(iio));
459 if (!trig)
460 return -ENOMEM;
461
462 trig->dev.parent = adc->dev;
463 iio_trigger_set_drvdata(trig, iio);
464 trig->ops = &mxs_lradc_adc_trigger_ops;
465
466 ret = iio_trigger_register(trig);
467 if (ret)
468 return ret;
469
470 adc->trig = trig;
471
472 return 0;
473 }
474
mxs_lradc_adc_trigger_remove(struct iio_dev * iio)475 static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
476 {
477 struct mxs_lradc_adc *adc = iio_priv(iio);
478
479 iio_trigger_unregister(adc->trig);
480 }
481
mxs_lradc_adc_buffer_preenable(struct iio_dev * iio)482 static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
483 {
484 struct mxs_lradc_adc *adc = iio_priv(iio);
485 struct mxs_lradc *lradc = adc->lradc;
486 int chan, ofs = 0;
487 unsigned long enable = 0;
488 u32 ctrl4_set = 0;
489 u32 ctrl4_clr = 0;
490 u32 ctrl1_irq = 0;
491 const u32 chan_value = LRADC_CH_ACCUMULATE |
492 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
493
494 if (lradc->soc == IMX28_LRADC)
495 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
496 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
497 writel(lradc->buffer_vchans,
498 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
499
500 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
501 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
502 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
503 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
504 writel(chan_value, adc->base + LRADC_CH(ofs));
505 bitmap_set(&enable, ofs, 1);
506 ofs++;
507 }
508
509 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
510 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
511 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
512 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
513 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
514 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
515 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
516
517 return 0;
518 }
519
mxs_lradc_adc_buffer_postdisable(struct iio_dev * iio)520 static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
521 {
522 struct mxs_lradc_adc *adc = iio_priv(iio);
523 struct mxs_lradc *lradc = adc->lradc;
524
525 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
526 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
527
528 writel(lradc->buffer_vchans,
529 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
530 if (lradc->soc == IMX28_LRADC)
531 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
532 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
533
534 return 0;
535 }
536
mxs_lradc_adc_validate_scan_mask(struct iio_dev * iio,const unsigned long * mask)537 static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
538 const unsigned long *mask)
539 {
540 struct mxs_lradc_adc *adc = iio_priv(iio);
541 struct mxs_lradc *lradc = adc->lradc;
542 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
543 int rsvd_chans = 0;
544 unsigned long rsvd_mask = 0;
545
546 if (lradc->use_touchbutton)
547 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
548 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
549 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
550 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
551 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
552
553 if (lradc->use_touchbutton)
554 rsvd_chans++;
555 if (lradc->touchscreen_wire)
556 rsvd_chans += 2;
557
558 /* Test for attempts to map channels with special mode of operation. */
559 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
560 return false;
561
562 /* Test for attempts to map more channels then available slots. */
563 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
564 return false;
565
566 return true;
567 }
568
569 static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
570 .preenable = &mxs_lradc_adc_buffer_preenable,
571 .postdisable = &mxs_lradc_adc_buffer_postdisable,
572 .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
573 };
574
575 /* Driver initialization */
576 #define MXS_ADC_CHAN(idx, chan_type, name) { \
577 .type = (chan_type), \
578 .indexed = 1, \
579 .scan_index = (idx), \
580 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
581 BIT(IIO_CHAN_INFO_SCALE), \
582 .channel = (idx), \
583 .address = (idx), \
584 .scan_type = { \
585 .sign = 'u', \
586 .realbits = LRADC_RESOLUTION, \
587 .storagebits = 32, \
588 }, \
589 .datasheet_name = (name), \
590 }
591
592 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
593 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
594 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
595 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
596 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
597 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
598 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
599 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
600 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
601 /* Combined Temperature sensors */
602 {
603 .type = IIO_TEMP,
604 .indexed = 1,
605 .scan_index = 8,
606 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
607 BIT(IIO_CHAN_INFO_OFFSET) |
608 BIT(IIO_CHAN_INFO_SCALE),
609 .channel = 8,
610 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
611 .datasheet_name = "TEMP_DIE",
612 },
613 /* Hidden channel to keep indexes */
614 {
615 .type = IIO_TEMP,
616 .indexed = 1,
617 .scan_index = -1,
618 .channel = 9,
619 },
620 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
621 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
622 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
623 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
624 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
625 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
626 };
627
628 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
629 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
630 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
631 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
632 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
633 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
634 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
635 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
636 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
637 /* Combined Temperature sensors */
638 {
639 .type = IIO_TEMP,
640 .indexed = 1,
641 .scan_index = 8,
642 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
643 BIT(IIO_CHAN_INFO_OFFSET) |
644 BIT(IIO_CHAN_INFO_SCALE),
645 .channel = 8,
646 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
647 .datasheet_name = "TEMP_DIE",
648 },
649 /* Hidden channel to keep indexes */
650 {
651 .type = IIO_TEMP,
652 .indexed = 1,
653 .scan_index = -1,
654 .channel = 9,
655 },
656 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
657 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
658 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
659 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
660 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
661 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
662 };
663
mxs_lradc_adc_hw_init(struct mxs_lradc_adc * adc)664 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
665 {
666 /* The ADC always uses DELAY CHANNEL 0. */
667 const u32 adc_cfg =
668 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
669 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
670
671 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
672 writel(adc_cfg, adc->base + LRADC_DELAY(0));
673
674 /*
675 * Start internal temperature sensing by clearing bit
676 * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
677 * after power up.
678 */
679 writel(0, adc->base + LRADC_CTRL2);
680 }
681
mxs_lradc_adc_hw_stop(struct mxs_lradc_adc * adc)682 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
683 {
684 writel(0, adc->base + LRADC_DELAY(0));
685 }
686
mxs_lradc_adc_probe(struct platform_device * pdev)687 static int mxs_lradc_adc_probe(struct platform_device *pdev)
688 {
689 struct device *dev = &pdev->dev;
690 struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
691 struct mxs_lradc_adc *adc;
692 struct iio_dev *iio;
693 struct resource *iores;
694 int ret, irq, virq, i, s, n;
695 u64 scale_uv;
696 const char **irq_name;
697
698 /* Allocate the IIO device. */
699 iio = devm_iio_device_alloc(dev, sizeof(*adc));
700 if (!iio) {
701 dev_err(dev, "Failed to allocate IIO device\n");
702 return -ENOMEM;
703 }
704
705 adc = iio_priv(iio);
706 adc->lradc = lradc;
707 adc->dev = dev;
708
709 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
710 if (!iores)
711 return -EINVAL;
712
713 adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
714 if (!adc->base)
715 return -ENOMEM;
716
717 init_completion(&adc->completion);
718 spin_lock_init(&adc->lock);
719
720 platform_set_drvdata(pdev, iio);
721
722 iio->name = pdev->name;
723 iio->dev.of_node = dev->parent->of_node;
724 iio->info = &mxs_lradc_adc_iio_info;
725 iio->modes = INDIO_DIRECT_MODE;
726
727 if (lradc->soc == IMX23_LRADC) {
728 iio->channels = mx23_lradc_chan_spec;
729 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
730 irq_name = mx23_lradc_adc_irq_names;
731 n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
732 } else {
733 iio->channels = mx28_lradc_chan_spec;
734 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
735 irq_name = mx28_lradc_adc_irq_names;
736 n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
737 }
738
739 ret = stmp_reset_block(adc->base);
740 if (ret)
741 return ret;
742
743 for (i = 0; i < n; i++) {
744 irq = platform_get_irq_byname(pdev, irq_name[i]);
745 if (irq < 0)
746 return irq;
747
748 virq = irq_of_parse_and_map(dev->parent->of_node, irq);
749
750 ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
751 0, irq_name[i], iio);
752 if (ret)
753 return ret;
754 }
755
756 ret = mxs_lradc_adc_trigger_init(iio);
757 if (ret)
758 return ret;
759
760 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
761 &mxs_lradc_adc_trigger_handler,
762 &mxs_lradc_adc_buffer_ops);
763 if (ret)
764 goto err_trig;
765
766 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
767
768 /* Populate available ADC input ranges */
769 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
770 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
771 /*
772 * [s=0] = optional divider by two disabled (default)
773 * [s=1] = optional divider by two enabled
774 *
775 * The scale is calculated by doing:
776 * Vref >> (realbits - s)
777 * which multiplies by two on the second component
778 * of the array.
779 */
780 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
781 (LRADC_RESOLUTION - s);
782 adc->scale_avail[i][s].nano =
783 do_div(scale_uv, 100000000) * 10;
784 adc->scale_avail[i][s].integer = scale_uv;
785 }
786 }
787
788 /* Configure the hardware. */
789 mxs_lradc_adc_hw_init(adc);
790
791 /* Register IIO device. */
792 ret = iio_device_register(iio);
793 if (ret) {
794 dev_err(dev, "Failed to register IIO device\n");
795 goto err_dev;
796 }
797
798 return 0;
799
800 err_dev:
801 mxs_lradc_adc_hw_stop(adc);
802 iio_triggered_buffer_cleanup(iio);
803 err_trig:
804 mxs_lradc_adc_trigger_remove(iio);
805 return ret;
806 }
807
mxs_lradc_adc_remove(struct platform_device * pdev)808 static void mxs_lradc_adc_remove(struct platform_device *pdev)
809 {
810 struct iio_dev *iio = platform_get_drvdata(pdev);
811 struct mxs_lradc_adc *adc = iio_priv(iio);
812
813 iio_device_unregister(iio);
814 mxs_lradc_adc_hw_stop(adc);
815 iio_triggered_buffer_cleanup(iio);
816 mxs_lradc_adc_trigger_remove(iio);
817 }
818
819 static struct platform_driver mxs_lradc_adc_driver = {
820 .driver = {
821 .name = "mxs-lradc-adc",
822 },
823 .probe = mxs_lradc_adc_probe,
824 .remove = mxs_lradc_adc_remove,
825 };
826 module_platform_driver(mxs_lradc_adc_driver);
827
828 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
829 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
830 MODULE_LICENSE("GPL");
831 MODULE_ALIAS("platform:mxs-lradc-adc");
832