1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * An I2C and SPI driver for the NXP PCF2127/29/31 RTC
4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
8 * Watchdog and tamper functions
9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
10 *
11 * PCF2131 support
12 * Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
13 *
14 * based on the other drivers in this same directory.
15 *
16 * Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
17 * https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf
18 */
19
20 #include <linux/i2c.h>
21 #include <linux/spi/spi.h>
22 #include <linux/bcd.h>
23 #include <linux/bitfield.h>
24 #include <linux/rtc.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_device.h>
30 #include <linux/regmap.h>
31 #include <linux/watchdog.h>
32
33 /* Control register 1 */
34 #define PCF2127_REG_CTRL1 0x00
35 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3)
36 #define PCF2127_BIT_CTRL1_TSF1 BIT(4)
37 #define PCF2127_BIT_CTRL1_STOP BIT(5)
38 /* Control register 2 */
39 #define PCF2127_REG_CTRL2 0x01
40 #define PCF2127_BIT_CTRL2_AIE BIT(1)
41 #define PCF2127_BIT_CTRL2_TSIE BIT(2)
42 #define PCF2127_BIT_CTRL2_AF BIT(4)
43 #define PCF2127_BIT_CTRL2_TSF2 BIT(5)
44 #define PCF2127_BIT_CTRL2_WDTF BIT(6)
45 /* Control register 3 */
46 #define PCF2127_REG_CTRL3 0x02
47 #define PCF2127_BIT_CTRL3_BLIE BIT(0)
48 #define PCF2127_BIT_CTRL3_BIE BIT(1)
49 #define PCF2127_BIT_CTRL3_BLF BIT(2)
50 #define PCF2127_BIT_CTRL3_BF BIT(3)
51 #define PCF2127_BIT_CTRL3_BTSE BIT(4)
52 #define PCF2127_CTRL3_PM GENMASK(7, 5)
53 /* Time and date registers */
54 #define PCF2127_REG_TIME_BASE 0x03
55 #define PCF2127_BIT_SC_OSF BIT(7)
56 /* Alarm registers */
57 #define PCF2127_REG_ALARM_BASE 0x0A
58 #define PCF2127_BIT_ALARM_AE BIT(7)
59 /* CLKOUT control register */
60 #define PCF2127_REG_CLKOUT 0x0f
61 #define PCF2127_BIT_CLKOUT_OTPR BIT(5)
62 /* Watchdog registers */
63 #define PCF2127_REG_WD_CTL 0x10
64 #define PCF2127_BIT_WD_CTL_TF0 BIT(0)
65 #define PCF2127_BIT_WD_CTL_TF1 BIT(1)
66 #define PCF2127_BIT_WD_CTL_CD0 BIT(6)
67 #define PCF2127_BIT_WD_CTL_CD1 BIT(7)
68 #define PCF2127_REG_WD_VAL 0x11
69 /* Tamper timestamp1 registers */
70 #define PCF2127_REG_TS1_BASE 0x12
71 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
72 #define PCF2127_BIT_TS_CTRL_TSM BIT(7)
73 /*
74 * RAM registers
75 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
76 * battery backed and can survive a power outage.
77 * PCF2129/31 doesn't have this feature.
78 */
79 #define PCF2127_REG_RAM_ADDR_MSB 0x1A
80 #define PCF2127_REG_RAM_WRT_CMD 0x1C
81 #define PCF2127_REG_RAM_RD_CMD 0x1D
82
83 /* Watchdog timer value constants */
84 #define PCF2127_WD_VAL_STOP 0
85 /* PCF2127/29 watchdog timer value constants */
86 #define PCF2127_WD_CLOCK_HZ_X1000 1000 /* 1Hz */
87 #define PCF2127_WD_MIN_HW_HEARTBEAT_MS 500
88 /* PCF2131 watchdog timer value constants */
89 #define PCF2131_WD_CLOCK_HZ_X1000 250 /* 1/4Hz */
90 #define PCF2131_WD_MIN_HW_HEARTBEAT_MS 4000
91
92 #define PCF2127_WD_DEFAULT_TIMEOUT_S 60
93
94 /* Mask for currently enabled interrupts */
95 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
96 #define PCF2127_CTRL2_IRQ_MASK ( \
97 PCF2127_BIT_CTRL2_AF | \
98 PCF2127_BIT_CTRL2_WDTF | \
99 PCF2127_BIT_CTRL2_TSF2)
100
101 #define PCF2127_MAX_TS_SUPPORTED 4
102
103 /* Control register 4 */
104 #define PCF2131_REG_CTRL4 0x03
105 #define PCF2131_BIT_CTRL4_TSF4 BIT(4)
106 #define PCF2131_BIT_CTRL4_TSF3 BIT(5)
107 #define PCF2131_BIT_CTRL4_TSF2 BIT(6)
108 #define PCF2131_BIT_CTRL4_TSF1 BIT(7)
109 /* Control register 5 */
110 #define PCF2131_REG_CTRL5 0x04
111 #define PCF2131_BIT_CTRL5_TSIE4 BIT(4)
112 #define PCF2131_BIT_CTRL5_TSIE3 BIT(5)
113 #define PCF2131_BIT_CTRL5_TSIE2 BIT(6)
114 #define PCF2131_BIT_CTRL5_TSIE1 BIT(7)
115 /* Software reset register */
116 #define PCF2131_REG_SR_RESET 0x05
117 #define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5))
118 #define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7))
119 /* Time and date registers */
120 #define PCF2131_REG_TIME_BASE 0x07
121 /* Alarm registers */
122 #define PCF2131_REG_ALARM_BASE 0x0E
123 /* CLKOUT control register */
124 #define PCF2131_REG_CLKOUT 0x13
125 /* Watchdog registers */
126 #define PCF2131_REG_WD_CTL 0x35
127 #define PCF2131_REG_WD_VAL 0x36
128 /* Tamper timestamp1 registers */
129 #define PCF2131_REG_TS1_BASE 0x14
130 /* Tamper timestamp2 registers */
131 #define PCF2131_REG_TS2_BASE 0x1B
132 /* Tamper timestamp3 registers */
133 #define PCF2131_REG_TS3_BASE 0x22
134 /* Tamper timestamp4 registers */
135 #define PCF2131_REG_TS4_BASE 0x29
136 /* Interrupt mask registers */
137 #define PCF2131_REG_INT_A_MASK1 0x31
138 #define PCF2131_REG_INT_A_MASK2 0x32
139 #define PCF2131_REG_INT_B_MASK1 0x33
140 #define PCF2131_REG_INT_B_MASK2 0x34
141 #define PCF2131_BIT_INT_BLIE BIT(0)
142 #define PCF2131_BIT_INT_BIE BIT(1)
143 #define PCF2131_BIT_INT_AIE BIT(2)
144 #define PCF2131_BIT_INT_WD_CD BIT(3)
145 #define PCF2131_BIT_INT_SI BIT(4)
146 #define PCF2131_BIT_INT_MI BIT(5)
147 #define PCF2131_CTRL2_IRQ_MASK ( \
148 PCF2127_BIT_CTRL2_AF | \
149 PCF2127_BIT_CTRL2_WDTF)
150 #define PCF2131_CTRL4_IRQ_MASK ( \
151 PCF2131_BIT_CTRL4_TSF4 | \
152 PCF2131_BIT_CTRL4_TSF3 | \
153 PCF2131_BIT_CTRL4_TSF2 | \
154 PCF2131_BIT_CTRL4_TSF1)
155
156 enum pcf21xx_type {
157 PCF2127,
158 PCF2129,
159 PCF2131,
160 PCF21XX_LAST_ID
161 };
162
163 struct pcf21xx_ts_config {
164 u8 reg_base; /* Base register to read timestamp values. */
165
166 /*
167 * If the TS input pin is driven to GND, an interrupt can be generated
168 * (supported by all variants).
169 */
170 u8 gnd_detect_reg; /* Interrupt control register address. */
171 u8 gnd_detect_bit; /* Interrupt bit. */
172
173 /*
174 * If the TS input pin is driven to an intermediate level between GND
175 * and supply, an interrupt can be generated (optional feature depending
176 * on variant).
177 */
178 u8 inter_detect_reg; /* Interrupt control register address. */
179 u8 inter_detect_bit; /* Interrupt bit. */
180
181 u8 ie_reg; /* Interrupt enable control register. */
182 u8 ie_bit; /* Interrupt enable bit. */
183 };
184
185 struct pcf21xx_config {
186 int type; /* IC variant */
187 int max_register;
188 unsigned int has_nvmem:1;
189 unsigned int has_bit_wd_ctl_cd0:1;
190 unsigned int wd_val_reg_readable:1; /* If watchdog value register can be read. */
191 unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */
192 u8 reg_time_base; /* Time/date base register. */
193 u8 regs_alarm_base; /* Alarm function base registers. */
194 u8 reg_wd_ctl; /* Watchdog control register. */
195 u8 reg_wd_val; /* Watchdog value register. */
196 u8 reg_clkout; /* Clkout register. */
197 int wdd_clock_hz_x1000; /* Watchdog clock in Hz multiplicated by 1000 */
198 int wdd_min_hw_heartbeat_ms;
199 unsigned int ts_count;
200 struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED];
201 struct attribute_group attribute_group;
202 };
203
204 struct pcf2127 {
205 struct rtc_device *rtc;
206 struct watchdog_device wdd;
207 struct regmap *regmap;
208 const struct pcf21xx_config *cfg;
209 bool irq_enabled;
210 time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */
211 bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */
212 };
213
214 /*
215 * In the routines that deal directly with the pcf2127 hardware, we use
216 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
217 */
pcf2127_rtc_read_time(struct device * dev,struct rtc_time * tm)218 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
219 {
220 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
221 unsigned char buf[7];
222 int ret;
223
224 /*
225 * Avoid reading CTRL2 register as it causes WD_VAL register
226 * value to reset to 0 which means watchdog is stopped.
227 */
228 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base,
229 buf, sizeof(buf));
230 if (ret) {
231 dev_err(dev, "%s: read error\n", __func__);
232 return ret;
233 }
234
235 /* Clock integrity is not guaranteed when OSF flag is set. */
236 if (buf[0] & PCF2127_BIT_SC_OSF) {
237 /*
238 * no need clear the flag here,
239 * it will be cleared once the new date is saved
240 */
241 dev_warn(dev,
242 "oscillator stop detected, date/time is not reliable\n");
243 return -EINVAL;
244 }
245
246 dev_dbg(dev,
247 "%s: raw data is sec=%02x, min=%02x, hr=%02x, "
248 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
249 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
250
251 tm->tm_sec = bcd2bin(buf[0] & 0x7F);
252 tm->tm_min = bcd2bin(buf[1] & 0x7F);
253 tm->tm_hour = bcd2bin(buf[2] & 0x3F);
254 tm->tm_mday = bcd2bin(buf[3] & 0x3F);
255 tm->tm_wday = buf[4] & 0x07;
256 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1;
257 tm->tm_year = bcd2bin(buf[6]);
258 tm->tm_year += 100;
259
260 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
261 "mday=%d, mon=%d, year=%d, wday=%d\n",
262 __func__,
263 tm->tm_sec, tm->tm_min, tm->tm_hour,
264 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
265
266 return 0;
267 }
268
pcf2127_rtc_set_time(struct device * dev,struct rtc_time * tm)269 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
270 {
271 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
272 unsigned char buf[7];
273 int i = 0, err;
274
275 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
276 "mday=%d, mon=%d, year=%d, wday=%d\n",
277 __func__,
278 tm->tm_sec, tm->tm_min, tm->tm_hour,
279 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
280
281 /* hours, minutes and seconds */
282 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
283 buf[i++] = bin2bcd(tm->tm_min);
284 buf[i++] = bin2bcd(tm->tm_hour);
285 buf[i++] = bin2bcd(tm->tm_mday);
286 buf[i++] = tm->tm_wday & 0x07;
287
288 /* month, 1 - 12 */
289 buf[i++] = bin2bcd(tm->tm_mon + 1);
290
291 /* year */
292 buf[i++] = bin2bcd(tm->tm_year - 100);
293
294 /* Write access to time registers:
295 * PCF2127/29: no special action required.
296 * PCF2131: requires setting the STOP and CPR bits. STOP bit needs to
297 * be cleared after time registers are updated.
298 */
299 if (pcf2127->cfg->type == PCF2131) {
300 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
301 PCF2127_BIT_CTRL1_STOP,
302 PCF2127_BIT_CTRL1_STOP);
303 if (err) {
304 dev_dbg(dev, "setting STOP bit failed\n");
305 return err;
306 }
307
308 err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET,
309 PCF2131_SR_RESET_CPR_CMD);
310 if (err) {
311 dev_dbg(dev, "sending CPR cmd failed\n");
312 return err;
313 }
314 }
315
316 /* write time register's data */
317 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i);
318 if (err) {
319 dev_dbg(dev, "%s: err=%d", __func__, err);
320 return err;
321 }
322
323 if (pcf2127->cfg->type == PCF2131) {
324 /* Clear STOP bit (PCF2131 only) after write is completed. */
325 err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
326 PCF2127_BIT_CTRL1_STOP, 0);
327 if (err) {
328 dev_dbg(dev, "clearing STOP bit failed\n");
329 return err;
330 }
331 }
332
333 return 0;
334 }
335
pcf2127_param_get(struct device * dev,struct rtc_param * param)336 static int pcf2127_param_get(struct device *dev, struct rtc_param *param)
337 {
338 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
339 u32 value;
340 int ret;
341
342 switch (param->param) {
343 case RTC_PARAM_BACKUP_SWITCH_MODE:
344 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &value);
345 if (ret < 0)
346 return ret;
347
348 value = FIELD_GET(PCF2127_CTRL3_PM, value);
349
350 if (value < 0x3)
351 param->uvalue = RTC_BSM_LEVEL;
352 else if (value < 0x6)
353 param->uvalue = RTC_BSM_DIRECT;
354 else
355 param->uvalue = RTC_BSM_DISABLED;
356
357 break;
358
359 default:
360 return -EINVAL;
361 }
362
363 return 0;
364 }
365
pcf2127_param_set(struct device * dev,struct rtc_param * param)366 static int pcf2127_param_set(struct device *dev, struct rtc_param *param)
367 {
368 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
369 u8 mode = 0;
370 u32 value;
371 int ret;
372
373 switch (param->param) {
374 case RTC_PARAM_BACKUP_SWITCH_MODE:
375 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &value);
376 if (ret < 0)
377 return ret;
378
379 value = FIELD_GET(PCF2127_CTRL3_PM, value);
380
381 if (value > 5)
382 value -= 5;
383 else if (value > 2)
384 value -= 3;
385
386 switch (param->uvalue) {
387 case RTC_BSM_LEVEL:
388 break;
389 case RTC_BSM_DIRECT:
390 mode = 3;
391 break;
392 case RTC_BSM_DISABLED:
393 if (value == 0)
394 value = 1;
395 mode = 5;
396 break;
397 default:
398 return -EINVAL;
399 }
400
401 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
402 PCF2127_CTRL3_PM,
403 FIELD_PREP(PCF2127_CTRL3_PM, mode + value));
404
405 break;
406
407 default:
408 return -EINVAL;
409 }
410
411 return 0;
412 }
413
pcf2127_rtc_ioctl(struct device * dev,unsigned int cmd,unsigned long arg)414 static int pcf2127_rtc_ioctl(struct device *dev,
415 unsigned int cmd, unsigned long arg)
416 {
417 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
418 int val, touser = 0;
419 int ret;
420
421 switch (cmd) {
422 case RTC_VL_READ:
423 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
424 if (ret)
425 return ret;
426
427 if (val & PCF2127_BIT_CTRL3_BLF)
428 touser |= RTC_VL_BACKUP_LOW;
429
430 if (val & PCF2127_BIT_CTRL3_BF)
431 touser |= RTC_VL_BACKUP_SWITCH;
432
433 return put_user(touser, (unsigned int __user *)arg);
434
435 case RTC_VL_CLR:
436 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
437 PCF2127_BIT_CTRL3_BF, 0);
438
439 default:
440 return -ENOIOCTLCMD;
441 }
442 }
443
pcf2127_nvmem_read(void * priv,unsigned int offset,void * val,size_t bytes)444 static int pcf2127_nvmem_read(void *priv, unsigned int offset,
445 void *val, size_t bytes)
446 {
447 struct pcf2127 *pcf2127 = priv;
448 int ret;
449 unsigned char offsetbuf[] = { offset >> 8, offset };
450
451 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
452 offsetbuf, 2);
453 if (ret)
454 return ret;
455
456 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
457 val, bytes);
458 }
459
pcf2127_nvmem_write(void * priv,unsigned int offset,void * val,size_t bytes)460 static int pcf2127_nvmem_write(void *priv, unsigned int offset,
461 void *val, size_t bytes)
462 {
463 struct pcf2127 *pcf2127 = priv;
464 int ret;
465 unsigned char offsetbuf[] = { offset >> 8, offset };
466
467 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
468 offsetbuf, 2);
469 if (ret)
470 return ret;
471
472 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
473 val, bytes);
474 }
475
476 /* watchdog driver */
477
pcf2127_wdt_ping(struct watchdog_device * wdd)478 static int pcf2127_wdt_ping(struct watchdog_device *wdd)
479 {
480 int wd_val;
481 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
482
483 /*
484 * Compute counter value of WATCHDG_TIM_VAL to obtain desired period
485 * in seconds, depending on the source clock frequency.
486 */
487 wd_val = ((wdd->timeout * pcf2127->cfg->wdd_clock_hz_x1000) / 1000) + 1;
488
489 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wd_val);
490 }
491
492 /*
493 * Restart watchdog timer if feature is active.
494 *
495 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
496 * since register also contain control/status flags for other features.
497 * Always call this function after reading CTRL2 register.
498 */
pcf2127_wdt_active_ping(struct watchdog_device * wdd)499 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
500 {
501 int ret = 0;
502
503 if (watchdog_active(wdd)) {
504 ret = pcf2127_wdt_ping(wdd);
505 if (ret)
506 dev_err(wdd->parent,
507 "%s: watchdog restart failed, ret=%d\n",
508 __func__, ret);
509 }
510
511 return ret;
512 }
513
pcf2127_wdt_start(struct watchdog_device * wdd)514 static int pcf2127_wdt_start(struct watchdog_device *wdd)
515 {
516 return pcf2127_wdt_ping(wdd);
517 }
518
pcf2127_wdt_stop(struct watchdog_device * wdd)519 static int pcf2127_wdt_stop(struct watchdog_device *wdd)
520 {
521 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
522
523 return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
524 PCF2127_WD_VAL_STOP);
525 }
526
pcf2127_wdt_set_timeout(struct watchdog_device * wdd,unsigned int new_timeout)527 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
528 unsigned int new_timeout)
529 {
530 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
531 new_timeout, wdd->timeout);
532
533 wdd->timeout = new_timeout;
534
535 return pcf2127_wdt_active_ping(wdd);
536 }
537
538 static const struct watchdog_info pcf2127_wdt_info = {
539 .identity = "NXP PCF2127/PCF2129 Watchdog",
540 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
541 };
542
543 static const struct watchdog_ops pcf2127_watchdog_ops = {
544 .owner = THIS_MODULE,
545 .start = pcf2127_wdt_start,
546 .stop = pcf2127_wdt_stop,
547 .ping = pcf2127_wdt_ping,
548 .set_timeout = pcf2127_wdt_set_timeout,
549 };
550
551 /*
552 * Compute watchdog period, t, in seconds, from the WATCHDG_TIM_VAL register
553 * value, n, and the clock frequency, f1000, in Hz x 1000.
554 *
555 * The PCF2127/29 datasheet gives t as:
556 * t = n / f
557 * The PCF2131 datasheet gives t as:
558 * t = (n - 1) / f
559 * For both variants, the watchdog is triggered when the WATCHDG_TIM_VAL reaches
560 * the value 1, and not zero. Consequently, the equation from the PCF2131
561 * datasheet seems to be the correct one for both variants.
562 */
pcf2127_watchdog_get_period(int n,int f1000)563 static int pcf2127_watchdog_get_period(int n, int f1000)
564 {
565 return (1000 * (n - 1)) / f1000;
566 }
567
pcf2127_watchdog_init(struct device * dev,struct pcf2127 * pcf2127)568 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
569 {
570 int ret;
571
572 if (!IS_ENABLED(CONFIG_WATCHDOG) ||
573 !device_property_read_bool(dev, "reset-source"))
574 return 0;
575
576 pcf2127->wdd.parent = dev;
577 pcf2127->wdd.info = &pcf2127_wdt_info;
578 pcf2127->wdd.ops = &pcf2127_watchdog_ops;
579
580 pcf2127->wdd.min_timeout =
581 pcf2127_watchdog_get_period(
582 2, pcf2127->cfg->wdd_clock_hz_x1000);
583 pcf2127->wdd.max_timeout =
584 pcf2127_watchdog_get_period(
585 255, pcf2127->cfg->wdd_clock_hz_x1000);
586 pcf2127->wdd.timeout = PCF2127_WD_DEFAULT_TIMEOUT_S;
587
588 dev_dbg(dev, "%s clock = %d Hz / 1000\n", __func__,
589 pcf2127->cfg->wdd_clock_hz_x1000);
590
591 pcf2127->wdd.min_hw_heartbeat_ms = pcf2127->cfg->wdd_min_hw_heartbeat_ms;
592 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
593
594 watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
595
596 /* Test if watchdog timer is started by bootloader */
597 if (pcf2127->cfg->wd_val_reg_readable) {
598 u32 wdd_timeout;
599
600 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
601 &wdd_timeout);
602 if (ret)
603 return ret;
604
605 if (wdd_timeout)
606 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
607 }
608
609 return devm_watchdog_register_device(dev, &pcf2127->wdd);
610 }
611
612 /* Alarm */
pcf2127_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)613 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
614 {
615 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
616 u8 buf[5];
617 unsigned int ctrl2;
618 int ret;
619
620 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
621 if (ret)
622 return ret;
623
624 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
625 if (ret)
626 return ret;
627
628 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
629 buf, sizeof(buf));
630 if (ret)
631 return ret;
632
633 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
634 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
635
636 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
637 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
638 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
639 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
640
641 return 0;
642 }
643
pcf2127_rtc_alarm_irq_enable(struct device * dev,u32 enable)644 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
645 {
646 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
647 int ret;
648
649 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
650 PCF2127_BIT_CTRL2_AIE,
651 enable ? PCF2127_BIT_CTRL2_AIE : 0);
652 if (ret)
653 return ret;
654
655 return pcf2127_wdt_active_ping(&pcf2127->wdd);
656 }
657
pcf2127_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)658 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
659 {
660 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
661 uint8_t buf[5];
662 int ret;
663
664 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
665 PCF2127_BIT_CTRL2_AF, 0);
666 if (ret)
667 return ret;
668
669 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
670 if (ret)
671 return ret;
672
673 buf[0] = bin2bcd(alrm->time.tm_sec);
674 buf[1] = bin2bcd(alrm->time.tm_min);
675 buf[2] = bin2bcd(alrm->time.tm_hour);
676 buf[3] = bin2bcd(alrm->time.tm_mday);
677 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
678
679 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
680 buf, sizeof(buf));
681 if (ret)
682 return ret;
683
684 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
685 }
686
687 /*
688 * This function reads one timestamp function data, caller is responsible for
689 * calling pcf2127_wdt_active_ping()
690 */
pcf2127_rtc_ts_read(struct device * dev,time64_t * ts,int ts_id)691 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts,
692 int ts_id)
693 {
694 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
695 struct rtc_time tm;
696 int ret;
697 unsigned char data[7];
698
699 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base,
700 data, sizeof(data));
701 if (ret) {
702 dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
703 return ret;
704 }
705
706 dev_dbg(dev,
707 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
708 __func__, data[1], data[2], data[3], data[4], data[5], data[6]);
709
710 tm.tm_sec = bcd2bin(data[1] & 0x7F);
711 tm.tm_min = bcd2bin(data[2] & 0x7F);
712 tm.tm_hour = bcd2bin(data[3] & 0x3F);
713 tm.tm_mday = bcd2bin(data[4] & 0x3F);
714 /* TS_MO register (month) value range: 1-12 */
715 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
716 tm.tm_year = bcd2bin(data[6]);
717 if (tm.tm_year < 70)
718 tm.tm_year += 100; /* assume we are in 1970...2069 */
719
720 ret = rtc_valid_tm(&tm);
721 if (ret) {
722 dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
723 return ret;
724 }
725
726 *ts = rtc_tm_to_time64(&tm);
727 return 0;
728 };
729
pcf2127_rtc_ts_snapshot(struct device * dev,int ts_id)730 static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id)
731 {
732 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
733 int ret;
734
735 if (ts_id >= pcf2127->cfg->ts_count)
736 return;
737
738 /* Let userspace read the first timestamp */
739 if (pcf2127->ts_valid[ts_id])
740 return;
741
742 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id);
743 if (!ret)
744 pcf2127->ts_valid[ts_id] = true;
745 }
746
pcf2127_rtc_irq(int irq,void * dev)747 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
748 {
749 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
750 unsigned int ctrl2;
751 int ret = 0;
752
753 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
754 if (ret)
755 return IRQ_NONE;
756
757 if (pcf2127->cfg->ts_count == 1) {
758 /* PCF2127/29 */
759 unsigned int ctrl1;
760
761 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
762 if (ret)
763 return IRQ_NONE;
764
765 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
766 return IRQ_NONE;
767
768 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
769 pcf2127_rtc_ts_snapshot(dev, 0);
770
771 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
772 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
773 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
774
775 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
776 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
777 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
778 } else {
779 /* PCF2131. */
780 unsigned int ctrl4;
781
782 ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4);
783 if (ret)
784 return IRQ_NONE;
785
786 if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK))
787 return IRQ_NONE;
788
789 if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) {
790 int i;
791 int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */
792
793 for (i = 0; i < pcf2127->cfg->ts_count; i++) {
794 if (ctrl4 & tsf_bit)
795 pcf2127_rtc_ts_snapshot(dev, i);
796
797 tsf_bit = tsf_bit >> 1;
798 }
799
800 regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4,
801 ctrl4 & ~PCF2131_CTRL4_IRQ_MASK);
802 }
803
804 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK)
805 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
806 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK);
807 }
808
809 if (ctrl2 & PCF2127_BIT_CTRL2_AF)
810 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
811
812 pcf2127_wdt_active_ping(&pcf2127->wdd);
813
814 return IRQ_HANDLED;
815 }
816
817 static const struct rtc_class_ops pcf2127_rtc_ops = {
818 .ioctl = pcf2127_rtc_ioctl,
819 .read_time = pcf2127_rtc_read_time,
820 .set_time = pcf2127_rtc_set_time,
821 .read_alarm = pcf2127_rtc_read_alarm,
822 .set_alarm = pcf2127_rtc_set_alarm,
823 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
824 .param_get = pcf2127_param_get,
825 .param_set = pcf2127_param_set,
826 };
827
828 /* sysfs interface */
829
timestamp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count,int ts_id)830 static ssize_t timestamp_store(struct device *dev,
831 struct device_attribute *attr,
832 const char *buf, size_t count, int ts_id)
833 {
834 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
835 int ret;
836
837 if (ts_id >= pcf2127->cfg->ts_count)
838 return 0;
839
840 if (pcf2127->irq_enabled) {
841 pcf2127->ts_valid[ts_id] = false;
842 } else {
843 /* Always clear GND interrupt bit. */
844 ret = regmap_update_bits(pcf2127->regmap,
845 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
846 pcf2127->cfg->ts[ts_id].gnd_detect_bit,
847 0);
848
849 if (ret) {
850 dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret);
851 return ret;
852 }
853
854 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
855 /* Clear intermediate level interrupt bit if supported. */
856 ret = regmap_update_bits(pcf2127->regmap,
857 pcf2127->cfg->ts[ts_id].inter_detect_reg,
858 pcf2127->cfg->ts[ts_id].inter_detect_bit,
859 0);
860 if (ret) {
861 dev_err(dev, "%s: update TS intermediate level detect ret=%d\n",
862 __func__, ret);
863 return ret;
864 }
865 }
866
867 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
868 if (ret)
869 return ret;
870 }
871
872 return count;
873 }
874
timestamp0_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)875 static ssize_t timestamp0_store(struct device *dev,
876 struct device_attribute *attr,
877 const char *buf, size_t count)
878 {
879 return timestamp_store(dev, attr, buf, count, 0);
880 };
881
timestamp1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)882 static ssize_t timestamp1_store(struct device *dev,
883 struct device_attribute *attr,
884 const char *buf, size_t count)
885 {
886 return timestamp_store(dev, attr, buf, count, 1);
887 };
888
timestamp2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)889 static ssize_t timestamp2_store(struct device *dev,
890 struct device_attribute *attr,
891 const char *buf, size_t count)
892 {
893 return timestamp_store(dev, attr, buf, count, 2);
894 };
895
timestamp3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)896 static ssize_t timestamp3_store(struct device *dev,
897 struct device_attribute *attr,
898 const char *buf, size_t count)
899 {
900 return timestamp_store(dev, attr, buf, count, 3);
901 };
902
timestamp_show(struct device * dev,struct device_attribute * attr,char * buf,int ts_id)903 static ssize_t timestamp_show(struct device *dev,
904 struct device_attribute *attr, char *buf,
905 int ts_id)
906 {
907 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
908 int ret;
909 time64_t ts;
910
911 if (ts_id >= pcf2127->cfg->ts_count)
912 return 0;
913
914 if (pcf2127->irq_enabled) {
915 if (!pcf2127->ts_valid[ts_id])
916 return 0;
917 ts = pcf2127->ts[ts_id];
918 } else {
919 u8 valid_low = 0;
920 u8 valid_inter = 0;
921 unsigned int ctrl;
922
923 /* Check if TS input pin is driven to GND, supported by all
924 * variants.
925 */
926 ret = regmap_read(pcf2127->regmap,
927 pcf2127->cfg->ts[ts_id].gnd_detect_reg,
928 &ctrl);
929 if (ret)
930 return 0;
931
932 valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit;
933
934 if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
935 /* Check if TS input pin is driven to intermediate level
936 * between GND and supply, if supported by variant.
937 */
938 ret = regmap_read(pcf2127->regmap,
939 pcf2127->cfg->ts[ts_id].inter_detect_reg,
940 &ctrl);
941 if (ret)
942 return 0;
943
944 valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit;
945 }
946
947 if (!valid_low && !valid_inter)
948 return 0;
949
950 ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id);
951 if (ret)
952 return 0;
953
954 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
955 if (ret)
956 return ret;
957 }
958 return sprintf(buf, "%llu\n", (unsigned long long)ts);
959 }
960
timestamp0_show(struct device * dev,struct device_attribute * attr,char * buf)961 static ssize_t timestamp0_show(struct device *dev,
962 struct device_attribute *attr, char *buf)
963 {
964 return timestamp_show(dev, attr, buf, 0);
965 };
966
timestamp1_show(struct device * dev,struct device_attribute * attr,char * buf)967 static ssize_t timestamp1_show(struct device *dev,
968 struct device_attribute *attr, char *buf)
969 {
970 return timestamp_show(dev, attr, buf, 1);
971 };
972
timestamp2_show(struct device * dev,struct device_attribute * attr,char * buf)973 static ssize_t timestamp2_show(struct device *dev,
974 struct device_attribute *attr, char *buf)
975 {
976 return timestamp_show(dev, attr, buf, 2);
977 };
978
timestamp3_show(struct device * dev,struct device_attribute * attr,char * buf)979 static ssize_t timestamp3_show(struct device *dev,
980 struct device_attribute *attr, char *buf)
981 {
982 return timestamp_show(dev, attr, buf, 3);
983 };
984
985 static DEVICE_ATTR_RW(timestamp0);
986 static DEVICE_ATTR_RW(timestamp1);
987 static DEVICE_ATTR_RW(timestamp2);
988 static DEVICE_ATTR_RW(timestamp3);
989
990 static struct attribute *pcf2127_attrs[] = {
991 &dev_attr_timestamp0.attr,
992 NULL
993 };
994
995 static struct attribute *pcf2131_attrs[] = {
996 &dev_attr_timestamp0.attr,
997 &dev_attr_timestamp1.attr,
998 &dev_attr_timestamp2.attr,
999 &dev_attr_timestamp3.attr,
1000 NULL
1001 };
1002
1003 static struct pcf21xx_config pcf21xx_cfg[] = {
1004 [PCF2127] = {
1005 .type = PCF2127,
1006 .max_register = 0x1d,
1007 .has_nvmem = 1,
1008 .has_bit_wd_ctl_cd0 = 1,
1009 .wd_val_reg_readable = 1,
1010 .has_int_a_b = 0,
1011 .reg_time_base = PCF2127_REG_TIME_BASE,
1012 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
1013 .reg_wd_ctl = PCF2127_REG_WD_CTL,
1014 .reg_wd_val = PCF2127_REG_WD_VAL,
1015 .reg_clkout = PCF2127_REG_CLKOUT,
1016 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
1017 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
1018 .ts_count = 1,
1019 .ts[0] = {
1020 .reg_base = PCF2127_REG_TS1_BASE,
1021 .gnd_detect_reg = PCF2127_REG_CTRL1,
1022 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
1023 .inter_detect_reg = PCF2127_REG_CTRL2,
1024 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
1025 .ie_reg = PCF2127_REG_CTRL2,
1026 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
1027 },
1028 .attribute_group = {
1029 .attrs = pcf2127_attrs,
1030 },
1031 },
1032 [PCF2129] = {
1033 .type = PCF2129,
1034 .max_register = 0x19,
1035 .has_nvmem = 0,
1036 .has_bit_wd_ctl_cd0 = 0,
1037 .wd_val_reg_readable = 1,
1038 .has_int_a_b = 0,
1039 .reg_time_base = PCF2127_REG_TIME_BASE,
1040 .regs_alarm_base = PCF2127_REG_ALARM_BASE,
1041 .reg_wd_ctl = PCF2127_REG_WD_CTL,
1042 .reg_wd_val = PCF2127_REG_WD_VAL,
1043 .reg_clkout = PCF2127_REG_CLKOUT,
1044 .wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
1045 .wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
1046 .ts_count = 1,
1047 .ts[0] = {
1048 .reg_base = PCF2127_REG_TS1_BASE,
1049 .gnd_detect_reg = PCF2127_REG_CTRL1,
1050 .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
1051 .inter_detect_reg = PCF2127_REG_CTRL2,
1052 .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
1053 .ie_reg = PCF2127_REG_CTRL2,
1054 .ie_bit = PCF2127_BIT_CTRL2_TSIE,
1055 },
1056 .attribute_group = {
1057 .attrs = pcf2127_attrs,
1058 },
1059 },
1060 [PCF2131] = {
1061 .type = PCF2131,
1062 .max_register = 0x36,
1063 .has_nvmem = 0,
1064 .has_bit_wd_ctl_cd0 = 0,
1065 .wd_val_reg_readable = 0,
1066 .has_int_a_b = 1,
1067 .reg_time_base = PCF2131_REG_TIME_BASE,
1068 .regs_alarm_base = PCF2131_REG_ALARM_BASE,
1069 .reg_wd_ctl = PCF2131_REG_WD_CTL,
1070 .reg_wd_val = PCF2131_REG_WD_VAL,
1071 .reg_clkout = PCF2131_REG_CLKOUT,
1072 .wdd_clock_hz_x1000 = PCF2131_WD_CLOCK_HZ_X1000,
1073 .wdd_min_hw_heartbeat_ms = PCF2131_WD_MIN_HW_HEARTBEAT_MS,
1074 .ts_count = 4,
1075 .ts[0] = {
1076 .reg_base = PCF2131_REG_TS1_BASE,
1077 .gnd_detect_reg = PCF2131_REG_CTRL4,
1078 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1,
1079 .inter_detect_bit = 0,
1080 .ie_reg = PCF2131_REG_CTRL5,
1081 .ie_bit = PCF2131_BIT_CTRL5_TSIE1,
1082 },
1083 .ts[1] = {
1084 .reg_base = PCF2131_REG_TS2_BASE,
1085 .gnd_detect_reg = PCF2131_REG_CTRL4,
1086 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2,
1087 .inter_detect_bit = 0,
1088 .ie_reg = PCF2131_REG_CTRL5,
1089 .ie_bit = PCF2131_BIT_CTRL5_TSIE2,
1090 },
1091 .ts[2] = {
1092 .reg_base = PCF2131_REG_TS3_BASE,
1093 .gnd_detect_reg = PCF2131_REG_CTRL4,
1094 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3,
1095 .inter_detect_bit = 0,
1096 .ie_reg = PCF2131_REG_CTRL5,
1097 .ie_bit = PCF2131_BIT_CTRL5_TSIE3,
1098 },
1099 .ts[3] = {
1100 .reg_base = PCF2131_REG_TS4_BASE,
1101 .gnd_detect_reg = PCF2131_REG_CTRL4,
1102 .gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4,
1103 .inter_detect_bit = 0,
1104 .ie_reg = PCF2131_REG_CTRL5,
1105 .ie_bit = PCF2131_BIT_CTRL5_TSIE4,
1106 },
1107 .attribute_group = {
1108 .attrs = pcf2131_attrs,
1109 },
1110 },
1111 };
1112
1113 /*
1114 * Enable timestamp function and corresponding interrupt(s).
1115 */
pcf2127_enable_ts(struct device * dev,int ts_id)1116 static int pcf2127_enable_ts(struct device *dev, int ts_id)
1117 {
1118 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
1119 int ret;
1120
1121 if (ts_id >= pcf2127->cfg->ts_count) {
1122 dev_err(dev, "%s: invalid tamper detection ID (%d)\n",
1123 __func__, ts_id);
1124 return -EINVAL;
1125 }
1126
1127 /* Enable timestamp function. */
1128 ret = regmap_update_bits(pcf2127->regmap,
1129 pcf2127->cfg->ts[ts_id].reg_base,
1130 PCF2127_BIT_TS_CTRL_TSOFF |
1131 PCF2127_BIT_TS_CTRL_TSM,
1132 PCF2127_BIT_TS_CTRL_TSM);
1133 if (ret) {
1134 dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n",
1135 __func__, ts_id);
1136 return ret;
1137 }
1138
1139 /*
1140 * Enable interrupt generation when TSF timestamp flag is set.
1141 * Interrupt signals are open-drain outputs and can be left floating if
1142 * unused.
1143 */
1144 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg,
1145 pcf2127->cfg->ts[ts_id].ie_bit,
1146 pcf2127->cfg->ts[ts_id].ie_bit);
1147 if (ret) {
1148 dev_err(dev, "%s: tamper detection TSIE%d config failed\n",
1149 __func__, ts_id);
1150 return ret;
1151 }
1152
1153 return ret;
1154 }
1155
1156 /* Route all interrupt sources to INT A pin. */
pcf2127_configure_interrupt_pins(struct device * dev)1157 static int pcf2127_configure_interrupt_pins(struct device *dev)
1158 {
1159 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
1160 int ret;
1161
1162 /* Mask bits need to be cleared to enable corresponding
1163 * interrupt source.
1164 */
1165 ret = regmap_write(pcf2127->regmap,
1166 PCF2131_REG_INT_A_MASK1, 0);
1167 if (ret)
1168 return ret;
1169
1170 ret = regmap_write(pcf2127->regmap,
1171 PCF2131_REG_INT_A_MASK2, 0);
1172 if (ret)
1173 return ret;
1174
1175 return ret;
1176 }
1177
pcf2127_probe(struct device * dev,struct regmap * regmap,int alarm_irq,const struct pcf21xx_config * config)1178 static int pcf2127_probe(struct device *dev, struct regmap *regmap,
1179 int alarm_irq, const struct pcf21xx_config *config)
1180 {
1181 struct pcf2127 *pcf2127;
1182 int ret = 0;
1183 unsigned int val;
1184
1185 dev_dbg(dev, "%s\n", __func__);
1186
1187 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
1188 if (!pcf2127)
1189 return -ENOMEM;
1190
1191 pcf2127->regmap = regmap;
1192 pcf2127->cfg = config;
1193
1194 dev_set_drvdata(dev, pcf2127);
1195
1196 pcf2127->rtc = devm_rtc_allocate_device(dev);
1197 if (IS_ERR(pcf2127->rtc))
1198 return PTR_ERR(pcf2127->rtc);
1199
1200 pcf2127->rtc->ops = &pcf2127_rtc_ops;
1201 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
1202 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
1203 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
1204
1205 /*
1206 * PCF2127/29 do not work correctly when setting alarms at 1s intervals.
1207 * PCF2131 is ok.
1208 */
1209 if (pcf2127->cfg->type == PCF2127 || pcf2127->cfg->type == PCF2129) {
1210 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features);
1211 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features);
1212 }
1213
1214 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
1215
1216 if (alarm_irq > 0) {
1217 unsigned long flags;
1218
1219 /*
1220 * If flags = 0, devm_request_threaded_irq() will use IRQ flags
1221 * obtained from device tree.
1222 */
1223 if (dev_fwnode(dev))
1224 flags = 0;
1225 else
1226 flags = IRQF_TRIGGER_LOW;
1227
1228 ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
1229 pcf2127_rtc_irq,
1230 flags | IRQF_ONESHOT,
1231 dev_name(dev), dev);
1232 if (ret) {
1233 dev_err(dev, "failed to request alarm irq\n");
1234 return ret;
1235 }
1236 pcf2127->irq_enabled = true;
1237 }
1238
1239 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
1240 device_init_wakeup(dev, true);
1241 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
1242 }
1243
1244 if (pcf2127->cfg->has_int_a_b) {
1245 /* Configure int A/B pins, independently of alarm_irq. */
1246 ret = pcf2127_configure_interrupt_pins(dev);
1247 if (ret) {
1248 dev_err(dev, "failed to configure interrupt pins\n");
1249 return ret;
1250 }
1251 }
1252
1253 if (pcf2127->cfg->has_nvmem) {
1254 struct nvmem_config nvmem_cfg = {
1255 .priv = pcf2127,
1256 .reg_read = pcf2127_nvmem_read,
1257 .reg_write = pcf2127_nvmem_write,
1258 .size = 512,
1259 };
1260
1261 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
1262 }
1263
1264 /*
1265 * The "Power-On Reset Override" facility prevents the RTC to do a reset
1266 * after power on. For normal operation the PORO must be disabled.
1267 */
1268 ret = regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
1269 PCF2127_BIT_CTRL1_POR_OVRD);
1270 if (ret < 0)
1271 return ret;
1272
1273 ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val);
1274 if (ret < 0)
1275 return ret;
1276
1277 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) {
1278 ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout,
1279 PCF2127_BIT_CLKOUT_OTPR);
1280 if (ret < 0)
1281 return ret;
1282
1283 msleep(100);
1284 }
1285
1286 /*
1287 * Watchdog timer enabled and reset pin /RST activated when timed out.
1288 * Select 1Hz clock source for watchdog timer (1/4Hz for PCF2131).
1289 * Note: Countdown timer disabled and not available.
1290 * For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD
1291 * of register watchdg_tim_ctl. The bit[6] is labeled
1292 * as T. Bits labeled as T must always be written with
1293 * logic 0.
1294 */
1295 ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl,
1296 PCF2127_BIT_WD_CTL_CD1 |
1297 PCF2127_BIT_WD_CTL_CD0 |
1298 PCF2127_BIT_WD_CTL_TF1 |
1299 PCF2127_BIT_WD_CTL_TF0,
1300 PCF2127_BIT_WD_CTL_CD1 |
1301 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
1302 PCF2127_BIT_WD_CTL_TF1);
1303 if (ret) {
1304 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
1305 return ret;
1306 }
1307
1308 pcf2127_watchdog_init(dev, pcf2127);
1309
1310 /*
1311 * Disable battery low/switch-over timestamp and interrupts.
1312 * Clear battery interrupt flags which can block new trigger events.
1313 * Note: This is the default chip behaviour but added to ensure
1314 * correct tamper timestamp and interrupt function.
1315 */
1316 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
1317 PCF2127_BIT_CTRL3_BTSE |
1318 PCF2127_BIT_CTRL3_BIE |
1319 PCF2127_BIT_CTRL3_BLIE, 0);
1320 if (ret) {
1321 dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
1322 __func__);
1323 return ret;
1324 }
1325
1326 /*
1327 * Enable timestamp functions 1 to 4.
1328 */
1329 for (int i = 0; i < pcf2127->cfg->ts_count; i++) {
1330 ret = pcf2127_enable_ts(dev, i);
1331 if (ret)
1332 return ret;
1333 }
1334
1335 ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group);
1336 if (ret) {
1337 dev_err(dev, "%s: tamper sysfs registering failed\n",
1338 __func__);
1339 return ret;
1340 }
1341
1342 return devm_rtc_register_device(pcf2127->rtc);
1343 }
1344
1345 #ifdef CONFIG_OF
1346 static const struct of_device_id pcf2127_of_match[] = {
1347 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] },
1348 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] },
1349 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] },
1350 { .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] },
1351 {}
1352 };
1353 MODULE_DEVICE_TABLE(of, pcf2127_of_match);
1354 #endif
1355
1356 #if IS_ENABLED(CONFIG_I2C)
1357
pcf2127_i2c_write(void * context,const void * data,size_t count)1358 static int pcf2127_i2c_write(void *context, const void *data, size_t count)
1359 {
1360 struct device *dev = context;
1361 struct i2c_client *client = to_i2c_client(dev);
1362 int ret;
1363
1364 ret = i2c_master_send(client, data, count);
1365 if (ret != count)
1366 return ret < 0 ? ret : -EIO;
1367
1368 return 0;
1369 }
1370
pcf2127_i2c_gather_write(void * context,const void * reg,size_t reg_size,const void * val,size_t val_size)1371 static int pcf2127_i2c_gather_write(void *context,
1372 const void *reg, size_t reg_size,
1373 const void *val, size_t val_size)
1374 {
1375 struct device *dev = context;
1376 struct i2c_client *client = to_i2c_client(dev);
1377 int ret;
1378 void *buf;
1379
1380 if (WARN_ON(reg_size != 1))
1381 return -EINVAL;
1382
1383 buf = kmalloc(val_size + 1, GFP_KERNEL);
1384 if (!buf)
1385 return -ENOMEM;
1386
1387 memcpy(buf, reg, 1);
1388 memcpy(buf + 1, val, val_size);
1389
1390 ret = i2c_master_send(client, buf, val_size + 1);
1391
1392 kfree(buf);
1393
1394 if (ret != val_size + 1)
1395 return ret < 0 ? ret : -EIO;
1396
1397 return 0;
1398 }
1399
pcf2127_i2c_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)1400 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
1401 void *val, size_t val_size)
1402 {
1403 struct device *dev = context;
1404 struct i2c_client *client = to_i2c_client(dev);
1405 int ret;
1406
1407 if (WARN_ON(reg_size != 1))
1408 return -EINVAL;
1409
1410 ret = i2c_master_send(client, reg, 1);
1411 if (ret != 1)
1412 return ret < 0 ? ret : -EIO;
1413
1414 ret = i2c_master_recv(client, val, val_size);
1415 if (ret != val_size)
1416 return ret < 0 ? ret : -EIO;
1417
1418 return 0;
1419 }
1420
1421 /*
1422 * The reason we need this custom regmap_bus instead of using regmap_init_i2c()
1423 * is that the STOP condition is required between set register address and
1424 * read register data when reading from registers.
1425 */
1426 static const struct regmap_bus pcf2127_i2c_regmap = {
1427 .write = pcf2127_i2c_write,
1428 .gather_write = pcf2127_i2c_gather_write,
1429 .read = pcf2127_i2c_read,
1430 };
1431
1432 static struct i2c_driver pcf2127_i2c_driver;
1433
1434 static const struct i2c_device_id pcf2127_i2c_id[] = {
1435 { "pcf2127", PCF2127 },
1436 { "pcf2129", PCF2129 },
1437 { "pca2129", PCF2129 },
1438 { "pcf2131", PCF2131 },
1439 { }
1440 };
1441 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
1442
pcf2127_i2c_probe(struct i2c_client * client)1443 static int pcf2127_i2c_probe(struct i2c_client *client)
1444 {
1445 struct regmap *regmap;
1446 static struct regmap_config config = {
1447 .reg_bits = 8,
1448 .val_bits = 8,
1449 };
1450 const struct pcf21xx_config *variant;
1451
1452 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
1453 return -ENODEV;
1454
1455 if (client->dev.of_node) {
1456 variant = of_device_get_match_data(&client->dev);
1457 if (!variant)
1458 return -ENODEV;
1459 } else {
1460 enum pcf21xx_type type =
1461 i2c_match_id(pcf2127_i2c_id, client)->driver_data;
1462
1463 if (type >= PCF21XX_LAST_ID)
1464 return -ENODEV;
1465 variant = &pcf21xx_cfg[type];
1466 }
1467
1468 config.max_register = variant->max_register,
1469
1470 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
1471 &client->dev, &config);
1472 if (IS_ERR(regmap)) {
1473 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
1474 __func__, PTR_ERR(regmap));
1475 return PTR_ERR(regmap);
1476 }
1477
1478 return pcf2127_probe(&client->dev, regmap, client->irq, variant);
1479 }
1480
1481 static struct i2c_driver pcf2127_i2c_driver = {
1482 .driver = {
1483 .name = "rtc-pcf2127-i2c",
1484 .of_match_table = of_match_ptr(pcf2127_of_match),
1485 },
1486 .probe = pcf2127_i2c_probe,
1487 .id_table = pcf2127_i2c_id,
1488 };
1489
pcf2127_i2c_register_driver(void)1490 static int pcf2127_i2c_register_driver(void)
1491 {
1492 return i2c_add_driver(&pcf2127_i2c_driver);
1493 }
1494
pcf2127_i2c_unregister_driver(void)1495 static void pcf2127_i2c_unregister_driver(void)
1496 {
1497 i2c_del_driver(&pcf2127_i2c_driver);
1498 }
1499
1500 #else
1501
pcf2127_i2c_register_driver(void)1502 static int pcf2127_i2c_register_driver(void)
1503 {
1504 return 0;
1505 }
1506
pcf2127_i2c_unregister_driver(void)1507 static void pcf2127_i2c_unregister_driver(void)
1508 {
1509 }
1510
1511 #endif
1512
1513 #if IS_ENABLED(CONFIG_SPI_MASTER)
1514
1515 static struct spi_driver pcf2127_spi_driver;
1516 static const struct spi_device_id pcf2127_spi_id[];
1517
pcf2127_spi_probe(struct spi_device * spi)1518 static int pcf2127_spi_probe(struct spi_device *spi)
1519 {
1520 static struct regmap_config config = {
1521 .reg_bits = 8,
1522 .val_bits = 8,
1523 .read_flag_mask = 0xa0,
1524 .write_flag_mask = 0x20,
1525 };
1526 struct regmap *regmap;
1527 const struct pcf21xx_config *variant;
1528
1529 if (spi->dev.of_node) {
1530 variant = of_device_get_match_data(&spi->dev);
1531 if (!variant)
1532 return -ENODEV;
1533 } else {
1534 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data;
1535
1536 if (type >= PCF21XX_LAST_ID)
1537 return -ENODEV;
1538 variant = &pcf21xx_cfg[type];
1539 }
1540
1541 config.max_register = variant->max_register,
1542
1543 regmap = devm_regmap_init_spi(spi, &config);
1544 if (IS_ERR(regmap)) {
1545 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
1546 __func__, PTR_ERR(regmap));
1547 return PTR_ERR(regmap);
1548 }
1549
1550 return pcf2127_probe(&spi->dev, regmap, spi->irq, variant);
1551 }
1552
1553 static const struct spi_device_id pcf2127_spi_id[] = {
1554 { "pcf2127", PCF2127 },
1555 { "pcf2129", PCF2129 },
1556 { "pca2129", PCF2129 },
1557 { "pcf2131", PCF2131 },
1558 { }
1559 };
1560 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
1561
1562 static struct spi_driver pcf2127_spi_driver = {
1563 .driver = {
1564 .name = "rtc-pcf2127-spi",
1565 .of_match_table = of_match_ptr(pcf2127_of_match),
1566 },
1567 .probe = pcf2127_spi_probe,
1568 .id_table = pcf2127_spi_id,
1569 };
1570
pcf2127_spi_register_driver(void)1571 static int pcf2127_spi_register_driver(void)
1572 {
1573 return spi_register_driver(&pcf2127_spi_driver);
1574 }
1575
pcf2127_spi_unregister_driver(void)1576 static void pcf2127_spi_unregister_driver(void)
1577 {
1578 spi_unregister_driver(&pcf2127_spi_driver);
1579 }
1580
1581 #else
1582
pcf2127_spi_register_driver(void)1583 static int pcf2127_spi_register_driver(void)
1584 {
1585 return 0;
1586 }
1587
pcf2127_spi_unregister_driver(void)1588 static void pcf2127_spi_unregister_driver(void)
1589 {
1590 }
1591
1592 #endif
1593
pcf2127_init(void)1594 static int __init pcf2127_init(void)
1595 {
1596 int ret;
1597
1598 ret = pcf2127_i2c_register_driver();
1599 if (ret) {
1600 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
1601 return ret;
1602 }
1603
1604 ret = pcf2127_spi_register_driver();
1605 if (ret) {
1606 pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
1607 pcf2127_i2c_unregister_driver();
1608 }
1609
1610 return ret;
1611 }
module_init(pcf2127_init)1612 module_init(pcf2127_init)
1613
1614 static void __exit pcf2127_exit(void)
1615 {
1616 pcf2127_spi_unregister_driver();
1617 pcf2127_i2c_unregister_driver();
1618 }
1619 module_exit(pcf2127_exit)
1620
1621 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
1622 MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver");
1623 MODULE_LICENSE("GPL v2");
1624