1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1999 Seigo Tanimura 5 * All rights reserved. 6 * 7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 43 #ifdef HAVE_KERNEL_OPTION_HEADERS 44 #include "opt_snd.h" 45 #endif 46 47 #include <dev/sound/pcm/sound.h> 48 #include <dev/sound/pci/csareg.h> 49 #include <dev/sound/pci/csavar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <dev/sound/pci/cs461x_dsp.h> 55 56 /* This is the pci device id. */ 57 #define CS4610_PCI_ID 0x60011013 58 #define CS4614_PCI_ID 0x60031013 59 #define CS4615_PCI_ID 0x60041013 60 61 /* Here is the parameter structure per a device. */ 62 struct csa_softc { 63 device_t dev; /* device */ 64 csa_res res; /* resources */ 65 66 device_t pcm; /* pcm device */ 67 driver_intr_t* pcmintr; /* pcm intr */ 68 void *pcmintr_arg; /* pcm intr arg */ 69 device_t midi; /* midi device */ 70 driver_intr_t* midiintr; /* midi intr */ 71 void *midiintr_arg; /* midi intr arg */ 72 void *ih; /* cookie */ 73 74 struct csa_card *card; 75 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 76 }; 77 78 typedef struct csa_softc *sc_p; 79 80 static int csa_probe(device_t dev); 81 static int csa_attach(device_t dev); 82 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int rid, 83 rman_res_t start, rman_res_t end, 84 rman_res_t count, unsigned int flags); 85 static int csa_release_resource(device_t bus, device_t child, struct resource *r); 86 static int csa_setup_intr(device_t bus, device_t child, 87 struct resource *irq, int flags, 88 driver_filter_t *filter, 89 driver_intr_t *intr, void *arg, void **cookiep); 90 static int csa_teardown_intr(device_t bus, device_t child, 91 struct resource *irq, void *cookie); 92 static driver_intr_t csa_intr; 93 static int csa_initialize(sc_p scp); 94 static int csa_downloadimage(csa_res *resp); 95 static int csa_transferimage(csa_res *resp, uint32_t *src, unsigned long dest, 96 unsigned long len); 97 98 static void 99 amp_none(void) 100 { 101 } 102 103 static void 104 amp_voyetra(void) 105 { 106 } 107 108 static int 109 clkrun_hack(int run) 110 { 111 #ifdef __i386__ 112 device_t child; 113 int port; 114 uint16_t control; 115 bus_space_tag_t btag; 116 117 child = pci_find_device(0x8086, 0x7113); 118 if (child == NULL) 119 return (ENXIO); 120 121 port = (pci_read_config(child, 0x41, 1) << 8) + 0x10; 122 /* XXX */ 123 btag = X86_BUS_SPACE_IO; 124 125 control = bus_space_read_2(btag, 0x0, port); 126 control &= ~0x2000; 127 control |= run? 0 : 0x2000; 128 bus_space_write_2(btag, 0x0, port, control); 129 #endif 130 return (0); 131 } 132 133 static struct csa_card cards_4610[] = { 134 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 135 }; 136 137 static struct csa_card cards_4614[] = { 138 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 139 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 140 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 141 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 142 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 143 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 144 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 145 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 146 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0}, 147 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 148 }; 149 150 static struct csa_card cards_4615[] = { 151 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 152 }; 153 154 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 155 156 struct card_type { 157 uint32_t devid; 158 char *name; 159 struct csa_card *cards; 160 }; 161 162 static struct card_type cards[] = { 163 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 164 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 165 {CS4615_PCI_ID, "CS4615", cards_4615}, 166 {0, NULL, NULL}, 167 }; 168 169 static struct card_type * 170 csa_findcard(device_t dev) 171 { 172 int i; 173 174 i = 0; 175 while (cards[i].devid != 0) { 176 if (pci_get_devid(dev) == cards[i].devid) 177 return &cards[i]; 178 i++; 179 } 180 return NULL; 181 } 182 183 struct csa_card * 184 csa_findsubcard(device_t dev) 185 { 186 int i; 187 struct card_type *card; 188 struct csa_card *subcard; 189 190 card = csa_findcard(dev); 191 if (card == NULL) 192 return &nocard; 193 subcard = card->cards; 194 i = 0; 195 while (subcard[i].subvendor != 0) { 196 if (pci_get_subvendor(dev) == subcard[i].subvendor 197 && pci_get_subdevice(dev) == subcard[i].subdevice) { 198 return &subcard[i]; 199 } 200 i++; 201 } 202 return &subcard[i]; 203 } 204 205 static int 206 csa_probe(device_t dev) 207 { 208 struct card_type *card; 209 210 card = csa_findcard(dev); 211 if (card) { 212 device_set_desc(dev, card->name); 213 return BUS_PROBE_DEFAULT; 214 } 215 return ENXIO; 216 } 217 218 static int 219 csa_attach(device_t dev) 220 { 221 sc_p scp; 222 csa_res *resp; 223 int error = ENXIO; 224 225 scp = device_get_softc(dev); 226 227 /* Fill in the softc. */ 228 bzero(scp, sizeof(*scp)); 229 scp->dev = dev; 230 231 pci_enable_busmaster(dev); 232 233 /* Allocate the resources. */ 234 resp = &scp->res; 235 scp->card = csa_findsubcard(dev); 236 scp->binfo.card = scp->card; 237 printf("csa: card is %s\n", scp->card->name); 238 resp->io_rid = PCIR_BAR(0); 239 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 240 &resp->io_rid, RF_ACTIVE); 241 if (resp->io == NULL) 242 return (ENXIO); 243 resp->mem_rid = PCIR_BAR(1); 244 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 245 &resp->mem_rid, RF_ACTIVE); 246 if (resp->mem == NULL) 247 goto err_io; 248 resp->irq_rid = 0; 249 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 250 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 251 if (resp->irq == NULL) 252 goto err_mem; 253 254 /* Enable interrupt. */ 255 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 256 goto err_intr; 257 #if 0 258 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 259 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 260 #endif 261 262 /* Initialize the chip. */ 263 if (csa_initialize(scp)) 264 goto err_teardown; 265 266 /* Reset the Processor. */ 267 csa_resetdsp(resp); 268 269 /* Download the Processor Image to the processor. */ 270 if (csa_downloadimage(resp)) 271 goto err_teardown; 272 273 /* Attach the children. */ 274 275 /* PCM Audio */ 276 scp->pcm = device_add_child(dev, "pcm", DEVICE_UNIT_ANY); 277 device_set_ivars(scp->pcm, &scp->binfo); 278 279 /* Midi Interface */ 280 scp->midi = device_add_child(dev, "midi", DEVICE_UNIT_ANY); 281 device_set_ivars(scp->midi, &scp->binfo); 282 283 bus_attach_children(dev); 284 285 return (0); 286 287 err_teardown: 288 bus_teardown_intr(dev, resp->irq, scp->ih); 289 err_intr: 290 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 291 err_mem: 292 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 293 err_io: 294 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 295 return (error); 296 } 297 298 static int 299 csa_detach(device_t dev) 300 { 301 csa_res *resp; 302 sc_p scp; 303 int err; 304 305 scp = device_get_softc(dev); 306 resp = &scp->res; 307 308 err = bus_generic_detach(dev); 309 if (err != 0) 310 return err; 311 312 bus_teardown_intr(dev, resp->irq, scp->ih); 313 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 314 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 315 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 316 317 return (0); 318 } 319 320 static int 321 csa_resume(device_t dev) 322 { 323 csa_res *resp; 324 sc_p scp; 325 326 scp = device_get_softc(dev); 327 resp = &scp->res; 328 329 /* Initialize the chip. */ 330 if (csa_initialize(scp)) 331 return (ENXIO); 332 333 /* Reset the Processor. */ 334 csa_resetdsp(resp); 335 336 /* Download the Processor Image to the processor. */ 337 if (csa_downloadimage(resp)) 338 return (ENXIO); 339 340 return (bus_generic_resume(dev)); 341 } 342 343 static struct resource * 344 csa_alloc_resource(device_t bus, device_t child, int type, int rid, 345 rman_res_t start, rman_res_t end, rman_res_t count, unsigned int flags) 346 { 347 sc_p scp; 348 csa_res *resp; 349 struct resource *res; 350 351 scp = device_get_softc(bus); 352 resp = &scp->res; 353 switch (type) { 354 case SYS_RES_IRQ: 355 if (rid != 0) 356 return (NULL); 357 res = resp->irq; 358 break; 359 case SYS_RES_MEMORY: 360 switch (rid) { 361 case PCIR_BAR(0): 362 res = resp->io; 363 break; 364 case PCIR_BAR(1): 365 res = resp->mem; 366 break; 367 default: 368 return (NULL); 369 } 370 break; 371 default: 372 return (NULL); 373 } 374 375 return res; 376 } 377 378 static int 379 csa_release_resource(device_t bus, device_t child, struct resource *r) 380 { 381 return (0); 382 } 383 384 /* 385 * The following three functions deal with interrupt handling. 386 * An interrupt is primarily handled by the bridge driver. 387 * The bridge driver then determines the child devices to pass 388 * the interrupt. Certain information of the device can be read 389 * only once(eg the value of HISR). The bridge driver is responsible 390 * to pass such the information to the children. 391 */ 392 393 static int 394 csa_setup_intr(device_t bus, device_t child, 395 struct resource *irq, int flags, 396 driver_filter_t *filter, 397 driver_intr_t *intr, void *arg, void **cookiep) 398 { 399 sc_p scp; 400 csa_res *resp; 401 402 if (filter != NULL) { 403 printf("ata-csa.c: we cannot use a filter here\n"); 404 return (EINVAL); 405 } 406 scp = device_get_softc(bus); 407 resp = &scp->res; 408 409 if (irq != resp->irq) 410 return (EINVAL); 411 412 /* 413 * Look at which child device this is to determine the 414 * appropriate handler for it. 415 */ 416 if (child == scp->pcm) { 417 scp->pcmintr = intr; 418 scp->pcmintr_arg = arg; 419 } else if (child == scp->midi) { 420 scp->midiintr = intr; 421 scp->midiintr_arg = arg; 422 } else 423 return (EINVAL); 424 *cookiep = scp; 425 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 426 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 427 428 return (0); 429 } 430 431 static int 432 csa_teardown_intr(device_t bus, device_t child, 433 struct resource *irq, void *cookie) 434 { 435 sc_p scp; 436 csa_res *resp; 437 438 scp = device_get_softc(bus); 439 resp = &scp->res; 440 441 if (irq != resp->irq || cookie != scp) 442 return (EINVAL); 443 444 /* 445 * Look at which child device this is to determine the 446 * appropriate handler for it. 447 */ 448 if (child == scp->pcm) { 449 scp->pcmintr = NULL; 450 scp->pcmintr_arg = NULL; 451 } else if (child == scp->midi) { 452 scp->midiintr = NULL; 453 scp->midiintr_arg = NULL; 454 } else 455 return (EINVAL); 456 457 return (0); 458 } 459 460 /* The interrupt handler */ 461 static void 462 csa_intr(void *arg) 463 { 464 sc_p scp = arg; 465 csa_res *resp; 466 uint32_t hisr; 467 468 resp = &scp->res; 469 470 /* Is this interrupt for us? */ 471 hisr = csa_readio(resp, BA0_HISR); 472 if ((hisr & 0x7fffffff) == 0) { 473 /* Throw an eoi. */ 474 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 475 return; 476 } 477 478 /* 479 * Pass the value of HISR via struct csa_bridgeinfo. 480 * The children get access through their ivars. 481 */ 482 scp->binfo.hisr = hisr; 483 484 /* Invoke the handlers of the children. */ 485 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 486 scp->pcmintr(scp->pcmintr_arg); 487 hisr &= ~(HISR_VC0 | HISR_VC1); 488 } 489 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 490 scp->midiintr(scp->midiintr_arg); 491 hisr &= ~HISR_MIDI; 492 } 493 494 /* Throw an eoi. */ 495 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 496 } 497 498 static int 499 csa_initialize(sc_p scp) 500 { 501 int i; 502 uint32_t acsts, acisv; 503 csa_res *resp; 504 505 resp = &scp->res; 506 507 /* 508 * First, blast the clock control register to zero so that the PLL starts 509 * out in a known state, and blast the master serial port control register 510 * to zero so that the serial ports also start out in a known state. 511 */ 512 csa_writeio(resp, BA0_CLKCR1, 0); 513 csa_writeio(resp, BA0_SERMC1, 0); 514 515 /* 516 * If we are in AC97 mode, then we must set the part to a host controlled 517 * AC-link. Otherwise, we won't be able to bring up the link. 518 */ 519 #if 1 520 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 521 #else 522 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 523 #endif /* 1 */ 524 525 /* 526 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 527 * spec) and then drive it high. This is done for non AC97 modes since 528 * there might be logic external to the CS461x that uses the ARST# line 529 * for a reset. 530 */ 531 csa_writeio(resp, BA0_ACCTL, 1); 532 DELAY(50); 533 csa_writeio(resp, BA0_ACCTL, 0); 534 DELAY(50); 535 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 536 537 /* 538 * The first thing we do here is to enable sync generation. As soon 539 * as we start receiving bit clock, we'll start producing the SYNC 540 * signal. 541 */ 542 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 543 544 /* 545 * Now wait for a short while to allow the AC97 part to start 546 * generating bit clock (so we don't try to start the PLL without an 547 * input clock). 548 */ 549 DELAY(50000); 550 551 /* 552 * Set the serial port timing configuration, so that 553 * the clock control circuit gets its clock from the correct place. 554 */ 555 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 556 DELAY(700000); 557 558 /* 559 * Write the selected clock control setup to the hardware. Do not turn on 560 * SWCE yet (if requested), so that the devices clocked by the output of 561 * PLL are not clocked until the PLL is stable. 562 */ 563 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 564 csa_writeio(resp, BA0_PLLM, 0x3a); 565 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 566 567 /* 568 * Power up the PLL. 569 */ 570 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 571 572 /* 573 * Wait until the PLL has stabilized. 574 */ 575 DELAY(5000); 576 577 /* 578 * Turn on clocking of the core so that we can setup the serial ports. 579 */ 580 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 581 582 /* 583 * Fill the serial port FIFOs with silence. 584 */ 585 csa_clearserialfifos(resp); 586 587 /* 588 * Set the serial port FIFO pointer to the first sample in the FIFO. 589 */ 590 #ifdef notdef 591 csa_writeio(resp, BA0_SERBSP, 0); 592 #endif /* notdef */ 593 594 /* 595 * Write the serial port configuration to the part. The master 596 * enable bit is not set until all other values have been written. 597 */ 598 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 599 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 600 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 601 602 /* 603 * Wait for the codec ready signal from the AC97 codec. 604 */ 605 acsts = 0; 606 for (i = 0 ; i < 1000 ; i++) { 607 /* 608 * First, lets wait a short while to let things settle out a bit, 609 * and to prevent retrying the read too quickly. 610 */ 611 DELAY(125); 612 613 /* 614 * Read the AC97 status register to see if we've seen a CODEC READY 615 * signal from the AC97 codec. 616 */ 617 acsts = csa_readio(resp, BA0_ACSTS); 618 if ((acsts & ACSTS_CRDY) != 0) 619 break; 620 } 621 622 /* 623 * Make sure we sampled CODEC READY. 624 */ 625 if ((acsts & ACSTS_CRDY) == 0) 626 return (ENXIO); 627 628 /* 629 * Assert the vaid frame signal so that we can start sending commands 630 * to the AC97 codec. 631 */ 632 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 633 634 /* 635 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 636 * the codec is pumping ADC data across the AC-link. 637 */ 638 acisv = 0; 639 for (i = 0 ; i < 2000 ; i++) { 640 /* 641 * First, lets wait a short while to let things settle out a bit, 642 * and to prevent retrying the read too quickly. 643 */ 644 #ifdef notdef 645 DELAY(10000000L); /* clw */ 646 #else 647 DELAY(1000); 648 #endif /* notdef */ 649 /* 650 * Read the input slot valid register and see if input slots 3 and 651 * 4 are valid yet. 652 */ 653 acisv = csa_readio(resp, BA0_ACISV); 654 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 655 break; 656 } 657 /* 658 * Make sure we sampled valid input slots 3 and 4. If not, then return 659 * an error. 660 */ 661 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 662 return (ENXIO); 663 664 /* 665 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 666 * commense the transfer of digital audio data to the AC97 codec. 667 */ 668 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 669 670 /* 671 * Power down the DAC and ADC. We will power them up (if) when we need 672 * them. 673 */ 674 #ifdef notdef 675 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 676 #endif /* notdef */ 677 678 /* 679 * Turn off the Processor by turning off the software clock enable flag in 680 * the clock control register. 681 */ 682 #ifdef notdef 683 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 684 csa_writeio(resp, BA0_CLKCR1, clkcr1); 685 #endif /* notdef */ 686 687 /* 688 * Enable interrupts on the part. 689 */ 690 #if 0 691 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 692 #endif /* notdef */ 693 694 return (0); 695 } 696 697 void 698 csa_clearserialfifos(csa_res *resp) 699 { 700 int i, j, pwr; 701 uint8_t clkcr1, serbst; 702 703 /* 704 * See if the devices are powered down. If so, we must power them up first 705 * or they will not respond. 706 */ 707 pwr = 1; 708 clkcr1 = csa_readio(resp, BA0_CLKCR1); 709 if ((clkcr1 & CLKCR1_SWCE) == 0) { 710 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 711 pwr = 0; 712 } 713 714 /* 715 * We want to clear out the serial port FIFOs so we don't end up playing 716 * whatever random garbage happens to be in them. We fill the sample FIFOs 717 * with zero (silence). 718 */ 719 csa_writeio(resp, BA0_SERBWP, 0); 720 721 /* Fill all 256 sample FIFO locations. */ 722 serbst = 0; 723 for (i = 0 ; i < 256 ; i++) { 724 /* Make sure the previous FIFO write operation has completed. */ 725 for (j = 0 ; j < 5 ; j++) { 726 DELAY(100); 727 serbst = csa_readio(resp, BA0_SERBST); 728 if ((serbst & SERBST_WBSY) == 0) 729 break; 730 } 731 if ((serbst & SERBST_WBSY) != 0) { 732 if (!pwr) 733 csa_writeio(resp, BA0_CLKCR1, clkcr1); 734 } 735 /* Write the serial port FIFO index. */ 736 csa_writeio(resp, BA0_SERBAD, i); 737 /* Tell the serial port to load the new value into the FIFO location. */ 738 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 739 } 740 /* 741 * Now, if we powered up the devices, then power them back down again. 742 * This is kinda ugly, but should never happen. 743 */ 744 if (!pwr) 745 csa_writeio(resp, BA0_CLKCR1, clkcr1); 746 } 747 748 void 749 csa_resetdsp(csa_res *resp) 750 { 751 int i; 752 753 /* 754 * Write the reset bit of the SP control register. 755 */ 756 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 757 758 /* 759 * Write the control register. 760 */ 761 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 762 763 /* 764 * Clear the trap registers. 765 */ 766 for (i = 0 ; i < 8 ; i++) { 767 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 768 csa_writemem(resp, BA1_TWPR, 0xffff); 769 } 770 csa_writemem(resp, BA1_DREG, 0); 771 772 /* 773 * Set the frame timer to reflect the number of cycles per frame. 774 */ 775 csa_writemem(resp, BA1_FRMT, 0xadf); 776 } 777 778 static int 779 csa_downloadimage(csa_res *resp) 780 { 781 int ret; 782 unsigned long ul, offset; 783 784 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 785 /* 786 * DMA this block from host memory to the appropriate 787 * memory on the CSDevice. 788 */ 789 ret = csa_transferimage(resp, 790 cs461x_firmware.BA1Array + offset, 791 cs461x_firmware.MemoryStat[ul].ulDestAddr, 792 cs461x_firmware.MemoryStat[ul].ulSourceSize); 793 if (ret) 794 return (ret); 795 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 796 } 797 return (0); 798 } 799 800 static int 801 csa_transferimage(csa_res *resp, uint32_t *src, unsigned long dest, 802 unsigned long len) 803 { 804 unsigned long ul; 805 806 /* 807 * We do not allow DMAs from host memory to host memory (although the DMA 808 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 809 * in size (because that DMA can not do that). Return an error if either 810 * of these conditions exist. 811 */ 812 if ((len & 0x3) != 0) 813 return (EINVAL); 814 815 /* Check the destination address that it is a multiple of 4 */ 816 if ((dest & 0x3) != 0) 817 return (EINVAL); 818 819 /* Write the buffer out. */ 820 for (ul = 0 ; ul < len ; ul += 4) 821 csa_writemem(resp, dest + ul, src[ul >> 2]); 822 return (0); 823 } 824 825 int 826 csa_readcodec(csa_res *resp, unsigned long offset, uint32_t *data) 827 { 828 int i; 829 uint32_t acctl, acsts; 830 831 /* 832 * Make sure that there is not data sitting around from a previous 833 * uncompleted access. ACSDA = Status Data Register = 47Ch 834 */ 835 csa_readio(resp, BA0_ACSDA); 836 837 /* 838 * Setup the AC97 control registers on the CS461x to send the 839 * appropriate command to the AC97 to perform the read. 840 * ACCAD = Command Address Register = 46Ch 841 * ACCDA = Command Data Register = 470h 842 * ACCTL = Control Register = 460h 843 * set DCV - will clear when process completed 844 * set CRW - Read command 845 * set VFRM - valid frame enabled 846 * set ESYN - ASYNC generation enabled 847 * set RSTN - ARST# inactive, AC97 codec not reset 848 */ 849 850 /* 851 * Get the actual AC97 register from the offset 852 */ 853 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 854 csa_writeio(resp, BA0_ACCDA, 0); 855 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 856 857 /* 858 * Wait for the read to occur. 859 */ 860 acctl = 0; 861 for (i = 0 ; i < 10 ; i++) { 862 /* 863 * First, we want to wait for a short time. 864 */ 865 DELAY(25); 866 867 /* 868 * Now, check to see if the read has completed. 869 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 870 */ 871 acctl = csa_readio(resp, BA0_ACCTL); 872 if ((acctl & ACCTL_DCV) == 0) 873 break; 874 } 875 876 /* 877 * Make sure the read completed. 878 */ 879 if ((acctl & ACCTL_DCV) != 0) 880 return (EAGAIN); 881 882 /* 883 * Wait for the valid status bit to go active. 884 */ 885 acsts = 0; 886 for (i = 0 ; i < 10 ; i++) { 887 /* 888 * Read the AC97 status register. 889 * ACSTS = Status Register = 464h 890 */ 891 acsts = csa_readio(resp, BA0_ACSTS); 892 /* 893 * See if we have valid status. 894 * VSTS - Valid Status 895 */ 896 if ((acsts & ACSTS_VSTS) != 0) 897 break; 898 /* 899 * Wait for a short while. 900 */ 901 DELAY(25); 902 } 903 904 /* 905 * Make sure we got valid status. 906 */ 907 if ((acsts & ACSTS_VSTS) == 0) 908 return (EAGAIN); 909 910 /* 911 * Read the data returned from the AC97 register. 912 * ACSDA = Status Data Register = 474h 913 */ 914 *data = csa_readio(resp, BA0_ACSDA); 915 916 return (0); 917 } 918 919 int 920 csa_writecodec(csa_res *resp, unsigned long offset, uint32_t data) 921 { 922 int i; 923 uint32_t acctl; 924 925 /* 926 * Setup the AC97 control registers on the CS461x to send the 927 * appropriate command to the AC97 to perform the write. 928 * ACCAD = Command Address Register = 46Ch 929 * ACCDA = Command Data Register = 470h 930 * ACCTL = Control Register = 460h 931 * set DCV - will clear when process completed 932 * set VFRM - valid frame enabled 933 * set ESYN - ASYNC generation enabled 934 * set RSTN - ARST# inactive, AC97 codec not reset 935 */ 936 937 /* 938 * Get the actual AC97 register from the offset 939 */ 940 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 941 csa_writeio(resp, BA0_ACCDA, data); 942 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 943 944 /* 945 * Wait for the write to occur. 946 */ 947 acctl = 0; 948 for (i = 0 ; i < 10 ; i++) { 949 /* 950 * First, we want to wait for a short time. 951 */ 952 DELAY(25); 953 954 /* 955 * Now, check to see if the read has completed. 956 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 957 */ 958 acctl = csa_readio(resp, BA0_ACCTL); 959 if ((acctl & ACCTL_DCV) == 0) 960 break; 961 } 962 963 /* 964 * Make sure the write completed. 965 */ 966 if ((acctl & ACCTL_DCV) != 0) 967 return (EAGAIN); 968 969 return (0); 970 } 971 972 uint32_t 973 csa_readio(csa_res *resp, unsigned long offset) 974 { 975 uint32_t ul; 976 977 if (offset < BA0_AC97_RESET) 978 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 979 else { 980 if (csa_readcodec(resp, offset, &ul)) 981 ul = 0; 982 return (ul); 983 } 984 } 985 986 void 987 csa_writeio(csa_res *resp, unsigned long offset, uint32_t data) 988 { 989 if (offset < BA0_AC97_RESET) 990 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 991 else 992 csa_writecodec(resp, offset, data); 993 } 994 995 uint32_t 996 csa_readmem(csa_res *resp, unsigned long offset) 997 { 998 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 999 } 1000 1001 void 1002 csa_writemem(csa_res *resp, unsigned long offset, uint32_t data) 1003 { 1004 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1005 } 1006 1007 static device_method_t csa_methods[] = { 1008 /* Device interface */ 1009 DEVMETHOD(device_probe, csa_probe), 1010 DEVMETHOD(device_attach, csa_attach), 1011 DEVMETHOD(device_detach, csa_detach), 1012 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1013 DEVMETHOD(device_suspend, bus_generic_suspend), 1014 DEVMETHOD(device_resume, csa_resume), 1015 1016 /* Bus interface */ 1017 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1018 DEVMETHOD(bus_release_resource, csa_release_resource), 1019 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1020 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1021 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1022 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1023 1024 DEVMETHOD_END 1025 }; 1026 1027 static driver_t csa_driver = { 1028 "csa", 1029 csa_methods, 1030 sizeof(struct csa_softc), 1031 }; 1032 1033 /* 1034 * csa can be attached to a pci bus. 1035 */ 1036 DRIVER_MODULE(snd_csa, pci, csa_driver, 0, 0); 1037 MODULE_DEPEND(snd_csa, sound, 1, 1, 1); 1038 MODULE_VERSION(snd_csa, 1); 1039