1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 */
4
5 /*
6 * 2002-07 Benny Sjostrand benny@hostmobility.com
7 */
8
9
10 #include <linux/io.h>
11 #include <linux/delay.h>
12 #include <linux/pm.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/mutex.h>
16
17 #include <sound/core.h>
18 #include <sound/control.h>
19 #include <sound/info.h>
20 #include "cs46xx.h"
21
22 #include "cs46xx_lib.h"
23 #include "dsp_spos.h"
24
25 struct proc_scb_info {
26 struct dsp_scb_descriptor * scb_desc;
27 struct snd_cs46xx *chip;
28 };
29
remove_symbol(struct snd_cs46xx * chip,struct dsp_symbol_entry * symbol)30 static void remove_symbol (struct snd_cs46xx * chip, struct dsp_symbol_entry * symbol)
31 {
32 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
33 int symbol_index = (int)(symbol - ins->symbol_table.symbols);
34
35 if (snd_BUG_ON(ins->symbol_table.nsymbols <= 0))
36 return;
37 if (snd_BUG_ON(symbol_index < 0 ||
38 symbol_index >= ins->symbol_table.nsymbols))
39 return;
40
41 ins->symbol_table.symbols[symbol_index].deleted = 1;
42
43 if (symbol_index < ins->symbol_table.highest_frag_index) {
44 ins->symbol_table.highest_frag_index = symbol_index;
45 }
46
47 if (symbol_index == ins->symbol_table.nsymbols - 1)
48 ins->symbol_table.nsymbols --;
49
50 if (ins->symbol_table.highest_frag_index > ins->symbol_table.nsymbols) {
51 ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
52 }
53
54 }
55
56 #ifdef CONFIG_SND_PROC_FS
cs46xx_dsp_proc_scb_info_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)57 static void cs46xx_dsp_proc_scb_info_read (struct snd_info_entry *entry,
58 struct snd_info_buffer *buffer)
59 {
60 struct proc_scb_info * scb_info = entry->private_data;
61 struct dsp_scb_descriptor * scb = scb_info->scb_desc;
62 struct snd_cs46xx *chip = scb_info->chip;
63 int j,col;
64 void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
65
66 mutex_lock(&chip->spos_mutex);
67 snd_iprintf(buffer,"%04x %s:\n",scb->address,scb->scb_name);
68
69 for (col = 0,j = 0;j < 0x10; j++,col++) {
70 if (col == 4) {
71 snd_iprintf(buffer,"\n");
72 col = 0;
73 }
74 snd_iprintf(buffer,"%08x ",readl(dst + (scb->address + j) * sizeof(u32)));
75 }
76
77 snd_iprintf(buffer,"\n");
78
79 if (scb->parent_scb_ptr != NULL) {
80 snd_iprintf(buffer,"parent [%s:%04x] ",
81 scb->parent_scb_ptr->scb_name,
82 scb->parent_scb_ptr->address);
83 } else snd_iprintf(buffer,"parent [none] ");
84
85 snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
86 scb->sub_list_ptr->scb_name,
87 scb->sub_list_ptr->address,
88 scb->next_scb_ptr->scb_name,
89 scb->next_scb_ptr->address,
90 scb->task_entry->symbol_name,
91 scb->task_entry->address);
92
93 snd_iprintf(buffer,"index [%d] ref_count [%d]\n",scb->index,scb->ref_count);
94 mutex_unlock(&chip->spos_mutex);
95 }
96 #endif
97
_dsp_unlink_scb(struct snd_cs46xx * chip,struct dsp_scb_descriptor * scb)98 static void _dsp_unlink_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
99 {
100 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
101
102 if ( scb->parent_scb_ptr ) {
103 /* unlink parent SCB */
104 if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr != scb &&
105 scb->parent_scb_ptr->next_scb_ptr != scb))
106 return;
107
108 if (scb->parent_scb_ptr->sub_list_ptr == scb) {
109
110 if (scb->next_scb_ptr == ins->the_null_scb) {
111 /* last and only node in parent sublist */
112 scb->parent_scb_ptr->sub_list_ptr = scb->sub_list_ptr;
113
114 if (scb->sub_list_ptr != ins->the_null_scb) {
115 scb->sub_list_ptr->parent_scb_ptr = scb->parent_scb_ptr;
116 }
117 scb->sub_list_ptr = ins->the_null_scb;
118 } else {
119 /* first node in parent sublist */
120 scb->parent_scb_ptr->sub_list_ptr = scb->next_scb_ptr;
121
122 if (scb->next_scb_ptr != ins->the_null_scb) {
123 /* update next node parent ptr. */
124 scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
125 }
126 scb->next_scb_ptr = ins->the_null_scb;
127 }
128 } else {
129 scb->parent_scb_ptr->next_scb_ptr = scb->next_scb_ptr;
130
131 if (scb->next_scb_ptr != ins->the_null_scb) {
132 /* update next node parent ptr. */
133 scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
134 }
135 scb->next_scb_ptr = ins->the_null_scb;
136 }
137
138 /* update parent first entry in DSP RAM */
139 cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
140
141 /* then update entry in DSP RAM */
142 cs46xx_dsp_spos_update_scb(chip,scb);
143
144 scb->parent_scb_ptr = NULL;
145 }
146 }
147
_dsp_clear_sample_buffer(struct snd_cs46xx * chip,u32 sample_buffer_addr,int dword_count)148 static void _dsp_clear_sample_buffer (struct snd_cs46xx *chip, u32 sample_buffer_addr,
149 int dword_count)
150 {
151 void __iomem *dst = chip->region.idx[2].remap_addr + sample_buffer_addr;
152 int i;
153
154 for (i = 0; i < dword_count ; ++i ) {
155 writel(0, dst);
156 dst += 4;
157 }
158 }
159
cs46xx_dsp_remove_scb(struct snd_cs46xx * chip,struct dsp_scb_descriptor * scb)160 void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
161 {
162 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
163 unsigned long flags;
164
165 /* check integrety */
166 if (snd_BUG_ON(scb->index < 0 ||
167 scb->index >= ins->nscb ||
168 (ins->scbs + scb->index) != scb))
169 return;
170
171 #if 0
172 /* can't remove a SCB with childs before
173 removing childs first */
174 if (snd_BUG_ON(scb->sub_list_ptr != ins->the_null_scb ||
175 scb->next_scb_ptr != ins->the_null_scb))
176 goto _end;
177 #endif
178
179 spin_lock_irqsave(&chip->reg_lock, flags);
180 _dsp_unlink_scb (chip,scb);
181 spin_unlock_irqrestore(&chip->reg_lock, flags);
182
183 cs46xx_dsp_proc_free_scb_desc(scb);
184 if (snd_BUG_ON(!scb->scb_symbol))
185 return;
186 remove_symbol (chip,scb->scb_symbol);
187
188 ins->scbs[scb->index].deleted = 1;
189 #ifdef CONFIG_PM_SLEEP
190 kfree(ins->scbs[scb->index].data);
191 ins->scbs[scb->index].data = NULL;
192 #endif
193
194 if (scb->index < ins->scb_highest_frag_index)
195 ins->scb_highest_frag_index = scb->index;
196
197 if (scb->index == ins->nscb - 1) {
198 ins->nscb --;
199 }
200
201 if (ins->scb_highest_frag_index > ins->nscb) {
202 ins->scb_highest_frag_index = ins->nscb;
203 }
204 }
205
206
207 #ifdef CONFIG_SND_PROC_FS
cs46xx_dsp_proc_free_scb_desc(struct dsp_scb_descriptor * scb)208 void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb)
209 {
210 if (scb->proc_info) {
211 struct proc_scb_info * scb_info = scb->proc_info->private_data;
212 struct snd_cs46xx *chip = scb_info->chip;
213
214 dev_dbg(chip->card->dev,
215 "cs46xx_dsp_proc_free_scb_desc: freeing %s\n",
216 scb->scb_name);
217
218 snd_info_free_entry(scb->proc_info);
219 scb->proc_info = NULL;
220
221 kfree (scb_info);
222 }
223 }
224
cs46xx_dsp_proc_register_scb_desc(struct snd_cs46xx * chip,struct dsp_scb_descriptor * scb)225 void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
226 struct dsp_scb_descriptor * scb)
227 {
228 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
229 struct snd_info_entry * entry;
230 struct proc_scb_info * scb_info;
231
232 /* register to proc */
233 if (ins->snd_card != NULL && ins->proc_dsp_dir != NULL &&
234 scb->proc_info == NULL) {
235
236 entry = snd_info_create_card_entry(ins->snd_card, scb->scb_name,
237 ins->proc_dsp_dir);
238 if (entry) {
239 scb_info = kmalloc(sizeof(struct proc_scb_info), GFP_KERNEL);
240 if (!scb_info) {
241 snd_info_free_entry(entry);
242 entry = NULL;
243 goto out;
244 }
245
246 scb_info->chip = chip;
247 scb_info->scb_desc = scb;
248 snd_info_set_text_ops(entry, scb_info,
249 cs46xx_dsp_proc_scb_info_read);
250 }
251 out:
252 scb->proc_info = entry;
253 }
254 }
255 #endif /* CONFIG_SND_PROC_FS */
256
257 static struct dsp_scb_descriptor *
_dsp_create_generic_scb(struct snd_cs46xx * chip,char * name,u32 * scb_data,u32 dest,struct dsp_symbol_entry * task_entry,struct dsp_scb_descriptor * parent_scb,int scb_child_type)258 _dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest,
259 struct dsp_symbol_entry * task_entry,
260 struct dsp_scb_descriptor * parent_scb,
261 int scb_child_type)
262 {
263 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
264 struct dsp_scb_descriptor * scb;
265
266 unsigned long flags;
267
268 if (snd_BUG_ON(!ins->the_null_scb))
269 return NULL;
270
271 /* fill the data that will be wroten to DSP */
272 scb_data[SCBsubListPtr] =
273 (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address;
274
275 scb_data[SCBfuncEntryPtr] &= 0xFFFF0000;
276 scb_data[SCBfuncEntryPtr] |= task_entry->address;
277
278 dev_dbg(chip->card->dev, "dsp_spos: creating SCB <%s>\n", name);
279
280 scb = cs46xx_dsp_create_scb(chip,name,scb_data,dest);
281
282
283 scb->sub_list_ptr = ins->the_null_scb;
284 scb->next_scb_ptr = ins->the_null_scb;
285
286 scb->parent_scb_ptr = parent_scb;
287 scb->task_entry = task_entry;
288
289
290 /* update parent SCB */
291 if (scb->parent_scb_ptr) {
292 #if 0
293 dev_dbg(chip->card->dev,
294 "scb->parent_scb_ptr = %s\n",
295 scb->parent_scb_ptr->scb_name);
296 dev_dbg(chip->card->dev,
297 "scb->parent_scb_ptr->next_scb_ptr = %s\n",
298 scb->parent_scb_ptr->next_scb_ptr->scb_name);
299 dev_dbg(chip->card->dev,
300 "scb->parent_scb_ptr->sub_list_ptr = %s\n",
301 scb->parent_scb_ptr->sub_list_ptr->scb_name);
302 #endif
303 /* link to parent SCB */
304 if (scb_child_type == SCB_ON_PARENT_NEXT_SCB) {
305 if (snd_BUG_ON(scb->parent_scb_ptr->next_scb_ptr !=
306 ins->the_null_scb))
307 return NULL;
308
309 scb->parent_scb_ptr->next_scb_ptr = scb;
310
311 } else if (scb_child_type == SCB_ON_PARENT_SUBLIST_SCB) {
312 if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr !=
313 ins->the_null_scb))
314 return NULL;
315
316 scb->parent_scb_ptr->sub_list_ptr = scb;
317 } else {
318 snd_BUG();
319 }
320
321 spin_lock_irqsave(&chip->reg_lock, flags);
322
323 /* update entry in DSP RAM */
324 cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
325
326 spin_unlock_irqrestore(&chip->reg_lock, flags);
327 }
328
329
330 cs46xx_dsp_proc_register_scb_desc (chip,scb);
331
332 return scb;
333 }
334
335 static struct dsp_scb_descriptor *
cs46xx_dsp_create_generic_scb(struct snd_cs46xx * chip,char * name,u32 * scb_data,u32 dest,char * task_entry_name,struct dsp_scb_descriptor * parent_scb,int scb_child_type)336 cs46xx_dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data,
337 u32 dest, char * task_entry_name,
338 struct dsp_scb_descriptor * parent_scb,
339 int scb_child_type)
340 {
341 struct dsp_symbol_entry * task_entry;
342
343 task_entry = cs46xx_dsp_lookup_symbol (chip,task_entry_name,
344 SYMBOL_CODE);
345
346 if (task_entry == NULL) {
347 dev_err(chip->card->dev,
348 "dsp_spos: symbol %s not found\n", task_entry_name);
349 return NULL;
350 }
351
352 return _dsp_create_generic_scb (chip,name,scb_data,dest,task_entry,
353 parent_scb,scb_child_type);
354 }
355
356 struct dsp_scb_descriptor *
cs46xx_dsp_create_timing_master_scb(struct snd_cs46xx * chip)357 cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip)
358 {
359 struct dsp_scb_descriptor * scb;
360
361 struct dsp_timing_master_scb timing_master_scb = {
362 { 0,
363 0,
364 0,
365 0
366 },
367 { 0,
368 0,
369 0,
370 0,
371 0
372 },
373 0,0,
374 0,NULL_SCB_ADDR,
375 0,0, /* extraSampleAccum:TMreserved */
376 0,0, /* codecFIFOptr:codecFIFOsyncd */
377 0x0001,0x8000, /* fracSampAccumQm1:TMfrmsLeftInGroup */
378 0x0001,0x0000, /* fracSampCorrectionQm1:TMfrmGroupLength */
379 0x00060000 /* nSampPerFrmQ15 */
380 };
381
382 scb = cs46xx_dsp_create_generic_scb(chip,"TimingMasterSCBInst",(u32 *)&timing_master_scb,
383 TIMINGMASTER_SCB_ADDR,
384 "TIMINGMASTER",NULL,SCB_NO_PARENT);
385
386 return scb;
387 }
388
389
390 struct dsp_scb_descriptor *
cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip,char * codec_name,u16 channel_disp,u16 fifo_addr,u16 child_scb_addr,u32 dest,struct dsp_scb_descriptor * parent_scb,int scb_child_type)391 cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip, char * codec_name,
392 u16 channel_disp, u16 fifo_addr, u16 child_scb_addr,
393 u32 dest, struct dsp_scb_descriptor * parent_scb,
394 int scb_child_type)
395 {
396 struct dsp_scb_descriptor * scb;
397
398 struct dsp_codec_output_scb codec_out_scb = {
399 { 0,
400 0,
401 0,
402 0
403 },
404 {
405 0,
406 0,
407 0,
408 0,
409 0
410 },
411 0,0,
412 0,NULL_SCB_ADDR,
413 0, /* COstrmRsConfig */
414 0, /* COstrmBufPtr */
415 channel_disp,fifo_addr, /* leftChanBaseIOaddr:rightChanIOdisp */
416 0x0000,0x0080, /* (!AC97!) COexpVolChangeRate:COscaleShiftCount */
417 0,child_scb_addr /* COreserved - need child scb to work with rom code */
418 };
419
420
421 scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_out_scb,
422 dest,"S16_CODECOUTPUTTASK",parent_scb,
423 scb_child_type);
424
425 return scb;
426 }
427
428 struct dsp_scb_descriptor *
cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip,char * codec_name,u16 channel_disp,u16 fifo_addr,u16 sample_buffer_addr,u32 dest,struct dsp_scb_descriptor * parent_scb,int scb_child_type)429 cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
430 u16 channel_disp, u16 fifo_addr, u16 sample_buffer_addr,
431 u32 dest, struct dsp_scb_descriptor * parent_scb,
432 int scb_child_type)
433 {
434
435 struct dsp_scb_descriptor * scb;
436 struct dsp_codec_input_scb codec_input_scb = {
437 { 0,
438 0,
439 0,
440 0
441 },
442 {
443 0,
444 0,
445 0,
446 0,
447 0
448 },
449
450 #if 0 /* cs4620 */
451 SyncIOSCB,NULL_SCB_ADDR
452 #else
453 0 , 0,
454 #endif
455 0,0,
456
457 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64, /* strmRsConfig */
458 sample_buffer_addr << 0x10, /* strmBufPtr; defined as a dword ptr, used as a byte ptr */
459 channel_disp,fifo_addr, /* (!AC97!) leftChanBaseINaddr=AC97primary
460 link input slot 3 :rightChanINdisp=""slot 4 */
461 0x0000,0x0000, /* (!AC97!) ????:scaleShiftCount; no shift needed
462 because AC97 is already 20 bits */
463 0x80008000 /* ??clw cwcgame.scb has 0 */
464 };
465
466 scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_input_scb,
467 dest,"S16_CODECINPUTTASK",parent_scb,
468 scb_child_type);
469 return scb;
470 }
471
472
473 static struct dsp_scb_descriptor *
cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip,char * scb_name,u16 sample_buffer_addr,u32 dest,int virtual_channel,u32 playback_hw_addr,struct dsp_scb_descriptor * parent_scb,int scb_child_type)474 cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip, char * scb_name,
475 u16 sample_buffer_addr, u32 dest,
476 int virtual_channel, u32 playback_hw_addr,
477 struct dsp_scb_descriptor * parent_scb,
478 int scb_child_type)
479 {
480 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
481 struct dsp_scb_descriptor * scb;
482
483 struct dsp_generic_scb pcm_reader_scb = {
484
485 /*
486 Play DMA Task xfers data from host buffer to SP buffer
487 init/runtime variables:
488 PlayAC: Play Audio Data Conversion - SCB loc: 2nd dword, mask: 0x0000F000L
489 DATA_FMT_16BIT_ST_LTLEND(0x00000000L) from 16-bit stereo, little-endian
490 DATA_FMT_8_BIT_ST_SIGNED(0x00001000L) from 8-bit stereo, signed
491 DATA_FMT_16BIT_MN_LTLEND(0x00002000L) from 16-bit mono, little-endian
492 DATA_FMT_8_BIT_MN_SIGNED(0x00003000L) from 8-bit mono, signed
493 DATA_FMT_16BIT_ST_BIGEND(0x00004000L) from 16-bit stereo, big-endian
494 DATA_FMT_16BIT_MN_BIGEND(0x00006000L) from 16-bit mono, big-endian
495 DATA_FMT_8_BIT_ST_UNSIGNED(0x00009000L) from 8-bit stereo, unsigned
496 DATA_FMT_8_BIT_MN_UNSIGNED(0x0000b000L) from 8-bit mono, unsigned
497 ? Other combinations possible from:
498 DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
499 DMA_RQ_C2_AC_NONE 0x00000000L
500 DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
501 DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
502 DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
503 DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
504
505 HostBuffAddr: Host Buffer Physical Byte Address - SCB loc:3rd dword, Mask: 0xFFFFFFFFL
506 aligned to dword boundary
507 */
508 /* Basic (non scatter/gather) DMA requestor (4 ints) */
509 { DMA_RQ_C1_SOURCE_ON_HOST + /* source buffer is on the host */
510 DMA_RQ_C1_SOURCE_MOD1024 + /* source buffer is 1024 dwords (4096 bytes) */
511 DMA_RQ_C1_DEST_MOD32 + /* dest buffer(PCMreaderBuf) is 32 dwords*/
512 DMA_RQ_C1_WRITEBACK_SRC_FLAG + /* ?? */
513 DMA_RQ_C1_WRITEBACK_DEST_FLAG + /* ?? */
514 15, /* DwordCount-1: picked 16 for DwordCount because Jim */
515 /* Barnette said that is what we should use since */
516 /* we are not running in optimized mode? */
517 DMA_RQ_C2_AC_NONE +
518 DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG + /* set play interrupt (bit0) in HISR when source */
519 /* buffer (on host) crosses half-way point */
520 virtual_channel, /* Play DMA channel arbitrarily set to 0 */
521 playback_hw_addr, /* HostBuffAddr (source) */
522 DMA_RQ_SD_SP_SAMPLE_ADDR + /* destination buffer is in SP Sample Memory */
523 sample_buffer_addr /* SP Buffer Address (destination) */
524 },
525 /* Scatter/gather DMA requestor extension (5 ints) */
526 {
527 0,
528 0,
529 0,
530 0,
531 0
532 },
533 /* Sublist pointer & next stream control block (SCB) link. */
534 NULL_SCB_ADDR,NULL_SCB_ADDR,
535 /* Pointer to this tasks parameter block & stream function pointer */
536 0,NULL_SCB_ADDR,
537 /* rsConfig register for stream buffer (rsDMA reg. is loaded from basicReq.daw */
538 /* for incoming streams, or basicReq.saw, for outgoing streams) */
539 RSCONFIG_DMA_ENABLE + /* enable DMA */
540 (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) + /* MAX_DMA_SIZE picked to be 19 since SPUD */
541 /* uses it for some reason */
542 ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) + /* stream number = SCBaddr/16 */
543 RSCONFIG_SAMPLE_16STEREO +
544 RSCONFIG_MODULO_32, /* dest buffer(PCMreaderBuf) is 32 dwords (256 bytes) */
545 /* Stream sample pointer & MAC-unit mode for this stream */
546 (sample_buffer_addr << 0x10),
547 /* Fractional increment per output sample in the input sample buffer */
548 0,
549 {
550 /* Standard stereo volume control
551 default muted */
552 0xffff,0xffff,
553 0xffff,0xffff
554 }
555 };
556
557 if (ins->null_algorithm == NULL) {
558 ins->null_algorithm = cs46xx_dsp_lookup_symbol (chip,"NULLALGORITHM",
559 SYMBOL_CODE);
560
561 if (ins->null_algorithm == NULL) {
562 dev_err(chip->card->dev,
563 "dsp_spos: symbol NULLALGORITHM not found\n");
564 return NULL;
565 }
566 }
567
568 scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_reader_scb,
569 dest,ins->null_algorithm,parent_scb,
570 scb_child_type);
571
572 return scb;
573 }
574
575 #define GOF_PER_SEC 200
576
577 struct dsp_scb_descriptor *
cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip,char * scb_name,int rate,u16 src_buffer_addr,u16 src_delay_buffer_addr,u32 dest,struct dsp_scb_descriptor * parent_scb,int scb_child_type,int pass_through)578 cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
579 int rate,
580 u16 src_buffer_addr,
581 u16 src_delay_buffer_addr, u32 dest,
582 struct dsp_scb_descriptor * parent_scb,
583 int scb_child_type,
584 int pass_through)
585 {
586
587 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
588 struct dsp_scb_descriptor * scb;
589 unsigned int tmp1, tmp2;
590 unsigned int phiIncr;
591 unsigned int correctionPerGOF, correctionPerSec;
592
593 dev_dbg(chip->card->dev, "dsp_spos: setting %s rate to %u\n",
594 scb_name, rate);
595
596 /*
597 * Compute the values used to drive the actual sample rate conversion.
598 * The following formulas are being computed, using inline assembly
599 * since we need to use 64 bit arithmetic to compute the values:
600 *
601 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
602 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
603 * GOF_PER_SEC)
604 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
605 * GOF_PER_SEC * correctionPerGOF
606 *
607 * i.e.
608 *
609 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
610 * correctionPerGOF:correctionPerSec =
611 * dividend:remainder(ulOther / GOF_PER_SEC)
612 */
613 tmp1 = rate << 16;
614 phiIncr = tmp1 / 48000;
615 tmp1 -= phiIncr * 48000;
616 tmp1 <<= 10;
617 phiIncr <<= 10;
618 tmp2 = tmp1 / 48000;
619 phiIncr += tmp2;
620 tmp1 -= tmp2 * 48000;
621 correctionPerGOF = tmp1 / GOF_PER_SEC;
622 tmp1 -= correctionPerGOF * GOF_PER_SEC;
623 correctionPerSec = tmp1;
624
625 {
626 struct dsp_src_task_scb src_task_scb = {
627 0x0028,0x00c8,
628 0x5555,0x0000,
629 0x0000,0x0000,
630 src_buffer_addr,1,
631 correctionPerGOF,correctionPerSec,
632 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
633 0x0000,src_delay_buffer_addr,
634 0x0,
635 0x080,(src_delay_buffer_addr + (24 * 4)),
636 0,0, /* next_scb, sub_list_ptr */
637 0,0, /* entry, this_spb */
638 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
639 src_buffer_addr << 0x10,
640 phiIncr,
641 {
642 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left,
643 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left
644 }
645 };
646
647 if (ins->s16_up == NULL) {
648 ins->s16_up = cs46xx_dsp_lookup_symbol (chip,"S16_UPSRC",
649 SYMBOL_CODE);
650
651 if (ins->s16_up == NULL) {
652 dev_err(chip->card->dev,
653 "dsp_spos: symbol S16_UPSRC not found\n");
654 return NULL;
655 }
656 }
657
658 /* clear buffers */
659 _dsp_clear_sample_buffer (chip,src_buffer_addr,8);
660 _dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
661
662 if (pass_through) {
663 /* wont work with any other rate than
664 the native DSP rate */
665 snd_BUG_ON(rate != 48000);
666
667 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
668 dest,"DMAREADER",parent_scb,
669 scb_child_type);
670 } else {
671 scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
672 dest,ins->s16_up,parent_scb,
673 scb_child_type);
674 }
675
676
677 }
678
679 return scb;
680 }
681
682 #if 0 /* not used */
683 struct dsp_scb_descriptor *
684 cs46xx_dsp_create_filter_scb(struct snd_cs46xx * chip, char * scb_name,
685 u16 buffer_addr, u32 dest,
686 struct dsp_scb_descriptor * parent_scb,
687 int scb_child_type) {
688 struct dsp_scb_descriptor * scb;
689
690 struct dsp_filter_scb filter_scb = {
691 .a0_right = 0x41a9,
692 .a0_left = 0x41a9,
693 .a1_right = 0xb8e4,
694 .a1_left = 0xb8e4,
695 .a2_right = 0x3e55,
696 .a2_left = 0x3e55,
697
698 .filter_unused3 = 0x0000,
699 .filter_unused2 = 0x0000,
700
701 .output_buf_ptr = buffer_addr,
702 .init = 0x000,
703
704 .prev_sample_output1 = 0x00000000,
705 .prev_sample_output2 = 0x00000000,
706
707 .prev_sample_input1 = 0x00000000,
708 .prev_sample_input2 = 0x00000000,
709
710 .next_scb_ptr = 0x0000,
711 .sub_list_ptr = 0x0000,
712
713 .entry_point = 0x0000,
714 .spb_ptr = 0x0000,
715
716 .b0_right = 0x0e38,
717 .b0_left = 0x0e38,
718 .b1_right = 0x1c71,
719 .b1_left = 0x1c71,
720 .b2_right = 0x0e38,
721 .b2_left = 0x0e38,
722 };
723
724
725 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&filter_scb,
726 dest,"FILTERTASK",parent_scb,
727 scb_child_type);
728
729 return scb;
730 }
731 #endif /* not used */
732
733 struct dsp_scb_descriptor *
cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip,char * scb_name,u16 mix_buffer_addr,u32 dest,struct dsp_scb_descriptor * parent_scb,int scb_child_type)734 cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
735 u16 mix_buffer_addr, u32 dest,
736 struct dsp_scb_descriptor * parent_scb,
737 int scb_child_type)
738 {
739 struct dsp_scb_descriptor * scb;
740
741 struct dsp_mix_only_scb master_mix_scb = {
742 /* 0 */ { 0,
743 /* 1 */ 0,
744 /* 2 */ mix_buffer_addr,
745 /* 3 */ 0
746 /* */ },
747 {
748 /* 4 */ 0,
749 /* 5 */ 0,
750 /* 6 */ 0,
751 /* 7 */ 0,
752 /* 8 */ 0x00000080
753 },
754 /* 9 */ 0,0,
755 /* A */ 0,0,
756 /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
757 /* C */ (mix_buffer_addr + (16 * 4)) << 0x10,
758 /* D */ 0,
759 {
760 /* E */ 0x8000,0x8000,
761 /* F */ 0x8000,0x8000
762 }
763 };
764
765
766 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&master_mix_scb,
767 dest,"S16_MIX",parent_scb,
768 scb_child_type);
769 return scb;
770 }
771
772
773 struct dsp_scb_descriptor *
cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip,char * scb_name,u16 mix_buffer_addr,u16 writeback_spb,u32 dest,struct dsp_scb_descriptor * parent_scb,int scb_child_type)774 cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
775 u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
776 struct dsp_scb_descriptor * parent_scb,
777 int scb_child_type)
778 {
779 struct dsp_scb_descriptor * scb;
780
781 struct dsp_mix2_ostream_scb mix2_ostream_scb = {
782 /* Basic (non scatter/gather) DMA requestor (4 ints) */
783 {
784 DMA_RQ_C1_SOURCE_MOD64 +
785 DMA_RQ_C1_DEST_ON_HOST +
786 DMA_RQ_C1_DEST_MOD1024 +
787 DMA_RQ_C1_WRITEBACK_SRC_FLAG +
788 DMA_RQ_C1_WRITEBACK_DEST_FLAG +
789 15,
790
791 DMA_RQ_C2_AC_NONE +
792 DMA_RQ_C2_SIGNAL_DEST_PINGPONG +
793
794 CS46XX_DSP_CAPTURE_CHANNEL,
795 DMA_RQ_SD_SP_SAMPLE_ADDR +
796 mix_buffer_addr,
797 0x0
798 },
799
800 { 0, 0, 0, 0, 0, },
801 0,0,
802 0,writeback_spb,
803
804 RSCONFIG_DMA_ENABLE +
805 (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) +
806
807 ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) +
808 RSCONFIG_DMA_TO_HOST +
809 RSCONFIG_SAMPLE_16STEREO +
810 RSCONFIG_MODULO_64,
811 (mix_buffer_addr + (32 * 4)) << 0x10,
812 1,0,
813 0x0001,0x0080,
814 0xFFFF,0
815 };
816
817
818 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&mix2_ostream_scb,
819
820 dest,"S16_MIX_TO_OSTREAM",parent_scb,
821 scb_child_type);
822
823 return scb;
824 }
825
826
827 struct dsp_scb_descriptor *
cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,u16 vari_buffer_addr0,u16 vari_buffer_addr1,u32 dest,struct dsp_scb_descriptor * parent_scb,int scb_child_type)828 cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,
829 u16 vari_buffer_addr0,
830 u16 vari_buffer_addr1,
831 u32 dest,
832 struct dsp_scb_descriptor * parent_scb,
833 int scb_child_type)
834 {
835
836 struct dsp_scb_descriptor * scb;
837
838 struct dsp_vari_decimate_scb vari_decimate_scb = {
839 0x0028,0x00c8,
840 0x5555,0x0000,
841 0x0000,0x0000,
842 vari_buffer_addr0,vari_buffer_addr1,
843
844 0x0028,0x00c8,
845 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256,
846
847 0xFF800000,
848 0,
849 0x0080,vari_buffer_addr1 + (25 * 4),
850
851 0,0,
852 0,0,
853
854 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
855 vari_buffer_addr0 << 0x10,
856 0x04000000,
857 {
858 0x8000,0x8000,
859 0xFFFF,0xFFFF
860 }
861 };
862
863 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&vari_decimate_scb,
864 dest,"VARIDECIMATE",parent_scb,
865 scb_child_type);
866
867 return scb;
868 }
869
870
871 static struct dsp_scb_descriptor *
cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip,char * scb_name,u32 dest,struct dsp_scb_descriptor * input_scb,struct dsp_scb_descriptor * parent_scb,int scb_child_type)872 cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
873 struct dsp_scb_descriptor * input_scb,
874 struct dsp_scb_descriptor * parent_scb,
875 int scb_child_type)
876 {
877
878 struct dsp_scb_descriptor * scb;
879
880
881 struct dsp_pcm_serial_input_scb pcm_serial_input_scb = {
882 { 0,
883 0,
884 0,
885 0
886 },
887 {
888 0,
889 0,
890 0,
891 0,
892 0
893 },
894
895 0,0,
896 0,0,
897
898 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
899 0,
900 /* 0xD */ 0,input_scb->address,
901 {
902 /* 0xE */ 0x8000,0x8000,
903 /* 0xF */ 0x8000,0x8000
904 }
905 };
906
907 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_serial_input_scb,
908 dest,"PCMSERIALINPUTTASK",parent_scb,
909 scb_child_type);
910 return scb;
911 }
912
913
914 static struct dsp_scb_descriptor *
cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip,char * scb_name,u32 dest,u16 hfg_scb_address,u16 asynch_buffer_address,struct dsp_scb_descriptor * parent_scb,int scb_child_type)915 cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
916 u16 hfg_scb_address,
917 u16 asynch_buffer_address,
918 struct dsp_scb_descriptor * parent_scb,
919 int scb_child_type)
920 {
921
922 struct dsp_scb_descriptor * scb;
923
924 struct dsp_asynch_fg_tx_scb asynch_fg_tx_scb = {
925 0xfc00,0x03ff, /* Prototype sample buffer size of 256 dwords */
926 0x0058,0x0028, /* Min Delta 7 dwords == 28 bytes */
927 /* : Max delta 25 dwords == 100 bytes */
928 0,hfg_scb_address, /* Point to HFG task SCB */
929 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
930 0, /* Initialize accumulated Phi to 0 */
931 0,0x2aab, /* Const 1/3 */
932
933 {
934 0, /* Define the unused elements */
935 0,
936 0
937 },
938
939 0,0,
940 0,dest + AFGTxAccumPhi,
941
942 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256, /* Stereo, 256 dword */
943 (asynch_buffer_address) << 0x10, /* This should be automagically synchronized
944 to the producer pointer */
945
946 /* There is no correct initial value, it will depend upon the detected
947 rate etc */
948 0x18000000, /* Phi increment for approx 32k operation */
949 0x8000,0x8000, /* Volume controls are unused at this time */
950 0x8000,0x8000
951 };
952
953 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_tx_scb,
954 dest,"ASYNCHFGTXCODE",parent_scb,
955 scb_child_type);
956
957 return scb;
958 }
959
960
961 struct dsp_scb_descriptor *
cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip,char * scb_name,u32 dest,u16 hfg_scb_address,u16 asynch_buffer_address,struct dsp_scb_descriptor * parent_scb,int scb_child_type)962 cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
963 u16 hfg_scb_address,
964 u16 asynch_buffer_address,
965 struct dsp_scb_descriptor * parent_scb,
966 int scb_child_type)
967 {
968 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
969 struct dsp_scb_descriptor * scb;
970
971 struct dsp_asynch_fg_rx_scb asynch_fg_rx_scb = {
972 0xfe00,0x01ff, /* Prototype sample buffer size of 128 dwords */
973 0x0064,0x001c, /* Min Delta 7 dwords == 28 bytes */
974 /* : Max delta 25 dwords == 100 bytes */
975 0,hfg_scb_address, /* Point to HFG task SCB */
976 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
977 {
978 0, /* Define the unused elements */
979 0,
980 0,
981 0,
982 0
983 },
984
985 0,0,
986 0,dest,
987
988 RSCONFIG_MODULO_128 |
989 RSCONFIG_SAMPLE_16STEREO, /* Stereo, 128 dword */
990 ( (asynch_buffer_address + (16 * 4)) << 0x10), /* This should be automagically
991 synchrinized to the producer pointer */
992
993 /* There is no correct initial value, it will depend upon the detected
994 rate etc */
995 0x18000000,
996
997 /* Set IEC958 input volume */
998 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
999 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
1000 };
1001
1002 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_rx_scb,
1003 dest,"ASYNCHFGRXCODE",parent_scb,
1004 scb_child_type);
1005
1006 return scb;
1007 }
1008
1009
1010 #if 0 /* not used */
1011 struct dsp_scb_descriptor *
1012 cs46xx_dsp_create_output_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
1013 u16 snoop_buffer_address,
1014 struct dsp_scb_descriptor * snoop_scb,
1015 struct dsp_scb_descriptor * parent_scb,
1016 int scb_child_type)
1017 {
1018
1019 struct dsp_scb_descriptor * scb;
1020
1021 struct dsp_output_snoop_scb output_snoop_scb = {
1022 { 0, /* not used. Zero */
1023 0,
1024 0,
1025 0,
1026 },
1027 {
1028 0, /* not used. Zero */
1029 0,
1030 0,
1031 0,
1032 0
1033 },
1034
1035 0,0,
1036 0,0,
1037
1038 RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
1039 snoop_buffer_address << 0x10,
1040 0,0,
1041 0,
1042 0,snoop_scb->address
1043 };
1044
1045 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&output_snoop_scb,
1046 dest,"OUTPUTSNOOP",parent_scb,
1047 scb_child_type);
1048 return scb;
1049 }
1050 #endif /* not used */
1051
1052
1053 struct dsp_scb_descriptor *
cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip,char * scb_name,u32 dest,struct dsp_scb_descriptor * parent_scb,int scb_child_type)1054 cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
1055 struct dsp_scb_descriptor * parent_scb,
1056 int scb_child_type)
1057 {
1058 struct dsp_scb_descriptor * scb;
1059
1060 struct dsp_spio_write_scb spio_write_scb = {
1061 0,0, /* SPIOWAddress2:SPIOWAddress1; */
1062 0, /* SPIOWData1; */
1063 0, /* SPIOWData2; */
1064 0,0, /* SPIOWAddress4:SPIOWAddress3; */
1065 0, /* SPIOWData3; */
1066 0, /* SPIOWData4; */
1067 0,0, /* SPIOWDataPtr:Unused1; */
1068 { 0,0 }, /* Unused2[2]; */
1069
1070 0,0, /* SPIOWChildPtr:SPIOWSiblingPtr; */
1071 0,0, /* SPIOWThisPtr:SPIOWEntryPoint; */
1072
1073 {
1074 0,
1075 0,
1076 0,
1077 0,
1078 0 /* Unused3[5]; */
1079 }
1080 };
1081
1082 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&spio_write_scb,
1083 dest,"SPIOWRITE",parent_scb,
1084 scb_child_type);
1085
1086 return scb;
1087 }
1088
1089 struct dsp_scb_descriptor *
cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip,char * scb_name,u32 dest,u16 snoop_buffer_address,struct dsp_scb_descriptor * snoop_scb,struct dsp_scb_descriptor * parent_scb,int scb_child_type)1090 cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
1091 u16 snoop_buffer_address,
1092 struct dsp_scb_descriptor * snoop_scb,
1093 struct dsp_scb_descriptor * parent_scb,
1094 int scb_child_type)
1095 {
1096 struct dsp_scb_descriptor * scb;
1097
1098 struct dsp_magic_snoop_task magic_snoop_scb = {
1099 /* 0 */ 0, /* i0 */
1100 /* 1 */ 0, /* i1 */
1101 /* 2 */ snoop_buffer_address << 0x10,
1102 /* 3 */ 0,snoop_scb->address,
1103 /* 4 */ 0, /* i3 */
1104 /* 5 */ 0, /* i4 */
1105 /* 6 */ 0, /* i5 */
1106 /* 7 */ 0, /* i6 */
1107 /* 8 */ 0, /* i7 */
1108 /* 9 */ 0,0, /* next_scb, sub_list_ptr */
1109 /* A */ 0,0, /* entry_point, this_ptr */
1110 /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
1111 /* C */ snoop_buffer_address << 0x10,
1112 /* D */ 0,
1113 /* E */ { 0x8000,0x8000,
1114 /* F */ 0xffff,0xffff
1115 }
1116 };
1117
1118 scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&magic_snoop_scb,
1119 dest,"MAGICSNOOPTASK",parent_scb,
1120 scb_child_type);
1121
1122 return scb;
1123 }
1124
1125 static struct dsp_scb_descriptor *
find_next_free_scb(struct snd_cs46xx * chip,struct dsp_scb_descriptor * from)1126 find_next_free_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * from)
1127 {
1128 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1129 struct dsp_scb_descriptor * scb = from;
1130
1131 while (scb->next_scb_ptr != ins->the_null_scb) {
1132 if (snd_BUG_ON(!scb->next_scb_ptr))
1133 return NULL;
1134
1135 scb = scb->next_scb_ptr;
1136 }
1137
1138 return scb;
1139 }
1140
1141 static const u32 pcm_reader_buffer_addr[DSP_MAX_PCM_CHANNELS] = {
1142 0x0600, /* 1 */
1143 0x1500, /* 2 */
1144 0x1580, /* 3 */
1145 0x1600, /* 4 */
1146 0x1680, /* 5 */
1147 0x1700, /* 6 */
1148 0x1780, /* 7 */
1149 0x1800, /* 8 */
1150 0x1880, /* 9 */
1151 0x1900, /* 10 */
1152 0x1980, /* 11 */
1153 0x1A00, /* 12 */
1154 0x1A80, /* 13 */
1155 0x1B00, /* 14 */
1156 0x1B80, /* 15 */
1157 0x1C00, /* 16 */
1158 0x1C80, /* 17 */
1159 0x1D00, /* 18 */
1160 0x1D80, /* 19 */
1161 0x1E00, /* 20 */
1162 0x1E80, /* 21 */
1163 0x1F00, /* 22 */
1164 0x1F80, /* 23 */
1165 0x2000, /* 24 */
1166 0x2080, /* 25 */
1167 0x2100, /* 26 */
1168 0x2180, /* 27 */
1169 0x2200, /* 28 */
1170 0x2280, /* 29 */
1171 0x2300, /* 30 */
1172 0x2380, /* 31 */
1173 0x2400, /* 32 */
1174 };
1175
1176 static const u32 src_output_buffer_addr[DSP_MAX_SRC_NR] = {
1177 0x2B80,
1178 0x2BA0,
1179 0x2BC0,
1180 0x2BE0,
1181 0x2D00,
1182 0x2D20,
1183 0x2D40,
1184 0x2D60,
1185 0x2D80,
1186 0x2DA0,
1187 0x2DC0,
1188 0x2DE0,
1189 0x2E00,
1190 0x2E20
1191 };
1192
1193 static const u32 src_delay_buffer_addr[DSP_MAX_SRC_NR] = {
1194 0x2480,
1195 0x2500,
1196 0x2580,
1197 0x2600,
1198 0x2680,
1199 0x2700,
1200 0x2780,
1201 0x2800,
1202 0x2880,
1203 0x2900,
1204 0x2980,
1205 0x2A00,
1206 0x2A80,
1207 0x2B00
1208 };
1209
1210 struct dsp_pcm_channel_descriptor *
cs46xx_dsp_create_pcm_channel(struct snd_cs46xx * chip,u32 sample_rate,void * private_data,u32 hw_dma_addr,int pcm_channel_id)1211 cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip,
1212 u32 sample_rate, void * private_data,
1213 u32 hw_dma_addr,
1214 int pcm_channel_id)
1215 {
1216 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1217 struct dsp_scb_descriptor * src_scb = NULL, * pcm_scb, * mixer_scb = NULL;
1218 struct dsp_scb_descriptor * src_parent_scb = NULL;
1219
1220 /* struct dsp_scb_descriptor * pcm_parent_scb; */
1221 char scb_name[DSP_MAX_SCB_NAME];
1222 int i, pcm_index = -1, insert_point, src_index = -1, pass_through = 0;
1223 unsigned long flags;
1224
1225 switch (pcm_channel_id) {
1226 case DSP_PCM_MAIN_CHANNEL:
1227 mixer_scb = ins->master_mix_scb;
1228 break;
1229 case DSP_PCM_REAR_CHANNEL:
1230 mixer_scb = ins->rear_mix_scb;
1231 break;
1232 case DSP_PCM_CENTER_LFE_CHANNEL:
1233 mixer_scb = ins->center_lfe_mix_scb;
1234 break;
1235 case DSP_PCM_S71_CHANNEL:
1236 /* TODO */
1237 snd_BUG();
1238 break;
1239 case DSP_IEC958_CHANNEL:
1240 if (snd_BUG_ON(!ins->asynch_tx_scb))
1241 return NULL;
1242 mixer_scb = ins->asynch_tx_scb;
1243
1244 /* if sample rate is set to 48khz we pass
1245 the Sample Rate Converted (which could
1246 alter the raw data stream ...) */
1247 if (sample_rate == 48000) {
1248 dev_dbg(chip->card->dev, "IEC958 pass through\n");
1249 /* Hack to bypass creating a new SRC */
1250 pass_through = 1;
1251 }
1252 break;
1253 default:
1254 snd_BUG();
1255 return NULL;
1256 }
1257 /* default sample rate is 44100 */
1258 if (!sample_rate) sample_rate = 44100;
1259
1260 /* search for a already created SRC SCB with the same sample rate */
1261 for (i = 0; i < DSP_MAX_PCM_CHANNELS &&
1262 (pcm_index == -1 || src_scb == NULL); ++i) {
1263
1264 /* virtual channel reserved
1265 for capture */
1266 if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue;
1267
1268 if (ins->pcm_channels[i].active) {
1269 if (!src_scb &&
1270 ins->pcm_channels[i].sample_rate == sample_rate &&
1271 ins->pcm_channels[i].mixer_scb == mixer_scb) {
1272 src_scb = ins->pcm_channels[i].src_scb;
1273 ins->pcm_channels[i].src_scb->ref_count ++;
1274 src_index = ins->pcm_channels[i].src_slot;
1275 }
1276 } else if (pcm_index == -1) {
1277 pcm_index = i;
1278 }
1279 }
1280
1281 if (pcm_index == -1) {
1282 dev_err(chip->card->dev, "dsp_spos: no free PCM channel\n");
1283 return NULL;
1284 }
1285
1286 if (src_scb == NULL) {
1287 if (ins->nsrc_scb >= DSP_MAX_SRC_NR) {
1288 dev_err(chip->card->dev,
1289 "dsp_spos: too many SRC instances\n!");
1290 return NULL;
1291 }
1292
1293 /* find a free slot */
1294 for (i = 0; i < DSP_MAX_SRC_NR; ++i) {
1295 if (ins->src_scb_slots[i] == 0) {
1296 src_index = i;
1297 ins->src_scb_slots[i] = 1;
1298 break;
1299 }
1300 }
1301 if (snd_BUG_ON(src_index == -1))
1302 return NULL;
1303
1304 /* we need to create a new SRC SCB */
1305 if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
1306 src_parent_scb = mixer_scb;
1307 insert_point = SCB_ON_PARENT_SUBLIST_SCB;
1308 } else {
1309 src_parent_scb = find_next_free_scb(chip,mixer_scb->sub_list_ptr);
1310 insert_point = SCB_ON_PARENT_NEXT_SCB;
1311 }
1312
1313 snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
1314
1315 dev_dbg(chip->card->dev,
1316 "dsp_spos: creating SRC \"%s\"\n", scb_name);
1317 src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
1318 sample_rate,
1319 src_output_buffer_addr[src_index],
1320 src_delay_buffer_addr[src_index],
1321 /* 0x400 - 0x600 source SCBs */
1322 0x400 + (src_index * 0x10) ,
1323 src_parent_scb,
1324 insert_point,
1325 pass_through);
1326
1327 if (!src_scb) {
1328 dev_err(chip->card->dev,
1329 "dsp_spos: failed to create SRCtaskSCB\n");
1330 return NULL;
1331 }
1332
1333 /* cs46xx_dsp_set_src_sample_rate(chip,src_scb,sample_rate); */
1334
1335 ins->nsrc_scb ++;
1336 }
1337
1338
1339 snprintf (scb_name,DSP_MAX_SCB_NAME,"PCMReader_SCB%d",pcm_index);
1340
1341 dev_dbg(chip->card->dev, "dsp_spos: creating PCM \"%s\" (%d)\n",
1342 scb_name, pcm_channel_id);
1343
1344 pcm_scb = cs46xx_dsp_create_pcm_reader_scb(chip,scb_name,
1345 pcm_reader_buffer_addr[pcm_index],
1346 /* 0x200 - 400 PCMreader SCBs */
1347 (pcm_index * 0x10) + 0x200,
1348 pcm_index, /* virtual channel 0-31 */
1349 hw_dma_addr, /* pcm hw addr */
1350 NULL, /* parent SCB ptr */
1351 0 /* insert point */
1352 );
1353
1354 if (!pcm_scb) {
1355 dev_err(chip->card->dev,
1356 "dsp_spos: failed to create PCMreaderSCB\n");
1357 return NULL;
1358 }
1359
1360 spin_lock_irqsave(&chip->reg_lock, flags);
1361 ins->pcm_channels[pcm_index].sample_rate = sample_rate;
1362 ins->pcm_channels[pcm_index].pcm_reader_scb = pcm_scb;
1363 ins->pcm_channels[pcm_index].src_scb = src_scb;
1364 ins->pcm_channels[pcm_index].unlinked = 1;
1365 ins->pcm_channels[pcm_index].private_data = private_data;
1366 ins->pcm_channels[pcm_index].src_slot = src_index;
1367 ins->pcm_channels[pcm_index].active = 1;
1368 ins->pcm_channels[pcm_index].pcm_slot = pcm_index;
1369 ins->pcm_channels[pcm_index].mixer_scb = mixer_scb;
1370 ins->npcm_channels ++;
1371 spin_unlock_irqrestore(&chip->reg_lock, flags);
1372
1373 return (ins->pcm_channels + pcm_index);
1374 }
1375
cs46xx_dsp_pcm_channel_set_period(struct snd_cs46xx * chip,struct dsp_pcm_channel_descriptor * pcm_channel,int period_size)1376 int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
1377 struct dsp_pcm_channel_descriptor * pcm_channel,
1378 int period_size)
1379 {
1380 u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);
1381 temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;
1382
1383 switch (period_size) {
1384 case 2048:
1385 temp |= DMA_RQ_C1_SOURCE_MOD1024;
1386 break;
1387 case 1024:
1388 temp |= DMA_RQ_C1_SOURCE_MOD512;
1389 break;
1390 case 512:
1391 temp |= DMA_RQ_C1_SOURCE_MOD256;
1392 break;
1393 case 256:
1394 temp |= DMA_RQ_C1_SOURCE_MOD128;
1395 break;
1396 case 128:
1397 temp |= DMA_RQ_C1_SOURCE_MOD64;
1398 break;
1399 case 64:
1400 temp |= DMA_RQ_C1_SOURCE_MOD32;
1401 break;
1402 case 32:
1403 temp |= DMA_RQ_C1_SOURCE_MOD16;
1404 break;
1405 default:
1406 dev_dbg(chip->card->dev,
1407 "period size (%d) not supported by HW\n", period_size);
1408 return -EINVAL;
1409 }
1410
1411 snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);
1412
1413 return 0;
1414 }
1415
cs46xx_dsp_pcm_ostream_set_period(struct snd_cs46xx * chip,int period_size)1416 int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip,
1417 int period_size)
1418 {
1419 u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);
1420 temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;
1421
1422 switch (period_size) {
1423 case 2048:
1424 temp |= DMA_RQ_C1_DEST_MOD1024;
1425 break;
1426 case 1024:
1427 temp |= DMA_RQ_C1_DEST_MOD512;
1428 break;
1429 case 512:
1430 temp |= DMA_RQ_C1_DEST_MOD256;
1431 break;
1432 case 256:
1433 temp |= DMA_RQ_C1_DEST_MOD128;
1434 break;
1435 case 128:
1436 temp |= DMA_RQ_C1_DEST_MOD64;
1437 break;
1438 case 64:
1439 temp |= DMA_RQ_C1_DEST_MOD32;
1440 break;
1441 case 32:
1442 temp |= DMA_RQ_C1_DEST_MOD16;
1443 break;
1444 default:
1445 dev_dbg(chip->card->dev,
1446 "period size (%d) not supported by HW\n", period_size);
1447 return -EINVAL;
1448 }
1449
1450 snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);
1451
1452 return 0;
1453 }
1454
cs46xx_dsp_destroy_pcm_channel(struct snd_cs46xx * chip,struct dsp_pcm_channel_descriptor * pcm_channel)1455 void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
1456 struct dsp_pcm_channel_descriptor * pcm_channel)
1457 {
1458 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1459 unsigned long flags;
1460
1461 if (snd_BUG_ON(!pcm_channel->active ||
1462 ins->npcm_channels <= 0 ||
1463 pcm_channel->src_scb->ref_count <= 0))
1464 return;
1465
1466 spin_lock_irqsave(&chip->reg_lock, flags);
1467 pcm_channel->unlinked = 1;
1468 pcm_channel->active = 0;
1469 pcm_channel->private_data = NULL;
1470 pcm_channel->src_scb->ref_count --;
1471 ins->npcm_channels --;
1472 spin_unlock_irqrestore(&chip->reg_lock, flags);
1473
1474 cs46xx_dsp_remove_scb(chip,pcm_channel->pcm_reader_scb);
1475
1476 if (!pcm_channel->src_scb->ref_count) {
1477 cs46xx_dsp_remove_scb(chip,pcm_channel->src_scb);
1478
1479 if (snd_BUG_ON(pcm_channel->src_slot < 0 ||
1480 pcm_channel->src_slot >= DSP_MAX_SRC_NR))
1481 return;
1482
1483 ins->src_scb_slots[pcm_channel->src_slot] = 0;
1484 ins->nsrc_scb --;
1485 }
1486 }
1487
cs46xx_dsp_pcm_unlink(struct snd_cs46xx * chip,struct dsp_pcm_channel_descriptor * pcm_channel)1488 int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
1489 struct dsp_pcm_channel_descriptor * pcm_channel)
1490 {
1491 unsigned long flags;
1492
1493 if (snd_BUG_ON(!pcm_channel->active ||
1494 chip->dsp_spos_instance->npcm_channels <= 0))
1495 return -EIO;
1496
1497 spin_lock_irqsave(&chip->reg_lock, flags);
1498 if (pcm_channel->unlinked) {
1499 spin_unlock_irqrestore(&chip->reg_lock, flags);
1500 return -EIO;
1501 }
1502
1503 pcm_channel->unlinked = 1;
1504
1505 _dsp_unlink_scb (chip,pcm_channel->pcm_reader_scb);
1506 spin_unlock_irqrestore(&chip->reg_lock, flags);
1507
1508 return 0;
1509 }
1510
cs46xx_dsp_pcm_link(struct snd_cs46xx * chip,struct dsp_pcm_channel_descriptor * pcm_channel)1511 int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
1512 struct dsp_pcm_channel_descriptor * pcm_channel)
1513 {
1514 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1515 struct dsp_scb_descriptor * parent_scb;
1516 struct dsp_scb_descriptor * src_scb = pcm_channel->src_scb;
1517 unsigned long flags;
1518
1519 spin_lock_irqsave(&chip->reg_lock, flags);
1520
1521 if (pcm_channel->unlinked == 0) {
1522 spin_unlock_irqrestore(&chip->reg_lock, flags);
1523 return -EIO;
1524 }
1525
1526 parent_scb = src_scb;
1527
1528 if (src_scb->sub_list_ptr != ins->the_null_scb) {
1529 src_scb->sub_list_ptr->parent_scb_ptr = pcm_channel->pcm_reader_scb;
1530 pcm_channel->pcm_reader_scb->next_scb_ptr = src_scb->sub_list_ptr;
1531 }
1532
1533 src_scb->sub_list_ptr = pcm_channel->pcm_reader_scb;
1534
1535 snd_BUG_ON(pcm_channel->pcm_reader_scb->parent_scb_ptr);
1536 pcm_channel->pcm_reader_scb->parent_scb_ptr = parent_scb;
1537
1538 /* update SCB entry in DSP RAM */
1539 cs46xx_dsp_spos_update_scb(chip,pcm_channel->pcm_reader_scb);
1540
1541 /* update parent SCB entry */
1542 cs46xx_dsp_spos_update_scb(chip,parent_scb);
1543
1544 pcm_channel->unlinked = 0;
1545 spin_unlock_irqrestore(&chip->reg_lock, flags);
1546 return 0;
1547 }
1548
1549 struct dsp_scb_descriptor *
cs46xx_add_record_source(struct snd_cs46xx * chip,struct dsp_scb_descriptor * source,u16 addr,char * scb_name)1550 cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
1551 u16 addr, char * scb_name)
1552 {
1553 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1554 struct dsp_scb_descriptor * parent;
1555 struct dsp_scb_descriptor * pcm_input;
1556 int insert_point;
1557
1558 if (snd_BUG_ON(!ins->record_mixer_scb))
1559 return NULL;
1560
1561 if (ins->record_mixer_scb->sub_list_ptr != ins->the_null_scb) {
1562 parent = find_next_free_scb (chip,ins->record_mixer_scb->sub_list_ptr);
1563 insert_point = SCB_ON_PARENT_NEXT_SCB;
1564 } else {
1565 parent = ins->record_mixer_scb;
1566 insert_point = SCB_ON_PARENT_SUBLIST_SCB;
1567 }
1568
1569 pcm_input = cs46xx_dsp_create_pcm_serial_input_scb(chip,scb_name,addr,
1570 source, parent,
1571 insert_point);
1572
1573 return pcm_input;
1574 }
1575
cs46xx_src_unlink(struct snd_cs46xx * chip,struct dsp_scb_descriptor * src)1576 int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
1577 {
1578 unsigned long flags;
1579
1580 if (snd_BUG_ON(!src->parent_scb_ptr))
1581 return -EINVAL;
1582
1583 /* mute SCB */
1584 cs46xx_dsp_scb_set_volume (chip,src,0,0);
1585
1586 spin_lock_irqsave(&chip->reg_lock, flags);
1587 _dsp_unlink_scb (chip,src);
1588 spin_unlock_irqrestore(&chip->reg_lock, flags);
1589
1590 return 0;
1591 }
1592
cs46xx_src_link(struct snd_cs46xx * chip,struct dsp_scb_descriptor * src)1593 int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
1594 {
1595 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1596 struct dsp_scb_descriptor * parent_scb;
1597
1598 if (snd_BUG_ON(src->parent_scb_ptr))
1599 return -EINVAL;
1600 if (snd_BUG_ON(!ins->master_mix_scb))
1601 return -EINVAL;
1602
1603 if (ins->master_mix_scb->sub_list_ptr != ins->the_null_scb) {
1604 parent_scb = find_next_free_scb (chip,ins->master_mix_scb->sub_list_ptr);
1605 parent_scb->next_scb_ptr = src;
1606 } else {
1607 parent_scb = ins->master_mix_scb;
1608 parent_scb->sub_list_ptr = src;
1609 }
1610
1611 src->parent_scb_ptr = parent_scb;
1612
1613 /* update entry in DSP RAM */
1614 cs46xx_dsp_spos_update_scb(chip,parent_scb);
1615
1616 return 0;
1617 }
1618
cs46xx_dsp_enable_spdif_out(struct snd_cs46xx * chip)1619 int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip)
1620 {
1621 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1622
1623 if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
1624 cs46xx_dsp_enable_spdif_hw (chip);
1625 }
1626
1627 /* dont touch anything if SPDIF is open */
1628 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
1629 /* when cs46xx_iec958_post_close(...) is called it
1630 will call this function if necessary depending on
1631 this bit */
1632 ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
1633
1634 return -EBUSY;
1635 }
1636
1637 if (snd_BUG_ON(ins->asynch_tx_scb))
1638 return -EINVAL;
1639 if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr !=
1640 ins->the_null_scb))
1641 return -EINVAL;
1642
1643 /* reset output snooper sample buffer pointer */
1644 snd_cs46xx_poke (chip, (ins->ref_snoop_scb->address + 2) << 2,
1645 (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10 );
1646
1647 /* The asynch. transfer task */
1648 ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
1649 SPDIFO_SCB_INST,
1650 SPDIFO_IP_OUTPUT_BUFFER1,
1651 ins->master_mix_scb,
1652 SCB_ON_PARENT_NEXT_SCB);
1653 if (!ins->asynch_tx_scb) return -ENOMEM;
1654
1655 ins->spdif_pcm_input_scb = cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_II",
1656 PCMSERIALINII_SCB_ADDR,
1657 ins->ref_snoop_scb,
1658 ins->asynch_tx_scb,
1659 SCB_ON_PARENT_SUBLIST_SCB);
1660
1661
1662 if (!ins->spdif_pcm_input_scb) return -ENOMEM;
1663
1664 /* monitor state */
1665 ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
1666
1667 return 0;
1668 }
1669
cs46xx_dsp_disable_spdif_out(struct snd_cs46xx * chip)1670 int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip)
1671 {
1672 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1673
1674 /* dont touch anything if SPDIF is open */
1675 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
1676 ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
1677 return -EBUSY;
1678 }
1679
1680 /* check integrety */
1681 if (snd_BUG_ON(!ins->asynch_tx_scb))
1682 return -EINVAL;
1683 if (snd_BUG_ON(!ins->spdif_pcm_input_scb))
1684 return -EINVAL;
1685 if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr != ins->asynch_tx_scb))
1686 return -EINVAL;
1687 if (snd_BUG_ON(ins->asynch_tx_scb->parent_scb_ptr !=
1688 ins->master_mix_scb))
1689 return -EINVAL;
1690
1691 cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
1692 cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
1693
1694 ins->spdif_pcm_input_scb = NULL;
1695 ins->asynch_tx_scb = NULL;
1696
1697 /* clear buffer to prevent any undesired noise */
1698 _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
1699
1700 /* monitor state */
1701 ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
1702
1703
1704 return 0;
1705 }
1706
cs46xx_iec958_pre_open(struct snd_cs46xx * chip)1707 int cs46xx_iec958_pre_open (struct snd_cs46xx *chip)
1708 {
1709 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1710
1711 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
1712 /* remove AsynchFGTxSCB and PCMSerialInput_II */
1713 cs46xx_dsp_disable_spdif_out (chip);
1714
1715 /* save state */
1716 ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
1717 }
1718
1719 /* if not enabled already */
1720 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
1721 cs46xx_dsp_enable_spdif_hw (chip);
1722 }
1723
1724 /* Create the asynch. transfer task for playback */
1725 ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
1726 SPDIFO_SCB_INST,
1727 SPDIFO_IP_OUTPUT_BUFFER1,
1728 ins->master_mix_scb,
1729 SCB_ON_PARENT_NEXT_SCB);
1730
1731
1732 /* set spdif channel status value for streaming */
1733 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_stream);
1734
1735 ins->spdif_status_out |= DSP_SPDIF_STATUS_PLAYBACK_OPEN;
1736
1737 return 0;
1738 }
1739
cs46xx_iec958_post_close(struct snd_cs46xx * chip)1740 int cs46xx_iec958_post_close (struct snd_cs46xx *chip)
1741 {
1742 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1743
1744 if (snd_BUG_ON(!ins->asynch_tx_scb))
1745 return -EINVAL;
1746
1747 ins->spdif_status_out &= ~DSP_SPDIF_STATUS_PLAYBACK_OPEN;
1748
1749 /* restore settings */
1750 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
1751
1752 /* deallocate stuff */
1753 if (ins->spdif_pcm_input_scb != NULL) {
1754 cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
1755 ins->spdif_pcm_input_scb = NULL;
1756 }
1757
1758 cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
1759 ins->asynch_tx_scb = NULL;
1760
1761 /* clear buffer to prevent any undesired noise */
1762 _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
1763
1764 /* restore state */
1765 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
1766 cs46xx_dsp_enable_spdif_out (chip);
1767 }
1768
1769 return 0;
1770 }
1771