1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 /*
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/bus.h>
39 #include <sys/sysctl.h>
40
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44
45 #include <dev/ic/ns16550.h>
46
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49
50 #include <dev/puc/puc_bus.h>
51 #include <dev/puc/puc_cfg.h>
52 #include <dev/puc/puc_bfe.h>
53
54 static puc_config_f puc_config_advantech;
55 static puc_config_f puc_config_amc;
56 static puc_config_f puc_config_diva;
57 static puc_config_f puc_config_exar;
58 static puc_config_f puc_config_exar_pcie;
59 static puc_config_f puc_config_icbook;
60 static puc_config_f puc_config_moxa;
61 static puc_config_f puc_config_oxford_pci954;
62 static puc_config_f puc_config_oxford_pcie;
63 static puc_config_f puc_config_quatech;
64 static puc_config_f puc_config_syba;
65 static puc_config_f puc_config_siig;
66 static puc_config_f puc_config_sunix;
67 static puc_config_f puc_config_timedia;
68 static puc_config_f puc_config_titan;
69
70 const struct puc_cfg puc_pci_devices[] = {
71 { 0x0009, 0x7168, 0xffff, 0,
72 "Sunix SUN1889",
73 DEFAULT_RCLK * 8,
74 PUC_PORT_2S, 0x10, 0, 8,
75 },
76
77 { 0x103c, 0x1048, 0x103c, 0x1049,
78 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
79 DEFAULT_RCLK,
80 PUC_PORT_3S, 0x10, 0, -1,
81 .config_function = puc_config_diva
82 },
83
84 { 0x103c, 0x1048, 0x103c, 0x104a,
85 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
86 DEFAULT_RCLK,
87 PUC_PORT_2S, 0x10, 0, -1,
88 .config_function = puc_config_diva
89 },
90
91 { 0x103c, 0x1048, 0x103c, 0x104b,
92 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
93 DEFAULT_RCLK,
94 PUC_PORT_4S, 0x10, 0, -1,
95 .config_function = puc_config_diva
96 },
97
98 { 0x103c, 0x1048, 0x103c, 0x1223,
99 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
100 DEFAULT_RCLK,
101 PUC_PORT_3S, 0x10, 0, -1,
102 .config_function = puc_config_diva
103 },
104
105 { 0x103c, 0x1048, 0x103c, 0x1226,
106 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
107 DEFAULT_RCLK,
108 PUC_PORT_3S, 0x10, 0, -1,
109 .config_function = puc_config_diva
110 },
111
112 { 0x103c, 0x1048, 0x103c, 0x1282,
113 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
114 DEFAULT_RCLK,
115 PUC_PORT_3S, 0x10, 0, -1,
116 .config_function = puc_config_diva
117 },
118
119 { 0x10b5, 0x1076, 0x10b5, 0x1076,
120 "VScom PCI-800",
121 DEFAULT_RCLK * 8,
122 PUC_PORT_8S, 0x18, 0, 8,
123 },
124
125 { 0x10b5, 0x1077, 0x10b5, 0x1077,
126 "VScom PCI-400",
127 DEFAULT_RCLK * 8,
128 PUC_PORT_4S, 0x18, 0, 8,
129 },
130
131 { 0x10b5, 0x1103, 0x10b5, 0x1103,
132 "VScom PCI-200",
133 DEFAULT_RCLK * 8,
134 PUC_PORT_2S, 0x18, 4, 0,
135 },
136
137 /*
138 * Boca Research Turbo Serial 658 (8 serial port) card.
139 * Appears to be the same as Chase Research PLC PCI-FAST8
140 * and Perle PCI-FAST8 Multi-Port serial cards.
141 */
142 { 0x10b5, 0x9050, 0x12e0, 0x0021,
143 "Boca Research Turbo Serial 658",
144 DEFAULT_RCLK * 4,
145 PUC_PORT_8S, 0x18, 0, 8,
146 },
147
148 { 0x10b5, 0x9050, 0x12e0, 0x0031,
149 "Boca Research Turbo Serial 654",
150 DEFAULT_RCLK * 4,
151 PUC_PORT_4S, 0x18, 0, 8,
152 },
153
154 /*
155 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
156 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
157 * into the subsystem fields, and claims that it's a
158 * network/misc (0x02/0x80) device.
159 */
160 { 0x10b5, 0x9050, 0xd84d, 0x6808,
161 "Dolphin Peripherals 4035",
162 DEFAULT_RCLK,
163 PUC_PORT_2S, 0x18, 4, 0,
164 },
165
166 /*
167 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
168 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
169 * into the subsystem fields, and claims that it's a
170 * network/misc (0x02/0x80) device.
171 */
172 { 0x10b5, 0x9050, 0xd84d, 0x6810,
173 "Dolphin Peripherals 4014",
174 0,
175 PUC_PORT_2P, 0x20, 4, 0,
176 },
177
178 { 0x10e8, 0x818e, 0xffff, 0,
179 "Applied Micro Circuits 8 Port UART",
180 DEFAULT_RCLK,
181 PUC_PORT_8S, 0x14, -1, -1,
182 .config_function = puc_config_amc
183 },
184
185 /*
186 * The following members of the Digi International Neo series are
187 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV.
188 * Accordingly, the PCIe versions of these cards incorporate a PLX
189 * PCIe-PCI-bridge.
190 */
191
192 { 0x114f, 0x00b0, 0xffff, 0,
193 "Digi Neo PCI 4 Port",
194 DEFAULT_RCLK * 8,
195 PUC_PORT_4S, 0x10, 0, -1,
196 .config_function = puc_config_exar
197 },
198
199 { 0x114f, 0x00b1, 0xffff, 0,
200 "Digi Neo PCI 8 Port",
201 DEFAULT_RCLK * 8,
202 PUC_PORT_8S, 0x10, 0, -1,
203 .config_function = puc_config_exar
204 },
205
206 { 0x114f, 0x00f0, 0xffff, 0,
207 "Digi Neo PCIe 8 Port",
208 DEFAULT_RCLK * 8,
209 PUC_PORT_8S, 0x10, 0, -1,
210 .config_function = puc_config_exar
211 },
212
213 { 0x114f, 0x00f1, 0xffff, 0,
214 "Digi Neo PCIe 4 Port",
215 DEFAULT_RCLK * 8,
216 PUC_PORT_4S, 0x10, 0, -1,
217 .config_function = puc_config_exar
218 },
219
220 { 0x114f, 0x00f2, 0xffff, 0,
221 "Digi Neo PCIe 4 Port RJ45",
222 DEFAULT_RCLK * 8,
223 PUC_PORT_4S, 0x10, 0, -1,
224 .config_function = puc_config_exar
225 },
226
227 { 0x114f, 0x00f3, 0xffff, 0,
228 "Digi Neo PCIe 8 Port RJ45",
229 DEFAULT_RCLK * 8,
230 PUC_PORT_8S, 0x10, 0, -1,
231 .config_function = puc_config_exar
232 },
233
234 { 0x11fe, 0x8010, 0xffff, 0,
235 "Comtrol RocketPort 550/8 RJ11 part A",
236 DEFAULT_RCLK * 4,
237 PUC_PORT_4S, 0x10, 0, 8,
238 },
239
240 { 0x11fe, 0x8011, 0xffff, 0,
241 "Comtrol RocketPort 550/8 RJ11 part B",
242 DEFAULT_RCLK * 4,
243 PUC_PORT_4S, 0x10, 0, 8,
244 },
245
246 { 0x11fe, 0x8012, 0xffff, 0,
247 "Comtrol RocketPort 550/8 Octa part A",
248 DEFAULT_RCLK * 4,
249 PUC_PORT_4S, 0x10, 0, 8,
250 },
251
252 { 0x11fe, 0x8013, 0xffff, 0,
253 "Comtrol RocketPort 550/8 Octa part B",
254 DEFAULT_RCLK * 4,
255 PUC_PORT_4S, 0x10, 0, 8,
256 },
257
258 { 0x11fe, 0x8014, 0xffff, 0,
259 "Comtrol RocketPort 550/4 RJ45",
260 DEFAULT_RCLK * 4,
261 PUC_PORT_4S, 0x10, 0, 8,
262 },
263
264 { 0x11fe, 0x8015, 0xffff, 0,
265 "Comtrol RocketPort 550/Quad",
266 DEFAULT_RCLK * 4,
267 PUC_PORT_4S, 0x10, 0, 8,
268 },
269
270 { 0x11fe, 0x8016, 0xffff, 0,
271 "Comtrol RocketPort 550/16 part A",
272 DEFAULT_RCLK * 4,
273 PUC_PORT_4S, 0x10, 0, 8,
274 },
275
276 { 0x11fe, 0x8017, 0xffff, 0,
277 "Comtrol RocketPort 550/16 part B",
278 DEFAULT_RCLK * 4,
279 PUC_PORT_12S, 0x10, 0, 8,
280 },
281
282 { 0x11fe, 0x8018, 0xffff, 0,
283 "Comtrol RocketPort 550/8 part A",
284 DEFAULT_RCLK * 4,
285 PUC_PORT_4S, 0x10, 0, 8,
286 },
287
288 { 0x11fe, 0x8019, 0xffff, 0,
289 "Comtrol RocketPort 550/8 part B",
290 DEFAULT_RCLK * 4,
291 PUC_PORT_4S, 0x10, 0, 8,
292 },
293
294 /*
295 * IBM SurePOS 300 Series (481033H) serial ports
296 * Details can be found on the IBM RSS websites
297 */
298
299 { 0x1014, 0x0297, 0xffff, 0,
300 "IBM SurePOS 300 Series (481033H) serial ports",
301 DEFAULT_RCLK,
302 PUC_PORT_4S, 0x10, 4, 0
303 },
304
305 /*
306 * SIIG Boards.
307 *
308 * SIIG provides documentation for their boards at:
309 * <URL:http://www.siig.com/downloads.asp>
310 */
311
312 { 0x131f, 0x1010, 0xffff, 0,
313 "SIIG Cyber I/O PCI 16C550 (10x family)",
314 DEFAULT_RCLK,
315 PUC_PORT_1S1P, 0x18, 4, 0,
316 },
317
318 { 0x131f, 0x1011, 0xffff, 0,
319 "SIIG Cyber I/O PCI 16C650 (10x family)",
320 DEFAULT_RCLK,
321 PUC_PORT_1S1P, 0x18, 4, 0,
322 },
323
324 { 0x131f, 0x1012, 0xffff, 0,
325 "SIIG Cyber I/O PCI 16C850 (10x family)",
326 DEFAULT_RCLK,
327 PUC_PORT_1S1P, 0x18, 4, 0,
328 },
329
330 { 0x131f, 0x1021, 0xffff, 0,
331 "SIIG Cyber Parallel Dual PCI (10x family)",
332 0,
333 PUC_PORT_2P, 0x18, 8, 0,
334 },
335
336 { 0x131f, 0x1030, 0xffff, 0,
337 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
338 DEFAULT_RCLK,
339 PUC_PORT_2S, 0x18, 4, 0,
340 },
341
342 { 0x131f, 0x1031, 0xffff, 0,
343 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
344 DEFAULT_RCLK,
345 PUC_PORT_2S, 0x18, 4, 0,
346 },
347
348 { 0x131f, 0x1032, 0xffff, 0,
349 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
350 DEFAULT_RCLK,
351 PUC_PORT_2S, 0x18, 4, 0,
352 },
353
354 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
355 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
356 DEFAULT_RCLK,
357 PUC_PORT_2S1P, 0x18, 4, 0,
358 },
359
360 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
361 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
362 DEFAULT_RCLK,
363 PUC_PORT_2S1P, 0x18, 4, 0,
364 },
365
366 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
367 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
368 DEFAULT_RCLK,
369 PUC_PORT_2S1P, 0x18, 4, 0,
370 },
371
372 { 0x131f, 0x1050, 0xffff, 0,
373 "SIIG Cyber 4S PCI 16C550 (10x family)",
374 DEFAULT_RCLK,
375 PUC_PORT_4S, 0x18, 4, 0,
376 },
377
378 { 0x131f, 0x1051, 0xffff, 0,
379 "SIIG Cyber 4S PCI 16C650 (10x family)",
380 DEFAULT_RCLK,
381 PUC_PORT_4S, 0x18, 4, 0,
382 },
383
384 { 0x131f, 0x1052, 0xffff, 0,
385 "SIIG Cyber 4S PCI 16C850 (10x family)",
386 DEFAULT_RCLK,
387 PUC_PORT_4S, 0x18, 4, 0,
388 },
389
390 { 0x131f, 0x2010, 0xffff, 0,
391 "SIIG Cyber I/O PCI 16C550 (20x family)",
392 DEFAULT_RCLK,
393 PUC_PORT_1S1P, 0x10, 4, 0,
394 },
395
396 { 0x131f, 0x2011, 0xffff, 0,
397 "SIIG Cyber I/O PCI 16C650 (20x family)",
398 DEFAULT_RCLK,
399 PUC_PORT_1S1P, 0x10, 4, 0,
400 },
401
402 { 0x131f, 0x2012, 0xffff, 0,
403 "SIIG Cyber I/O PCI 16C850 (20x family)",
404 DEFAULT_RCLK,
405 PUC_PORT_1S1P, 0x10, 4, 0,
406 },
407
408 { 0x131f, 0x2021, 0xffff, 0,
409 "SIIG Cyber Parallel Dual PCI (20x family)",
410 0,
411 PUC_PORT_2P, 0x10, 8, 0,
412 },
413
414 { 0x131f, 0x2030, 0xffff, 0,
415 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
416 DEFAULT_RCLK,
417 PUC_PORT_2S, 0x10, 4, 0,
418 },
419
420 { 0x131f, 0x2031, 0xffff, 0,
421 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
422 DEFAULT_RCLK,
423 PUC_PORT_2S, 0x10, 4, 0,
424 },
425
426 { 0x131f, 0x2032, 0xffff, 0,
427 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
428 DEFAULT_RCLK,
429 PUC_PORT_2S, 0x10, 4, 0,
430 },
431
432 { 0x131f, 0x2040, 0xffff, 0,
433 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
434 DEFAULT_RCLK,
435 PUC_PORT_1S2P, 0x10, -1, 0,
436 .config_function = puc_config_siig
437 },
438
439 { 0x131f, 0x2041, 0xffff, 0,
440 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
441 DEFAULT_RCLK,
442 PUC_PORT_1S2P, 0x10, -1, 0,
443 .config_function = puc_config_siig
444 },
445
446 { 0x131f, 0x2042, 0xffff, 0,
447 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
448 DEFAULT_RCLK,
449 PUC_PORT_1S2P, 0x10, -1, 0,
450 .config_function = puc_config_siig
451 },
452
453 { 0x131f, 0x2050, 0xffff, 0,
454 "SIIG Cyber 4S PCI 16C550 (20x family)",
455 DEFAULT_RCLK,
456 PUC_PORT_4S, 0x10, 4, 0,
457 },
458
459 { 0x131f, 0x2051, 0xffff, 0,
460 "SIIG Cyber 4S PCI 16C650 (20x family)",
461 DEFAULT_RCLK,
462 PUC_PORT_4S, 0x10, 4, 0,
463 },
464
465 { 0x131f, 0x2052, 0xffff, 0,
466 "SIIG Cyber 4S PCI 16C850 (20x family)",
467 DEFAULT_RCLK,
468 PUC_PORT_4S, 0x10, 4, 0,
469 },
470
471 { 0x131f, 0x2060, 0xffff, 0,
472 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
473 DEFAULT_RCLK,
474 PUC_PORT_2S1P, 0x10, 4, 0,
475 },
476
477 { 0x131f, 0x2061, 0xffff, 0,
478 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
479 DEFAULT_RCLK,
480 PUC_PORT_2S1P, 0x10, 4, 0,
481 },
482
483 { 0x131f, 0x2062, 0xffff, 0,
484 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
485 DEFAULT_RCLK,
486 PUC_PORT_2S1P, 0x10, 4, 0,
487 },
488
489 { 0x131f, 0x2081, 0xffff, 0,
490 "SIIG PS8000 8S PCI 16C650 (20x family)",
491 DEFAULT_RCLK,
492 PUC_PORT_8S, 0x10, -1, -1,
493 .config_function = puc_config_siig
494 },
495
496 { 0x135a, 0x0841, 0xffff, 0,
497 "Brainboxes UC-268",
498 DEFAULT_RCLK,
499 PUC_PORT_4S, 0x18, 0, 8,
500 },
501
502 { 0x135a, 0x0861, 0xffff, 0,
503 "Brainboxes UC-257",
504 DEFAULT_RCLK,
505 PUC_PORT_2S, 0x18, 0, 8,
506 },
507
508 { 0x135a, 0x0862, 0xffff, 0,
509 "Brainboxes UC-257",
510 DEFAULT_RCLK,
511 PUC_PORT_2S, 0x18, 0, 8,
512 },
513
514 { 0x135a, 0x0863, 0xffff, 0,
515 "Brainboxes UC-257",
516 DEFAULT_RCLK,
517 PUC_PORT_2S, 0x18, 0, 8,
518 },
519
520 { 0x135a, 0x0881, 0xffff, 0,
521 "Brainboxes UC-279",
522 DEFAULT_RCLK,
523 PUC_PORT_8S, 0x18, 0, 8,
524 },
525
526 { 0x135a, 0x08a1, 0xffff, 0,
527 "Brainboxes UC-313",
528 DEFAULT_RCLK,
529 PUC_PORT_2S, 0x18, 0, 8,
530 },
531
532 { 0x135a, 0x08a2, 0xffff, 0,
533 "Brainboxes UC-313",
534 DEFAULT_RCLK,
535 PUC_PORT_2S, 0x18, 0, 8,
536 },
537
538 { 0x135a, 0x08a3, 0xffff, 0,
539 "Brainboxes UC-313",
540 DEFAULT_RCLK,
541 PUC_PORT_2S, 0x18, 0, 8,
542 },
543
544 { 0x135a, 0x08c1, 0xffff, 0,
545 "Brainboxes UC-310",
546 DEFAULT_RCLK,
547 PUC_PORT_2S, 0x18, 0, 8,
548 },
549
550 { 0x135a, 0x08e1, 0xffff, 0,
551 "Brainboxes UC-302",
552 DEFAULT_RCLK,
553 PUC_PORT_2S, 0x18, 0, 8,
554 },
555
556 { 0x135a, 0x08e2, 0xffff, 0,
557 "Brainboxes UC-302",
558 DEFAULT_RCLK,
559 PUC_PORT_2S, 0x18, 0, 8,
560 },
561
562 { 0x135a, 0x08e3, 0xffff, 0,
563 "Brainboxes UC-302",
564 DEFAULT_RCLK,
565 PUC_PORT_2S, 0x18, 0, 8,
566 },
567
568 { 0x135a, 0x0901, 0xffff, 0,
569 "Brainboxes UC-431",
570 DEFAULT_RCLK,
571 PUC_PORT_3S, 0x18, 0, 8,
572 },
573
574 { 0x135a, 0x0921, 0xffff, 0,
575 "Brainboxes UC-420",
576 DEFAULT_RCLK,
577 PUC_PORT_4S, 0x18, 0, 8,
578 },
579
580 { 0x135a, 0x0981, 0xffff, 0,
581 "Brainboxes UC-475",
582 DEFAULT_RCLK,
583 PUC_PORT_2S, 0x18, 0, 8,
584 },
585
586 { 0x135a, 0x0982, 0xffff, 0,
587 "Brainboxes UC-475",
588 DEFAULT_RCLK,
589 PUC_PORT_2S, 0x18, 0, 8,
590 },
591
592 { 0x135a, 0x09a1, 0xffff, 0,
593 "Brainboxes UC-607",
594 DEFAULT_RCLK,
595 PUC_PORT_2S, 0x18, 0, 8,
596 },
597
598 { 0x135a, 0x09a2, 0xffff, 0,
599 "Brainboxes UC-607",
600 DEFAULT_RCLK,
601 PUC_PORT_2S, 0x18, 0, 8,
602 },
603
604 { 0x135a, 0x09a3, 0xffff, 0,
605 "Brainboxes UC-607",
606 DEFAULT_RCLK,
607 PUC_PORT_2S, 0x18, 0, 8,
608 },
609
610 { 0x135a, 0x0a81, 0xffff, 0,
611 "Brainboxes UC-357",
612 DEFAULT_RCLK,
613 PUC_PORT_2S, 0x18, 0, 8,
614 },
615
616 { 0x135a, 0x0a82, 0xffff, 0,
617 "Brainboxes UC-357",
618 DEFAULT_RCLK,
619 PUC_PORT_2S, 0x18, 0, 8,
620 },
621
622 { 0x135a, 0x0a83, 0xffff, 0,
623 "Brainboxes UC-357",
624 DEFAULT_RCLK,
625 PUC_PORT_2S, 0x18, 0, 8,
626 },
627
628 { 0x135a, 0x0ac1, 0xffff, 0,
629 "Brainboxes UP-189",
630 DEFAULT_RCLK,
631 PUC_PORT_2S, 0x18, 0, 8,
632 },
633
634 { 0x135a, 0x0ac2, 0xffff, 0,
635 "Brainboxes UP-189",
636 DEFAULT_RCLK,
637 PUC_PORT_2S, 0x18, 0, 8,
638 },
639
640 { 0x135a, 0x0ac3, 0xffff, 0,
641 "Brainboxes UP-189",
642 DEFAULT_RCLK,
643 PUC_PORT_2S, 0x18, 0, 8,
644 },
645
646 { 0x135a, 0x0b01, 0xffff, 0,
647 "Brainboxes UC-346",
648 DEFAULT_RCLK,
649 PUC_PORT_4S, 0x18, 0, 8,
650 },
651
652 { 0x135a, 0x0b02, 0xffff, 0,
653 "Brainboxes UC-346",
654 DEFAULT_RCLK,
655 PUC_PORT_4S, 0x18, 0, 8,
656 },
657
658 { 0x135a, 0x0b21, 0xffff, 0,
659 "Brainboxes UP-200",
660 DEFAULT_RCLK,
661 PUC_PORT_2S, 0x18, 0, 8,
662 },
663
664 { 0x135a, 0x0b22, 0xffff, 0,
665 "Brainboxes UP-200",
666 DEFAULT_RCLK,
667 PUC_PORT_2S, 0x18, 0, 8,
668 },
669
670 { 0x135a, 0x0b23, 0xffff, 0,
671 "Brainboxes UP-200",
672 DEFAULT_RCLK,
673 PUC_PORT_2S, 0x18, 0, 8,
674 },
675
676 { 0x135a, 0x0ba1, 0xffff, 0,
677 "Brainboxes UC-101",
678 DEFAULT_RCLK,
679 PUC_PORT_2S, 0x18, 0, 8,
680 },
681
682 { 0x135a, 0x0bc1, 0xffff, 0,
683 "Brainboxes UC-203",
684 DEFAULT_RCLK,
685 PUC_PORT_2S, 0x18, 0, 8,
686 },
687
688 { 0x135a, 0x0bc2, 0xffff, 0,
689 "Brainboxes UC-203",
690 DEFAULT_RCLK,
691 PUC_PORT_2S, 0x18, 0, 8,
692 },
693
694 { 0x135a, 0x0c01, 0xffff, 0,
695 "Brainboxes UP-869",
696 DEFAULT_RCLK,
697 PUC_PORT_2S, 0x18, 0, 8,
698 },
699
700 { 0x135a, 0x0c02, 0xffff, 0,
701 "Brainboxes UP-869",
702 DEFAULT_RCLK,
703 PUC_PORT_2S, 0x18, 0, 8,
704 },
705
706 { 0x135a, 0x0c03, 0xffff, 0,
707 "Brainboxes UP-869",
708 DEFAULT_RCLK,
709 PUC_PORT_2S, 0x18, 0, 8,
710 },
711
712 { 0x135a, 0x0c21, 0xffff, 0,
713 "Brainboxes UP-880",
714 DEFAULT_RCLK,
715 PUC_PORT_2S, 0x18, 0, 8,
716 },
717
718 { 0x135a, 0x0c22, 0xffff, 0,
719 "Brainboxes UP-880",
720 DEFAULT_RCLK,
721 PUC_PORT_2S, 0x18, 0, 8,
722 },
723
724 { 0x135a, 0x0c23, 0xffff, 0,
725 "Brainboxes UP-880",
726 DEFAULT_RCLK,
727 PUC_PORT_2S, 0x18, 0, 8,
728 },
729
730 { 0x135a, 0x0c41, 0xffff, 0,
731 "Brainboxes UC-368",
732 DEFAULT_RCLK,
733 PUC_PORT_4S, 0x18, 0, 8,
734 },
735
736 { 0x135a, 0x0ca1, 0xffff, 0,
737 "Brainboxes UC-253",
738 DEFAULT_RCLK,
739 PUC_PORT_2S, 0x18, 0, 8,
740 },
741
742 { 0x135a, 0x0d21, 0xffff, 0,
743 "Brainboxes UC-260",
744 DEFAULT_RCLK,
745 PUC_PORT_4S, 0x18, 0, 8,
746 },
747
748 { 0x135a, 0x0d41, 0xffff, 0,
749 "Brainboxes UC-836",
750 DEFAULT_RCLK,
751 PUC_PORT_4S, 0x18, 0, 8,
752 },
753
754 { 0x135a, 0x0d80, 0xffff, 0,
755 "Intashield IS-200",
756 DEFAULT_RCLK,
757 PUC_PORT_2S, 0x18, 0, 8,
758 },
759
760 { 0x135a, 0x0dc0, 0xffff, 0,
761 "Intashield IS-400",
762 DEFAULT_RCLK,
763 PUC_PORT_4S, 0x18, 0, 8,
764 },
765
766 { 0x135a, 0x0e41, 0xffff, 0,
767 "Brainboxes PX-279",
768 DEFAULT_RCLK,
769 PUC_PORT_8S, 0x18, 0, 8,
770 },
771
772 { 0x135a, 0x0e61, 0xffff, 0,
773 "Brainboxes UC-414",
774 DEFAULT_RCLK,
775 PUC_PORT_4S, 0x18, 0, 8,
776 },
777
778 { 0x135a, 0x400a, 0xffff, 0,
779 "Brainboxes PX-260",
780 DEFAULT_RCLK * 0x22,
781 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
782 .config_function = puc_config_oxford_pcie
783 },
784
785 { 0x135a, 0x400b, 0xffff, 0,
786 "Brainboxes PX-320",
787 DEFAULT_RCLK * 0x22,
788 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
789 .config_function = puc_config_oxford_pcie
790 },
791
792 { 0x135a, 0x400c, 0xffff, 0,
793 "Brainboxes PX-313",
794 DEFAULT_RCLK * 0x22,
795 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
796 .config_function = puc_config_oxford_pcie
797 },
798
799 { 0x135a, 0x400e, 0xffff, 0,
800 "Brainboxes PX-310",
801 DEFAULT_RCLK * 0x22,
802 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
803 .config_function = puc_config_oxford_pcie
804 },
805
806 { 0x135a, 0x400f, 0xffff, 0,
807 "Brainboxes PX-346",
808 DEFAULT_RCLK * 0x22,
809 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
810 .config_function = puc_config_oxford_pcie
811 },
812
813 { 0x135a, 0x4010, 0xffff, 0,
814 "Brainboxes PX-368",
815 DEFAULT_RCLK * 0x22,
816 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
817 .config_function = puc_config_oxford_pcie
818 },
819
820 { 0x135a, 0x4011, 0xffff, 0,
821 "Brainboxes PX-420",
822 DEFAULT_RCLK * 0x22,
823 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
824 .config_function = puc_config_oxford_pcie
825 },
826
827 { 0x135a, 0x4012, 0xffff, 0,
828 "Brainboxes PX-431",
829 DEFAULT_RCLK * 0x22,
830 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
831 .config_function = puc_config_oxford_pcie
832 },
833
834 { 0x135a, 0x4013, 0xffff, 0,
835 "Brainboxes PX-820",
836 DEFAULT_RCLK * 0x22,
837 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
838 .config_function = puc_config_oxford_pcie
839 },
840
841 { 0x135a, 0x4014, 0xffff, 0,
842 "Brainboxes PX-831",
843 DEFAULT_RCLK * 0x22,
844 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
845 .config_function = puc_config_oxford_pcie
846 },
847
848 { 0x135a, 0x4015, 0xffff, 0,
849 "Brainboxes PX-257",
850 DEFAULT_RCLK * 0x22,
851 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
852 .config_function = puc_config_oxford_pcie
853 },
854
855 { 0x135a, 0x4016, 0xffff, 0,
856 "Brainboxes PX-246",
857 DEFAULT_RCLK * 0x22,
858 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
859 .config_function = puc_config_oxford_pcie
860 },
861
862 { 0x135a, 0x4017, 0xffff, 0,
863 "Brainboxes PX-846",
864 DEFAULT_RCLK * 0x22,
865 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
866 .config_function = puc_config_oxford_pcie
867 },
868
869 { 0x135a, 0x4018, 0xffff, 0,
870 "Brainboxes PX-857",
871 DEFAULT_RCLK * 0x22,
872 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
873 .config_function = puc_config_oxford_pcie
874 },
875
876 { 0x135a, 0x4019, 0xffff, 0,
877 "Brainboxes PX-101",
878 DEFAULT_RCLK * 0x22,
879 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
880 .config_function = puc_config_oxford_pcie
881 },
882
883 { 0x135a, 0x401d, 0xffff, 0,
884 "Brainboxes PX-475",
885 DEFAULT_RCLK * 0x22,
886 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
887 .config_function = puc_config_oxford_pcie
888 },
889
890 { 0x135a, 0x401e, 0xffff, 0,
891 "Brainboxes PX-803",
892 DEFAULT_RCLK * 0x22,
893 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
894 .config_function = puc_config_oxford_pcie
895 },
896
897 { 0x135a, 0x4027, 0xffff, 0,
898 "Intashield IX-100",
899 DEFAULT_RCLK * 0x22,
900 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
901 .config_function = puc_config_oxford_pcie
902 },
903
904 { 0x135a, 0x4028, 0xffff, 0,
905 "Intashield IX-200",
906 DEFAULT_RCLK * 0x22,
907 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
908 .config_function = puc_config_oxford_pcie
909 },
910
911 { 0x135a, 0x4029, 0xffff, 0,
912 "Intashield IX-400",
913 DEFAULT_RCLK * 0x22,
914 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
915 .config_function = puc_config_oxford_pcie
916 },
917
918 { 0x135c, 0x0010, 0xffff, 0,
919 "Quatech QSC-100",
920 -3, /* max 8x clock rate */
921 PUC_PORT_4S, 0x14, 0, 8,
922 .config_function = puc_config_quatech
923 },
924
925 { 0x135c, 0x0020, 0xffff, 0,
926 "Quatech DSC-100",
927 -1, /* max 2x clock rate */
928 PUC_PORT_2S, 0x14, 0, 8,
929 .config_function = puc_config_quatech
930 },
931
932 { 0x135c, 0x0030, 0xffff, 0,
933 "Quatech DSC-200/300",
934 -1, /* max 2x clock rate */
935 PUC_PORT_2S, 0x14, 0, 8,
936 .config_function = puc_config_quatech
937 },
938
939 { 0x135c, 0x0040, 0xffff, 0,
940 "Quatech QSC-200/300",
941 -3, /* max 8x clock rate */
942 PUC_PORT_4S, 0x14, 0, 8,
943 .config_function = puc_config_quatech
944 },
945
946 { 0x135c, 0x0050, 0xffff, 0,
947 "Quatech ESC-100D",
948 -3, /* max 8x clock rate */
949 PUC_PORT_8S, 0x14, 0, 8,
950 .config_function = puc_config_quatech
951 },
952
953 { 0x135c, 0x0060, 0xffff, 0,
954 "Quatech ESC-100M",
955 -3, /* max 8x clock rate */
956 PUC_PORT_8S, 0x14, 0, 8,
957 .config_function = puc_config_quatech
958 },
959
960 { 0x135c, 0x0170, 0xffff, 0,
961 "Quatech QSCLP-100",
962 -1, /* max 2x clock rate */
963 PUC_PORT_4S, 0x18, 0, 8,
964 .config_function = puc_config_quatech
965 },
966
967 { 0x135c, 0x0180, 0xffff, 0,
968 "Quatech DSCLP-100",
969 -1, /* max 3x clock rate */
970 PUC_PORT_2S, 0x18, 0, 8,
971 .config_function = puc_config_quatech
972 },
973
974 { 0x135c, 0x01b0, 0xffff, 0,
975 "Quatech DSCLP-200/300",
976 -1, /* max 2x clock rate */
977 PUC_PORT_2S, 0x18, 0, 8,
978 .config_function = puc_config_quatech
979 },
980
981 { 0x135c, 0x01e0, 0xffff, 0,
982 "Quatech ESCLP-100",
983 -3, /* max 8x clock rate */
984 PUC_PORT_8S, 0x10, 0, 8,
985 .config_function = puc_config_quatech
986 },
987
988 { 0x1393, 0x1024, 0xffff, 0,
989 "Moxa Technologies, Smartio CP-102E/PCIe",
990 DEFAULT_RCLK * 8,
991 PUC_PORT_2S, 0x14, 0, -1,
992 .config_function = puc_config_moxa
993 },
994
995 { 0x1393, 0x1025, 0xffff, 0,
996 "Moxa Technologies, Smartio CP-102EL/PCIe",
997 DEFAULT_RCLK * 8,
998 PUC_PORT_2S, 0x14, 0, -1,
999 .config_function = puc_config_moxa
1000 },
1001
1002 { 0x1393, 0x1040, 0xffff, 0,
1003 "Moxa Technologies, Smartio C104H/PCI",
1004 DEFAULT_RCLK * 8,
1005 PUC_PORT_4S, 0x18, 0, 8,
1006 },
1007
1008 { 0x1393, 0x1041, 0xffff, 0,
1009 "Moxa Technologies, Smartio CP-104UL/PCI",
1010 DEFAULT_RCLK * 8,
1011 PUC_PORT_4S, 0x18, 0, 8,
1012 },
1013
1014 { 0x1393, 0x1042, 0xffff, 0,
1015 "Moxa Technologies, Smartio CP-104JU/PCI",
1016 DEFAULT_RCLK * 8,
1017 PUC_PORT_4S, 0x18, 0, 8,
1018 },
1019
1020 { 0x1393, 0x1043, 0xffff, 0,
1021 "Moxa Technologies, Smartio CP-104EL/PCIe",
1022 DEFAULT_RCLK * 8,
1023 PUC_PORT_4S, 0x18, 0, 8,
1024 },
1025
1026 { 0x1393, 0x1045, 0xffff, 0,
1027 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
1028 DEFAULT_RCLK * 8,
1029 PUC_PORT_4S, 0x14, 0, -1,
1030 .config_function = puc_config_moxa
1031 },
1032
1033 { 0x1393, 0x1120, 0xffff, 0,
1034 "Moxa Technologies, CP-112UL",
1035 DEFAULT_RCLK * 8,
1036 PUC_PORT_2S, 0x18, 0, 8,
1037 },
1038
1039 { 0x1393, 0x1141, 0xffff, 0,
1040 "Moxa Technologies, Industio CP-114",
1041 DEFAULT_RCLK * 8,
1042 PUC_PORT_4S, 0x18, 0, 8,
1043 },
1044
1045 { 0x1393, 0x1144, 0xffff, 0,
1046 "Moxa Technologies, Smartio CP-114EL/PCIe",
1047 DEFAULT_RCLK * 8,
1048 PUC_PORT_4S, 0x14, 0, -1,
1049 .config_function = puc_config_moxa
1050 },
1051
1052 { 0x1393, 0x1182, 0xffff, 0,
1053 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
1054 DEFAULT_RCLK * 8,
1055 PUC_PORT_8S, 0x14, 0, -1,
1056 .config_function = puc_config_moxa
1057 },
1058
1059 { 0x1393, 0x1680, 0xffff, 0,
1060 "Moxa Technologies, C168H/PCI",
1061 DEFAULT_RCLK * 8,
1062 PUC_PORT_8S, 0x18, 0, 8,
1063 },
1064
1065 { 0x1393, 0x1681, 0xffff, 0,
1066 "Moxa Technologies, C168U/PCI",
1067 DEFAULT_RCLK * 8,
1068 PUC_PORT_8S, 0x18, 0, 8,
1069 },
1070
1071 { 0x1393, 0x1682, 0xffff, 0,
1072 "Moxa Technologies, CP-168EL/PCIe",
1073 DEFAULT_RCLK * 8,
1074 PUC_PORT_8S, 0x18, 0, 8,
1075 },
1076
1077 { 0x1393, 0x1683, 0xffff, 0,
1078 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
1079 DEFAULT_RCLK * 8,
1080 PUC_PORT_8S, 0x14, 0, -1,
1081 .config_function = puc_config_moxa
1082 },
1083
1084 { 0x13a8, 0x0152, 0xffff, 0,
1085 "Exar XR17C/D152",
1086 DEFAULT_RCLK * 8,
1087 PUC_PORT_2S, 0x10, 0, -1,
1088 .config_function = puc_config_exar
1089 },
1090
1091 { 0x13a8, 0x0154, 0xffff, 0,
1092 "Exar XR17C154",
1093 DEFAULT_RCLK * 8,
1094 PUC_PORT_4S, 0x10, 0, -1,
1095 .config_function = puc_config_exar
1096 },
1097
1098 { 0x13a8, 0x0158, 0xffff, 0,
1099 "Exar XR17C158",
1100 DEFAULT_RCLK * 8,
1101 PUC_PORT_8S, 0x10, 0, -1,
1102 .config_function = puc_config_exar
1103 },
1104
1105 { 0x13a8, 0x0258, 0xffff, 0,
1106 "Exar XR17V258IV",
1107 DEFAULT_RCLK * 8,
1108 PUC_PORT_8S, 0x10, 0, -1,
1109 .config_function = puc_config_exar
1110 },
1111
1112 { 0x13a8, 0x0352, 0xffff, 0,
1113 "Exar XR17V352",
1114 125000000,
1115 PUC_PORT_2S, 0x10, 0, -1,
1116 .config_function = puc_config_exar_pcie
1117 },
1118
1119 { 0x13a8, 0x0354, 0xffff, 0,
1120 "Exar XR17V354",
1121 125000000,
1122 PUC_PORT_4S, 0x10, 0, -1,
1123 .config_function = puc_config_exar_pcie
1124 },
1125
1126 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
1127 { 0x13a8, 0x0358, 0xffff, 0,
1128 "Exar XR17V358",
1129 125000000,
1130 PUC_PORT_8S, 0x10, 0, -1,
1131 .config_function = puc_config_exar_pcie
1132 },
1133
1134 /*
1135 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford
1136 * Semiconductor OXuPCI954. Note these boards have a hardware bug in
1137 * that they drive the RS-422/485 transmitters after power-on until a
1138 * driver initializes the UARTs.
1139 */
1140 { 0x13fe, 0x1600, 0x1602, 0x0002,
1141 "Advantech PCI-1602 Rev. A",
1142 DEFAULT_RCLK * 8,
1143 PUC_PORT_2S, 0x10, 0, 8,
1144 .config_function = puc_config_advantech
1145 },
1146
1147 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */
1148 { 0x13fe, 0xa102, 0x13fe, 0xa102,
1149 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)",
1150 DEFAULT_RCLK * 8,
1151 PUC_PORT_2S, 0x10, 4, 0,
1152 .config_function = puc_config_advantech
1153 },
1154
1155 { 0x1407, 0x0100, 0xffff, 0,
1156 "Lava Computers Dual Serial",
1157 DEFAULT_RCLK,
1158 PUC_PORT_2S, 0x10, 4, 0,
1159 },
1160
1161 { 0x1407, 0x0101, 0xffff, 0,
1162 "Lava Computers Quatro A",
1163 DEFAULT_RCLK,
1164 PUC_PORT_2S, 0x10, 4, 0,
1165 },
1166
1167 { 0x1407, 0x0102, 0xffff, 0,
1168 "Lava Computers Quatro B",
1169 DEFAULT_RCLK,
1170 PUC_PORT_2S, 0x10, 4, 0,
1171 },
1172
1173 { 0x1407, 0x0120, 0xffff, 0,
1174 "Lava Computers Quattro-PCI A",
1175 DEFAULT_RCLK,
1176 PUC_PORT_2S, 0x10, 4, 0,
1177 },
1178
1179 { 0x1407, 0x0121, 0xffff, 0,
1180 "Lava Computers Quattro-PCI B",
1181 DEFAULT_RCLK,
1182 PUC_PORT_2S, 0x10, 4, 0,
1183 },
1184
1185 { 0x1407, 0x0180, 0xffff, 0,
1186 "Lava Computers Octo A",
1187 DEFAULT_RCLK,
1188 PUC_PORT_4S, 0x10, 4, 0,
1189 },
1190
1191 { 0x1407, 0x0181, 0xffff, 0,
1192 "Lava Computers Octo B",
1193 DEFAULT_RCLK,
1194 PUC_PORT_4S, 0x10, 4, 0,
1195 },
1196
1197 { 0x1409, 0x7268, 0xffff, 0,
1198 "Sunix SUN1888",
1199 0,
1200 PUC_PORT_2P, 0x10, 0, 8,
1201 },
1202
1203 { 0x1409, 0x7168, 0xffff, 0,
1204 NULL,
1205 DEFAULT_RCLK * 8,
1206 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
1207 .config_function = puc_config_timedia
1208 },
1209
1210 /*
1211 * Boards with an Oxford Semiconductor chip.
1212 *
1213 * Oxford Semiconductor provides documentation for their chip at:
1214 * <URL:http://www.plxtech.com/products/uart/>
1215 *
1216 * As sold by Kouwell <URL:http://www.kouwell.com/>.
1217 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
1218 */
1219 {
1220 0x1415, 0x9501, 0x10fc, 0xc070,
1221 "I-O DATA RSA-PCI2/R",
1222 DEFAULT_RCLK * 8,
1223 PUC_PORT_2S, 0x10, 0, 8,
1224 },
1225
1226 { 0x1415, 0x9501, 0x131f, 0x2050,
1227 "SIIG Cyber 4 PCI 16550",
1228 DEFAULT_RCLK * 10,
1229 PUC_PORT_4S, 0x10, 0, 8,
1230 },
1231
1232 { 0x1415, 0x9501, 0x131f, 0x2051,
1233 "SIIG Cyber 4S PCI 16C650 (20x family)",
1234 DEFAULT_RCLK * 10,
1235 PUC_PORT_4S, 0x10, 0, 8,
1236 },
1237
1238 { 0x1415, 0x9501, 0x131f, 0x2052,
1239 "SIIG Quartet Serial 850",
1240 DEFAULT_RCLK * 10,
1241 PUC_PORT_4S, 0x10, 0, 8,
1242 },
1243
1244 { 0x1415, 0x9501, 0x14db, 0x2150,
1245 "Kuroutoshikou SERIAL4P-LPPCI2",
1246 DEFAULT_RCLK * 10,
1247 PUC_PORT_4S, 0x10, 0, 8,
1248 },
1249
1250 { 0x1415, 0x9501, 0xffff, 0,
1251 "Oxford Semiconductor OX16PCI954 UARTs",
1252 0,
1253 PUC_PORT_4S, 0x10, 0, 8,
1254 .config_function = puc_config_oxford_pci954
1255 },
1256
1257 { 0x1415, 0x950a, 0x131f, 0x2030,
1258 "SIIG Cyber 2S PCIe",
1259 DEFAULT_RCLK * 10,
1260 PUC_PORT_2S, 0x10, 0, 8,
1261 },
1262
1263 { 0x1415, 0x950a, 0x131f, 0x2032,
1264 "SIIG Cyber Serial Dual PCI 16C850",
1265 DEFAULT_RCLK * 10,
1266 PUC_PORT_4S, 0x10, 0, 8,
1267 },
1268
1269 { 0x1415, 0x950a, 0x131f, 0x2061,
1270 "SIIG Cyber 2SP1 PCIe",
1271 DEFAULT_RCLK * 10,
1272 PUC_PORT_2S, 0x10, 0, 8,
1273 },
1274
1275 { 0x1415, 0x950a, 0xffff, 0,
1276 "Oxford Semiconductor OX16PCI954 UARTs",
1277 DEFAULT_RCLK,
1278 PUC_PORT_4S, 0x10, 0, 8,
1279 },
1280
1281 { 0x1415, 0x9511, 0xffff, 0,
1282 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
1283 DEFAULT_RCLK,
1284 PUC_PORT_4S, 0x10, 0, 8,
1285 },
1286
1287 { 0x1415, 0x9521, 0xffff, 0,
1288 "Oxford Semiconductor OX16PCI952 UARTs",
1289 DEFAULT_RCLK,
1290 PUC_PORT_2S, 0x10, 4, 0,
1291 },
1292
1293 { 0x1415, 0x9538, 0xffff, 0,
1294 "Oxford Semiconductor OX16PCI958 UARTs",
1295 DEFAULT_RCLK,
1296 PUC_PORT_8S, 0x18, 0, 8,
1297 },
1298
1299 /*
1300 * Perle boards use Oxford Semiconductor chips, but they store the
1301 * Oxford Semiconductor device ID as a subvendor device ID and use
1302 * their own device IDs.
1303 */
1304
1305 { 0x155f, 0x0331, 0xffff, 0,
1306 "Perle Ultraport4 Express",
1307 DEFAULT_RCLK * 8,
1308 PUC_PORT_4S, 0x10, 0, 8,
1309 },
1310
1311 { 0x155f, 0xB012, 0xffff, 0,
1312 "Perle Speed2 LE",
1313 DEFAULT_RCLK * 8,
1314 PUC_PORT_2S, 0x10, 0, 8,
1315 },
1316
1317 { 0x155f, 0xB022, 0xffff, 0,
1318 "Perle Speed2 LE",
1319 DEFAULT_RCLK * 8,
1320 PUC_PORT_2S, 0x10, 0, 8,
1321 },
1322
1323 { 0x155f, 0xB004, 0xffff, 0,
1324 "Perle Speed4 LE",
1325 DEFAULT_RCLK * 8,
1326 PUC_PORT_4S, 0x10, 0, 8,
1327 },
1328
1329 { 0x155f, 0xB008, 0xffff, 0,
1330 "Perle Speed8 LE",
1331 DEFAULT_RCLK * 8,
1332 PUC_PORT_8S, 0x10, 0, 8,
1333 },
1334
1335 /*
1336 * Oxford Semiconductor PCI Express Expresso family
1337 *
1338 * Found in many 'native' PCI Express serial boards such as:
1339 *
1340 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
1341 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
1342 *
1343 * Lindy 51189 (4 port)
1344 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
1345 *
1346 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
1347 * <URL:http://www.startech.com>
1348 */
1349
1350 { 0x1415, 0xc11b, 0xffff, 0,
1351 "Oxford Semiconductor OXPCIe952 1S1P",
1352 DEFAULT_RCLK * 0x22,
1353 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1354 .config_function = puc_config_oxford_pcie
1355 },
1356
1357 { 0x1415, 0xc138, 0xffff, 0,
1358 "Oxford Semiconductor OXPCIe952 UARTs",
1359 DEFAULT_RCLK * 0x22,
1360 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1361 .config_function = puc_config_oxford_pcie
1362 },
1363
1364 { 0x1415, 0xc158, 0xffff, 0,
1365 "Oxford Semiconductor OXPCIe952 UARTs",
1366 DEFAULT_RCLK * 0x22,
1367 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1368 .config_function = puc_config_oxford_pcie
1369 },
1370
1371 { 0x1415, 0xc15d, 0xffff, 0,
1372 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
1373 DEFAULT_RCLK * 0x22,
1374 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1375 .config_function = puc_config_oxford_pcie
1376 },
1377
1378 { 0x1415, 0xc208, 0xffff, 0,
1379 "Oxford Semiconductor OXPCIe954 UARTs",
1380 DEFAULT_RCLK * 0x22,
1381 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1382 .config_function = puc_config_oxford_pcie
1383 },
1384
1385 { 0x1415, 0xc20d, 0xffff, 0,
1386 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
1387 DEFAULT_RCLK * 0x22,
1388 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1389 .config_function = puc_config_oxford_pcie
1390 },
1391
1392 { 0x1415, 0xc308, 0xffff, 0,
1393 "Oxford Semiconductor OXPCIe958 UARTs",
1394 DEFAULT_RCLK * 0x22,
1395 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1396 .config_function = puc_config_oxford_pcie
1397 },
1398
1399 { 0x1415, 0xc30d, 0xffff, 0,
1400 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
1401 DEFAULT_RCLK * 0x22,
1402 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1403 .config_function = puc_config_oxford_pcie
1404 },
1405
1406 { 0x14d2, 0x8010, 0xffff, 0,
1407 "VScom PCI-100L",
1408 DEFAULT_RCLK * 8,
1409 PUC_PORT_1S, 0x14, 0, 0,
1410 },
1411
1412 { 0x14d2, 0x8020, 0xffff, 0,
1413 "VScom PCI-200L",
1414 DEFAULT_RCLK * 8,
1415 PUC_PORT_2S, 0x14, 4, 0,
1416 },
1417
1418 { 0x14d2, 0x8028, 0xffff, 0,
1419 "VScom 200Li",
1420 DEFAULT_RCLK,
1421 PUC_PORT_2S, 0x20, 0, 8,
1422 },
1423
1424 /*
1425 * VScom (Titan?) PCI-800L. More modern variant of the
1426 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
1427 * two of them obviously implemented as macro cells in
1428 * the ASIC. This causes the weird port access pattern
1429 * below, where two of the IO port ranges each access
1430 * one of the ASIC UARTs, and a block of IO addresses
1431 * access the external UARTs.
1432 */
1433 { 0x14d2, 0x8080, 0xffff, 0,
1434 "Titan VScom PCI-800L",
1435 DEFAULT_RCLK * 8,
1436 PUC_PORT_8S, 0x14, -1, -1,
1437 .config_function = puc_config_titan
1438 },
1439
1440 /*
1441 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
1442 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1443 * device ID 3 and PCI device 1 device ID 4.
1444 */
1445 { 0x14d2, 0xa003, 0xffff, 0,
1446 "Titan PCI-800H",
1447 DEFAULT_RCLK * 8,
1448 PUC_PORT_4S, 0x10, 0, 8,
1449 },
1450
1451 { 0x14d2, 0xa004, 0xffff, 0,
1452 "Titan PCI-800H",
1453 DEFAULT_RCLK * 8,
1454 PUC_PORT_4S, 0x10, 0, 8,
1455 },
1456
1457 { 0x14d2, 0xa005, 0xffff, 0,
1458 "Titan PCI-200H",
1459 DEFAULT_RCLK * 8,
1460 PUC_PORT_2S, 0x10, 0, 8,
1461 },
1462
1463 { 0x14d2, 0xe020, 0xffff, 0,
1464 "Titan VScom PCI-200HV2",
1465 DEFAULT_RCLK * 8,
1466 PUC_PORT_2S, 0x10, 4, 0,
1467 },
1468
1469 { 0x14d2, 0xa007, 0xffff, 0,
1470 "Titan VScom PCIex-800H",
1471 DEFAULT_RCLK * 8,
1472 PUC_PORT_4S, 0x10, 0, 8,
1473 },
1474
1475 { 0x14d2, 0xa008, 0xffff, 0,
1476 "Titan VScom PCIex-800H",
1477 DEFAULT_RCLK * 8,
1478 PUC_PORT_4S, 0x10, 0, 8,
1479 },
1480
1481 { 0x14db, 0x2130, 0xffff, 0,
1482 "Avlab Technology, PCI IO 2S",
1483 DEFAULT_RCLK,
1484 PUC_PORT_2S, 0x10, 4, 0,
1485 },
1486
1487 { 0x14db, 0x2150, 0xffff, 0,
1488 "Avlab Low Profile PCI 4 Serial",
1489 DEFAULT_RCLK,
1490 PUC_PORT_4S, 0x10, 4, 0,
1491 },
1492
1493 { 0x14db, 0x2152, 0xffff, 0,
1494 "Avlab Low Profile PCI 4 Serial",
1495 DEFAULT_RCLK,
1496 PUC_PORT_4S, 0x10, 4, 0,
1497 },
1498
1499 { 0x1592, 0x0781, 0xffff, 0,
1500 "Syba Tech Ltd. PCI-4S2P-550-ECP",
1501 DEFAULT_RCLK,
1502 PUC_PORT_4S1P, 0x10, 0, -1,
1503 .config_function = puc_config_syba
1504 },
1505
1506 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
1507 "Sunix SER5xxxx 2-port serial",
1508 DEFAULT_RCLK * 8,
1509 PUC_PORT_2S, 0x10, 0, 8,
1510 },
1511
1512 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1513 "Sunix SER5xxxx 4-port serial",
1514 DEFAULT_RCLK * 8,
1515 PUC_PORT_4S, 0x10, 0, 8,
1516 },
1517
1518 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1519 "Sunix SER5xxxx 8-port serial",
1520 DEFAULT_RCLK * 8,
1521 PUC_PORT_8S, -1, -1, -1,
1522 .config_function = puc_config_sunix
1523 },
1524
1525 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1526 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1527 DEFAULT_RCLK * 8,
1528 PUC_PORT_1S1P, -1, -1, -1,
1529 .config_function = puc_config_sunix
1530 },
1531
1532 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1533 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1534 DEFAULT_RCLK * 8,
1535 PUC_PORT_2S1P, -1, -1, -1,
1536 .config_function = puc_config_sunix
1537 },
1538
1539 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1540 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1541 DEFAULT_RCLK * 8,
1542 PUC_PORT_4S1P, -1, -1, -1,
1543 .config_function = puc_config_sunix
1544 },
1545
1546 { 0x5372, 0x6872, 0xffff, 0,
1547 "Feasso PCI FPP-02 2S1P",
1548 DEFAULT_RCLK,
1549 PUC_PORT_2S1P, 0x10, 4, 0,
1550 },
1551
1552 { 0x5372, 0x6873, 0xffff, 0,
1553 "Sun 1040 PCI Quad Serial",
1554 DEFAULT_RCLK,
1555 PUC_PORT_4S, 0x10, 4, 0,
1556 },
1557
1558 { 0x6666, 0x0001, 0xffff, 0,
1559 "Decision Computer Inc, PCCOM 4-port serial",
1560 DEFAULT_RCLK,
1561 PUC_PORT_4S, 0x1c, 0, 8,
1562 },
1563
1564 { 0x6666, 0x0002, 0xffff, 0,
1565 "Decision Computer Inc, PCCOM 8-port serial",
1566 DEFAULT_RCLK,
1567 PUC_PORT_8S, 0x1c, 0, 8,
1568 },
1569
1570 { 0x6666, 0x0004, 0xffff, 0,
1571 "PCCOM dual port RS232/422/485",
1572 DEFAULT_RCLK,
1573 PUC_PORT_2S, 0x1c, 0, 8,
1574 },
1575
1576 { 0x9710, 0x9815, 0xffff, 0,
1577 "NetMos NM9815 Dual 1284 Printer port",
1578 0,
1579 PUC_PORT_2P, 0x10, 8, 0,
1580 },
1581
1582 /*
1583 * This is more specific than the generic NM9835 entry, and is placed
1584 * here to _prevent_ puc(4) from claiming this single port card.
1585 *
1586 * uart(4) will claim this device.
1587 */
1588 { 0x9710, 0x9835, 0x1000, 1,
1589 "NetMos NM9835 based 1-port serial",
1590 DEFAULT_RCLK,
1591 PUC_PORT_1S, 0x10, 4, 0,
1592 },
1593
1594 { 0x9710, 0x9835, 0x1000, 2,
1595 "NetMos NM9835 based 2-port serial",
1596 DEFAULT_RCLK,
1597 PUC_PORT_2S, 0x10, 4, 0,
1598 },
1599
1600 { 0x9710, 0x9835, 0xffff, 0,
1601 "NetMos NM9835 Dual UART and 1284 Printer port",
1602 DEFAULT_RCLK,
1603 PUC_PORT_2S1P, 0x10, 4, 0,
1604 },
1605
1606 { 0x9710, 0x9845, 0x1000, 0x0006,
1607 "NetMos NM9845 6 Port UART",
1608 DEFAULT_RCLK,
1609 PUC_PORT_6S, 0x10, 4, 0,
1610 },
1611
1612 { 0x9710, 0x9845, 0xffff, 0,
1613 "NetMos NM9845 Quad UART and 1284 Printer port",
1614 DEFAULT_RCLK,
1615 PUC_PORT_4S1P, 0x10, 4, 0,
1616 },
1617
1618 { 0x9710, 0x9865, 0xa000, 0x3002,
1619 "NetMos NM9865 Dual UART",
1620 DEFAULT_RCLK,
1621 PUC_PORT_2S, 0x10, 4, 0,
1622 },
1623
1624 { 0x9710, 0x9865, 0xa000, 0x3003,
1625 "NetMos NM9865 Triple UART",
1626 DEFAULT_RCLK,
1627 PUC_PORT_3S, 0x10, 4, 0,
1628 },
1629
1630 { 0x9710, 0x9865, 0xa000, 0x3004,
1631 "NetMos NM9865 Quad UART",
1632 DEFAULT_RCLK,
1633 PUC_PORT_4S, 0x10, 4, 0,
1634 },
1635
1636 { 0x9710, 0x9865, 0xa000, 0x3011,
1637 "NetMos NM9865 Single UART and 1284 Printer port",
1638 DEFAULT_RCLK,
1639 PUC_PORT_1S1P, 0x10, 4, 0,
1640 },
1641
1642 { 0x9710, 0x9865, 0xa000, 0x3012,
1643 "NetMos NM9865 Dual UART and 1284 Printer port",
1644 DEFAULT_RCLK,
1645 PUC_PORT_2S1P, 0x10, 4, 0,
1646 },
1647
1648 { 0x9710, 0x9865, 0xa000, 0x3020,
1649 "NetMos NM9865 Dual 1284 Printer port",
1650 DEFAULT_RCLK,
1651 PUC_PORT_2P, 0x10, 4, 0,
1652 },
1653
1654 { 0xb00c, 0x021c, 0xffff, 0,
1655 "IC Book Labs Gunboat x4 Lite",
1656 DEFAULT_RCLK,
1657 PUC_PORT_4S, 0x10, 0, 8,
1658 .config_function = puc_config_icbook
1659 },
1660
1661 { 0xb00c, 0x031c, 0xffff, 0,
1662 "IC Book Labs Gunboat x4 Pro",
1663 DEFAULT_RCLK,
1664 PUC_PORT_4S, 0x10, 0, 8,
1665 .config_function = puc_config_icbook
1666 },
1667
1668 { 0xb00c, 0x041c, 0xffff, 0,
1669 "IC Book Labs Ironclad x8 Lite",
1670 DEFAULT_RCLK,
1671 PUC_PORT_8S, 0x10, 0, 8,
1672 .config_function = puc_config_icbook
1673 },
1674
1675 { 0xb00c, 0x051c, 0xffff, 0,
1676 "IC Book Labs Ironclad x8 Pro",
1677 DEFAULT_RCLK,
1678 PUC_PORT_8S, 0x10, 0, 8,
1679 .config_function = puc_config_icbook
1680 },
1681
1682 { 0xb00c, 0x081c, 0xffff, 0,
1683 "IC Book Labs Dreadnought x16 Pro",
1684 DEFAULT_RCLK * 8,
1685 PUC_PORT_16S, 0x10, 0, 8,
1686 .config_function = puc_config_icbook
1687 },
1688
1689 { 0xb00c, 0x091c, 0xffff, 0,
1690 "IC Book Labs Dreadnought x16 Lite",
1691 DEFAULT_RCLK,
1692 PUC_PORT_16S, 0x10, 0, 8,
1693 .config_function = puc_config_icbook
1694 },
1695
1696 { 0xb00c, 0x0a1c, 0xffff, 0,
1697 "IC Book Labs Gunboat x2 Low Profile",
1698 DEFAULT_RCLK,
1699 PUC_PORT_2S, 0x10, 0, 8,
1700 },
1701
1702 { 0xb00c, 0x0b1c, 0xffff, 0,
1703 "IC Book Labs Gunboat x4 Low Profile",
1704 DEFAULT_RCLK,
1705 PUC_PORT_4S, 0x10, 0, 8,
1706 .config_function = puc_config_icbook
1707 },
1708 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1709 };
1710
1711 static int
puc_config_advantech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res __unused)1712 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1713 intptr_t *res __unused)
1714 {
1715 const struct puc_cfg *cfg;
1716 struct resource *cres;
1717 struct puc_bar *bar;
1718 device_t cdev, dev;
1719 bus_size_t off;
1720 int base, crtype, fixed, high, i, oxpcie;
1721 uint8_t acr, func, mask;
1722
1723 if (cmd != PUC_CFG_SETUP)
1724 return (ENXIO);
1725
1726 base = fixed = oxpcie = 0;
1727 crtype = SYS_RES_IOPORT;
1728 acr = mask = 0x0;
1729 func = high = 1;
1730 off = 0x60;
1731
1732 cfg = sc->sc_cfg;
1733 switch (cfg->subvendor) {
1734 case 0x13fe:
1735 switch (cfg->device) {
1736 case 0xa102:
1737 high = 0;
1738 break;
1739 default:
1740 break;
1741 }
1742 default:
1743 break;
1744 }
1745 if (fixed == 1)
1746 goto setup;
1747
1748 dev = sc->sc_dev;
1749 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1750 pci_get_slot(dev), func);
1751 if (cdev == NULL) {
1752 device_printf(dev, "could not find config function\n");
1753 return (ENXIO);
1754 }
1755
1756 i = PCIR_BAR(0);
1757 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE);
1758 if (cres == NULL) {
1759 device_printf(dev, "could not allocate config resource\n");
1760 return (ENXIO);
1761 }
1762
1763 if (oxpcie == 0) {
1764 mask = bus_read_1(cres, off);
1765 if (pci_get_function(dev) == 1)
1766 base = 4;
1767 }
1768
1769 setup:
1770 for (i = 0; i < sc->sc_nports; ++i) {
1771 device_printf(dev, "port %d: ", i);
1772 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid);
1773 if (bar == NULL) {
1774 printf("could not get BAR\n");
1775 continue;
1776 }
1777
1778 if (fixed == 0) {
1779 if ((mask & (1 << (base + i))) == 0) {
1780 acr = 0;
1781 printf("RS-232\n");
1782 } else {
1783 acr = (high == 1 ? 0x18 : 0x10);
1784 printf("RS-422/RS-485, active-%s auto-DTR\n",
1785 high == 1 ? "high" : "low");
1786 }
1787 }
1788
1789 bus_write_1(bar->b_res, REG_SPR, REG_ACR);
1790 bus_write_1(bar->b_res, REG_ICR, acr);
1791 }
1792
1793 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres);
1794 return (0);
1795 }
1796
1797 static int
puc_config_amc(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1798 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port,
1799 intptr_t *res)
1800 {
1801
1802 switch (cmd) {
1803 case PUC_CFG_GET_OFS:
1804 *res = 8 * (port & 1);
1805 return (0);
1806 case PUC_CFG_GET_RID:
1807 *res = 0x14 + (port >> 1) * 4;
1808 return (0);
1809 default:
1810 break;
1811 }
1812 return (ENXIO);
1813 }
1814
1815 static int
puc_config_diva(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1816 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1817 intptr_t *res)
1818 {
1819 const struct puc_cfg *cfg = sc->sc_cfg;
1820
1821 if (cmd == PUC_CFG_GET_OFS) {
1822 if (cfg->subdevice == 0x1282) /* Everest SP */
1823 port <<= 1;
1824 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1825 port = (port == 3) ? 4 : port;
1826 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1827 return (0);
1828 }
1829 return (ENXIO);
1830 }
1831
1832 static int
puc_config_exar(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1833 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1834 int port, intptr_t *res)
1835 {
1836
1837 if (cmd == PUC_CFG_GET_OFS) {
1838 *res = port * 0x200;
1839 return (0);
1840 }
1841 return (ENXIO);
1842 }
1843
1844 static int
puc_config_exar_pcie(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1845 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1846 int port, intptr_t *res)
1847 {
1848
1849 if (cmd == PUC_CFG_GET_OFS) {
1850 *res = port * 0x400;
1851 return (0);
1852 }
1853 return (ENXIO);
1854 }
1855
1856 static int
puc_config_icbook(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1857 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1858 int port __unused, intptr_t *res)
1859 {
1860
1861 if (cmd == PUC_CFG_GET_ILR) {
1862 *res = PUC_ILR_DIGI;
1863 return (0);
1864 }
1865 return (ENXIO);
1866 }
1867
1868 static int
puc_config_moxa(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1869 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1870 intptr_t *res)
1871 {
1872 const struct puc_cfg *cfg = sc->sc_cfg;
1873
1874 if (cmd == PUC_CFG_GET_OFS) {
1875 if (port == 3 && (cfg->device == 0x1045 ||
1876 cfg->device == 0x1144))
1877 port = 7;
1878 *res = port * 0x200;
1879
1880 return 0;
1881 }
1882 return (ENXIO);
1883 }
1884
1885 static int
puc_config_quatech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1886 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1887 int port __unused, intptr_t *res)
1888 {
1889 const struct puc_cfg *cfg = sc->sc_cfg;
1890 struct puc_bar *bar;
1891 uint8_t v0, v1;
1892
1893 switch (cmd) {
1894 case PUC_CFG_SETUP:
1895 /*
1896 * Check if the scratchpad register is enabled or if the
1897 * interrupt status and options registers are active.
1898 */
1899 bar = puc_get_bar(sc, cfg->rid);
1900 if (bar == NULL)
1901 return (ENXIO);
1902 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);
1903 bus_write_1(bar->b_res, REG_SPR, 0);
1904 v0 = bus_read_1(bar->b_res, REG_SPR);
1905 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);
1906 v1 = bus_read_1(bar->b_res, REG_SPR);
1907 bus_write_1(bar->b_res, REG_LCR, 0);
1908 sc->sc_cfg_data = (v0 << 8) | v1;
1909 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1910 /*
1911 * The SPR register echoed the two values written
1912 * by us. This means that the SPAD jumper is set.
1913 */
1914 device_printf(sc->sc_dev, "warning: extra features "
1915 "not usable -- SPAD compatibility enabled\n");
1916 return (0);
1917 }
1918 if (v0 != 0) {
1919 /*
1920 * The first value doesn't match. This can only mean
1921 * that the SPAD jumper is not set and that a non-
1922 * standard fixed clock multiplier jumper is set.
1923 */
1924 if (bootverbose)
1925 device_printf(sc->sc_dev, "fixed clock rate "
1926 "multiplier of %d\n", 1 << v0);
1927 if (v0 < -cfg->clock)
1928 device_printf(sc->sc_dev, "warning: "
1929 "suboptimal fixed clock rate multiplier "
1930 "setting\n");
1931 return (0);
1932 }
1933 /*
1934 * The first value matched, but the second didn't. We know
1935 * that the SPAD jumper is not set. We also know that the
1936 * clock rate multiplier is software controlled *and* that
1937 * we just programmed it to the maximum allowed.
1938 */
1939 if (bootverbose)
1940 device_printf(sc->sc_dev, "clock rate multiplier of "
1941 "%d selected\n", 1 << -cfg->clock);
1942 return (0);
1943 case PUC_CFG_GET_CLOCK:
1944 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1945 v1 = sc->sc_cfg_data & 0xff;
1946 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1947 /*
1948 * XXX With the SPAD jumper applied, there's no
1949 * easy way of knowing if there's also a clock
1950 * rate multiplier jumper installed. Let's hope
1951 * not ...
1952 */
1953 *res = DEFAULT_RCLK;
1954 } else if (v0 == 0) {
1955 /*
1956 * No clock rate multiplier jumper installed,
1957 * so we programmed the board with the maximum
1958 * multiplier allowed as given to us in the
1959 * clock field of the config record (negated).
1960 */
1961 *res = DEFAULT_RCLK << -cfg->clock;
1962 } else
1963 *res = DEFAULT_RCLK << v0;
1964 return (0);
1965 case PUC_CFG_GET_ILR:
1966 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1967 v1 = sc->sc_cfg_data & 0xff;
1968 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ?
1969 PUC_ILR_NONE : PUC_ILR_QUATECH;
1970 return (0);
1971 default:
1972 break;
1973 }
1974 return (ENXIO);
1975 }
1976
1977 static int
puc_config_syba(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1978 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1979 intptr_t *res)
1980 {
1981 static int base[] = { 0x251, 0x3f0, 0 };
1982 const struct puc_cfg *cfg = sc->sc_cfg;
1983 struct puc_bar *bar;
1984 int efir, idx, ofs;
1985 uint8_t v;
1986
1987 switch (cmd) {
1988 case PUC_CFG_SETUP:
1989 bar = puc_get_bar(sc, cfg->rid);
1990 if (bar == NULL)
1991 return (ENXIO);
1992
1993 /* configure both W83877TFs */
1994 bus_write_1(bar->b_res, 0x250, 0x89);
1995 bus_write_1(bar->b_res, 0x3f0, 0x87);
1996 bus_write_1(bar->b_res, 0x3f0, 0x87);
1997 idx = 0;
1998 while (base[idx] != 0) {
1999 efir = base[idx];
2000 bus_write_1(bar->b_res, efir, 0x09);
2001 v = bus_read_1(bar->b_res, efir + 1);
2002 if ((v & 0x0f) != 0x0c)
2003 return (ENXIO);
2004 bus_write_1(bar->b_res, efir, 0x16);
2005 v = bus_read_1(bar->b_res, efir + 1);
2006 bus_write_1(bar->b_res, efir, 0x16);
2007 bus_write_1(bar->b_res, efir + 1, v | 0x04);
2008 bus_write_1(bar->b_res, efir, 0x16);
2009 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
2010 ofs = base[idx] & 0x300;
2011 bus_write_1(bar->b_res, efir, 0x23);
2012 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
2013 bus_write_1(bar->b_res, efir, 0x24);
2014 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
2015 bus_write_1(bar->b_res, efir, 0x25);
2016 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
2017 bus_write_1(bar->b_res, efir, 0x17);
2018 bus_write_1(bar->b_res, efir + 1, 0x03);
2019 bus_write_1(bar->b_res, efir, 0x28);
2020 bus_write_1(bar->b_res, efir + 1, 0x43);
2021 idx++;
2022 }
2023 bus_write_1(bar->b_res, 0x250, 0xaa);
2024 bus_write_1(bar->b_res, 0x3f0, 0xaa);
2025 return (0);
2026 case PUC_CFG_GET_OFS:
2027 switch (port) {
2028 case 0:
2029 *res = 0x2f8;
2030 return (0);
2031 case 1:
2032 *res = 0x2e8;
2033 return (0);
2034 case 2:
2035 *res = 0x3f8;
2036 return (0);
2037 case 3:
2038 *res = 0x3e8;
2039 return (0);
2040 case 4:
2041 *res = 0x278;
2042 return (0);
2043 }
2044 break;
2045 default:
2046 break;
2047 }
2048 return (ENXIO);
2049 }
2050
2051 static int
puc_config_siig(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2052 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2053 intptr_t *res)
2054 {
2055 const struct puc_cfg *cfg = sc->sc_cfg;
2056
2057 switch (cmd) {
2058 case PUC_CFG_GET_OFS:
2059 if (cfg->ports == PUC_PORT_8S) {
2060 *res = (port > 4) ? 8 * (port - 4) : 0;
2061 return (0);
2062 }
2063 break;
2064 case PUC_CFG_GET_RID:
2065 if (cfg->ports == PUC_PORT_8S) {
2066 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
2067 return (0);
2068 }
2069 if (cfg->ports == PUC_PORT_2S1P) {
2070 switch (port) {
2071 case 0: *res = 0x10; return (0);
2072 case 1: *res = 0x14; return (0);
2073 case 2: *res = 0x1c; return (0);
2074 }
2075 }
2076 break;
2077 default:
2078 break;
2079 }
2080 return (ENXIO);
2081 }
2082
2083 static int
puc_config_timedia(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2084 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2085 intptr_t *res)
2086 {
2087 static const uint16_t dual[] = {
2088 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
2089 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
2090 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
2091 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
2092 0xD079, 0
2093 };
2094 static const uint16_t quad[] = {
2095 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
2096 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
2097 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
2098 0xB157, 0
2099 };
2100 static const uint16_t octa[] = {
2101 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
2102 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
2103 };
2104 static const struct {
2105 int ports;
2106 const uint16_t *ids;
2107 } subdevs[] = {
2108 { 2, dual },
2109 { 4, quad },
2110 { 8, octa },
2111 { 0, NULL }
2112 };
2113 static char desc[64];
2114 int dev, id;
2115 uint16_t subdev;
2116
2117 switch (cmd) {
2118 case PUC_CFG_GET_CLOCK:
2119 if (port < 2)
2120 *res = DEFAULT_RCLK * 8;
2121 else
2122 *res = DEFAULT_RCLK;
2123 return (0);
2124 case PUC_CFG_GET_DESC:
2125 snprintf(desc, sizeof(desc),
2126 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
2127 *res = (intptr_t)desc;
2128 return (0);
2129 case PUC_CFG_GET_NPORTS:
2130 subdev = pci_get_subdevice(sc->sc_dev);
2131 dev = 0;
2132 while (subdevs[dev].ports != 0) {
2133 id = 0;
2134 while (subdevs[dev].ids[id] != 0) {
2135 if (subdev == subdevs[dev].ids[id]) {
2136 sc->sc_cfg_data = subdevs[dev].ports;
2137 *res = sc->sc_cfg_data;
2138 return (0);
2139 }
2140 id++;
2141 }
2142 dev++;
2143 }
2144 return (ENXIO);
2145 case PUC_CFG_GET_OFS:
2146 *res = (port == 1 || port == 3) ? 8 : 0;
2147 return (0);
2148 case PUC_CFG_GET_RID:
2149 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
2150 return (0);
2151 case PUC_CFG_GET_TYPE:
2152 *res = PUC_TYPE_SERIAL;
2153 return (0);
2154 default:
2155 break;
2156 }
2157 return (ENXIO);
2158 }
2159
2160 static int
puc_config_oxford_pci954(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)2161 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
2162 int port __unused, intptr_t *res)
2163 {
2164
2165 switch (cmd) {
2166 case PUC_CFG_GET_CLOCK:
2167 /*
2168 * OXu16PCI954 use a 14.7456 MHz clock by default while
2169 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
2170 */
2171 if (pci_get_revid(sc->sc_dev) == 1)
2172 *res = DEFAULT_RCLK * 8;
2173 else
2174 *res = DEFAULT_RCLK;
2175 return (0);
2176 default:
2177 break;
2178 }
2179 return (ENXIO);
2180 }
2181
2182 static int
puc_config_oxford_pcie(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2183 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2184 intptr_t *res)
2185 {
2186 const struct puc_cfg *cfg = sc->sc_cfg;
2187 int idx;
2188 struct puc_bar *bar;
2189 uint8_t value;
2190
2191 switch (cmd) {
2192 case PUC_CFG_SETUP:
2193 device_printf(sc->sc_dev, "%d UARTs detected\n",
2194 sc->sc_nports);
2195
2196 /* Set UARTs to enhanced mode */
2197 bar = puc_get_bar(sc, cfg->rid);
2198 if (bar == NULL)
2199 return (ENXIO);
2200 for (idx = 0; idx < sc->sc_nports; idx++) {
2201 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
2202 0x92);
2203 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
2204 value | 0x10);
2205 }
2206 return (0);
2207 case PUC_CFG_GET_LEN:
2208 *res = 0x200;
2209 return (0);
2210 case PUC_CFG_GET_NPORTS:
2211 /*
2212 * Check if we are being called from puc_bfe_attach()
2213 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
2214 * puc_get_bar(), so we return a value of 16. This has
2215 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC,
2216 * sc->sc_cfg_data will not contain the true number of
2217 * ports in PUC_CFG_GET_DESC, but we are not implementing
2218 * that call for this device family anyway.
2219 *
2220 * The check is for initialization of sc->sc_bar[idx],
2221 * which is only done in puc_bfe_attach().
2222 */
2223 idx = 0;
2224 do {
2225 if (sc->sc_bar[idx++].b_rid != -1) {
2226 sc->sc_cfg_data = 16;
2227 *res = sc->sc_cfg_data;
2228 return (0);
2229 }
2230 } while (idx < PUC_PCI_BARS);
2231
2232 bar = puc_get_bar(sc, cfg->rid);
2233 if (bar == NULL)
2234 return (ENXIO);
2235
2236 value = bus_read_1(bar->b_res, 0x04);
2237 if (value == 0)
2238 return (ENXIO);
2239
2240 sc->sc_cfg_data = value;
2241 *res = sc->sc_cfg_data;
2242 return (0);
2243 case PUC_CFG_GET_OFS:
2244 *res = 0x1000 + (port << 9);
2245 return (0);
2246 case PUC_CFG_GET_TYPE:
2247 *res = PUC_TYPE_SERIAL;
2248 return (0);
2249 default:
2250 break;
2251 }
2252 return (ENXIO);
2253 }
2254
2255 static int
puc_config_sunix(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2256 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2257 intptr_t *res)
2258 {
2259 int error;
2260
2261 switch (cmd) {
2262 case PUC_CFG_GET_OFS:
2263 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
2264 if (error != 0)
2265 return (error);
2266 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
2267 return (0);
2268 case PUC_CFG_GET_RID:
2269 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
2270 if (error != 0)
2271 return (error);
2272 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
2273 return (0);
2274 default:
2275 break;
2276 }
2277 return (ENXIO);
2278 }
2279
2280 static int
puc_config_titan(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)2281 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
2282 int port, intptr_t *res)
2283 {
2284
2285 switch (cmd) {
2286 case PUC_CFG_GET_OFS:
2287 *res = (port < 3) ? 0 : (port - 2) << 3;
2288 return (0);
2289 case PUC_CFG_GET_RID:
2290 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
2291 return (0);
2292 default:
2293 break;
2294 }
2295 return (ENXIO);
2296 }
2297