1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include "opt_rss.h" 27 #include "opt_ratelimit.h" 28 29 #include <linux/module.h> 30 #include <linux/errno.h> 31 #include <linux/pci.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/slab.h> 34 #if defined(CONFIG_X86) 35 #include <asm/pat.h> 36 #endif 37 #include <linux/sched.h> 38 #include <linux/delay.h> 39 #include <linux/fs.h> 40 #undef inode 41 #include <rdma/ib_user_verbs.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_cache.h> 44 #include <dev/mlx5/port.h> 45 #include <dev/mlx5/vport.h> 46 #include <linux/list.h> 47 #include <rdma/ib_smi.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <linux/in.h> 51 #include <linux/etherdevice.h> 52 #include <dev/mlx5/fs.h> 53 #include <dev/mlx5/mlx5_ib/mlx5_ib.h> 54 55 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 56 MODULE_LICENSE("Dual BSD/GPL"); 57 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 58 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 59 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 60 MODULE_VERSION(mlx5ib, 1); 61 62 enum { 63 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 64 }; 65 66 static enum rdma_link_layer 67 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 68 { 69 switch (port_type_cap) { 70 case MLX5_CAP_PORT_TYPE_IB: 71 return IB_LINK_LAYER_INFINIBAND; 72 case MLX5_CAP_PORT_TYPE_ETH: 73 return IB_LINK_LAYER_ETHERNET; 74 default: 75 return IB_LINK_LAYER_UNSPECIFIED; 76 } 77 } 78 79 static enum rdma_link_layer 80 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 81 { 82 struct mlx5_ib_dev *dev = to_mdev(device); 83 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 84 85 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 86 } 87 88 static bool mlx5_netdev_match(if_t ndev, 89 struct mlx5_core_dev *mdev, 90 const char *dname) 91 { 92 return if_gettype(ndev) == IFT_ETHER && 93 if_getdname(ndev) != NULL && 94 strcmp(if_getdname(ndev), dname) == 0 && 95 if_getsoftc(ndev) != NULL && 96 *(struct mlx5_core_dev **)if_getsoftc(ndev) == mdev; 97 } 98 99 static int mlx5_netdev_event(struct notifier_block *this, 100 unsigned long event, void *ptr) 101 { 102 if_t ndev = netdev_notifier_info_to_ifp(ptr); 103 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 104 roce.nb); 105 106 switch (event) { 107 case NETDEV_REGISTER: 108 case NETDEV_UNREGISTER: 109 write_lock(&ibdev->roce.netdev_lock); 110 /* check if network interface belongs to mlx5en */ 111 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 112 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 113 NULL : ndev; 114 write_unlock(&ibdev->roce.netdev_lock); 115 break; 116 117 case NETDEV_UP: 118 case NETDEV_DOWN: { 119 if_t upper = NULL; 120 121 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 122 && ibdev->ib_active) { 123 struct ib_event ibev = {0}; 124 125 ibev.device = &ibdev->ib_dev; 126 ibev.event = (event == NETDEV_UP) ? 127 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 128 ibev.element.port_num = 1; 129 ib_dispatch_event(&ibev); 130 } 131 break; 132 } 133 134 default: 135 break; 136 } 137 138 return NOTIFY_DONE; 139 } 140 141 static if_t mlx5_ib_get_netdev(struct ib_device *device, 142 u8 port_num) 143 { 144 struct mlx5_ib_dev *ibdev = to_mdev(device); 145 if_t ndev; 146 147 /* Ensure ndev does not disappear before we invoke if_ref() 148 */ 149 read_lock(&ibdev->roce.netdev_lock); 150 ndev = ibdev->roce.netdev; 151 if (ndev) 152 if_ref(ndev); 153 read_unlock(&ibdev->roce.netdev_lock); 154 155 return ndev; 156 } 157 158 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 159 u8 *active_width) 160 { 161 switch (eth_proto_oper) { 162 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 163 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 164 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 165 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 166 *active_width = IB_WIDTH_1X; 167 *active_speed = IB_SPEED_SDR; 168 break; 169 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 170 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 171 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 172 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 173 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 174 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 175 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR): 176 *active_width = IB_WIDTH_1X; 177 *active_speed = IB_SPEED_QDR; 178 break; 179 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 180 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 181 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 182 *active_width = IB_WIDTH_1X; 183 *active_speed = IB_SPEED_EDR; 184 break; 185 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 186 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 187 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 188 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4): 189 *active_width = IB_WIDTH_4X; 190 *active_speed = IB_SPEED_QDR; 191 break; 192 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 193 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 194 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR4): 195 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 196 *active_width = IB_WIDTH_1X; 197 *active_speed = IB_SPEED_HDR; 198 break; 199 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 200 *active_width = IB_WIDTH_4X; 201 *active_speed = IB_SPEED_FDR; 202 break; 203 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 204 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 205 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 206 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 207 *active_width = IB_WIDTH_4X; 208 *active_speed = IB_SPEED_EDR; 209 break; 210 default: 211 *active_width = IB_WIDTH_4X; 212 *active_speed = IB_SPEED_QDR; 213 return -EINVAL; 214 } 215 216 return 0; 217 } 218 219 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 220 u8 *active_width) 221 { 222 switch (eth_proto_oper) { 223 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 224 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 225 *active_width = IB_WIDTH_1X; 226 *active_speed = IB_SPEED_SDR; 227 break; 228 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 229 *active_width = IB_WIDTH_1X; 230 *active_speed = IB_SPEED_DDR; 231 break; 232 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 233 *active_width = IB_WIDTH_1X; 234 *active_speed = IB_SPEED_QDR; 235 break; 236 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 237 *active_width = IB_WIDTH_4X; 238 *active_speed = IB_SPEED_QDR; 239 break; 240 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 241 *active_width = IB_WIDTH_1X; 242 *active_speed = IB_SPEED_EDR; 243 break; 244 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 245 *active_width = IB_WIDTH_2X; 246 *active_speed = IB_SPEED_EDR; 247 break; 248 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 249 *active_width = IB_WIDTH_1X; 250 *active_speed = IB_SPEED_HDR; 251 break; 252 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 253 *active_width = IB_WIDTH_4X; 254 *active_speed = IB_SPEED_EDR; 255 break; 256 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 257 *active_width = IB_WIDTH_2X; 258 *active_speed = IB_SPEED_HDR; 259 break; 260 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 261 *active_width = IB_WIDTH_1X; 262 *active_speed = IB_SPEED_NDR; 263 break; 264 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 265 *active_width = IB_WIDTH_4X; 266 *active_speed = IB_SPEED_HDR; 267 break; 268 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 269 *active_width = IB_WIDTH_2X; 270 *active_speed = IB_SPEED_NDR; 271 break; 272 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 273 *active_width = IB_WIDTH_4X; 274 *active_speed = IB_SPEED_NDR; 275 break; 276 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 277 *active_width = IB_WIDTH_2X; 278 *active_speed = IB_SPEED_XDR; 279 break; 280 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 281 *active_width = IB_WIDTH_8X; 282 *active_speed = IB_SPEED_NDR; 283 break; 284 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 285 *active_width = IB_WIDTH_4X; 286 *active_speed = IB_SPEED_XDR; 287 break; 288 default: 289 *active_width = IB_WIDTH_4X; 290 *active_speed = IB_SPEED_QDR; 291 return -EINVAL; 292 } 293 294 return 0; 295 } 296 297 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 298 struct ib_port_attr *props) 299 { 300 struct mlx5_ib_dev *dev = to_mdev(device); 301 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 302 if_t ndev; 303 enum ib_mtu ndev_ib_mtu; 304 u16 qkey_viol_cntr; 305 u32 eth_prot_oper; 306 bool ext; 307 int err; 308 309 memset(props, 0, sizeof(*props)); 310 311 /* Possible bad flows are checked before filling out props so in case 312 * of an error it will still be zeroed out. 313 */ 314 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN, 315 port_num); 316 if (err) 317 return err; 318 319 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 320 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 321 322 if (ext) 323 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed, 324 &props->active_width); 325 else 326 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 327 &props->active_width); 328 329 props->port_cap_flags |= IB_PORT_CM_SUP; 330 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 331 332 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 333 roce_address_table_size); 334 props->max_mtu = IB_MTU_4096; 335 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 336 props->pkey_tbl_len = 1; 337 props->state = IB_PORT_DOWN; 338 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 339 340 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 341 props->qkey_viol_cntr = qkey_viol_cntr; 342 343 ndev = mlx5_ib_get_netdev(device, port_num); 344 if (!ndev) 345 return 0; 346 347 if (if_getdrvflags(ndev) & IFF_DRV_RUNNING && 348 if_getlinkstate(ndev) == LINK_STATE_UP) { 349 props->state = IB_PORT_ACTIVE; 350 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 351 } 352 353 ndev_ib_mtu = iboe_get_mtu(if_getmtu(ndev)); 354 355 if_rele(ndev); 356 357 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 358 return 0; 359 } 360 361 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 362 const struct ib_gid_attr *attr, 363 void *mlx5_addr) 364 { 365 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 366 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 367 source_l3_address); 368 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 369 source_mac_47_32); 370 u16 vlan_id; 371 int ret; 372 373 if (!gid) 374 return; 375 376 377 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mlx5_addr_mac); 378 if (ret != 0) 379 return; 380 381 if (vlan_id != 0xffff) { 382 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 383 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 384 } 385 386 switch (attr->gid_type) { 387 case IB_GID_TYPE_IB: 388 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 389 break; 390 case IB_GID_TYPE_ROCE_UDP_ENCAP: 391 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 392 break; 393 394 default: 395 WARN_ON(true); 396 } 397 398 if (attr->gid_type != IB_GID_TYPE_IB) { 399 if (ipv6_addr_v4mapped((void *)gid)) 400 MLX5_SET_RA(mlx5_addr, roce_l3_type, 401 MLX5_ROCE_L3_TYPE_IPV4); 402 else 403 MLX5_SET_RA(mlx5_addr, roce_l3_type, 404 MLX5_ROCE_L3_TYPE_IPV6); 405 } 406 407 if ((attr->gid_type == IB_GID_TYPE_IB) || 408 !ipv6_addr_v4mapped((void *)gid)) 409 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 410 else 411 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 412 } 413 414 static int set_roce_addr(struct ib_device *device, u8 port_num, 415 unsigned int index, 416 const union ib_gid *gid, 417 const struct ib_gid_attr *attr) 418 { 419 struct mlx5_ib_dev *dev = to_mdev(device); 420 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 421 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 422 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 423 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 424 425 if (ll != IB_LINK_LAYER_ETHERNET) 426 return -EINVAL; 427 428 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 429 430 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 431 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 432 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 433 } 434 435 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 436 __always_unused void **context) 437 { 438 return set_roce_addr(attr->device, attr->port_num, attr->index, 439 &attr->gid, attr); 440 } 441 442 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 443 __always_unused void **context) 444 { 445 return set_roce_addr(attr->device, attr->port_num, attr->index, NULL, 446 NULL); 447 } 448 449 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 450 const struct ib_gid_attr *attr) 451 { 452 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 453 return 0; 454 455 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 456 } 457 458 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 459 { 460 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 461 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 462 return 0; 463 } 464 465 enum { 466 MLX5_VPORT_ACCESS_METHOD_MAD, 467 MLX5_VPORT_ACCESS_METHOD_HCA, 468 MLX5_VPORT_ACCESS_METHOD_NIC, 469 }; 470 471 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 472 { 473 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 474 return MLX5_VPORT_ACCESS_METHOD_MAD; 475 476 if (mlx5_ib_port_link_layer(ibdev, 1) == 477 IB_LINK_LAYER_ETHERNET) 478 return MLX5_VPORT_ACCESS_METHOD_NIC; 479 480 return MLX5_VPORT_ACCESS_METHOD_HCA; 481 } 482 483 static void get_atomic_caps(struct mlx5_ib_dev *dev, 484 struct ib_device_attr *props) 485 { 486 u8 tmp; 487 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 488 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 489 u8 atomic_req_8B_endianness_mode = 490 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 491 492 /* Check if HW supports 8 bytes standard atomic operations and capable 493 * of host endianness respond 494 */ 495 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 496 if (((atomic_operations & tmp) == tmp) && 497 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 498 (atomic_req_8B_endianness_mode)) { 499 props->atomic_cap = IB_ATOMIC_HCA; 500 } else { 501 props->atomic_cap = IB_ATOMIC_NONE; 502 } 503 } 504 505 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 506 __be64 *sys_image_guid) 507 { 508 struct mlx5_ib_dev *dev = to_mdev(ibdev); 509 struct mlx5_core_dev *mdev = dev->mdev; 510 u64 tmp; 511 int err; 512 513 switch (mlx5_get_vport_access_method(ibdev)) { 514 case MLX5_VPORT_ACCESS_METHOD_MAD: 515 return mlx5_query_mad_ifc_system_image_guid(ibdev, 516 sys_image_guid); 517 518 case MLX5_VPORT_ACCESS_METHOD_HCA: 519 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 520 break; 521 522 case MLX5_VPORT_ACCESS_METHOD_NIC: 523 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 524 break; 525 526 default: 527 return -EINVAL; 528 } 529 530 if (!err) 531 *sys_image_guid = cpu_to_be64(tmp); 532 533 return err; 534 535 } 536 537 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 538 u16 *max_pkeys) 539 { 540 struct mlx5_ib_dev *dev = to_mdev(ibdev); 541 struct mlx5_core_dev *mdev = dev->mdev; 542 543 switch (mlx5_get_vport_access_method(ibdev)) { 544 case MLX5_VPORT_ACCESS_METHOD_MAD: 545 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 546 547 case MLX5_VPORT_ACCESS_METHOD_HCA: 548 case MLX5_VPORT_ACCESS_METHOD_NIC: 549 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 550 pkey_table_size)); 551 return 0; 552 553 default: 554 return -EINVAL; 555 } 556 } 557 558 static int mlx5_query_vendor_id(struct ib_device *ibdev, 559 u32 *vendor_id) 560 { 561 struct mlx5_ib_dev *dev = to_mdev(ibdev); 562 563 switch (mlx5_get_vport_access_method(ibdev)) { 564 case MLX5_VPORT_ACCESS_METHOD_MAD: 565 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 566 567 case MLX5_VPORT_ACCESS_METHOD_HCA: 568 case MLX5_VPORT_ACCESS_METHOD_NIC: 569 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 570 571 default: 572 return -EINVAL; 573 } 574 } 575 576 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 577 __be64 *node_guid) 578 { 579 u64 tmp; 580 int err; 581 582 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 583 case MLX5_VPORT_ACCESS_METHOD_MAD: 584 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 585 586 case MLX5_VPORT_ACCESS_METHOD_HCA: 587 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 588 break; 589 590 case MLX5_VPORT_ACCESS_METHOD_NIC: 591 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 592 break; 593 594 default: 595 return -EINVAL; 596 } 597 598 if (!err) 599 *node_guid = cpu_to_be64(tmp); 600 601 return err; 602 } 603 604 struct mlx5_reg_node_desc { 605 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 606 }; 607 608 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 609 { 610 struct mlx5_reg_node_desc in; 611 612 if (mlx5_use_mad_ifc(dev)) 613 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 614 615 memset(&in, 0, sizeof(in)); 616 617 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 618 sizeof(struct mlx5_reg_node_desc), 619 MLX5_REG_NODE_DESC, 0, 0); 620 } 621 622 static int mlx5_ib_query_device(struct ib_device *ibdev, 623 struct ib_device_attr *props, 624 struct ib_udata *uhw) 625 { 626 struct mlx5_ib_dev *dev = to_mdev(ibdev); 627 struct mlx5_core_dev *mdev = dev->mdev; 628 int err = -ENOMEM; 629 int max_sq_desc; 630 int max_rq_sg; 631 int max_sq_sg; 632 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 633 struct mlx5_ib_query_device_resp resp = {}; 634 size_t resp_len; 635 u64 max_tso; 636 637 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 638 if (uhw->outlen && uhw->outlen < resp_len) 639 return -EINVAL; 640 else 641 resp.response_length = resp_len; 642 643 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 644 return -EINVAL; 645 646 memset(props, 0, sizeof(*props)); 647 err = mlx5_query_system_image_guid(ibdev, 648 &props->sys_image_guid); 649 if (err) 650 return err; 651 652 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 653 if (err) 654 return err; 655 656 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 657 if (err) 658 return err; 659 660 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 661 ((u32)fw_rev_min(dev->mdev) << 16) | 662 fw_rev_sub(dev->mdev); 663 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 664 IB_DEVICE_PORT_ACTIVE_EVENT | 665 IB_DEVICE_SYS_IMAGE_GUID | 666 IB_DEVICE_RC_RNR_NAK_GEN | 667 IB_DEVICE_KNOWSEPOCH; 668 669 if (MLX5_CAP_GEN(mdev, pkv)) 670 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 671 if (MLX5_CAP_GEN(mdev, qkv)) 672 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 673 if (MLX5_CAP_GEN(mdev, apm)) 674 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 675 if (MLX5_CAP_GEN(mdev, xrc)) 676 props->device_cap_flags |= IB_DEVICE_XRC; 677 if (MLX5_CAP_GEN(mdev, imaicl)) { 678 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 679 IB_DEVICE_MEM_WINDOW_TYPE_2B; 680 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 681 /* We support 'Gappy' memory registration too */ 682 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 683 } 684 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 685 if (MLX5_CAP_GEN(mdev, sho)) { 686 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 687 /* At this stage no support for signature handover */ 688 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 689 IB_PROT_T10DIF_TYPE_2 | 690 IB_PROT_T10DIF_TYPE_3; 691 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 692 IB_GUARD_T10DIF_CSUM; 693 } 694 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 695 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 696 697 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 698 if (MLX5_CAP_ETH(mdev, csum_cap)) 699 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 700 701 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 702 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 703 if (max_tso) { 704 resp.tso_caps.max_tso = 1 << max_tso; 705 resp.tso_caps.supported_qpts |= 706 1 << IB_QPT_RAW_PACKET; 707 resp.response_length += sizeof(resp.tso_caps); 708 } 709 } 710 711 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 712 resp.rss_caps.rx_hash_function = 713 MLX5_RX_HASH_FUNC_TOEPLITZ; 714 resp.rss_caps.rx_hash_fields_mask = 715 MLX5_RX_HASH_SRC_IPV4 | 716 MLX5_RX_HASH_DST_IPV4 | 717 MLX5_RX_HASH_SRC_IPV6 | 718 MLX5_RX_HASH_DST_IPV6 | 719 MLX5_RX_HASH_SRC_PORT_TCP | 720 MLX5_RX_HASH_DST_PORT_TCP | 721 MLX5_RX_HASH_SRC_PORT_UDP | 722 MLX5_RX_HASH_DST_PORT_UDP; 723 resp.response_length += sizeof(resp.rss_caps); 724 } 725 } else { 726 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 727 resp.response_length += sizeof(resp.tso_caps); 728 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 729 resp.response_length += sizeof(resp.rss_caps); 730 } 731 732 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 733 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 734 props->device_cap_flags |= IB_DEVICE_UD_TSO; 735 } 736 737 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 738 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 739 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 740 741 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 742 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 743 744 props->vendor_part_id = mdev->pdev->device; 745 props->hw_ver = mdev->pdev->revision; 746 747 props->max_mr_size = ~0ull; 748 props->page_size_cap = ~(min_page_size - 1); 749 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 750 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 751 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 752 sizeof(struct mlx5_wqe_data_seg); 753 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 754 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 755 sizeof(struct mlx5_wqe_raddr_seg)) / 756 sizeof(struct mlx5_wqe_data_seg); 757 props->max_sge = min(max_rq_sg, max_sq_sg); 758 props->max_sge_rd = MLX5_MAX_SGE_RD; 759 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 760 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 761 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 762 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 763 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 764 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 765 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 766 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 767 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 768 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 769 props->max_srq_sge = max_rq_sg - 1; 770 props->max_fast_reg_page_list_len = 771 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 772 get_atomic_caps(dev, props); 773 props->masked_atomic_cap = IB_ATOMIC_NONE; 774 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 775 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 776 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 777 props->max_mcast_grp; 778 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 779 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 780 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 781 782 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 783 if (MLX5_CAP_GEN(mdev, pg)) 784 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 785 props->odp_caps = dev->odp_caps; 786 #endif 787 788 if (MLX5_CAP_GEN(mdev, cd)) 789 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 790 791 if (!mlx5_core_is_pf(mdev)) 792 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 793 794 if (mlx5_ib_port_link_layer(ibdev, 1) == 795 IB_LINK_LAYER_ETHERNET) { 796 props->rss_caps.max_rwq_indirection_tables = 797 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 798 props->rss_caps.max_rwq_indirection_table_size = 799 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 800 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 801 props->max_wq_type_rq = 802 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 803 } 804 805 if (uhw->outlen) { 806 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 807 808 if (err) 809 return err; 810 } 811 812 return 0; 813 } 814 815 enum mlx5_ib_width { 816 MLX5_IB_WIDTH_1X = 1 << 0, 817 MLX5_IB_WIDTH_2X = 1 << 1, 818 MLX5_IB_WIDTH_4X = 1 << 2, 819 MLX5_IB_WIDTH_8X = 1 << 3, 820 MLX5_IB_WIDTH_12X = 1 << 4 821 }; 822 823 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 824 u8 *ib_width) 825 { 826 struct mlx5_ib_dev *dev = to_mdev(ibdev); 827 int err = 0; 828 829 if (active_width & MLX5_IB_WIDTH_1X) { 830 *ib_width = IB_WIDTH_1X; 831 } else if (active_width & MLX5_IB_WIDTH_2X) { 832 *ib_width = IB_WIDTH_2X; 833 } else if (active_width & MLX5_IB_WIDTH_4X) { 834 *ib_width = IB_WIDTH_4X; 835 } else if (active_width & MLX5_IB_WIDTH_8X) { 836 *ib_width = IB_WIDTH_8X; 837 } else if (active_width & MLX5_IB_WIDTH_12X) { 838 *ib_width = IB_WIDTH_12X; 839 } else { 840 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 841 (int)active_width); 842 err = -EINVAL; 843 } 844 845 return err; 846 } 847 848 enum ib_max_vl_num { 849 __IB_MAX_VL_0 = 1, 850 __IB_MAX_VL_0_1 = 2, 851 __IB_MAX_VL_0_3 = 3, 852 __IB_MAX_VL_0_7 = 4, 853 __IB_MAX_VL_0_14 = 5, 854 }; 855 856 enum mlx5_vl_hw_cap { 857 MLX5_VL_HW_0 = 1, 858 MLX5_VL_HW_0_1 = 2, 859 MLX5_VL_HW_0_2 = 3, 860 MLX5_VL_HW_0_3 = 4, 861 MLX5_VL_HW_0_4 = 5, 862 MLX5_VL_HW_0_5 = 6, 863 MLX5_VL_HW_0_6 = 7, 864 MLX5_VL_HW_0_7 = 8, 865 MLX5_VL_HW_0_14 = 15 866 }; 867 868 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 869 u8 *max_vl_num) 870 { 871 switch (vl_hw_cap) { 872 case MLX5_VL_HW_0: 873 *max_vl_num = __IB_MAX_VL_0; 874 break; 875 case MLX5_VL_HW_0_1: 876 *max_vl_num = __IB_MAX_VL_0_1; 877 break; 878 case MLX5_VL_HW_0_3: 879 *max_vl_num = __IB_MAX_VL_0_3; 880 break; 881 case MLX5_VL_HW_0_7: 882 *max_vl_num = __IB_MAX_VL_0_7; 883 break; 884 case MLX5_VL_HW_0_14: 885 *max_vl_num = __IB_MAX_VL_0_14; 886 break; 887 888 default: 889 return -EINVAL; 890 } 891 892 return 0; 893 } 894 895 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 896 struct ib_port_attr *props) 897 { 898 struct mlx5_ib_dev *dev = to_mdev(ibdev); 899 struct mlx5_core_dev *mdev = dev->mdev; 900 u32 *rep; 901 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 902 struct mlx5_ptys_reg *ptys; 903 struct mlx5_pmtu_reg *pmtu; 904 struct mlx5_pvlc_reg pvlc; 905 void *ctx; 906 int err; 907 908 rep = mlx5_vzalloc(replen); 909 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 910 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 911 if (!rep || !ptys || !pmtu) { 912 err = -ENOMEM; 913 goto out; 914 } 915 916 memset(props, 0, sizeof(*props)); 917 918 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 919 if (err) 920 goto out; 921 922 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 923 924 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 925 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 926 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 927 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 928 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 929 props->phys_state = MLX5_GET(hca_vport_context, ctx, 930 port_physical_state); 931 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 932 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 933 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 934 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 935 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 936 pkey_violation_counter); 937 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 938 qkey_violation_counter); 939 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 940 subnet_timeout); 941 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 942 init_type_reply); 943 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 944 945 ptys->proto_mask |= MLX5_PTYS_IB; 946 ptys->local_port = port; 947 err = mlx5_core_access_ptys(mdev, ptys, 0); 948 if (err) 949 goto out; 950 951 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 952 &props->active_width); 953 if (err) 954 goto out; 955 956 props->active_speed = (u16)ptys->ib_proto_oper; 957 958 pmtu->local_port = port; 959 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 960 if (err) 961 goto out; 962 963 props->max_mtu = pmtu->max_mtu; 964 props->active_mtu = pmtu->oper_mtu; 965 966 memset(&pvlc, 0, sizeof(pvlc)); 967 pvlc.local_port = port; 968 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 969 if (err) 970 goto out; 971 972 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 973 &props->max_vl_num); 974 out: 975 kvfree(rep); 976 kfree(ptys); 977 kfree(pmtu); 978 return err; 979 } 980 981 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 982 struct ib_port_attr *props) 983 { 984 switch (mlx5_get_vport_access_method(ibdev)) { 985 case MLX5_VPORT_ACCESS_METHOD_MAD: 986 return mlx5_query_mad_ifc_port(ibdev, port, props); 987 988 case MLX5_VPORT_ACCESS_METHOD_HCA: 989 return mlx5_query_hca_port(ibdev, port, props); 990 991 case MLX5_VPORT_ACCESS_METHOD_NIC: 992 return mlx5_query_port_roce(ibdev, port, props); 993 994 default: 995 return -EINVAL; 996 } 997 } 998 999 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1000 union ib_gid *gid) 1001 { 1002 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1003 struct mlx5_core_dev *mdev = dev->mdev; 1004 1005 switch (mlx5_get_vport_access_method(ibdev)) { 1006 case MLX5_VPORT_ACCESS_METHOD_MAD: 1007 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1008 1009 case MLX5_VPORT_ACCESS_METHOD_HCA: 1010 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 1011 1012 default: 1013 return -EINVAL; 1014 } 1015 1016 } 1017 1018 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1019 u16 *pkey) 1020 { 1021 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1022 struct mlx5_core_dev *mdev = dev->mdev; 1023 1024 switch (mlx5_get_vport_access_method(ibdev)) { 1025 case MLX5_VPORT_ACCESS_METHOD_MAD: 1026 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1027 1028 case MLX5_VPORT_ACCESS_METHOD_HCA: 1029 case MLX5_VPORT_ACCESS_METHOD_NIC: 1030 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1031 pkey); 1032 default: 1033 return -EINVAL; 1034 } 1035 } 1036 1037 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1038 struct ib_device_modify *props) 1039 { 1040 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1041 struct mlx5_reg_node_desc in; 1042 struct mlx5_reg_node_desc out; 1043 int err; 1044 1045 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1046 return -EOPNOTSUPP; 1047 1048 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1049 return 0; 1050 1051 /* 1052 * If possible, pass node desc to FW, so it can generate 1053 * a 144 trap. If cmd fails, just ignore. 1054 */ 1055 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1056 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1057 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1058 if (err) 1059 return err; 1060 1061 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1062 1063 return err; 1064 } 1065 1066 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1067 struct ib_port_modify *props) 1068 { 1069 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1070 struct ib_port_attr attr; 1071 u32 tmp; 1072 int err; 1073 1074 /* 1075 * CM layer calls ib_modify_port() regardless of the link 1076 * layer. For Ethernet ports, qkey violation and Port 1077 * capabilities are meaningless. 1078 */ 1079 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET) 1080 return 0; 1081 1082 mutex_lock(&dev->cap_mask_mutex); 1083 1084 err = mlx5_ib_query_port(ibdev, port, &attr); 1085 if (err) 1086 goto out; 1087 1088 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1089 ~props->clr_port_cap_mask; 1090 1091 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1092 1093 out: 1094 mutex_unlock(&dev->cap_mask_mutex); 1095 return err; 1096 } 1097 1098 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1099 { 1100 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1101 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1102 } 1103 1104 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1105 { 1106 /* Large page with non 4k uar support might limit the dynamic size */ 1107 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1108 return MLX5_MIN_DYN_BFREGS; 1109 1110 return MLX5_MAX_DYN_BFREGS; 1111 } 1112 1113 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1114 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1115 struct mlx5_bfreg_info *bfregi) 1116 { 1117 int uars_per_sys_page; 1118 int bfregs_per_sys_page; 1119 int ref_bfregs = req->total_num_bfregs; 1120 1121 if (req->total_num_bfregs == 0) 1122 return -EINVAL; 1123 1124 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1125 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1126 1127 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1128 return -ENOMEM; 1129 1130 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1131 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1132 /* This holds the required static allocation asked by the user */ 1133 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1134 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1135 return -EINVAL; 1136 1137 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1138 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1139 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1140 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1141 1142 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1143 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1144 lib_uar_4k ? "yes" : "no", ref_bfregs, 1145 req->total_num_bfregs, bfregi->total_num_bfregs, 1146 bfregi->num_sys_pages); 1147 1148 return 0; 1149 } 1150 1151 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1152 { 1153 struct mlx5_bfreg_info *bfregi; 1154 int err; 1155 int i; 1156 1157 bfregi = &context->bfregi; 1158 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1159 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1160 if (err) 1161 goto error; 1162 1163 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1164 } 1165 1166 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1167 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1168 1169 return 0; 1170 1171 error: 1172 for (--i; i >= 0; i--) 1173 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1174 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1175 1176 return err; 1177 } 1178 1179 static void deallocate_uars(struct mlx5_ib_dev *dev, 1180 struct mlx5_ib_ucontext *context) 1181 { 1182 struct mlx5_bfreg_info *bfregi; 1183 int i; 1184 1185 bfregi = &context->bfregi; 1186 for (i = 0; i < bfregi->num_sys_pages; i++) 1187 if (i < bfregi->num_static_sys_pages || 1188 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1189 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1190 } 1191 1192 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1193 u16 uid) 1194 { 1195 int err; 1196 1197 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1198 return 0; 1199 1200 err = mlx5_alloc_transport_domain(dev->mdev, tdn, uid); 1201 if (err) 1202 return err; 1203 1204 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1205 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1206 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1207 return 0; 1208 1209 mutex_lock(&dev->lb_mutex); 1210 dev->user_td++; 1211 1212 if (dev->user_td == 2) 1213 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1214 1215 mutex_unlock(&dev->lb_mutex); 1216 1217 if (err != 0) 1218 mlx5_dealloc_transport_domain(dev->mdev, *tdn, uid); 1219 return err; 1220 } 1221 1222 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1223 u16 uid) 1224 { 1225 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1226 return; 1227 1228 mlx5_dealloc_transport_domain(dev->mdev, tdn, uid); 1229 1230 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1231 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1232 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1233 return; 1234 1235 mutex_lock(&dev->lb_mutex); 1236 dev->user_td--; 1237 1238 if (dev->user_td < 2) 1239 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1240 1241 mutex_unlock(&dev->lb_mutex); 1242 } 1243 1244 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1245 struct ib_udata *udata) 1246 { 1247 struct ib_device *ibdev = uctx->device; 1248 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1249 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1250 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1251 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1252 struct mlx5_bfreg_info *bfregi; 1253 int ver; 1254 int err; 1255 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1256 max_cqe_version); 1257 bool lib_uar_4k; 1258 bool lib_uar_dyn; 1259 1260 if (!dev->ib_active) 1261 return -EAGAIN; 1262 1263 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1264 ver = 0; 1265 else if (udata->inlen >= min_req_v2) 1266 ver = 2; 1267 else 1268 return -EINVAL; 1269 1270 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1271 if (err) 1272 return err; 1273 1274 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1275 return -EOPNOTSUPP; 1276 1277 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1278 return -EOPNOTSUPP; 1279 1280 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1281 MLX5_NON_FP_BFREGS_PER_UAR); 1282 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1283 return -EINVAL; 1284 1285 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1286 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1287 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1288 resp.cache_line_size = cache_line_size(); 1289 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1290 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1291 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1292 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1293 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1294 resp.cqe_version = min_t(__u8, 1295 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1296 req.max_cqe_version); 1297 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1298 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1299 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1300 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1301 resp.response_length = min(offsetof(typeof(resp), response_length) + 1302 sizeof(resp.response_length), udata->outlen); 1303 1304 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1305 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1306 bfregi = &context->bfregi; 1307 1308 if (lib_uar_dyn) { 1309 bfregi->lib_uar_dyn = lib_uar_dyn; 1310 goto uar_done; 1311 } 1312 1313 /* updates req->total_num_bfregs */ 1314 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1315 if (err) 1316 goto out_ctx; 1317 1318 mutex_init(&bfregi->lock); 1319 bfregi->lib_uar_4k = lib_uar_4k; 1320 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1321 GFP_KERNEL); 1322 if (!bfregi->count) { 1323 err = -ENOMEM; 1324 goto out_ctx; 1325 } 1326 1327 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1328 sizeof(*bfregi->sys_pages), 1329 GFP_KERNEL); 1330 if (!bfregi->sys_pages) { 1331 err = -ENOMEM; 1332 goto out_count; 1333 } 1334 1335 err = allocate_uars(dev, context); 1336 if (err) 1337 goto out_sys_pages; 1338 1339 uar_done: 1340 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1341 err = mlx5_ib_devx_create(dev, true); 1342 if (err < 0) 1343 goto out_uars; 1344 context->devx_uid = err; 1345 } 1346 1347 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1348 context->devx_uid); 1349 if (err) 1350 goto out_devx; 1351 1352 INIT_LIST_HEAD(&context->db_page_list); 1353 mutex_init(&context->db_page_mutex); 1354 1355 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs; 1356 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1357 1358 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1359 resp.response_length += sizeof(resp.cqe_version); 1360 1361 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1362 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1363 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1364 resp.response_length += sizeof(resp.cmds_supp_uhw); 1365 } 1366 1367 /* 1368 * We don't want to expose information from the PCI bar that is located 1369 * after 4096 bytes, so if the arch only supports larger pages, let's 1370 * pretend we don't support reading the HCA's core clock. This is also 1371 * forced by mmap function. 1372 */ 1373 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) { 1374 if (PAGE_SIZE <= 4096) { 1375 resp.comp_mask |= 1376 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1377 resp.hca_core_clock_offset = 1378 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1379 } 1380 resp.response_length += sizeof(resp.hca_core_clock_offset); 1381 } 1382 1383 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen) 1384 resp.response_length += sizeof(resp.log_uar_size); 1385 1386 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen) 1387 resp.response_length += sizeof(resp.num_uars_per_page); 1388 1389 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) { 1390 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1391 resp.response_length += sizeof(resp.num_dyn_bfregs); 1392 } 1393 1394 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1395 if (err) 1396 goto out_mdev; 1397 1398 bfregi->ver = ver; 1399 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1400 context->cqe_version = resp.cqe_version; 1401 context->lib_caps = req.lib_caps; 1402 print_lib_caps(dev, context->lib_caps); 1403 1404 return 0; 1405 1406 out_mdev: 1407 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1408 out_devx: 1409 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1410 mlx5_ib_devx_destroy(dev, context->devx_uid); 1411 1412 out_uars: 1413 deallocate_uars(dev, context); 1414 1415 out_sys_pages: 1416 kfree(bfregi->sys_pages); 1417 1418 out_count: 1419 kfree(bfregi->count); 1420 1421 out_ctx: 1422 return err; 1423 } 1424 1425 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1426 { 1427 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1428 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1429 struct mlx5_bfreg_info *bfregi; 1430 1431 bfregi = &context->bfregi; 1432 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1433 1434 if (context->devx_uid) 1435 mlx5_ib_devx_destroy(dev, context->devx_uid); 1436 1437 deallocate_uars(dev, context); 1438 kfree(bfregi->sys_pages); 1439 kfree(bfregi->count); 1440 } 1441 1442 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1443 int uar_idx) 1444 { 1445 int fw_uars_per_page; 1446 1447 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1448 1449 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1450 } 1451 1452 static int get_command(unsigned long offset) 1453 { 1454 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1455 } 1456 1457 static int get_arg(unsigned long offset) 1458 { 1459 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1460 } 1461 1462 static int get_index(unsigned long offset) 1463 { 1464 return get_arg(offset); 1465 } 1466 1467 /* Index resides in an extra byte to enable larger values than 255 */ 1468 static int get_extended_index(unsigned long offset) 1469 { 1470 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1471 } 1472 1473 1474 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1475 { 1476 } 1477 1478 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1479 { 1480 switch (cmd) { 1481 case MLX5_IB_MMAP_WC_PAGE: 1482 return "WC"; 1483 case MLX5_IB_MMAP_REGULAR_PAGE: 1484 return "best effort WC"; 1485 case MLX5_IB_MMAP_NC_PAGE: 1486 return "NC"; 1487 default: 1488 return NULL; 1489 } 1490 } 1491 1492 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1493 struct vm_area_struct *vma, 1494 struct mlx5_ib_ucontext *context) 1495 { 1496 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 1497 !(vma->vm_flags & VM_SHARED)) 1498 return -EINVAL; 1499 1500 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1501 return -EOPNOTSUPP; 1502 1503 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 1504 return -EPERM; 1505 1506 return -EOPNOTSUPP; 1507 } 1508 1509 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 1510 { 1511 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 1512 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 1513 1514 switch (mentry->mmap_flag) { 1515 case MLX5_IB_MMAP_TYPE_UAR_WC: 1516 case MLX5_IB_MMAP_TYPE_UAR_NC: 1517 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 1518 kfree(mentry); 1519 break; 1520 default: 1521 WARN_ON(true); 1522 } 1523 } 1524 1525 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1526 struct vm_area_struct *vma, 1527 struct mlx5_ib_ucontext *context) 1528 { 1529 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1530 int err; 1531 unsigned long idx; 1532 phys_addr_t pfn; 1533 pgprot_t prot; 1534 u32 bfreg_dyn_idx = 0; 1535 u32 uar_index; 1536 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 1537 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 1538 bfregi->num_static_sys_pages; 1539 1540 if (bfregi->lib_uar_dyn) 1541 return -EINVAL; 1542 1543 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1544 return -EINVAL; 1545 1546 if (dyn_uar) 1547 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 1548 else 1549 idx = get_index(vma->vm_pgoff); 1550 1551 if (idx >= max_valid_idx) { 1552 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 1553 idx, max_valid_idx); 1554 return -EINVAL; 1555 } 1556 1557 switch (cmd) { 1558 case MLX5_IB_MMAP_WC_PAGE: 1559 case MLX5_IB_MMAP_ALLOC_WC: 1560 case MLX5_IB_MMAP_REGULAR_PAGE: 1561 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1562 prot = pgprot_writecombine(vma->vm_page_prot); 1563 break; 1564 case MLX5_IB_MMAP_NC_PAGE: 1565 prot = pgprot_noncached(vma->vm_page_prot); 1566 break; 1567 default: 1568 return -EINVAL; 1569 } 1570 1571 if (dyn_uar) { 1572 int uars_per_page; 1573 1574 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1575 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 1576 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 1577 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 1578 bfreg_dyn_idx, bfregi->total_num_bfregs); 1579 return -EINVAL; 1580 } 1581 1582 mutex_lock(&bfregi->lock); 1583 /* Fail if uar already allocated, first bfreg index of each 1584 * page holds its count. 1585 */ 1586 if (bfregi->count[bfreg_dyn_idx]) { 1587 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 1588 mutex_unlock(&bfregi->lock); 1589 return -EINVAL; 1590 } 1591 1592 bfregi->count[bfreg_dyn_idx]++; 1593 mutex_unlock(&bfregi->lock); 1594 1595 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 1596 if (err) { 1597 mlx5_ib_warn(dev, "UAR alloc failed\n"); 1598 goto free_bfreg; 1599 } 1600 } else { 1601 uar_index = bfregi->sys_pages[idx]; 1602 } 1603 1604 pfn = uar_index2pfn(dev, uar_index); 1605 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1606 1607 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 1608 prot, NULL); 1609 if (err) { 1610 mlx5_ib_err(dev, 1611 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 1612 err, mmap_cmd2str(cmd)); 1613 goto err; 1614 } 1615 1616 if (dyn_uar) 1617 bfregi->sys_pages[idx] = uar_index; 1618 return 0; 1619 1620 err: 1621 if (!dyn_uar) 1622 return err; 1623 1624 mlx5_cmd_free_uar(dev->mdev, idx); 1625 1626 free_bfreg: 1627 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 1628 1629 return err; 1630 } 1631 1632 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 1633 { 1634 unsigned long idx; 1635 u8 command; 1636 1637 command = get_command(vma->vm_pgoff); 1638 idx = get_extended_index(vma->vm_pgoff); 1639 1640 return (command << 16 | idx); 1641 } 1642 1643 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 1644 struct vm_area_struct *vma, 1645 struct ib_ucontext *ucontext) 1646 { 1647 struct mlx5_user_mmap_entry *mentry; 1648 struct rdma_user_mmap_entry *entry; 1649 unsigned long pgoff; 1650 pgprot_t prot; 1651 phys_addr_t pfn; 1652 int ret; 1653 1654 pgoff = mlx5_vma_to_pgoff(vma); 1655 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 1656 if (!entry) 1657 return -EINVAL; 1658 1659 mentry = to_mmmap(entry); 1660 pfn = (mentry->address >> PAGE_SHIFT); 1661 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 1662 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 1663 prot = pgprot_noncached(vma->vm_page_prot); 1664 else 1665 prot = pgprot_writecombine(vma->vm_page_prot); 1666 ret = rdma_user_mmap_io(ucontext, vma, pfn, 1667 entry->npages * PAGE_SIZE, 1668 prot, 1669 entry); 1670 rdma_user_mmap_entry_put(&mentry->rdma_entry); 1671 return ret; 1672 } 1673 1674 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1675 { 1676 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1677 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1678 unsigned long command; 1679 phys_addr_t pfn; 1680 1681 command = get_command(vma->vm_pgoff); 1682 switch (command) { 1683 case MLX5_IB_MMAP_WC_PAGE: 1684 case MLX5_IB_MMAP_ALLOC_WC: 1685 if (!dev->wc_support) 1686 return -EPERM; 1687 /* FALLTHROUGH */ 1688 case MLX5_IB_MMAP_NC_PAGE: 1689 case MLX5_IB_MMAP_REGULAR_PAGE: 1690 return uar_mmap(dev, command, vma, context); 1691 1692 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1693 return -ENOSYS; 1694 1695 case MLX5_IB_MMAP_CORE_CLOCK: 1696 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1697 return -EINVAL; 1698 1699 if (vma->vm_flags & VM_WRITE) 1700 return -EPERM; 1701 1702 /* Don't expose to user-space information it shouldn't have */ 1703 if (PAGE_SIZE > 4096) 1704 return -EOPNOTSUPP; 1705 1706 pfn = (dev->mdev->iseg_base + 1707 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1708 PAGE_SHIFT; 1709 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 1710 PAGE_SIZE, 1711 pgprot_noncached(vma->vm_page_prot), 1712 NULL); 1713 case MLX5_IB_MMAP_CLOCK_INFO: 1714 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 1715 1716 default: 1717 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 1718 } 1719 1720 return 0; 1721 } 1722 1723 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 1724 { 1725 struct mlx5_ib_pd *pd = to_mpd(ibpd); 1726 struct ib_device *ibdev = ibpd->device; 1727 struct mlx5_ib_alloc_pd_resp resp; 1728 int err; 1729 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1730 udata, struct mlx5_ib_ucontext, ibucontext); 1731 u16 uid = context ? context->devx_uid : 0; 1732 1733 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn, uid); 1734 if (err) 1735 return (err); 1736 1737 pd->uid = uid; 1738 if (udata) { 1739 resp.pdn = pd->pdn; 1740 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1741 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 1742 return -EFAULT; 1743 } 1744 } 1745 1746 return 0; 1747 } 1748 1749 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 1750 { 1751 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1752 struct mlx5_ib_pd *mpd = to_mpd(pd); 1753 1754 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 1755 } 1756 1757 enum { 1758 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1759 MATCH_CRITERIA_ENABLE_MISC_BIT, 1760 MATCH_CRITERIA_ENABLE_INNER_BIT 1761 }; 1762 1763 #define HEADER_IS_ZERO(match_criteria, headers) \ 1764 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1765 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1766 1767 static u8 get_match_criteria_enable(u32 *match_criteria) 1768 { 1769 u8 match_criteria_enable; 1770 1771 match_criteria_enable = 1772 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1773 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1774 match_criteria_enable |= 1775 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1776 MATCH_CRITERIA_ENABLE_MISC_BIT; 1777 match_criteria_enable |= 1778 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1779 MATCH_CRITERIA_ENABLE_INNER_BIT; 1780 1781 return match_criteria_enable; 1782 } 1783 1784 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1785 { 1786 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1787 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1788 } 1789 1790 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1791 { 1792 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1793 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1794 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1795 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1796 } 1797 1798 #define LAST_ETH_FIELD vlan_tag 1799 #define LAST_IB_FIELD sl 1800 #define LAST_IPV4_FIELD tos 1801 #define LAST_IPV6_FIELD traffic_class 1802 #define LAST_TCP_UDP_FIELD src_port 1803 1804 /* Field is the last supported field */ 1805 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1806 memchr_inv((void *)&filter.field +\ 1807 sizeof(filter.field), 0,\ 1808 sizeof(filter) -\ 1809 offsetof(typeof(filter), field) -\ 1810 sizeof(filter.field)) 1811 1812 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1813 const union ib_flow_spec *ib_spec) 1814 { 1815 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1816 outer_headers); 1817 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1818 outer_headers); 1819 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1820 misc_parameters); 1821 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1822 misc_parameters); 1823 1824 switch (ib_spec->type) { 1825 case IB_FLOW_SPEC_ETH: 1826 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1827 return -ENOTSUPP; 1828 1829 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1830 dmac_47_16), 1831 ib_spec->eth.mask.dst_mac); 1832 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1833 dmac_47_16), 1834 ib_spec->eth.val.dst_mac); 1835 1836 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1837 smac_47_16), 1838 ib_spec->eth.mask.src_mac); 1839 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1840 smac_47_16), 1841 ib_spec->eth.val.src_mac); 1842 1843 if (ib_spec->eth.mask.vlan_tag) { 1844 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1845 cvlan_tag, 1); 1846 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1847 cvlan_tag, 1); 1848 1849 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1850 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1851 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1852 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1853 1854 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1855 first_cfi, 1856 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1857 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1858 first_cfi, 1859 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1860 1861 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1862 first_prio, 1863 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1864 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1865 first_prio, 1866 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1867 } 1868 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1869 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1870 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1871 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1872 break; 1873 case IB_FLOW_SPEC_IPV4: 1874 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1875 return -ENOTSUPP; 1876 1877 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1878 ethertype, 0xffff); 1879 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1880 ethertype, ETH_P_IP); 1881 1882 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1883 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1884 &ib_spec->ipv4.mask.src_ip, 1885 sizeof(ib_spec->ipv4.mask.src_ip)); 1886 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1887 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1888 &ib_spec->ipv4.val.src_ip, 1889 sizeof(ib_spec->ipv4.val.src_ip)); 1890 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1891 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1892 &ib_spec->ipv4.mask.dst_ip, 1893 sizeof(ib_spec->ipv4.mask.dst_ip)); 1894 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1895 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1896 &ib_spec->ipv4.val.dst_ip, 1897 sizeof(ib_spec->ipv4.val.dst_ip)); 1898 1899 set_tos(outer_headers_c, outer_headers_v, 1900 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1901 1902 set_proto(outer_headers_c, outer_headers_v, 1903 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1904 break; 1905 case IB_FLOW_SPEC_IPV6: 1906 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1907 return -ENOTSUPP; 1908 1909 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1910 ethertype, 0xffff); 1911 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1912 ethertype, ETH_P_IPV6); 1913 1914 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1915 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1916 &ib_spec->ipv6.mask.src_ip, 1917 sizeof(ib_spec->ipv6.mask.src_ip)); 1918 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1919 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1920 &ib_spec->ipv6.val.src_ip, 1921 sizeof(ib_spec->ipv6.val.src_ip)); 1922 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1923 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1924 &ib_spec->ipv6.mask.dst_ip, 1925 sizeof(ib_spec->ipv6.mask.dst_ip)); 1926 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1927 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1928 &ib_spec->ipv6.val.dst_ip, 1929 sizeof(ib_spec->ipv6.val.dst_ip)); 1930 1931 set_tos(outer_headers_c, outer_headers_v, 1932 ib_spec->ipv6.mask.traffic_class, 1933 ib_spec->ipv6.val.traffic_class); 1934 1935 set_proto(outer_headers_c, outer_headers_v, 1936 ib_spec->ipv6.mask.next_hdr, 1937 ib_spec->ipv6.val.next_hdr); 1938 1939 MLX5_SET(fte_match_set_misc, misc_params_c, 1940 outer_ipv6_flow_label, 1941 ntohl(ib_spec->ipv6.mask.flow_label)); 1942 MLX5_SET(fte_match_set_misc, misc_params_v, 1943 outer_ipv6_flow_label, 1944 ntohl(ib_spec->ipv6.val.flow_label)); 1945 break; 1946 case IB_FLOW_SPEC_TCP: 1947 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1948 LAST_TCP_UDP_FIELD)) 1949 return -ENOTSUPP; 1950 1951 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1952 0xff); 1953 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1954 IPPROTO_TCP); 1955 1956 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1957 ntohs(ib_spec->tcp_udp.mask.src_port)); 1958 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1959 ntohs(ib_spec->tcp_udp.val.src_port)); 1960 1961 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1962 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1963 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1964 ntohs(ib_spec->tcp_udp.val.dst_port)); 1965 break; 1966 case IB_FLOW_SPEC_UDP: 1967 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1968 LAST_TCP_UDP_FIELD)) 1969 return -ENOTSUPP; 1970 1971 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1972 0xff); 1973 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1974 IPPROTO_UDP); 1975 1976 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1977 ntohs(ib_spec->tcp_udp.mask.src_port)); 1978 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1979 ntohs(ib_spec->tcp_udp.val.src_port)); 1980 1981 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1982 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1983 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1984 ntohs(ib_spec->tcp_udp.val.dst_port)); 1985 break; 1986 default: 1987 return -EINVAL; 1988 } 1989 1990 return 0; 1991 } 1992 1993 /* If a flow could catch both multicast and unicast packets, 1994 * it won't fall into the multicast flow steering table and this rule 1995 * could steal other multicast packets. 1996 */ 1997 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1998 { 1999 struct ib_flow_spec_eth *eth_spec; 2000 2001 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2002 ib_attr->size < sizeof(struct ib_flow_attr) + 2003 sizeof(struct ib_flow_spec_eth) || 2004 ib_attr->num_of_specs < 1) 2005 return false; 2006 2007 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 2008 if (eth_spec->type != IB_FLOW_SPEC_ETH || 2009 eth_spec->size != sizeof(*eth_spec)) 2010 return false; 2011 2012 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2013 is_multicast_ether_addr(eth_spec->val.dst_mac); 2014 } 2015 2016 static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 2017 { 2018 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2019 bool has_ipv4_spec = false; 2020 bool eth_type_ipv4 = true; 2021 unsigned int spec_index; 2022 2023 /* Validate that ethertype is correct */ 2024 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2025 if (ib_spec->type == IB_FLOW_SPEC_ETH && 2026 ib_spec->eth.mask.ether_type) { 2027 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 2028 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 2029 eth_type_ipv4 = false; 2030 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 2031 has_ipv4_spec = true; 2032 } 2033 ib_spec = (void *)ib_spec + ib_spec->size; 2034 } 2035 return !has_ipv4_spec || eth_type_ipv4; 2036 } 2037 2038 static void put_flow_table(struct mlx5_ib_dev *dev, 2039 struct mlx5_ib_flow_prio *prio, bool ft_added) 2040 { 2041 prio->refcount -= !!ft_added; 2042 if (!prio->refcount) { 2043 mlx5_destroy_flow_table(prio->flow_table); 2044 prio->flow_table = NULL; 2045 } 2046 } 2047 2048 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2049 { 2050 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2051 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2052 struct mlx5_ib_flow_handler, 2053 ibflow); 2054 struct mlx5_ib_flow_handler *iter, *tmp; 2055 2056 mutex_lock(&dev->flow_db.lock); 2057 2058 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2059 mlx5_del_flow_rules(&iter->rule); 2060 put_flow_table(dev, iter->prio, true); 2061 list_del(&iter->list); 2062 kfree(iter); 2063 } 2064 2065 mlx5_del_flow_rules(&handler->rule); 2066 put_flow_table(dev, handler->prio, true); 2067 mutex_unlock(&dev->flow_db.lock); 2068 2069 kfree(handler); 2070 2071 return 0; 2072 } 2073 2074 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2075 { 2076 priority *= 2; 2077 if (!dont_trap) 2078 priority++; 2079 return priority; 2080 } 2081 2082 enum flow_table_type { 2083 MLX5_IB_FT_RX, 2084 MLX5_IB_FT_TX 2085 }; 2086 2087 #define MLX5_FS_MAX_TYPES 10 2088 #define MLX5_FS_MAX_ENTRIES 32000UL 2089 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2090 struct ib_flow_attr *flow_attr, 2091 enum flow_table_type ft_type) 2092 { 2093 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2094 struct mlx5_flow_table_attr ft_attr = {}; 2095 struct mlx5_flow_namespace *ns = NULL; 2096 struct mlx5_ib_flow_prio *prio; 2097 struct mlx5_flow_table *ft; 2098 int num_entries; 2099 int num_groups; 2100 int priority; 2101 int err = 0; 2102 2103 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2104 if (flow_is_multicast_only(flow_attr) && 2105 !dont_trap) 2106 priority = MLX5_IB_FLOW_MCAST_PRIO; 2107 else 2108 priority = ib_prio_to_core_prio(flow_attr->priority, 2109 dont_trap); 2110 ns = mlx5_get_flow_namespace(dev->mdev, 2111 MLX5_FLOW_NAMESPACE_BYPASS); 2112 num_entries = MLX5_FS_MAX_ENTRIES; 2113 num_groups = MLX5_FS_MAX_TYPES; 2114 prio = &dev->flow_db.prios[priority]; 2115 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2116 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2117 ns = mlx5_get_flow_namespace(dev->mdev, 2118 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2119 build_leftovers_ft_param("bypass", &priority, 2120 &num_entries, 2121 &num_groups); 2122 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2123 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2124 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2125 allow_sniffer_and_nic_rx_shared_tir)) 2126 return ERR_PTR(-ENOTSUPP); 2127 2128 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2129 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2130 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2131 2132 prio = &dev->flow_db.sniffer[ft_type]; 2133 priority = 0; 2134 num_entries = 1; 2135 num_groups = 1; 2136 } 2137 2138 if (!ns) 2139 return ERR_PTR(-ENOTSUPP); 2140 2141 ft = prio->flow_table; 2142 if (!ft) { 2143 ft_attr.prio = priority; 2144 ft_attr.max_fte = num_entries; 2145 ft_attr.autogroup.max_num_groups = num_groups; 2146 2147 ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr); 2148 2149 if (!IS_ERR(ft)) { 2150 prio->refcount = 0; 2151 prio->flow_table = ft; 2152 } else { 2153 err = PTR_ERR(ft); 2154 } 2155 } 2156 2157 return err ? ERR_PTR(err) : prio; 2158 } 2159 2160 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2161 struct mlx5_ib_flow_prio *ft_prio, 2162 const struct ib_flow_attr *flow_attr, 2163 struct mlx5_flow_destination *dst) 2164 { 2165 struct mlx5_flow_table *ft = ft_prio->flow_table; 2166 struct mlx5_ib_flow_handler *handler; 2167 struct mlx5_flow_spec *spec; 2168 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2169 unsigned int spec_index; 2170 struct mlx5_flow_act flow_act = {}; 2171 2172 u32 action; 2173 int err = 0; 2174 2175 if (!is_valid_attr(flow_attr)) 2176 return ERR_PTR(-EINVAL); 2177 2178 spec = mlx5_vzalloc(sizeof(*spec)); 2179 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2180 if (!handler || !spec) { 2181 err = -ENOMEM; 2182 goto free; 2183 } 2184 2185 spec->flow_context.flags = FLOW_CONTEXT_HAS_TAG; 2186 spec->flow_context.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2187 2188 INIT_LIST_HEAD(&handler->list); 2189 2190 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2191 err = parse_flow_attr(spec->match_criteria, 2192 spec->match_value, ib_flow); 2193 if (err < 0) 2194 goto free; 2195 2196 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2197 } 2198 2199 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2200 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 0; 2201 flow_act.action = action; 2202 handler->rule = mlx5_add_flow_rules(ft, spec, &flow_act, dst, 1); 2203 2204 if (IS_ERR(handler->rule)) { 2205 err = PTR_ERR(handler->rule); 2206 goto free; 2207 } 2208 2209 ft_prio->refcount++; 2210 handler->prio = ft_prio; 2211 2212 ft_prio->flow_table = ft; 2213 free: 2214 if (err) 2215 kfree(handler); 2216 kvfree(spec); 2217 return err ? ERR_PTR(err) : handler; 2218 } 2219 2220 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2221 struct mlx5_ib_flow_prio *ft_prio, 2222 struct ib_flow_attr *flow_attr, 2223 struct mlx5_flow_destination *dst) 2224 { 2225 struct mlx5_ib_flow_handler *handler_dst = NULL; 2226 struct mlx5_ib_flow_handler *handler = NULL; 2227 2228 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2229 if (!IS_ERR(handler)) { 2230 handler_dst = create_flow_rule(dev, ft_prio, 2231 flow_attr, dst); 2232 if (IS_ERR(handler_dst)) { 2233 mlx5_del_flow_rules(&handler->rule); 2234 ft_prio->refcount--; 2235 kfree(handler); 2236 handler = handler_dst; 2237 } else { 2238 list_add(&handler_dst->list, &handler->list); 2239 } 2240 } 2241 2242 return handler; 2243 } 2244 enum { 2245 LEFTOVERS_MC, 2246 LEFTOVERS_UC, 2247 }; 2248 2249 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2250 struct mlx5_ib_flow_prio *ft_prio, 2251 struct ib_flow_attr *flow_attr, 2252 struct mlx5_flow_destination *dst) 2253 { 2254 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2255 struct mlx5_ib_flow_handler *handler = NULL; 2256 2257 static struct { 2258 struct ib_flow_attr flow_attr; 2259 struct ib_flow_spec_eth eth_flow; 2260 } leftovers_specs[] = { 2261 [LEFTOVERS_MC] = { 2262 .flow_attr = { 2263 .num_of_specs = 1, 2264 .size = sizeof(leftovers_specs[0]) 2265 }, 2266 .eth_flow = { 2267 .type = IB_FLOW_SPEC_ETH, 2268 .size = sizeof(struct ib_flow_spec_eth), 2269 .mask = {.dst_mac = {0x1} }, 2270 .val = {.dst_mac = {0x1} } 2271 } 2272 }, 2273 [LEFTOVERS_UC] = { 2274 .flow_attr = { 2275 .num_of_specs = 1, 2276 .size = sizeof(leftovers_specs[0]) 2277 }, 2278 .eth_flow = { 2279 .type = IB_FLOW_SPEC_ETH, 2280 .size = sizeof(struct ib_flow_spec_eth), 2281 .mask = {.dst_mac = {0x1} }, 2282 .val = {.dst_mac = {} } 2283 } 2284 } 2285 }; 2286 2287 handler = create_flow_rule(dev, ft_prio, 2288 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2289 dst); 2290 if (!IS_ERR(handler) && 2291 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2292 handler_ucast = create_flow_rule(dev, ft_prio, 2293 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2294 dst); 2295 if (IS_ERR(handler_ucast)) { 2296 mlx5_del_flow_rules(&handler->rule); 2297 ft_prio->refcount--; 2298 kfree(handler); 2299 handler = handler_ucast; 2300 } else { 2301 list_add(&handler_ucast->list, &handler->list); 2302 } 2303 } 2304 2305 return handler; 2306 } 2307 2308 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2309 struct mlx5_ib_flow_prio *ft_rx, 2310 struct mlx5_ib_flow_prio *ft_tx, 2311 struct mlx5_flow_destination *dst) 2312 { 2313 struct mlx5_ib_flow_handler *handler_rx; 2314 struct mlx5_ib_flow_handler *handler_tx; 2315 int err; 2316 static const struct ib_flow_attr flow_attr = { 2317 .num_of_specs = 0, 2318 .type = IB_FLOW_ATTR_SNIFFER, 2319 .size = sizeof(flow_attr) 2320 }; 2321 2322 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2323 if (IS_ERR(handler_rx)) { 2324 err = PTR_ERR(handler_rx); 2325 goto err; 2326 } 2327 2328 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2329 if (IS_ERR(handler_tx)) { 2330 err = PTR_ERR(handler_tx); 2331 goto err_tx; 2332 } 2333 2334 list_add(&handler_tx->list, &handler_rx->list); 2335 2336 return handler_rx; 2337 2338 err_tx: 2339 mlx5_del_flow_rules(&handler_rx->rule); 2340 ft_rx->refcount--; 2341 kfree(handler_rx); 2342 err: 2343 return ERR_PTR(err); 2344 } 2345 2346 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2347 struct ib_flow_attr *flow_attr, 2348 int domain, 2349 struct ib_udata *udata) 2350 { 2351 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2352 struct mlx5_ib_qp *mqp = to_mqp(qp); 2353 struct mlx5_ib_flow_handler *handler = NULL; 2354 struct mlx5_flow_destination *dst = NULL; 2355 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2356 struct mlx5_ib_flow_prio *ft_prio; 2357 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 2358 size_t min_ucmd_sz, required_ucmd_sz; 2359 int err; 2360 2361 if (udata && udata->inlen) { 2362 min_ucmd_sz = offsetofend(struct mlx5_ib_create_flow, reserved); 2363 if (udata->inlen < min_ucmd_sz) 2364 return ERR_PTR(-EOPNOTSUPP); 2365 2366 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 2367 if (err) 2368 return ERR_PTR(err); 2369 2370 /* currently supports only one counters data */ 2371 if (ucmd_hdr.ncounters_data > 1) 2372 return ERR_PTR(-EINVAL); 2373 2374 required_ucmd_sz = min_ucmd_sz + 2375 sizeof(struct mlx5_ib_flow_counters_data) * 2376 ucmd_hdr.ncounters_data; 2377 if (udata->inlen > required_ucmd_sz && 2378 !ib_is_udata_cleared(udata, required_ucmd_sz, 2379 udata->inlen - required_ucmd_sz)) 2380 return ERR_PTR(-EOPNOTSUPP); 2381 2382 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 2383 if (!ucmd) 2384 return ERR_PTR(-ENOMEM); 2385 2386 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 2387 if (err) 2388 goto free_ucmd; 2389 } 2390 2391 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 2392 err = -ENOMEM; 2393 goto free_ucmd; 2394 } 2395 2396 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2397 err = -EINVAL; 2398 goto free_ucmd; 2399 } 2400 2401 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2402 if (!dst) { 2403 err = -ENOMEM; 2404 goto free_ucmd; 2405 } 2406 2407 mutex_lock(&dev->flow_db.lock); 2408 2409 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2410 if (IS_ERR(ft_prio)) { 2411 err = PTR_ERR(ft_prio); 2412 goto unlock; 2413 } 2414 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2415 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2416 if (IS_ERR(ft_prio_tx)) { 2417 err = PTR_ERR(ft_prio_tx); 2418 ft_prio_tx = NULL; 2419 goto destroy_ft; 2420 } 2421 } 2422 2423 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2424 if (mqp->flags & MLX5_IB_QP_RSS) 2425 dst->tir_num = mqp->rss_qp.tirn; 2426 else 2427 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2428 2429 switch (flow_attr->type) { 2430 case IB_FLOW_ATTR_NORMAL: 2431 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2432 err = -EOPNOTSUPP; 2433 goto destroy_ft; 2434 } 2435 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2436 handler = create_dont_trap_rule(dev, ft_prio, flow_attr, dst); 2437 } else { 2438 handler = create_flow_rule(dev, ft_prio, flow_attr, dst); 2439 } 2440 break; 2441 case IB_FLOW_ATTR_ALL_DEFAULT: 2442 case IB_FLOW_ATTR_MC_DEFAULT: 2443 handler = create_leftovers_rule(dev, ft_prio, flow_attr, dst); 2444 break; 2445 case IB_FLOW_ATTR_SNIFFER: 2446 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2447 break; 2448 default: 2449 err = -EINVAL; 2450 goto destroy_ft; 2451 } 2452 2453 if (IS_ERR(handler)) { 2454 err = PTR_ERR(handler); 2455 handler = NULL; 2456 goto destroy_ft; 2457 } 2458 2459 mutex_unlock(&dev->flow_db.lock); 2460 kfree(dst); 2461 kfree(ucmd); 2462 2463 return &handler->ibflow; 2464 2465 destroy_ft: 2466 put_flow_table(dev, ft_prio, false); 2467 if (ft_prio_tx) 2468 put_flow_table(dev, ft_prio_tx, false); 2469 unlock: 2470 mutex_unlock(&dev->flow_db.lock); 2471 kfree(dst); 2472 free_ucmd: 2473 kfree(ucmd); 2474 return ERR_PTR(err); 2475 } 2476 2477 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2478 { 2479 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2480 int err; 2481 2482 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2483 if (err) 2484 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2485 ibqp->qp_num, gid->raw); 2486 2487 return err; 2488 } 2489 2490 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2491 { 2492 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2493 int err; 2494 2495 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2496 if (err) 2497 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2498 ibqp->qp_num, gid->raw); 2499 2500 return err; 2501 } 2502 2503 static int init_node_data(struct mlx5_ib_dev *dev) 2504 { 2505 int err; 2506 2507 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2508 if (err) 2509 return err; 2510 2511 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2512 } 2513 2514 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2515 char *buf) 2516 { 2517 struct mlx5_ib_dev *dev = 2518 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2519 2520 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2521 } 2522 2523 static ssize_t show_reg_pages(struct device *device, 2524 struct device_attribute *attr, char *buf) 2525 { 2526 struct mlx5_ib_dev *dev = 2527 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2528 2529 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2530 } 2531 2532 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2533 char *buf) 2534 { 2535 struct mlx5_ib_dev *dev = 2536 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2537 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2538 } 2539 2540 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2541 char *buf) 2542 { 2543 struct mlx5_ib_dev *dev = 2544 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2545 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2546 } 2547 2548 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2549 char *buf) 2550 { 2551 struct mlx5_ib_dev *dev = 2552 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2553 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2554 dev->mdev->board_id); 2555 } 2556 2557 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2558 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2559 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2560 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2561 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2562 2563 static struct device_attribute *mlx5_class_attributes[] = { 2564 &dev_attr_hw_rev, 2565 &dev_attr_hca_type, 2566 &dev_attr_board_id, 2567 &dev_attr_fw_pages, 2568 &dev_attr_reg_pages, 2569 }; 2570 2571 static void pkey_change_handler(struct work_struct *work) 2572 { 2573 struct mlx5_ib_port_resources *ports = 2574 container_of(work, struct mlx5_ib_port_resources, 2575 pkey_change_work); 2576 2577 mutex_lock(&ports->devr->mutex); 2578 mlx5_ib_gsi_pkey_change(ports->gsi); 2579 mutex_unlock(&ports->devr->mutex); 2580 } 2581 2582 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2583 { 2584 struct mlx5_ib_qp *mqp; 2585 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2586 struct mlx5_core_cq *mcq; 2587 struct list_head cq_armed_list; 2588 unsigned long flags_qp; 2589 unsigned long flags_cq; 2590 unsigned long flags; 2591 2592 INIT_LIST_HEAD(&cq_armed_list); 2593 2594 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2595 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2596 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2597 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2598 if (mqp->sq.tail != mqp->sq.head) { 2599 send_mcq = to_mcq(mqp->ibqp.send_cq); 2600 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2601 if (send_mcq->mcq.comp && 2602 mqp->ibqp.send_cq->comp_handler) { 2603 if (!send_mcq->mcq.reset_notify_added) { 2604 send_mcq->mcq.reset_notify_added = 1; 2605 list_add_tail(&send_mcq->mcq.reset_notify, 2606 &cq_armed_list); 2607 } 2608 } 2609 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2610 } 2611 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2612 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2613 /* no handling is needed for SRQ */ 2614 if (!mqp->ibqp.srq) { 2615 if (mqp->rq.tail != mqp->rq.head) { 2616 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2617 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2618 if (recv_mcq->mcq.comp && 2619 mqp->ibqp.recv_cq->comp_handler) { 2620 if (!recv_mcq->mcq.reset_notify_added) { 2621 recv_mcq->mcq.reset_notify_added = 1; 2622 list_add_tail(&recv_mcq->mcq.reset_notify, 2623 &cq_armed_list); 2624 } 2625 } 2626 spin_unlock_irqrestore(&recv_mcq->lock, 2627 flags_cq); 2628 } 2629 } 2630 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2631 } 2632 /*At that point all inflight post send were put to be executed as of we 2633 * lock/unlock above locks Now need to arm all involved CQs. 2634 */ 2635 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2636 mcq->comp(mcq, NULL); 2637 } 2638 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2639 } 2640 2641 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2642 enum mlx5_dev_event event, unsigned long param) 2643 { 2644 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2645 struct ib_event ibev; 2646 bool fatal = false; 2647 u8 port = (u8)param; 2648 2649 switch (event) { 2650 case MLX5_DEV_EVENT_SYS_ERROR: 2651 ibev.event = IB_EVENT_DEVICE_FATAL; 2652 mlx5_ib_handle_internal_error(ibdev); 2653 fatal = true; 2654 break; 2655 2656 case MLX5_DEV_EVENT_PORT_UP: 2657 case MLX5_DEV_EVENT_PORT_DOWN: 2658 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2659 /* In RoCE, port up/down events are handled in 2660 * mlx5_netdev_event(). 2661 */ 2662 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2663 IB_LINK_LAYER_ETHERNET) 2664 return; 2665 2666 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2667 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2668 break; 2669 2670 case MLX5_DEV_EVENT_LID_CHANGE: 2671 ibev.event = IB_EVENT_LID_CHANGE; 2672 break; 2673 2674 case MLX5_DEV_EVENT_PKEY_CHANGE: 2675 ibev.event = IB_EVENT_PKEY_CHANGE; 2676 2677 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2678 break; 2679 2680 case MLX5_DEV_EVENT_GUID_CHANGE: 2681 ibev.event = IB_EVENT_GID_CHANGE; 2682 break; 2683 2684 case MLX5_DEV_EVENT_CLIENT_REREG: 2685 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2686 break; 2687 2688 default: 2689 /* unsupported event */ 2690 return; 2691 } 2692 2693 ibev.device = &ibdev->ib_dev; 2694 ibev.element.port_num = port; 2695 2696 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2697 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2698 return; 2699 } 2700 2701 if (ibdev->ib_active) 2702 ib_dispatch_event(&ibev); 2703 2704 if (fatal) 2705 ibdev->ib_active = false; 2706 } 2707 2708 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2709 { 2710 int port; 2711 2712 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2713 mlx5_query_ext_port_caps(dev, port); 2714 } 2715 2716 static int get_port_caps(struct mlx5_ib_dev *dev) 2717 { 2718 struct ib_device_attr *dprops = NULL; 2719 struct ib_port_attr *pprops = NULL; 2720 int err = -ENOMEM; 2721 int port; 2722 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2723 2724 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2725 if (!pprops) 2726 goto out; 2727 2728 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2729 if (!dprops) 2730 goto out; 2731 2732 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2733 if (err) { 2734 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2735 goto out; 2736 } 2737 2738 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2739 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2740 if (err) { 2741 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2742 port, err); 2743 break; 2744 } 2745 dev->mdev->port_caps[port - 1].pkey_table_len = 2746 dprops->max_pkeys; 2747 dev->mdev->port_caps[port - 1].gid_table_len = 2748 pprops->gid_tbl_len; 2749 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2750 dprops->max_pkeys, pprops->gid_tbl_len); 2751 } 2752 2753 out: 2754 kfree(pprops); 2755 kfree(dprops); 2756 2757 return err; 2758 } 2759 2760 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2761 { 2762 int err; 2763 2764 err = mlx5_mr_cache_cleanup(dev); 2765 if (err) 2766 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2767 2768 if (dev->umrc.qp) 2769 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 2770 if (dev->umrc.cq) 2771 ib_free_cq(dev->umrc.cq); 2772 if (dev->umrc.pd) 2773 ib_dealloc_pd(dev->umrc.pd); 2774 } 2775 2776 enum { 2777 MAX_UMR_WR = 128, 2778 }; 2779 2780 static int create_umr_res(struct mlx5_ib_dev *dev) 2781 { 2782 struct ib_qp_init_attr *init_attr = NULL; 2783 struct ib_qp_attr *attr = NULL; 2784 struct ib_pd *pd; 2785 struct ib_cq *cq; 2786 struct ib_qp *qp; 2787 int ret; 2788 2789 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2790 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2791 if (!attr || !init_attr) { 2792 ret = -ENOMEM; 2793 goto error_0; 2794 } 2795 2796 pd = ib_alloc_pd(&dev->ib_dev, 0); 2797 if (IS_ERR(pd)) { 2798 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2799 ret = PTR_ERR(pd); 2800 goto error_0; 2801 } 2802 2803 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2804 if (IS_ERR(cq)) { 2805 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2806 ret = PTR_ERR(cq); 2807 goto error_2; 2808 } 2809 2810 init_attr->send_cq = cq; 2811 init_attr->recv_cq = cq; 2812 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2813 init_attr->cap.max_send_wr = MAX_UMR_WR; 2814 init_attr->cap.max_send_sge = 1; 2815 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2816 init_attr->port_num = 1; 2817 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2818 if (IS_ERR(qp)) { 2819 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2820 ret = PTR_ERR(qp); 2821 goto error_3; 2822 } 2823 qp->device = &dev->ib_dev; 2824 qp->real_qp = qp; 2825 qp->uobject = NULL; 2826 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2827 2828 attr->qp_state = IB_QPS_INIT; 2829 attr->port_num = 1; 2830 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2831 IB_QP_PORT, NULL); 2832 if (ret) { 2833 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2834 goto error_4; 2835 } 2836 2837 memset(attr, 0, sizeof(*attr)); 2838 attr->qp_state = IB_QPS_RTR; 2839 attr->path_mtu = IB_MTU_256; 2840 2841 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2842 if (ret) { 2843 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2844 goto error_4; 2845 } 2846 2847 memset(attr, 0, sizeof(*attr)); 2848 attr->qp_state = IB_QPS_RTS; 2849 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2850 if (ret) { 2851 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2852 goto error_4; 2853 } 2854 2855 dev->umrc.qp = qp; 2856 dev->umrc.cq = cq; 2857 dev->umrc.pd = pd; 2858 2859 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2860 ret = mlx5_mr_cache_init(dev); 2861 if (ret) { 2862 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2863 goto error_4; 2864 } 2865 2866 kfree(attr); 2867 kfree(init_attr); 2868 2869 return 0; 2870 2871 error_4: 2872 mlx5_ib_destroy_qp(qp, NULL); 2873 dev->umrc.qp = NULL; 2874 2875 error_3: 2876 ib_free_cq(cq); 2877 dev->umrc.cq = NULL; 2878 2879 error_2: 2880 ib_dealloc_pd(pd); 2881 dev->umrc.pd = NULL; 2882 2883 error_0: 2884 kfree(attr); 2885 kfree(init_attr); 2886 return ret; 2887 } 2888 2889 static int create_dev_resources(struct mlx5_ib_resources *devr) 2890 { 2891 struct ib_srq_init_attr attr; 2892 struct mlx5_ib_dev *dev; 2893 struct ib_device *ibdev; 2894 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2895 int port; 2896 int ret = 0; 2897 2898 dev = container_of(devr, struct mlx5_ib_dev, devr); 2899 ibdev = &dev->ib_dev; 2900 2901 mutex_init(&devr->mutex); 2902 2903 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 2904 if (!devr->p0) 2905 return -ENOMEM; 2906 2907 devr->p0->device = ibdev; 2908 devr->p0->uobject = NULL; 2909 atomic_set(&devr->p0->usecnt, 0); 2910 2911 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 2912 if (ret) 2913 goto error0; 2914 2915 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 2916 if (!devr->c0) { 2917 ret = -ENOMEM; 2918 goto error1; 2919 } 2920 2921 devr->c0->device = &dev->ib_dev; 2922 atomic_set(&devr->c0->usecnt, 0); 2923 2924 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 2925 if (ret) 2926 goto err_create_cq; 2927 2928 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 2929 if (IS_ERR(devr->x0)) { 2930 ret = PTR_ERR(devr->x0); 2931 goto error2; 2932 } 2933 devr->x0->device = &dev->ib_dev; 2934 devr->x0->inode = NULL; 2935 atomic_set(&devr->x0->usecnt, 0); 2936 mutex_init(&devr->x0->tgt_qp_mutex); 2937 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2938 2939 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 2940 if (IS_ERR(devr->x1)) { 2941 ret = PTR_ERR(devr->x1); 2942 goto error3; 2943 } 2944 devr->x1->device = &dev->ib_dev; 2945 devr->x1->inode = NULL; 2946 atomic_set(&devr->x1->usecnt, 0); 2947 mutex_init(&devr->x1->tgt_qp_mutex); 2948 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2949 2950 memset(&attr, 0, sizeof(attr)); 2951 attr.attr.max_sge = 1; 2952 attr.attr.max_wr = 1; 2953 attr.srq_type = IB_SRQT_XRC; 2954 attr.ext.cq = devr->c0; 2955 attr.ext.xrc.xrcd = devr->x0; 2956 2957 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2958 if (!devr->s0) { 2959 ret = -ENOMEM; 2960 goto error4; 2961 } 2962 2963 devr->s0->device = &dev->ib_dev; 2964 devr->s0->pd = devr->p0; 2965 devr->s0->srq_type = IB_SRQT_XRC; 2966 devr->s0->ext.xrc.xrcd = devr->x0; 2967 devr->s0->ext.cq = devr->c0; 2968 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 2969 if (ret) 2970 goto err_create; 2971 2972 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2973 atomic_inc(&devr->s0->ext.cq->usecnt); 2974 atomic_inc(&devr->p0->usecnt); 2975 atomic_set(&devr->s0->usecnt, 0); 2976 2977 memset(&attr, 0, sizeof(attr)); 2978 attr.attr.max_sge = 1; 2979 attr.attr.max_wr = 1; 2980 attr.srq_type = IB_SRQT_BASIC; 2981 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2982 if (!devr->s1) { 2983 ret = -ENOMEM; 2984 goto error5; 2985 } 2986 2987 devr->s1->device = &dev->ib_dev; 2988 devr->s1->pd = devr->p0; 2989 devr->s1->srq_type = IB_SRQT_BASIC; 2990 devr->s1->ext.cq = devr->c0; 2991 2992 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 2993 if (ret) 2994 goto error6; 2995 2996 atomic_inc(&devr->p0->usecnt); 2997 atomic_set(&devr->s1->usecnt, 0); 2998 2999 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3000 INIT_WORK(&devr->ports[port].pkey_change_work, 3001 pkey_change_handler); 3002 devr->ports[port].devr = devr; 3003 } 3004 3005 return 0; 3006 3007 error6: 3008 kfree(devr->s1); 3009 error5: 3010 mlx5_ib_destroy_srq(devr->s0, NULL); 3011 err_create: 3012 kfree(devr->s0); 3013 error4: 3014 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 3015 error3: 3016 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 3017 error2: 3018 mlx5_ib_destroy_cq(devr->c0, NULL); 3019 err_create_cq: 3020 kfree(devr->c0); 3021 error1: 3022 mlx5_ib_dealloc_pd(devr->p0, NULL); 3023 error0: 3024 kfree(devr->p0); 3025 return ret; 3026 } 3027 3028 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3029 { 3030 int port; 3031 3032 mlx5_ib_destroy_srq(devr->s1, NULL); 3033 kfree(devr->s1); 3034 mlx5_ib_destroy_srq(devr->s0, NULL); 3035 kfree(devr->s0); 3036 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 3037 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 3038 mlx5_ib_destroy_cq(devr->c0, NULL); 3039 kfree(devr->c0); 3040 mlx5_ib_dealloc_pd(devr->p0, NULL); 3041 kfree(devr->p0); 3042 3043 /* Make sure no change P_Key work items are still executing */ 3044 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3045 cancel_work_sync(&devr->ports[port].pkey_change_work); 3046 } 3047 3048 static u32 get_core_cap_flags(struct ib_device *ibdev) 3049 { 3050 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3051 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3052 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3053 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3054 u32 ret = 0; 3055 3056 if (ll == IB_LINK_LAYER_INFINIBAND) 3057 return RDMA_CORE_PORT_IBA_IB; 3058 3059 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3060 return 0; 3061 3062 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3063 return 0; 3064 3065 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3066 ret |= RDMA_CORE_PORT_IBA_ROCE; 3067 3068 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3069 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3070 3071 return ret; 3072 } 3073 3074 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3075 struct ib_port_immutable *immutable) 3076 { 3077 struct ib_port_attr attr; 3078 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3079 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3080 int err; 3081 3082 err = mlx5_ib_query_port(ibdev, port_num, &attr); 3083 if (err) 3084 return err; 3085 3086 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3087 immutable->gid_tbl_len = attr.gid_tbl_len; 3088 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3089 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3090 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3091 3092 return 0; 3093 } 3094 3095 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 3096 size_t str_len) 3097 { 3098 struct mlx5_ib_dev *dev = 3099 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3100 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 3101 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 3102 } 3103 3104 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 3105 { 3106 return 0; 3107 } 3108 3109 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 3110 { 3111 } 3112 3113 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 3114 { 3115 if (dev->roce.nb.notifier_call) { 3116 unregister_netdevice_notifier(&dev->roce.nb); 3117 dev->roce.nb.notifier_call = NULL; 3118 } 3119 } 3120 3121 static int 3122 mlx5_enable_roce_if_cb(if_t ifp, void *arg) 3123 { 3124 struct mlx5_ib_dev *dev = arg; 3125 3126 /* check if network interface belongs to mlx5en */ 3127 if (!mlx5_netdev_match(ifp, dev->mdev, "mce")) 3128 return (0); 3129 3130 write_lock(&dev->roce.netdev_lock); 3131 dev->roce.netdev = ifp; 3132 write_unlock(&dev->roce.netdev_lock); 3133 3134 return (0); 3135 } 3136 3137 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 3138 { 3139 struct epoch_tracker et; 3140 VNET_ITERATOR_DECL(vnet_iter); 3141 int err; 3142 3143 /* Check if mlx5en net device already exists */ 3144 VNET_LIST_RLOCK(); 3145 NET_EPOCH_ENTER(et); 3146 VNET_FOREACH(vnet_iter) { 3147 CURVNET_SET_QUIET(vnet_iter); 3148 if_foreach(mlx5_enable_roce_if_cb, dev); 3149 CURVNET_RESTORE(); 3150 } 3151 NET_EPOCH_EXIT(et); 3152 VNET_LIST_RUNLOCK(); 3153 3154 dev->roce.nb.notifier_call = mlx5_netdev_event; 3155 err = register_netdevice_notifier(&dev->roce.nb); 3156 if (err) { 3157 dev->roce.nb.notifier_call = NULL; 3158 return err; 3159 } 3160 3161 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3162 err = mlx5_nic_vport_enable_roce(dev->mdev); 3163 if (err) 3164 goto err_unregister_netdevice_notifier; 3165 } 3166 3167 err = mlx5_roce_lag_init(dev); 3168 if (err) 3169 goto err_disable_roce; 3170 3171 return 0; 3172 3173 err_disable_roce: 3174 if (MLX5_CAP_GEN(dev->mdev, roce)) 3175 mlx5_nic_vport_disable_roce(dev->mdev); 3176 3177 err_unregister_netdevice_notifier: 3178 mlx5_remove_roce_notifier(dev); 3179 return err; 3180 } 3181 3182 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 3183 { 3184 mlx5_roce_lag_cleanup(dev); 3185 if (MLX5_CAP_GEN(dev->mdev, roce)) 3186 mlx5_nic_vport_disable_roce(dev->mdev); 3187 } 3188 3189 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 3190 { 3191 mlx5_vport_dealloc_q_counter(dev->mdev, 3192 MLX5_INTERFACE_PROTOCOL_IB, 3193 dev->port[port_num].q_cnt_id); 3194 dev->port[port_num].q_cnt_id = 0; 3195 } 3196 3197 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 3198 { 3199 unsigned int i; 3200 3201 for (i = 0; i < dev->num_ports; i++) 3202 mlx5_ib_dealloc_q_port_counter(dev, i); 3203 } 3204 3205 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 3206 { 3207 int i; 3208 int ret; 3209 3210 for (i = 0; i < dev->num_ports; i++) { 3211 ret = mlx5_vport_alloc_q_counter(dev->mdev, 3212 MLX5_INTERFACE_PROTOCOL_IB, 3213 &dev->port[i].q_cnt_id); 3214 if (ret) { 3215 mlx5_ib_warn(dev, 3216 "couldn't allocate queue counter for port %d, err %d\n", 3217 i + 1, ret); 3218 goto dealloc_counters; 3219 } 3220 } 3221 3222 return 0; 3223 3224 dealloc_counters: 3225 while (--i >= 0) 3226 mlx5_ib_dealloc_q_port_counter(dev, i); 3227 3228 return ret; 3229 } 3230 3231 static const char * const names[] = { 3232 "rx_write_requests", 3233 "rx_read_requests", 3234 "rx_atomic_requests", 3235 "out_of_buffer", 3236 "out_of_sequence", 3237 "duplicate_request", 3238 "rnr_nak_retry_err", 3239 "packet_seq_err", 3240 "implied_nak_seq_err", 3241 "local_ack_timeout_err", 3242 }; 3243 3244 static const size_t stats_offsets[] = { 3245 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 3246 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 3247 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 3248 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 3249 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 3250 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 3251 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 3252 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 3253 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 3254 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 3255 }; 3256 3257 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3258 u8 port_num) 3259 { 3260 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 3261 3262 /* We support only per port stats */ 3263 if (port_num == 0) 3264 return NULL; 3265 3266 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 3267 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3268 } 3269 3270 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3271 struct rdma_hw_stats *stats, 3272 u8 port, int index) 3273 { 3274 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3275 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3276 void *out; 3277 __be32 val; 3278 int ret; 3279 int i; 3280 3281 if (!port || !stats) 3282 return -ENOSYS; 3283 3284 out = mlx5_vzalloc(outlen); 3285 if (!out) 3286 return -ENOMEM; 3287 3288 ret = mlx5_vport_query_q_counter(dev->mdev, 3289 dev->port[port - 1].q_cnt_id, 0, 3290 out, outlen); 3291 if (ret) 3292 goto free; 3293 3294 for (i = 0; i < ARRAY_SIZE(names); i++) { 3295 val = *(__be32 *)(out + stats_offsets[i]); 3296 stats->value[i] = (u64)be32_to_cpu(val); 3297 } 3298 free: 3299 kvfree(out); 3300 return ARRAY_SIZE(names); 3301 } 3302 3303 static int mlx5_ib_stage_bfreg_init(struct mlx5_ib_dev *dev) 3304 { 3305 int err; 3306 3307 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3308 if (err) 3309 return err; 3310 3311 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3312 if (err) { 3313 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3314 return err; 3315 } 3316 3317 err = mlx5_alloc_bfreg(dev->mdev, &dev->wc_bfreg, true, false); 3318 if (err) { 3319 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3320 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3321 } 3322 3323 return err; 3324 } 3325 3326 static void mlx5_ib_stage_bfreg_cleanup(struct mlx5_ib_dev *dev) 3327 { 3328 mlx5_free_bfreg(dev->mdev, &dev->wc_bfreg); 3329 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3330 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3331 } 3332 3333 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3334 { 3335 struct mlx5_ib_dev *dev; 3336 enum rdma_link_layer ll; 3337 int port_type_cap; 3338 int err; 3339 int i; 3340 3341 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3342 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3343 3344 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3345 if (!dev) 3346 return NULL; 3347 3348 dev->mdev = mdev; 3349 3350 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3351 GFP_KERNEL); 3352 if (!dev->port) 3353 goto err_dealloc; 3354 3355 rwlock_init(&dev->roce.netdev_lock); 3356 err = get_port_caps(dev); 3357 if (err) 3358 goto err_free_port; 3359 3360 if (mlx5_use_mad_ifc(dev)) 3361 get_ext_port_caps(dev); 3362 3363 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3364 3365 mutex_init(&dev->lb_mutex); 3366 3367 INIT_IB_DEVICE_OPS(&dev->ib_dev.ops, mlx5, MLX5); 3368 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 3369 dev->ib_dev.owner = THIS_MODULE; 3370 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3371 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3372 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3373 dev->ib_dev.phys_port_cnt = dev->num_ports; 3374 dev->ib_dev.num_comp_vectors = 3375 dev->mdev->priv.eq_table.num_comp_vectors; 3376 dev->ib_dev.dma_device = &mdev->pdev->dev; 3377 3378 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3379 dev->ib_dev.uverbs_cmd_mask = 3380 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3381 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3382 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3383 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3384 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3385 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3386 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3387 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3388 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3389 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3390 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3391 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3392 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3393 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3394 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3395 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3396 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3397 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3398 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3399 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3400 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3401 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3402 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3403 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3404 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3405 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3406 dev->ib_dev.uverbs_ex_cmd_mask = 3407 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3408 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3409 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3410 3411 dev->ib_dev.query_device = mlx5_ib_query_device; 3412 dev->ib_dev.query_port = mlx5_ib_query_port; 3413 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3414 if (ll == IB_LINK_LAYER_ETHERNET) 3415 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3416 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3417 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3418 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3419 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3420 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3421 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3422 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3423 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3424 dev->ib_dev.mmap = mlx5_ib_mmap; 3425 dev->ib_dev.mmap_free = mlx5_ib_mmap_free; 3426 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3427 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3428 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3429 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3430 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3431 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3432 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3433 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3434 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3435 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3436 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3437 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3438 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3439 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3440 dev->ib_dev.post_send = mlx5_ib_post_send; 3441 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3442 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3443 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3444 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3445 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3446 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3447 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3448 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3449 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3450 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3451 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3452 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3453 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3454 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3455 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3456 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3457 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3458 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3459 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3460 if (mlx5_core_is_pf(mdev)) { 3461 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3462 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3463 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3464 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3465 } 3466 3467 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3468 3469 mlx5_ib_internal_fill_odp_caps(dev); 3470 3471 if (MLX5_CAP_GEN(mdev, imaicl)) { 3472 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3473 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3474 dev->ib_dev.uverbs_cmd_mask |= 3475 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3476 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3477 } 3478 3479 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3480 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3481 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3482 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3483 } 3484 3485 if (MLX5_CAP_GEN(mdev, xrc)) { 3486 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3487 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3488 dev->ib_dev.uverbs_cmd_mask |= 3489 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3490 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3491 } 3492 3493 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3494 IB_LINK_LAYER_ETHERNET) { 3495 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3496 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3497 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3498 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3499 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3500 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3501 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3502 dev->ib_dev.uverbs_ex_cmd_mask |= 3503 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3504 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3505 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3506 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3507 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3508 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3509 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3510 } 3511 err = init_node_data(dev); 3512 if (err) 3513 goto err_free_port; 3514 3515 mutex_init(&dev->flow_db.lock); 3516 mutex_init(&dev->cap_mask_mutex); 3517 INIT_LIST_HEAD(&dev->qp_list); 3518 spin_lock_init(&dev->reset_flow_resource_lock); 3519 3520 if (ll == IB_LINK_LAYER_ETHERNET) { 3521 err = mlx5_enable_roce(dev); 3522 if (err) 3523 goto err_free_port; 3524 } 3525 3526 err = create_dev_resources(&dev->devr); 3527 if (err) 3528 goto err_disable_roce; 3529 3530 err = mlx5_ib_odp_init_one(dev); 3531 if (err) 3532 goto err_rsrc; 3533 3534 err = mlx5_ib_alloc_q_counters(dev); 3535 if (err) 3536 goto err_odp; 3537 3538 err = mlx5_ib_stage_bfreg_init(dev); 3539 if (err) 3540 goto err_q_cnt; 3541 3542 err = ib_register_device(&dev->ib_dev, NULL); 3543 if (err) 3544 goto err_bfreg; 3545 3546 err = create_umr_res(dev); 3547 if (err) 3548 goto err_dev; 3549 3550 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3551 err = device_create_file(&dev->ib_dev.dev, 3552 mlx5_class_attributes[i]); 3553 if (err) 3554 goto err_umrc; 3555 } 3556 3557 err = mlx5_ib_init_congestion(dev); 3558 if (err) 3559 goto err_umrc; 3560 3561 dev->ib_active = true; 3562 3563 return dev; 3564 3565 err_umrc: 3566 destroy_umrc_res(dev); 3567 3568 err_dev: 3569 ib_unregister_device(&dev->ib_dev); 3570 3571 err_bfreg: 3572 mlx5_ib_stage_bfreg_cleanup(dev); 3573 3574 err_q_cnt: 3575 mlx5_ib_dealloc_q_counters(dev); 3576 3577 err_odp: 3578 mlx5_ib_odp_remove_one(dev); 3579 3580 err_rsrc: 3581 destroy_dev_resources(&dev->devr); 3582 3583 err_disable_roce: 3584 if (ll == IB_LINK_LAYER_ETHERNET) { 3585 mlx5_disable_roce(dev); 3586 mlx5_remove_roce_notifier(dev); 3587 } 3588 3589 err_free_port: 3590 kfree(dev->port); 3591 3592 err_dealloc: 3593 ib_dealloc_device((struct ib_device *)dev); 3594 3595 return NULL; 3596 } 3597 3598 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3599 { 3600 struct mlx5_ib_dev *dev = context; 3601 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3602 3603 mlx5_ib_cleanup_congestion(dev); 3604 mlx5_remove_roce_notifier(dev); 3605 ib_unregister_device(&dev->ib_dev); 3606 mlx5_ib_stage_bfreg_cleanup(dev); 3607 mlx5_ib_dealloc_q_counters(dev); 3608 destroy_umrc_res(dev); 3609 mlx5_ib_odp_remove_one(dev); 3610 destroy_dev_resources(&dev->devr); 3611 if (ll == IB_LINK_LAYER_ETHERNET) 3612 mlx5_disable_roce(dev); 3613 kfree(dev->port); 3614 ib_dealloc_device(&dev->ib_dev); 3615 } 3616 3617 static struct mlx5_interface mlx5_ib_interface = { 3618 .add = mlx5_ib_add, 3619 .remove = mlx5_ib_remove, 3620 .event = mlx5_ib_event, 3621 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3622 }; 3623 3624 static int __init mlx5_ib_init(void) 3625 { 3626 int err; 3627 3628 err = mlx5_ib_odp_init(); 3629 if (err) 3630 return err; 3631 3632 err = mlx5_register_interface(&mlx5_ib_interface); 3633 if (err) 3634 goto clean_odp; 3635 3636 return err; 3637 3638 clean_odp: 3639 mlx5_ib_odp_cleanup(); 3640 return err; 3641 } 3642 3643 static void __exit mlx5_ib_cleanup(void) 3644 { 3645 mlx5_unregister_interface(&mlx5_ib_interface); 3646 mlx5_ib_odp_cleanup(); 3647 } 3648 3649 module_init_order(mlx5_ib_init, SI_ORDER_SEVENTH); 3650 module_exit_order(mlx5_ib_cleanup, SI_ORDER_SEVENTH); 3651