xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583)
1 //===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISC-V specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVELFStreamer.h"
16 #include "RISCVInstPrinter.h"
17 #include "RISCVMCAsmInfo.h"
18 #include "RISCVMCObjectFileInfo.h"
19 #include "RISCVTargetStreamer.h"
20 #include "TargetInfo/RISCVTargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/MC/MCAsmBackend.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCCodeEmitter.h"
25 #include "llvm/MC/MCInstrAnalysis.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCObjectFileInfo.h"
28 #include "llvm/MC/MCObjectWriter.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSubtargetInfo.h"
32 #include "llvm/MC/TargetRegistry.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include <bitset>
35 
36 #define GET_INSTRINFO_MC_DESC
37 #define ENABLE_INSTR_PREDICATE_VERIFIER
38 #include "RISCVGenInstrInfo.inc"
39 
40 #define GET_REGINFO_MC_DESC
41 #include "RISCVGenRegisterInfo.inc"
42 
43 #define GET_SUBTARGETINFO_MC_DESC
44 #include "RISCVGenSubtargetInfo.inc"
45 
46 namespace llvm::RISCVVInversePseudosTable {
47 
48 using namespace RISCV;
49 
50 #define GET_RISCVVInversePseudosTable_IMPL
51 #include "RISCVGenSearchableTables.inc"
52 
53 } // namespace llvm::RISCVVInversePseudosTable
54 
55 using namespace llvm;
56 
createRISCVMCInstrInfo()57 static MCInstrInfo *createRISCVMCInstrInfo() {
58   MCInstrInfo *X = new MCInstrInfo();
59   InitRISCVMCInstrInfo(X);
60   return X;
61 }
62 
createRISCVMCRegisterInfo(const Triple & TT)63 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
64   MCRegisterInfo *X = new MCRegisterInfo();
65   InitRISCVMCRegisterInfo(X, RISCV::X1);
66   return X;
67 }
68 
createRISCVMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT,const MCTargetOptions & Options)69 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
70                                        const Triple &TT,
71                                        const MCTargetOptions &Options) {
72   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
73 
74   MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
75   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
76   MAI->addInitialFrameState(Inst);
77 
78   return MAI;
79 }
80 
81 static MCObjectFileInfo *
createRISCVMCObjectFileInfo(MCContext & Ctx,bool PIC,bool LargeCodeModel=false)82 createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC,
83                             bool LargeCodeModel = false) {
84   MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo();
85   MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel);
86   return MOFI;
87 }
88 
createRISCVMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)89 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
90                                                    StringRef CPU, StringRef FS) {
91   if (CPU.empty() || CPU == "generic")
92     CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
93 
94   return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
95 }
96 
createRISCVMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)97 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
98                                                unsigned SyntaxVariant,
99                                                const MCAsmInfo &MAI,
100                                                const MCInstrInfo &MII,
101                                                const MCRegisterInfo &MRI) {
102   return new RISCVInstPrinter(MAI, MII, MRI);
103 }
104 
105 static MCTargetStreamer *
createRISCVObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)106 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
107   const Triple &TT = STI.getTargetTriple();
108   if (TT.isOSBinFormatELF())
109     return new RISCVTargetELFStreamer(S, STI);
110   return nullptr;
111 }
112 
113 static MCTargetStreamer *
createRISCVAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint)114 createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
115                              MCInstPrinter *InstPrint) {
116   return new RISCVTargetAsmStreamer(S, OS);
117 }
118 
createRISCVNullTargetStreamer(MCStreamer & S)119 static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
120   return new RISCVTargetStreamer(S);
121 }
122 
123 namespace {
124 
125 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
126   int64_t GPRState[31] = {};
127   std::bitset<31> GPRValidMask;
128 
isGPR(unsigned Reg)129   static bool isGPR(unsigned Reg) {
130     return Reg >= RISCV::X0 && Reg <= RISCV::X31;
131   }
132 
getRegIndex(unsigned Reg)133   static unsigned getRegIndex(unsigned Reg) {
134     assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");
135     return Reg - RISCV::X1;
136   }
137 
setGPRState(unsigned Reg,std::optional<int64_t> Value)138   void setGPRState(unsigned Reg, std::optional<int64_t> Value) {
139     if (Reg == RISCV::X0)
140       return;
141 
142     auto Index = getRegIndex(Reg);
143 
144     if (Value) {
145       GPRState[Index] = *Value;
146       GPRValidMask.set(Index);
147     } else {
148       GPRValidMask.reset(Index);
149     }
150   }
151 
getGPRState(unsigned Reg) const152   std::optional<int64_t> getGPRState(unsigned Reg) const {
153     if (Reg == RISCV::X0)
154       return 0;
155 
156     auto Index = getRegIndex(Reg);
157 
158     if (GPRValidMask.test(Index))
159       return GPRState[Index];
160     return std::nullopt;
161   }
162 
163 public:
RISCVMCInstrAnalysis(const MCInstrInfo * Info)164   explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
165       : MCInstrAnalysis(Info) {}
166 
resetState()167   void resetState() override { GPRValidMask.reset(); }
168 
updateState(const MCInst & Inst,uint64_t Addr)169   void updateState(const MCInst &Inst, uint64_t Addr) override {
170     // Terminators mark the end of a basic block which means the sequentially
171     // next instruction will be the first of another basic block and the current
172     // state will typically not be valid anymore. For calls, we assume all
173     // registers may be clobbered by the callee (TODO: should we take the
174     // calling convention into account?).
175     if (isTerminator(Inst) || isCall(Inst)) {
176       resetState();
177       return;
178     }
179 
180     switch (Inst.getOpcode()) {
181     default: {
182       // Clear the state of all defined registers for instructions that we don't
183       // explicitly support.
184       auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
185       for (unsigned I = 0; I < NumDefs; ++I) {
186         auto DefReg = Inst.getOperand(I).getReg();
187         if (isGPR(DefReg))
188           setGPRState(DefReg, std::nullopt);
189       }
190       break;
191     }
192     case RISCV::AUIPC:
193       setGPRState(Inst.getOperand(0).getReg(),
194                   Addr + (Inst.getOperand(1).getImm() << 12));
195       break;
196     }
197   }
198 
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const199   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
200                       uint64_t &Target) const override {
201     if (isConditionalBranch(Inst)) {
202       int64_t Imm;
203       if (Size == 2)
204         Imm = Inst.getOperand(1).getImm();
205       else
206         Imm = Inst.getOperand(2).getImm();
207       Target = Addr + Imm;
208       return true;
209     }
210 
211     if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
212       Target = Addr + Inst.getOperand(0).getImm();
213       return true;
214     }
215 
216     if (Inst.getOpcode() == RISCV::JAL) {
217       Target = Addr + Inst.getOperand(1).getImm();
218       return true;
219     }
220 
221     if (Inst.getOpcode() == RISCV::JALR) {
222       if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
223         Target = *TargetRegState + Inst.getOperand(2).getImm();
224         return true;
225       }
226 
227       return false;
228     }
229 
230     return false;
231   }
232 
isTerminator(const MCInst & Inst) const233   bool isTerminator(const MCInst &Inst) const override {
234     if (MCInstrAnalysis::isTerminator(Inst))
235       return true;
236 
237     switch (Inst.getOpcode()) {
238     default:
239       return false;
240     case RISCV::JAL:
241     case RISCV::JALR:
242       return Inst.getOperand(0).getReg() == RISCV::X0;
243     }
244   }
245 
isCall(const MCInst & Inst) const246   bool isCall(const MCInst &Inst) const override {
247     if (MCInstrAnalysis::isCall(Inst))
248       return true;
249 
250     switch (Inst.getOpcode()) {
251     default:
252       return false;
253     case RISCV::JAL:
254     case RISCV::JALR:
255       return Inst.getOperand(0).getReg() != RISCV::X0;
256     }
257   }
258 
isReturn(const MCInst & Inst) const259   bool isReturn(const MCInst &Inst) const override {
260     if (MCInstrAnalysis::isReturn(Inst))
261       return true;
262 
263     switch (Inst.getOpcode()) {
264     default:
265       return false;
266     case RISCV::JALR:
267       return Inst.getOperand(0).getReg() == RISCV::X0 &&
268              maybeReturnAddress(Inst.getOperand(1).getReg());
269     case RISCV::C_JR:
270       return maybeReturnAddress(Inst.getOperand(0).getReg());
271     }
272   }
273 
isBranch(const MCInst & Inst) const274   bool isBranch(const MCInst &Inst) const override {
275     if (MCInstrAnalysis::isBranch(Inst))
276       return true;
277 
278     return isBranchImpl(Inst);
279   }
280 
isUnconditionalBranch(const MCInst & Inst) const281   bool isUnconditionalBranch(const MCInst &Inst) const override {
282     if (MCInstrAnalysis::isUnconditionalBranch(Inst))
283       return true;
284 
285     return isBranchImpl(Inst);
286   }
287 
isIndirectBranch(const MCInst & Inst) const288   bool isIndirectBranch(const MCInst &Inst) const override {
289     if (MCInstrAnalysis::isIndirectBranch(Inst))
290       return true;
291 
292     switch (Inst.getOpcode()) {
293     default:
294       return false;
295     case RISCV::JALR:
296       return Inst.getOperand(0).getReg() == RISCV::X0 &&
297              !maybeReturnAddress(Inst.getOperand(1).getReg());
298     case RISCV::C_JR:
299       return !maybeReturnAddress(Inst.getOperand(0).getReg());
300     }
301   }
302 
303 private:
maybeReturnAddress(unsigned Reg)304   static bool maybeReturnAddress(unsigned Reg) {
305     // X1 is used for normal returns, X5 for returns from outlined functions.
306     return Reg == RISCV::X1 || Reg == RISCV::X5;
307   }
308 
isBranchImpl(const MCInst & Inst)309   static bool isBranchImpl(const MCInst &Inst) {
310     switch (Inst.getOpcode()) {
311     default:
312       return false;
313     case RISCV::JAL:
314       return Inst.getOperand(0).getReg() == RISCV::X0;
315     case RISCV::JALR:
316       return Inst.getOperand(0).getReg() == RISCV::X0 &&
317              !maybeReturnAddress(Inst.getOperand(1).getReg());
318     case RISCV::C_JR:
319       return !maybeReturnAddress(Inst.getOperand(0).getReg());
320     }
321   }
322 };
323 
324 } // end anonymous namespace
325 
createRISCVInstrAnalysis(const MCInstrInfo * Info)326 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
327   return new RISCVMCInstrAnalysis(Info);
328 }
329 
330 namespace {
createRISCVELFStreamer(const Triple & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && MOW,std::unique_ptr<MCCodeEmitter> && MCE)331 MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context,
332                                    std::unique_ptr<MCAsmBackend> &&MAB,
333                                    std::unique_ptr<MCObjectWriter> &&MOW,
334                                    std::unique_ptr<MCCodeEmitter> &&MCE) {
335   return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
336                                 std::move(MCE));
337 }
338 } // end anonymous namespace
339 
LLVMInitializeRISCVTargetMC()340 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
341   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
342     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
343     TargetRegistry::RegisterMCObjectFileInfo(*T, createRISCVMCObjectFileInfo);
344     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
345     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
346     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
347     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
348     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
349     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
350     TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
351     TargetRegistry::RegisterObjectTargetStreamer(
352         *T, createRISCVObjectTargetStreamer);
353     TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
354 
355     // Register the asm target streamer.
356     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
357     // Register the null target streamer.
358     TargetRegistry::RegisterNullTargetStreamer(*T,
359                                                createRISCVNullTargetStreamer);
360   }
361 }
362