1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MipsMCTargetDesc.h"
14 #include "MipsAsmBackend.h"
15 #include "MipsBaseInfo.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsInstPrinter.h"
18 #include "MipsMCAsmInfo.h"
19 #include "MipsMCNaCl.h"
20 #include "MipsTargetStreamer.h"
21 #include "TargetInfo/MipsTargetInfo.h"
22 #include "llvm/DebugInfo/CodeView/CodeView.h"
23 #include "llvm/MC/MCCodeEmitter.h"
24 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCInstrAnalysis.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCObjectWriter.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/MC/TargetRegistry.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/FormattedStream.h"
35 #include "llvm/TargetParser/Triple.h"
36
37 using namespace llvm;
38
39 #define GET_INSTRINFO_MC_DESC
40 #define ENABLE_INSTR_PREDICATE_VERIFIER
41 #include "MipsGenInstrInfo.inc"
42
43 #define GET_SUBTARGETINFO_MC_DESC
44 #include "MipsGenSubtargetInfo.inc"
45
46 #define GET_REGINFO_MC_DESC
47 #include "MipsGenRegisterInfo.inc"
48
initLLVMToCVRegMapping(MCRegisterInfo * MRI)49 void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
50 // Mapping from CodeView to MC register id.
51 static const struct {
52 codeview::RegisterId CVReg;
53 MCPhysReg Reg;
54 } RegMap[] = {
55 {codeview::RegisterId::MIPS_ZERO, Mips::ZERO},
56 {codeview::RegisterId::MIPS_AT, Mips::AT},
57 {codeview::RegisterId::MIPS_V0, Mips::V0},
58 {codeview::RegisterId::MIPS_V1, Mips::V1},
59 {codeview::RegisterId::MIPS_A0, Mips::A0},
60 {codeview::RegisterId::MIPS_A1, Mips::A1},
61 {codeview::RegisterId::MIPS_A2, Mips::A2},
62 {codeview::RegisterId::MIPS_A3, Mips::A3},
63 {codeview::RegisterId::MIPS_T0, Mips::T0},
64 {codeview::RegisterId::MIPS_T1, Mips::T1},
65 {codeview::RegisterId::MIPS_T2, Mips::T2},
66 {codeview::RegisterId::MIPS_T3, Mips::T3},
67 {codeview::RegisterId::MIPS_T4, Mips::T4},
68 {codeview::RegisterId::MIPS_T5, Mips::T5},
69 {codeview::RegisterId::MIPS_T6, Mips::T6},
70 {codeview::RegisterId::MIPS_T7, Mips::T7},
71 {codeview::RegisterId::MIPS_S0, Mips::S0},
72 {codeview::RegisterId::MIPS_S1, Mips::S1},
73 {codeview::RegisterId::MIPS_S2, Mips::S2},
74 {codeview::RegisterId::MIPS_S3, Mips::S3},
75 {codeview::RegisterId::MIPS_S4, Mips::S4},
76 {codeview::RegisterId::MIPS_S5, Mips::S5},
77 {codeview::RegisterId::MIPS_S6, Mips::S6},
78 {codeview::RegisterId::MIPS_S7, Mips::S7},
79 {codeview::RegisterId::MIPS_T8, Mips::T8},
80 {codeview::RegisterId::MIPS_T9, Mips::T9},
81 {codeview::RegisterId::MIPS_K0, Mips::K0},
82 {codeview::RegisterId::MIPS_K1, Mips::K1},
83 {codeview::RegisterId::MIPS_GP, Mips::GP},
84 {codeview::RegisterId::MIPS_SP, Mips::SP},
85 {codeview::RegisterId::MIPS_S8, Mips::FP},
86 {codeview::RegisterId::MIPS_RA, Mips::RA},
87 {codeview::RegisterId::MIPS_LO, Mips::HI0},
88 {codeview::RegisterId::MIPS_HI, Mips::LO0},
89 {codeview::RegisterId::MIPS_Fir, Mips::FCR0},
90 {codeview::RegisterId::MIPS_Psr, Mips::COP012}, // CP0.Status
91 {codeview::RegisterId::MIPS_F0, Mips::F0},
92 {codeview::RegisterId::MIPS_F1, Mips::F1},
93 {codeview::RegisterId::MIPS_F2, Mips::F2},
94 {codeview::RegisterId::MIPS_F3, Mips::F3},
95 {codeview::RegisterId::MIPS_F4, Mips::F4},
96 {codeview::RegisterId::MIPS_F5, Mips::F5},
97 {codeview::RegisterId::MIPS_F6, Mips::F6},
98 {codeview::RegisterId::MIPS_F7, Mips::F7},
99 {codeview::RegisterId::MIPS_F8, Mips::F8},
100 {codeview::RegisterId::MIPS_F9, Mips::F9},
101 {codeview::RegisterId::MIPS_F10, Mips::F10},
102 {codeview::RegisterId::MIPS_F11, Mips::F11},
103 {codeview::RegisterId::MIPS_F12, Mips::F12},
104 {codeview::RegisterId::MIPS_F13, Mips::F13},
105 {codeview::RegisterId::MIPS_F14, Mips::F14},
106 {codeview::RegisterId::MIPS_F15, Mips::F15},
107 {codeview::RegisterId::MIPS_F16, Mips::F16},
108 {codeview::RegisterId::MIPS_F17, Mips::F17},
109 {codeview::RegisterId::MIPS_F18, Mips::F18},
110 {codeview::RegisterId::MIPS_F19, Mips::F19},
111 {codeview::RegisterId::MIPS_F20, Mips::F20},
112 {codeview::RegisterId::MIPS_F21, Mips::F21},
113 {codeview::RegisterId::MIPS_F22, Mips::F22},
114 {codeview::RegisterId::MIPS_F23, Mips::F23},
115 {codeview::RegisterId::MIPS_F24, Mips::F24},
116 {codeview::RegisterId::MIPS_F25, Mips::F25},
117 {codeview::RegisterId::MIPS_F26, Mips::F26},
118 {codeview::RegisterId::MIPS_F27, Mips::F27},
119 {codeview::RegisterId::MIPS_F28, Mips::F28},
120 {codeview::RegisterId::MIPS_F29, Mips::F29},
121 {codeview::RegisterId::MIPS_F30, Mips::F30},
122 {codeview::RegisterId::MIPS_F31, Mips::F31},
123 {codeview::RegisterId::MIPS_Fsr, Mips::FCR31},
124 };
125 for (const auto &I : RegMap)
126 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
127 }
128
129 namespace {
130 class MipsWinCOFFTargetStreamer : public MipsTargetStreamer {
131 public:
MipsWinCOFFTargetStreamer(MCStreamer & S)132 MipsWinCOFFTargetStreamer(MCStreamer &S) : MipsTargetStreamer(S) {}
133 };
134 } // end namespace
135
136 /// Select the Mips CPU for the given triple and cpu name.
selectMipsCPU(const Triple & TT,StringRef CPU)137 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
138 if (CPU.empty() || CPU == "generic") {
139 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) {
140 if (TT.isMIPS32())
141 CPU = "mips32r6";
142 else
143 CPU = "mips64r6";
144 } else {
145 if (TT.isMIPS32())
146 CPU = "mips32";
147 else
148 CPU = "mips64";
149 }
150 }
151 return CPU;
152 }
153
createMipsMCInstrInfo()154 static MCInstrInfo *createMipsMCInstrInfo() {
155 MCInstrInfo *X = new MCInstrInfo();
156 InitMipsMCInstrInfo(X);
157 return X;
158 }
159
createMipsMCRegisterInfo(const Triple & TT)160 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
161 MCRegisterInfo *X = new MCRegisterInfo();
162 InitMipsMCRegisterInfo(X, Mips::RA);
163 return X;
164 }
165
createMipsMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)166 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
167 StringRef CPU, StringRef FS) {
168 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
169 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
170 }
171
createMipsMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT,const MCTargetOptions & Options)172 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
173 const Triple &TT,
174 const MCTargetOptions &Options) {
175 MCAsmInfo *MAI;
176
177 if (TT.isOSBinFormatCOFF())
178 MAI = new MipsCOFFMCAsmInfo();
179 else
180 MAI = new MipsELFMCAsmInfo(TT, Options);
181
182 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
183 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP);
184 MAI->addInitialFrameState(Inst);
185
186 return MAI;
187 }
188
createMipsMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)189 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
190 unsigned SyntaxVariant,
191 const MCAsmInfo &MAI,
192 const MCInstrInfo &MII,
193 const MCRegisterInfo &MRI) {
194 return new MipsInstPrinter(MAI, MII, MRI);
195 }
196
createMCStreamer(const Triple & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter)197 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
198 std::unique_ptr<MCAsmBackend> &&MAB,
199 std::unique_ptr<MCObjectWriter> &&OW,
200 std::unique_ptr<MCCodeEmitter> &&Emitter) {
201 MCStreamer *S;
202 if (!T.isOSNaCl())
203 S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
204 std::move(Emitter));
205 else
206 S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW),
207 std::move(Emitter));
208 return S;
209 }
210
createMipsAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint)211 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
212 formatted_raw_ostream &OS,
213 MCInstPrinter *InstPrint) {
214 return new MipsTargetAsmStreamer(S, OS);
215 }
216
createMipsNullTargetStreamer(MCStreamer & S)217 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
218 return new MipsTargetStreamer(S);
219 }
220
221 static MCTargetStreamer *
createMipsObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)222 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
223 if (STI.getTargetTriple().isOSBinFormatCOFF())
224 return new MipsWinCOFFTargetStreamer(S);
225 return new MipsTargetELFStreamer(S, STI);
226 }
227
228 namespace {
229
230 class MipsMCInstrAnalysis : public MCInstrAnalysis {
231 public:
MipsMCInstrAnalysis(const MCInstrInfo * Info)232 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
233
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const234 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
235 uint64_t &Target) const override {
236 unsigned NumOps = Inst.getNumOperands();
237 if (NumOps == 0)
238 return false;
239 switch (Info->get(Inst.getOpcode()).operands()[NumOps - 1].OperandType) {
240 case MCOI::OPERAND_UNKNOWN:
241 case MCOI::OPERAND_IMMEDIATE: {
242 // j, jal, jalx, jals
243 // Absolute branch within the current 256 MB-aligned region
244 uint64_t Region = Addr & ~uint64_t(0xfffffff);
245 Target = Region + Inst.getOperand(NumOps - 1).getImm();
246 return true;
247 }
248 case MCOI::OPERAND_PCREL:
249 // b, beq ...
250 Target = Addr + Inst.getOperand(NumOps - 1).getImm();
251 return true;
252 default:
253 return false;
254 }
255 }
256 };
257 }
258
createMipsMCInstrAnalysis(const MCInstrInfo * Info)259 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
260 return new MipsMCInstrAnalysis(Info);
261 }
262
LLVMInitializeMipsTargetMC()263 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() {
264 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
265 &getTheMips64Target(), &getTheMips64elTarget()}) {
266 // Register the MC asm info.
267 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
268
269 // Register the MC instruction info.
270 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
271
272 // Register the MC register info.
273 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
274
275 // Register the elf streamer.
276 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
277
278 // Register the asm target streamer.
279 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
280
281 TargetRegistry::RegisterNullTargetStreamer(*T,
282 createMipsNullTargetStreamer);
283
284 TargetRegistry::RegisterCOFFStreamer(*T, createMipsWinCOFFStreamer);
285
286 // Register the MC subtarget info.
287 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
288
289 // Register the MC instruction analyzer.
290 TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
291
292 // Register the MCInstPrinter.
293 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
294
295 TargetRegistry::RegisterObjectTargetStreamer(
296 *T, createMipsObjectTargetStreamer);
297
298 // Register the asm backend.
299 TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend);
300 }
301
302 // Register the MC Code Emitter
303 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
304 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
305
306 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
307 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
308 }
309