1 /*-
2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include "opt_rss.h"
27 #include "opt_ratelimit.h"
28
29 #include <dev/mlx5/mlx5_en/en.h>
30 #include <netinet/ip_var.h>
31 #include <machine/in_cksum.h>
32 #include <dev/mlx5/mlx5_accel/ipsec.h>
33
34 static inline int
mlx5e_alloc_rx_wqe(struct mlx5e_rq * rq,struct mlx5e_rx_wqe * wqe,u16 ix)35 mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq,
36 struct mlx5e_rx_wqe *wqe, u16 ix)
37 {
38 bus_dma_segment_t segs[MLX5E_MAX_BUSDMA_RX_SEGS];
39 struct mbuf *mb;
40 int nsegs;
41 int err;
42 struct mbuf *mb_head;
43 int i;
44
45 if (rq->mbuf[ix].mbuf != NULL)
46 return (0);
47
48 mb_head = mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rq->wqe_sz);
49 if (unlikely(mb == NULL))
50 return (-ENOMEM);
51
52 mb->m_len = rq->wqe_sz;
53 mb->m_pkthdr.len = rq->wqe_sz;
54
55 for (i = 1; i < rq->nsegs; i++) {
56 mb = mb->m_next = m_getjcl(M_NOWAIT, MT_DATA, 0, rq->wqe_sz);
57 if (unlikely(mb == NULL)) {
58 m_freem(mb_head);
59 return (-ENOMEM);
60 }
61 mb->m_len = rq->wqe_sz;
62 mb_head->m_pkthdr.len += rq->wqe_sz;
63 }
64 /* rewind to first mbuf in chain */
65 mb = mb_head;
66
67 /* get IP header aligned */
68 m_adj(mb, MLX5E_NET_IP_ALIGN);
69
70 err = mlx5_accel_ipsec_rx_tag_add(rq->ifp, &rq->mbuf[ix]);
71 if (err)
72 goto err_free_mbuf;
73 err = -bus_dmamap_load_mbuf_sg(rq->dma_tag, rq->mbuf[ix].dma_map,
74 mb, segs, &nsegs, BUS_DMA_NOWAIT);
75 if (err != 0)
76 goto err_free_mbuf;
77 if (unlikely(nsegs == 0)) {
78 bus_dmamap_unload(rq->dma_tag, rq->mbuf[ix].dma_map);
79 err = -ENOMEM;
80 goto err_free_mbuf;
81 }
82 wqe->data[0].addr = cpu_to_be64(segs[0].ds_addr);
83 wqe->data[0].byte_count = cpu_to_be32(segs[0].ds_len |
84 MLX5_HW_START_PADDING);
85 for (i = 1; i != nsegs; i++) {
86 wqe->data[i].addr = cpu_to_be64(segs[i].ds_addr);
87 wqe->data[i].byte_count = cpu_to_be32(segs[i].ds_len);
88 }
89 for (; i < rq->nsegs; i++) {
90 wqe->data[i].addr = 0;
91 wqe->data[i].byte_count = 0;
92 }
93
94 rq->mbuf[ix].mbuf = mb;
95 rq->mbuf[ix].data = mb->m_data;
96
97 bus_dmamap_sync(rq->dma_tag, rq->mbuf[ix].dma_map,
98 BUS_DMASYNC_PREREAD);
99 return (0);
100
101 err_free_mbuf:
102 m_freem(mb);
103 return (err);
104 }
105
106 static void
mlx5e_post_rx_wqes(struct mlx5e_rq * rq)107 mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
108 {
109 if (unlikely(rq->enabled == 0))
110 return;
111
112 while (!mlx5_wq_ll_is_full(&rq->wq)) {
113 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, rq->wq.head);
114
115 if (unlikely(mlx5e_alloc_rx_wqe(rq, wqe, rq->wq.head))) {
116 callout_reset_curcpu(&rq->watchdog, 1, (void *)&mlx5e_post_rx_wqes, rq);
117 break;
118 }
119 mlx5_wq_ll_push(&rq->wq, be16_to_cpu(wqe->next.next_wqe_index));
120 }
121
122 /* ensure wqes are visible to device before updating doorbell record */
123 atomic_thread_fence_rel();
124
125 mlx5_wq_ll_update_db_record(&rq->wq);
126 }
127
128 static uint32_t
csum_reduce(uint32_t val)129 csum_reduce(uint32_t val)
130 {
131 while (val > 0xffff)
132 val = (val >> 16) + (val & 0xffff);
133 return (val);
134 }
135
136 static u_short
csum_buf(uint32_t val,void * buf,int len)137 csum_buf(uint32_t val, void *buf, int len)
138 {
139 u_short x;
140
141 MPASS(len % 2 == 0);
142 for (int i = 0; i < len; i += 2) {
143 bcopy((char *)buf + i, &x, 2);
144 val = csum_reduce(val + x);
145 }
146 return (val);
147 }
148
149 static void
mlx5e_lro_update_hdr(struct mbuf * mb,struct mlx5_cqe64 * cqe)150 mlx5e_lro_update_hdr(struct mbuf *mb, struct mlx5_cqe64 *cqe)
151 {
152 /* TODO: consider vlans, ip options, ... */
153 struct ether_header *eh;
154 uint16_t eh_type;
155 uint16_t tot_len;
156 struct ip6_hdr *ip6 = NULL;
157 struct ip *ip4 = NULL;
158 struct tcphdr *th;
159 uint32_t *ts_ptr;
160 uint32_t tcp_csum;
161 uint8_t l4_hdr_type;
162 int tcp_ack;
163
164 eh = mtod(mb, struct ether_header *);
165 eh_type = ntohs(eh->ether_type);
166
167 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
168 tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
169 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
170
171 /* TODO: consider vlan */
172 tot_len = be32_to_cpu(cqe->byte_cnt) - ETHER_HDR_LEN;
173
174 switch (eh_type) {
175 case ETHERTYPE_IP:
176 ip4 = (struct ip *)(eh + 1);
177 th = (struct tcphdr *)(ip4 + 1);
178 break;
179 case ETHERTYPE_IPV6:
180 ip6 = (struct ip6_hdr *)(eh + 1);
181 th = (struct tcphdr *)(ip6 + 1);
182 break;
183 default:
184 return;
185 }
186
187 ts_ptr = (uint32_t *)(th + 1);
188
189 if (get_cqe_lro_tcppsh(cqe))
190 tcp_set_flags(th, tcp_get_flags(th) | TH_PUSH);
191
192 if (tcp_ack) {
193 tcp_set_flags(th, tcp_get_flags(th) | TH_ACK);
194 th->th_ack = cqe->lro_ack_seq_num;
195 th->th_win = cqe->lro_tcp_win;
196
197 /*
198 * FreeBSD handles only 32bit aligned timestamp right after
199 * the TCP hdr
200 * +--------+--------+--------+--------+
201 * | NOP | NOP | TSopt | 10 |
202 * +--------+--------+--------+--------+
203 * | TSval timestamp |
204 * +--------+--------+--------+--------+
205 * | TSecr timestamp |
206 * +--------+--------+--------+--------+
207 */
208 if (get_cqe_lro_timestamp_valid(cqe) &&
209 (__predict_true(*ts_ptr == ntohl(TCPOPT_NOP << 24 |
210 TCPOPT_NOP << 16 | TCPOPT_TIMESTAMP << 8 |
211 TCPOLEN_TIMESTAMP)))) {
212 /*
213 * cqe->timestamp is 64bit long.
214 * [0-31] - timestamp.
215 * [32-64] - timestamp echo replay.
216 */
217 ts_ptr[2] = *((uint32_t *)&cqe->timestamp + 1);
218 }
219 }
220 if (ip4) {
221 struct ipovly io;
222
223 ip4->ip_ttl = cqe->lro_min_ttl;
224 ip4->ip_len = cpu_to_be16(tot_len);
225 ip4->ip_sum = 0;
226 ip4->ip_sum = in_cksum_skip(mb, (ip4->ip_hl << 2) +
227 ETHER_HDR_LEN, ETHER_HDR_LEN);
228
229 /* TCP checksum: data */
230 tcp_csum = cqe->check_sum;
231
232 /* TCP checksum: IP pseudoheader */
233 bzero(io.ih_x1, sizeof(io.ih_x1));
234 io.ih_pr = IPPROTO_TCP;
235 io.ih_len = htons(ntohs(ip4->ip_len) - sizeof(*ip4));
236 io.ih_src = ip4->ip_src;
237 io.ih_dst = ip4->ip_dst;
238 tcp_csum = csum_buf(tcp_csum, &io, sizeof(io));
239
240 /* TCP checksum: TCP header */
241 th->th_sum = 0;
242 tcp_csum = csum_buf(tcp_csum, th, th->th_off * 4);
243 th->th_sum = ~tcp_csum & 0xffff;
244 } else {
245 ip6->ip6_hlim = cqe->lro_min_ttl;
246 ip6->ip6_plen = cpu_to_be16(tot_len -
247 sizeof(struct ip6_hdr));
248
249 /* TCP checksum */
250 th->th_sum = 0;
251 tcp_csum = ~in6_cksum_partial_l2(mb, IPPROTO_TCP,
252 sizeof(struct ether_header),
253 sizeof(struct ether_header) + sizeof(struct ip6_hdr),
254 tot_len - sizeof(struct ip6_hdr), th->th_off * 4) & 0xffff;
255 tcp_csum = csum_reduce(tcp_csum + cqe->check_sum);
256 th->th_sum = ~tcp_csum & 0xffff;
257 }
258 }
259
260 static uint64_t
mlx5e_mbuf_tstmp(struct mlx5e_priv * priv,uint64_t hw_tstmp)261 mlx5e_mbuf_tstmp(struct mlx5e_priv *priv, uint64_t hw_tstmp)
262 {
263 struct mlx5e_clbr_point *cp, dcp;
264 uint64_t tstmp_sec, tstmp_nsec;
265 uint64_t hw_clocks;
266 uint64_t rt_cur_to_prev, res_s, res_n, res_s_modulo, res;
267 uint64_t hw_clk_div;
268 u_int gen;
269
270 do {
271 cp = &priv->clbr_points[priv->clbr_curr];
272 gen = atomic_load_acq_int(&cp->clbr_gen);
273 if (gen == 0)
274 return (0);
275 dcp = *cp;
276 atomic_thread_fence_acq();
277 } while (gen != dcp.clbr_gen);
278 /*
279 * Our goal here is to have a result that is:
280 *
281 * ( (cur_time - prev_time) )
282 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time
283 * ( (hw_cur - hw_prev) )
284 *
285 * With the constraints that we cannot use float and we
286 * don't want to overflow the uint64_t numbers we are using.
287 *
288 * The plan is to take the clocking value of the hw timestamps
289 * and split them into seconds and nanosecond equivalent portions.
290 * Then we operate on the two portions seperately making sure to
291 * bring back the carry over from the seconds when we divide.
292 *
293 * First up lets get the two divided into separate entities
294 * i.e. the seconds. We use the clock frequency for this.
295 * Note that priv->cclk was setup with the clock frequency
296 * in hz so we are all set to go.
297 */
298 hw_clocks = hw_tstmp - dcp.clbr_hw_prev;
299 tstmp_sec = hw_clocks / priv->cclk;
300 tstmp_nsec = hw_clocks % priv->cclk;
301 /* Now work with them separately */
302 rt_cur_to_prev = (dcp.base_curr - dcp.base_prev);
303 res_s = tstmp_sec * rt_cur_to_prev;
304 res_n = tstmp_nsec * rt_cur_to_prev;
305 /* Now lets get our divider */
306 hw_clk_div = dcp.clbr_hw_curr - dcp.clbr_hw_prev;
307 /* Make sure to save the remainder from the seconds divide */
308 res_s_modulo = res_s % hw_clk_div;
309 res_s /= hw_clk_div;
310 /* scale the remainder to where it should be */
311 res_s_modulo *= priv->cclk;
312 /* Now add in the remainder */
313 res_n += res_s_modulo;
314 /* Now do the divide */
315 res_n /= hw_clk_div;
316 res_s *= priv->cclk;
317 /* Recombine the two */
318 res = res_s + res_n;
319 /* And now add in the base time to get to the real timestamp */
320 res += dcp.base_prev;
321 return (res);
322 }
323
324 static inline void
mlx5e_build_rx_mbuf(struct mlx5_cqe64 * cqe,struct mlx5e_rq * rq,struct mbuf * mb,struct mlx5e_rq_mbuf * mr,u32 cqe_bcnt)325 mlx5e_build_rx_mbuf(struct mlx5_cqe64 *cqe, struct mlx5e_rq *rq,
326 struct mbuf *mb, struct mlx5e_rq_mbuf *mr, u32 cqe_bcnt)
327 {
328 if_t ifp = rq->ifp;
329 struct mlx5e_channel *c;
330 struct mbuf *mb_head;
331 int lro_num_seg; /* HW LRO session aggregated packets counter */
332 uint64_t tstmp;
333
334 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
335 if (lro_num_seg > 1) {
336 mlx5e_lro_update_hdr(mb, cqe);
337 rq->stats.lro_packets++;
338 rq->stats.lro_bytes += cqe_bcnt;
339 }
340
341 mb->m_pkthdr.len = cqe_bcnt;
342 for (mb_head = mb; mb != NULL; mb = mb->m_next) {
343 if (mb->m_len > cqe_bcnt)
344 mb->m_len = cqe_bcnt;
345 cqe_bcnt -= mb->m_len;
346 if (likely(cqe_bcnt == 0)) {
347 if (likely(mb->m_next != NULL)) {
348 /* trim off empty mbufs */
349 m_freem(mb->m_next);
350 mb->m_next = NULL;
351 }
352 break;
353 }
354 }
355 /* rewind to first mbuf in chain */
356 mb = mb_head;
357
358 /* check if a Toeplitz hash was computed */
359 if (cqe->rss_hash_type != 0) {
360 mb->m_pkthdr.flowid = be32_to_cpu(cqe->rss_hash_result);
361 #ifdef RSS
362 /* decode the RSS hash type */
363 switch (cqe->rss_hash_type &
364 (CQE_RSS_DST_HTYPE_L4 | CQE_RSS_DST_HTYPE_IP)) {
365 /* IPv4 */
366 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV4):
367 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV4);
368 break;
369 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV4):
370 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV4);
371 break;
372 case CQE_RSS_DST_HTYPE_IPV4:
373 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV4);
374 break;
375 /* IPv6 */
376 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV6):
377 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV6);
378 break;
379 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV6):
380 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV6);
381 break;
382 case CQE_RSS_DST_HTYPE_IPV6:
383 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV6);
384 break;
385 default: /* Other */
386 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE_HASH);
387 break;
388 }
389 #else
390 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE_HASH);
391 #endif
392 #ifdef M_HASHTYPE_SETINNER
393 if (cqe_is_tunneled(cqe))
394 M_HASHTYPE_SETINNER(mb);
395 #endif
396 } else {
397 mb->m_pkthdr.flowid = rq->ix;
398 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE);
399 }
400 mb->m_pkthdr.rcvif = ifp;
401 mb->m_pkthdr.leaf_rcvif = ifp;
402
403 if (cqe_is_tunneled(cqe)) {
404 /*
405 * CQE can be tunneled only if TIR is configured to
406 * enable parsing of tunneled payload, so no need to
407 * check for capabilities.
408 */
409 if (((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK)) ==
410 (CQE_L2_OK | CQE_L3_OK))) {
411 mb->m_pkthdr.csum_flags |=
412 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
413 CSUM_IP_CHECKED | CSUM_IP_VALID |
414 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
415 mb->m_pkthdr.csum_data = htons(0xffff);
416
417 if (likely((cqe->hds_ip_ext & CQE_L4_OK) == CQE_L4_OK)) {
418 mb->m_pkthdr.csum_flags |=
419 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID;
420 }
421 } else {
422 rq->stats.csum_none++;
423 }
424 } else if (likely((if_getcapenable(ifp) & (IFCAP_RXCSUM |
425 IFCAP_RXCSUM_IPV6)) != 0) &&
426 ((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK)) ==
427 (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK))) {
428 mb->m_pkthdr.csum_flags =
429 CSUM_IP_CHECKED | CSUM_IP_VALID |
430 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
431 mb->m_pkthdr.csum_data = htons(0xffff);
432 } else {
433 rq->stats.csum_none++;
434 }
435
436 if (cqe_has_vlan(cqe)) {
437 mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->vlan_info);
438 mb->m_flags |= M_VLANTAG;
439 }
440
441 c = container_of(rq, struct mlx5e_channel, rq);
442 if (c->priv->clbr_done >= 2) {
443 tstmp = mlx5e_mbuf_tstmp(c->priv, be64_to_cpu(cqe->timestamp));
444 if ((tstmp & MLX5_CQE_TSTMP_PTP) != 0) {
445 /*
446 * Timestamp was taken on the packet entrance,
447 * instead of the cqe generation.
448 */
449 tstmp &= ~MLX5_CQE_TSTMP_PTP;
450 mb->m_flags |= M_TSTMP_HPREC;
451 }
452 if (tstmp != 0) {
453 mb->m_pkthdr.rcv_tstmp = tstmp;
454 mb->m_flags |= M_TSTMP;
455 }
456 }
457 switch (get_cqe_tls_offload(cqe)) {
458 case CQE_TLS_OFFLOAD_DECRYPTED:
459 /* set proper checksum flag for decrypted packets */
460 mb->m_pkthdr.csum_flags |= CSUM_TLS_DECRYPTED;
461 rq->stats.decrypted_ok_packets++;
462 break;
463 case CQE_TLS_OFFLOAD_ERROR:
464 rq->stats.decrypted_error_packets++;
465 break;
466 default:
467 break;
468 }
469
470 mlx5e_accel_ipsec_handle_rx(mb, cqe, mr);
471 }
472
473 static inline void
mlx5e_read_cqe_slot(struct mlx5e_cq * cq,u32 cc,void * data)474 mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data)
475 {
476 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, (cc & cq->wq.sz_m1)),
477 sizeof(struct mlx5_cqe64));
478 }
479
480 static inline void
mlx5e_write_cqe_slot(struct mlx5e_cq * cq,u32 cc,void * data)481 mlx5e_write_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data)
482 {
483 memcpy(mlx5_cqwq_get_wqe(&cq->wq, cc & cq->wq.sz_m1),
484 data, sizeof(struct mlx5_cqe64));
485 }
486
487 static inline void
mlx5e_decompress_cqe(struct mlx5e_cq * cq,struct mlx5_cqe64 * title,struct mlx5_mini_cqe8 * mini,u16 wqe_counter,int i)488 mlx5e_decompress_cqe(struct mlx5e_cq *cq, struct mlx5_cqe64 *title,
489 struct mlx5_mini_cqe8 *mini,
490 u16 wqe_counter, int i)
491 {
492 /*
493 * NOTE: The fields which are not set here are copied from the
494 * initial and common title. See memcpy() in
495 * mlx5e_write_cqe_slot().
496 */
497 title->byte_cnt = mini->byte_cnt;
498 title->wqe_counter = cpu_to_be16((wqe_counter + i) & cq->wq.sz_m1);
499 title->rss_hash_result = mini->rx_hash_result;
500 /*
501 * Since we use MLX5_CQE_FORMAT_HASH when creating the RX CQ,
502 * the value of the checksum should be ignored.
503 */
504 title->check_sum = 0;
505 title->op_own = (title->op_own & 0xf0) |
506 (((cq->wq.cc + i) >> cq->wq.log_sz) & 1);
507 }
508
509 #define MLX5E_MINI_ARRAY_SZ 8
510 /* Make sure structs are not packet differently */
511 CTASSERT(sizeof(struct mlx5_cqe64) ==
512 sizeof(struct mlx5_mini_cqe8) * MLX5E_MINI_ARRAY_SZ);
513 static void
mlx5e_decompress_cqes(struct mlx5e_cq * cq)514 mlx5e_decompress_cqes(struct mlx5e_cq *cq)
515 {
516 struct mlx5_mini_cqe8 mini_array[MLX5E_MINI_ARRAY_SZ];
517 struct mlx5_cqe64 title;
518 u32 cqe_count;
519 u32 i = 0;
520 u16 title_wqe_counter;
521
522 mlx5e_read_cqe_slot(cq, cq->wq.cc, &title);
523 title_wqe_counter = be16_to_cpu(title.wqe_counter);
524 cqe_count = be32_to_cpu(title.byte_cnt);
525
526 /* Make sure we won't overflow */
527 KASSERT(cqe_count <= cq->wq.sz_m1,
528 ("%s: cqe_count %u > cq->wq.sz_m1 %u", __func__,
529 cqe_count, cq->wq.sz_m1));
530
531 mlx5e_read_cqe_slot(cq, cq->wq.cc + 1, mini_array);
532 while (true) {
533 mlx5e_decompress_cqe(cq, &title,
534 &mini_array[i % MLX5E_MINI_ARRAY_SZ],
535 title_wqe_counter, i);
536 mlx5e_write_cqe_slot(cq, cq->wq.cc + i, &title);
537 i++;
538
539 if (i == cqe_count)
540 break;
541 if (i % MLX5E_MINI_ARRAY_SZ == 0)
542 mlx5e_read_cqe_slot(cq, cq->wq.cc + i, mini_array);
543 }
544 }
545
546 static int
mlx5e_poll_rx_cq(struct mlx5e_rq * rq,int budget)547 mlx5e_poll_rx_cq(struct mlx5e_rq *rq, int budget)
548 {
549 struct pfil_head *pfil;
550 int i, rv;
551
552 CURVNET_SET_QUIET(if_getvnet(rq->ifp));
553 pfil = rq->channel->priv->pfil;
554 for (i = 0; i < budget; i++) {
555 struct mlx5e_rx_wqe *wqe;
556 struct mlx5_cqe64 *cqe;
557 struct mbuf *mb;
558 __be16 wqe_counter_be;
559 u16 wqe_counter;
560 u32 byte_cnt, seglen;
561
562 cqe = mlx5e_get_cqe(&rq->cq);
563 if (!cqe)
564 break;
565
566 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED)
567 mlx5e_decompress_cqes(&rq->cq);
568
569 mlx5_cqwq_pop(&rq->cq.wq);
570
571 wqe_counter_be = cqe->wqe_counter;
572 wqe_counter = be16_to_cpu(wqe_counter_be);
573 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
574 byte_cnt = be32_to_cpu(cqe->byte_cnt);
575
576 bus_dmamap_sync(rq->dma_tag,
577 rq->mbuf[wqe_counter].dma_map,
578 BUS_DMASYNC_POSTREAD);
579
580 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
581 mlx5e_dump_err_cqe(&rq->cq, rq->rqn, (const void *)cqe);
582 rq->stats.wqe_err++;
583 goto wq_ll_pop;
584 }
585 if (pfil != NULL && PFIL_HOOKED_IN(pfil)) {
586 seglen = MIN(byte_cnt, MLX5E_MAX_RX_BYTES);
587 rv = pfil_mem_in(rq->channel->priv->pfil,
588 rq->mbuf[wqe_counter].data, seglen, rq->ifp, &mb);
589
590 switch (rv) {
591 case PFIL_DROPPED:
592 case PFIL_CONSUMED:
593 /*
594 * Filter dropped or consumed it. In
595 * either case, we can just recycle
596 * buffer; there is no more work to do.
597 */
598 rq->stats.packets++;
599 goto wq_ll_pop;
600 case PFIL_REALLOCED:
601 /*
602 * Filter copied it; recycle buffer
603 * and receive the new mbuf allocated
604 * by the Filter
605 */
606 goto rx_common;
607 default:
608 /*
609 * The Filter said it was OK, so
610 * receive like normal.
611 */
612 KASSERT(rv == PFIL_PASS,
613 ("Filter returned %d!\n", rv));
614 }
615 }
616 if (!mlx5e_accel_ipsec_flow(cqe) /* tag is already assigned
617 to rq->mbuf */ &&
618 MHLEN - MLX5E_NET_IP_ALIGN >= byte_cnt &&
619 (mb = m_gethdr(M_NOWAIT, MT_DATA)) != NULL) {
620 /* set maximum mbuf length */
621 mb->m_len = MHLEN - MLX5E_NET_IP_ALIGN;
622 /* get IP header aligned */
623 mb->m_data += MLX5E_NET_IP_ALIGN;
624
625 bcopy(rq->mbuf[wqe_counter].data, mtod(mb, caddr_t),
626 byte_cnt);
627 } else {
628 mb = rq->mbuf[wqe_counter].mbuf;
629 rq->mbuf[wqe_counter].mbuf = NULL; /* safety clear */
630
631 bus_dmamap_unload(rq->dma_tag,
632 rq->mbuf[wqe_counter].dma_map);
633 }
634 rx_common:
635 mlx5e_build_rx_mbuf(cqe, rq, mb, &rq->mbuf[wqe_counter],
636 byte_cnt);
637 rq->stats.bytes += byte_cnt;
638 rq->stats.packets++;
639 #ifdef NUMA
640 mb->m_pkthdr.numa_domain = if_getnumadomain(rq->ifp);
641 #endif
642
643 #if !defined(HAVE_TCP_LRO_RX)
644 tcp_lro_queue_mbuf(&rq->lro, mb);
645 #else
646 if (mb->m_pkthdr.csum_flags == 0 ||
647 (if_getcapenable(rq->ifp) & IFCAP_LRO) == 0 ||
648 rq->lro.lro_cnt == 0 ||
649 tcp_lro_rx(&rq->lro, mb, 0) != 0) {
650 if_input(rq->ifp, mb);
651 }
652 #endif
653 wq_ll_pop:
654 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
655 &wqe->next.next_wqe_index);
656 }
657 CURVNET_RESTORE();
658
659 mlx5_cqwq_update_db_record(&rq->cq.wq);
660
661 /* ensure cq space is freed before enabling more cqes */
662 atomic_thread_fence_rel();
663 return (i);
664 }
665
666 void
mlx5e_rx_cq_comp(struct mlx5_core_cq * mcq,struct mlx5_eqe * eqe __unused)667 mlx5e_rx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe __unused)
668 {
669 struct mlx5e_channel *c = container_of(mcq, struct mlx5e_channel, rq.cq.mcq);
670 struct mlx5e_rq *rq = container_of(mcq, struct mlx5e_rq, cq.mcq);
671 int i = 0;
672
673 #ifdef HAVE_PER_CQ_EVENT_PACKET
674 #if (MHLEN < 15)
675 #error "MHLEN is too small"
676 #endif
677 struct mbuf *mb = m_gethdr(M_NOWAIT, MT_DATA);
678
679 if (mb != NULL) {
680 /* this code is used for debugging purpose only */
681 mb->m_pkthdr.len = mb->m_len = 15;
682 memset(mb->m_data, 255, 14);
683 mb->m_data[14] = rq->ix;
684 mb->m_pkthdr.rcvif = rq->ifp;
685 mb->m_pkthdr.leaf_rcvif = rq->ifp;
686 if_input(rq->ifp, mb);
687 }
688 #endif
689 for (int j = 0; j != MLX5E_MAX_TX_NUM_TC; j++) {
690 mtx_lock(&c->sq[j].lock);
691 c->sq[j].db_inhibit++;
692 mtx_unlock(&c->sq[j].lock);
693 }
694
695 mtx_lock(&c->iq.lock);
696 c->iq.db_inhibit++;
697 mtx_unlock(&c->iq.lock);
698
699 mtx_lock(&rq->mtx);
700
701 /*
702 * Polling the entire CQ without posting new WQEs results in
703 * lack of receive WQEs during heavy traffic scenarios.
704 */
705 while (1) {
706 if (mlx5e_poll_rx_cq(rq, MLX5E_RX_BUDGET_MAX) !=
707 MLX5E_RX_BUDGET_MAX)
708 break;
709 i += MLX5E_RX_BUDGET_MAX;
710 if (i >= MLX5E_BUDGET_MAX)
711 break;
712 mlx5e_post_rx_wqes(rq);
713 }
714 mlx5e_post_rx_wqes(rq);
715 /* check for dynamic interrupt moderation callback */
716 if (rq->dim.mode != NET_DIM_CQ_PERIOD_MODE_DISABLED)
717 net_dim(&rq->dim, rq->stats.packets, rq->stats.bytes);
718 mlx5e_cq_arm(&rq->cq, MLX5_GET_DOORBELL_LOCK(&rq->channel->priv->doorbell_lock));
719 tcp_lro_flush_all(&rq->lro);
720 mtx_unlock(&rq->mtx);
721
722 for (int j = 0; j != MLX5E_MAX_TX_NUM_TC; j++) {
723 mtx_lock(&c->sq[j].lock);
724 c->sq[j].db_inhibit--;
725 /* Update the doorbell record, if any. */
726 mlx5e_tx_notify_hw(c->sq + j, true);
727 mtx_unlock(&c->sq[j].lock);
728 }
729
730 mtx_lock(&c->iq.lock);
731 c->iq.db_inhibit--;
732 mlx5e_iq_notify_hw(&c->iq);
733 mtx_unlock(&c->iq.lock);
734 }
735