1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/mman.h>
31 #include <sys/stat.h>
32
33 #include <machine/armreg.h>
34
35 #include <assert.h>
36 #include <err.h>
37 #include <errno.h>
38 #include <fcntl.h>
39 #include <stdlib.h>
40 #include <string.h>
41 #include <sysexits.h>
42 #include <unistd.h>
43
44 #include <vmmapi.h>
45
46 #include "bhyve_machdep.h"
47 #include "bhyverun.h"
48 #include "config.h"
49 #include "debug.h"
50 #include "fdt.h"
51 #include "mem.h"
52 #include "pci_emul.h"
53 #include "pci_irq.h"
54 #include "rtc_pl031.h"
55 #include "uart_emul.h"
56
57 /* Start of mem + 1M */
58 #define FDT_BASE 0x100000
59 #define FDT_SIZE (64 * 1024)
60
61 /* Start of lowmem + 64K */
62 #define UART_MMIO_BASE 0x10000
63 #define UART_MMIO_SIZE 0x1000
64 #define UART_INTR 32
65 #define RTC_MMIO_BASE 0x11000
66 #define RTC_MMIO_SIZE 0x1000
67 #define RTC_INTR 33
68
69 #define GIC_DIST_BASE 0x2f000000
70 #define GIC_DIST_SIZE 0x10000
71 #define GIC_REDIST_BASE 0x2f100000
72 #define GIC_REDIST_SIZE(ncpu) ((ncpu) * 2 * PAGE_SIZE_64K)
73
74 #define PCIE_INTA 34
75 #define PCIE_INTB 35
76 #define PCIE_INTC 36
77 #define PCIE_INTD 37
78
79 uint64_t *cpu_to_mpidr;
80
81 void
bhyve_init_config(void)82 bhyve_init_config(void)
83 {
84 init_config();
85
86 /* Set default values prior to option parsing. */
87 set_config_bool("acpi_tables", false);
88 set_config_bool("acpi_tables_in_memory", false);
89 set_config_value("memory.size", "256M");
90 }
91
92 void
bhyve_usage(int code)93 bhyve_usage(int code)
94 {
95 const char *progname;
96
97 progname = getprogname();
98
99 fprintf(stderr,
100 "Usage: %s [-CDHhSW]\n"
101 " %*s [-c [[cpus=]numcpus][,sockets=n][,cores=n][,threads=n]]\n"
102 " %*s [-k config_file] [-m mem] [-o var=value]\n"
103 " %*s [-p vcpu:hostcpu] [-r file] [-s pci] [-U uuid] vmname\n"
104 " -C: include guest memory in core file\n"
105 " -c: number of CPUs and/or topology specification\n"
106 " -D: destroy on power-off\n"
107 " -G: start a debug server\n"
108 " -h: help\n"
109 " -k: key=value flat config file\n"
110 " -m: memory size\n"
111 " -o: set config 'var' to 'value'\n"
112 " -p: pin 'vcpu' to 'hostcpu'\n"
113 " -S: guest memory cannot be swapped\n"
114 " -s: <slot,driver,configinfo> PCI slot config\n"
115 " -U: UUID\n"
116 " -W: force virtio to use single-vector MSI\n",
117 progname, (int)strlen(progname), "", (int)strlen(progname), "",
118 (int)strlen(progname), "");
119 exit(code);
120 }
121
122 void
bhyve_optparse(int argc,char ** argv)123 bhyve_optparse(int argc, char **argv)
124 {
125 const char *optstr;
126 int c;
127
128 optstr = "hCDSWk:f:o:p:G:c:s:m:U:";
129 while ((c = getopt(argc, argv, optstr)) != -1) {
130 switch (c) {
131 case 'c':
132 if (bhyve_topology_parse(optarg) != 0) {
133 errx(EX_USAGE, "invalid cpu topology '%s'",
134 optarg);
135 }
136 break;
137 case 'C':
138 set_config_bool("memory.guest_in_core", true);
139 break;
140 case 'D':
141 set_config_bool("destroy_on_poweroff", true);
142 break;
143 case 'G':
144 bhyve_parse_gdb_options(optarg);
145 break;
146 case 'k':
147 bhyve_parse_simple_config_file(optarg);
148 break;
149 case 'm':
150 set_config_value("memory.size", optarg);
151 break;
152 case 'o':
153 if (!bhyve_parse_config_option(optarg)) {
154 errx(EX_USAGE,
155 "invalid configuration option '%s'",
156 optarg);
157 }
158 break;
159 case 'p':
160 if (bhyve_pincpu_parse(optarg) != 0) {
161 errx(EX_USAGE,
162 "invalid vcpu pinning configuration '%s'",
163 optarg);
164 }
165 break;
166 case 's':
167 if (strncmp(optarg, "help", strlen(optarg)) == 0) {
168 pci_print_supported_devices();
169 exit(0);
170 } else if (pci_parse_slot(optarg) != 0)
171 exit(4);
172 else
173 break;
174 case 'S':
175 set_config_bool("memory.wired", true);
176 break;
177 case 'U':
178 set_config_value("uuid", optarg);
179 break;
180 case 'W':
181 set_config_bool("virtio_msix", false);
182 break;
183 case 'h':
184 bhyve_usage(0);
185 default:
186 bhyve_usage(1);
187 }
188 }
189 }
190
191 void
bhyve_init_vcpu(struct vcpu * vcpu __unused)192 bhyve_init_vcpu(struct vcpu *vcpu __unused)
193 {
194 }
195
196 void
bhyve_start_vcpu(struct vcpu * vcpu,bool bsp __unused)197 bhyve_start_vcpu(struct vcpu *vcpu, bool bsp __unused)
198 {
199 fbsdrun_addcpu(vcpu_id(vcpu));
200 }
201
202 /*
203 * Load the specified boot code at the beginning of high memory.
204 */
205 static void
load_bootrom(struct vmctx * ctx,const char * path,uint64_t * elrp)206 load_bootrom(struct vmctx *ctx, const char *path, uint64_t *elrp)
207 {
208 struct stat sb;
209 void *data, *gptr;
210 vm_paddr_t loadaddr;
211 off_t size;
212 int fd;
213
214 fd = open(path, O_RDONLY);
215 if (fd < 0)
216 err(1, "open(%s)", path);
217 if (fstat(fd, &sb) != 0)
218 err(1, "fstat(%s)", path);
219
220 size = sb.st_size;
221
222 loadaddr = vm_get_highmem_base(ctx);
223 gptr = vm_map_gpa(ctx, loadaddr, round_page(size));
224
225 data = mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0);
226 if (data == MAP_FAILED)
227 err(1, "mmap(%s)", path);
228 (void)close(fd);
229 memcpy(gptr, data, size);
230
231 if (munmap(data, size) != 0)
232 err(1, "munmap(%s)", path);
233
234 *elrp = loadaddr;
235 }
236
237 static void
mmio_uart_intr_assert(void * arg)238 mmio_uart_intr_assert(void *arg)
239 {
240 struct vmctx *ctx = arg;
241
242 vm_assert_irq(ctx, UART_INTR);
243 }
244
245 static void
mmio_uart_intr_deassert(void * arg)246 mmio_uart_intr_deassert(void *arg)
247 {
248 struct vmctx *ctx = arg;
249
250 vm_deassert_irq(ctx, UART_INTR);
251 }
252
253 static int
mmio_uart_mem_handler(struct vcpu * vcpu __unused,int dir,uint64_t addr,int size __unused,uint64_t * val,void * arg1,long arg2)254 mmio_uart_mem_handler(struct vcpu *vcpu __unused, int dir,
255 uint64_t addr, int size __unused, uint64_t *val, void *arg1, long arg2)
256 {
257 struct uart_pl011_softc *sc = arg1;
258 long reg;
259
260 reg = (addr - arg2) >> 2;
261 if (dir == MEM_F_WRITE)
262 uart_pl011_write(sc, reg, *val);
263 else
264 *val = uart_pl011_read(sc, reg);
265
266 return (0);
267 }
268
269 static bool
init_mmio_uart(struct vmctx * ctx)270 init_mmio_uart(struct vmctx *ctx)
271 {
272 struct uart_pl011_softc *sc;
273 struct mem_range mr;
274 const char *path;
275 int error;
276
277 path = get_config_value("console");
278 if (path == NULL)
279 return (false);
280
281 sc = uart_pl011_init(mmio_uart_intr_assert, mmio_uart_intr_deassert,
282 ctx);
283 if (uart_pl011_tty_open(sc, path) != 0) {
284 EPRINTLN("Unable to initialize backend '%s' for mmio uart",
285 path);
286 assert(0);
287 }
288
289 bzero(&mr, sizeof(struct mem_range));
290 mr.name = "uart";
291 mr.base = UART_MMIO_BASE;
292 mr.size = UART_MMIO_SIZE;
293 mr.flags = MEM_F_RW;
294 mr.handler = mmio_uart_mem_handler;
295 mr.arg1 = sc;
296 mr.arg2 = mr.base;
297 error = register_mem(&mr);
298 assert(error == 0);
299
300 return (true);
301 }
302
303 static void
mmio_rtc_intr_assert(void * arg)304 mmio_rtc_intr_assert(void *arg)
305 {
306 struct vmctx *ctx = arg;
307
308 vm_assert_irq(ctx, RTC_INTR);
309 }
310
311 static void
mmio_rtc_intr_deassert(void * arg)312 mmio_rtc_intr_deassert(void *arg)
313 {
314 struct vmctx *ctx = arg;
315
316 vm_deassert_irq(ctx, RTC_INTR);
317 }
318
319 static int
mmio_rtc_mem_handler(struct vcpu * vcpu __unused,int dir,uint64_t addr,int size __unused,uint64_t * val,void * arg1,long arg2)320 mmio_rtc_mem_handler(struct vcpu *vcpu __unused, int dir,
321 uint64_t addr, int size __unused, uint64_t *val, void *arg1, long arg2)
322 {
323 struct rtc_pl031_softc *sc = arg1;
324 long reg;
325
326 reg = addr - arg2;
327 if (dir == MEM_F_WRITE)
328 rtc_pl031_write(sc, reg, *val);
329 else
330 *val = rtc_pl031_read(sc, reg);
331
332 return (0);
333 }
334
335 static void
init_mmio_rtc(struct vmctx * ctx)336 init_mmio_rtc(struct vmctx *ctx)
337 {
338 struct rtc_pl031_softc *sc;
339 struct mem_range mr;
340 int error;
341
342 sc = rtc_pl031_init(mmio_rtc_intr_assert, mmio_rtc_intr_deassert,
343 ctx);
344
345 bzero(&mr, sizeof(struct mem_range));
346 mr.name = "rtc";
347 mr.base = RTC_MMIO_BASE;
348 mr.size = RTC_MMIO_SIZE;
349 mr.flags = MEM_F_RW;
350 mr.handler = mmio_rtc_mem_handler;
351 mr.arg1 = sc;
352 mr.arg2 = mr.base;
353 error = register_mem(&mr);
354 assert(error == 0);
355 }
356
357 static vm_paddr_t
fdt_gpa(struct vmctx * ctx)358 fdt_gpa(struct vmctx *ctx)
359 {
360 return (vm_get_highmem_base(ctx) + FDT_BASE);
361 }
362
363 int
bhyve_init_platform(struct vmctx * ctx,struct vcpu * bsp)364 bhyve_init_platform(struct vmctx *ctx, struct vcpu *bsp)
365 {
366 const char *bootrom;
367 uint64_t elr;
368 int error;
369 int pcie_intrs[4] = {PCIE_INTA, PCIE_INTB, PCIE_INTC, PCIE_INTD};
370
371 cpu_to_mpidr = calloc(guest_ncpus, sizeof(*cpu_to_mpidr));
372 if (cpu_to_mpidr == NULL) {
373 warnx("unable to allocate space for mpidr list");
374 return (ENOMEM);
375 }
376
377 for (uint64_t cpu = 0; cpu < (uint64_t)guest_ncpus; cpu++) {
378 uint64_t mpidr;
379
380 error = vm_get_register(fbsdrun_vcpu(cpu), VM_REG_GUEST_MPIDR_EL1,
381 &mpidr);
382 assert(error == 0);
383 #define MPIDR_AFF_MASK (MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | MPIDR_AFF2_MASK | MPIDR_AFF3_MASK)
384 cpu_to_mpidr[cpu] = mpidr & MPIDR_AFF_MASK;
385 #undef MPIDR_AFF_MASK
386 }
387
388 bootrom = get_config_value("bootrom");
389 if (bootrom == NULL) {
390 warnx("no bootrom specified");
391 return (ENOENT);
392 }
393 load_bootrom(ctx, bootrom, &elr);
394 error = vm_set_register(bsp, VM_REG_GUEST_PC, elr);
395 if (error != 0) {
396 warn("vm_set_register(GUEST_PC)");
397 return (error);
398 }
399
400 error = fdt_init(ctx, guest_ncpus, fdt_gpa(ctx), FDT_SIZE);
401 if (error != 0)
402 return (error);
403
404 fdt_add_gic(GIC_DIST_BASE, GIC_DIST_SIZE, GIC_REDIST_BASE,
405 GIC_REDIST_SIZE(guest_ncpus));
406 error = vm_attach_vgic(ctx, GIC_DIST_BASE, GIC_DIST_SIZE,
407 GIC_REDIST_BASE, GIC_REDIST_SIZE(guest_ncpus));
408 if (error != 0) {
409 warn("vm_attach_vgic()");
410 return (error);
411 }
412
413 if (init_mmio_uart(ctx))
414 fdt_add_uart(UART_MMIO_BASE, UART_MMIO_SIZE, UART_INTR);
415 init_mmio_rtc(ctx);
416 fdt_add_rtc(RTC_MMIO_BASE, RTC_MMIO_SIZE, RTC_INTR);
417 fdt_add_timer();
418 pci_irq_init(pcie_intrs);
419 fdt_add_pcie(pcie_intrs);
420
421 /* Mark CPU0 as running */
422 CPU_SET(0, &running_cpumask);
423
424 return (0);
425 }
426
427 int
bhyve_init_platform_late(struct vmctx * ctx,struct vcpu * bsp __unused)428 bhyve_init_platform_late(struct vmctx *ctx, struct vcpu *bsp __unused)
429 {
430 int error;
431
432 fdt_finalize();
433
434 error = vm_set_register(bsp, VM_REG_GUEST_X0, fdt_gpa(ctx));
435 assert(error == 0);
436
437 return (0);
438 }
439