1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/cpu.h> 47 #include <sys/eventhandler.h> 48 #include <sys/limits.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/sysctl.h> 52 #include <sys/power.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include <machine/asmacros.h> 58 #include <machine/clock.h> 59 #include <machine/cputypes.h> 60 #include <machine/frame.h> 61 #include <machine/intr_machdep.h> 62 #include <machine/md_var.h> 63 #include <machine/segments.h> 64 #include <machine/specialreg.h> 65 66 #include <amd64/vmm/intel/vmx_controls.h> 67 #include <x86/isa/icu.h> 68 #include <x86/vmware.h> 69 70 #ifdef XENHVM 71 #include <xen/xen-os.h> 72 #endif 73 74 #ifdef __i386__ 75 #define IDENTBLUE_CYRIX486 0 76 #define IDENTBLUE_IBMCPU 1 77 #define IDENTBLUE_CYRIXM2 2 78 79 static void identifycyrix(void); 80 static void print_transmeta_info(void); 81 #endif 82 static u_int find_cpu_vendor_id(void); 83 static void print_AMD_info(void); 84 static void print_INTEL_info(void); 85 static void print_INTEL_TLB(u_int data); 86 static void print_hypervisor_info(void); 87 static void print_svm_info(void); 88 static void print_via_padlock_info(void); 89 static void print_vmx_info(void); 90 91 #ifdef __i386__ 92 int cpu; /* Are we 386, 386sx, 486, etc? */ 93 int cpu_class; 94 #endif 95 u_int cpu_feature; /* Feature flags */ 96 u_int cpu_feature2; /* Feature flags */ 97 u_int amd_feature; /* AMD feature flags */ 98 u_int amd_feature2; /* AMD feature flags */ 99 u_int amd_rascap; /* AMD RAS capabilities */ 100 u_int amd_pminfo; /* AMD advanced power management info */ 101 u_int amd_extended_feature_extensions; 102 u_int via_feature_rng; /* VIA RNG features */ 103 u_int via_feature_xcrypt; /* VIA ACE features */ 104 u_int cpu_high; /* Highest arg to CPUID */ 105 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 106 u_int cpu_id; /* Stepping ID */ 107 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 108 u_int cpu_procinfo2; /* Multicore info */ 109 u_int cpu_procinfo3; 110 char cpu_vendor[20]; /* CPU Origin code */ 111 u_int cpu_vendor_id; /* CPU vendor ID */ 112 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 113 u_int cpu_clflush_line_size = 32; 114 /* leaf 7 %ecx = 0 */ 115 u_int cpu_stdext_feature; /* %ebx */ 116 u_int cpu_stdext_feature2; /* %ecx */ 117 u_int cpu_stdext_feature3; /* %edx */ 118 /* leaf 7 %ecx = 1 */ 119 u_int cpu_stdext_feature4; /* %eax */ 120 uint64_t cpu_ia32_arch_caps; 121 u_int cpu_max_ext_state_size; 122 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 123 u_int cpu_mon_mwait_edx; /* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */ 124 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 125 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 126 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 127 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */ 128 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */ 129 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */ 130 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */ 131 const char machine[] = MACHINE; 132 133 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 134 &via_feature_rng, 0, 135 "VIA RNG feature available in CPU"); 136 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 137 &via_feature_xcrypt, 0, 138 "VIA xcrypt feature available in CPU"); 139 140 #ifdef __amd64__ 141 #ifdef SCTL_MASK32 142 extern int adaptive_machine_arch; 143 #endif 144 145 static int 146 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 147 { 148 #ifdef SCTL_MASK32 149 static const char machine32[] = "i386"; 150 #endif 151 int error; 152 153 #ifdef SCTL_MASK32 154 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 155 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 156 else 157 #endif 158 error = SYSCTL_OUT(req, machine, sizeof(machine)); 159 return (error); 160 161 } 162 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 163 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 164 #else 165 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD, 166 machine, "Machine class"); 167 #endif 168 169 char cpu_model[128]; 170 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD, 171 cpu_model, 0, "Machine model"); 172 173 static int hw_clockrate; 174 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 175 &hw_clockrate, 0, "CPU instruction clock rate"); 176 177 u_int hv_base; 178 u_int hv_high; 179 char hv_vendor[16]; 180 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 181 0, "Hypervisor vendor"); 182 183 static eventhandler_tag tsc_post_tag; 184 185 static char cpu_brand[48]; 186 187 #ifdef __i386__ 188 #define MAX_BRAND_INDEX 8 189 190 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 191 NULL, /* No brand */ 192 "Intel Celeron", 193 "Intel Pentium III", 194 "Intel Pentium III Xeon", 195 NULL, 196 NULL, 197 NULL, 198 NULL, 199 "Intel Pentium 4" 200 }; 201 202 static struct { 203 char *cpu_name; 204 int cpu_class; 205 } cpus[] = { 206 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 207 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 208 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 209 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 210 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 211 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 212 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 213 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 214 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 215 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 216 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 217 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 218 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 219 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 220 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 221 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 222 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 223 }; 224 #endif 225 226 static struct { 227 char *vendor; 228 u_int vendor_id; 229 } cpu_vendors[] = { 230 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 231 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 232 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */ 233 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 234 #ifdef __i386__ 235 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 236 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 237 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 238 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 239 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 240 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 241 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 242 #if 0 243 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 244 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 245 #endif 246 #endif 247 }; 248 249 void 250 printcpuinfo(void) 251 { 252 u_int regs[4], i; 253 char *brand; 254 255 printf("CPU: "); 256 #ifdef __i386__ 257 cpu_class = cpus[cpu].cpu_class; 258 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 259 #else 260 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 261 #endif 262 263 /* Check for extended CPUID information and a processor name. */ 264 if (cpu_exthigh >= 0x80000004) { 265 brand = cpu_brand; 266 for (i = 0x80000002; i < 0x80000005; i++) { 267 do_cpuid(i, regs); 268 memcpy(brand, regs, sizeof(regs)); 269 brand += sizeof(regs); 270 } 271 } 272 273 switch (cpu_vendor_id) { 274 case CPU_VENDOR_INTEL: 275 #ifdef __i386__ 276 if ((cpu_id & 0xf00) > 0x300) { 277 u_int brand_index; 278 279 cpu_model[0] = '\0'; 280 281 switch (cpu_id & 0x3000) { 282 case 0x1000: 283 strcpy(cpu_model, "Overdrive "); 284 break; 285 case 0x2000: 286 strcpy(cpu_model, "Dual "); 287 break; 288 } 289 290 switch (cpu_id & 0xf00) { 291 case 0x400: 292 strcat(cpu_model, "i486 "); 293 /* Check the particular flavor of 486 */ 294 switch (cpu_id & 0xf0) { 295 case 0x00: 296 case 0x10: 297 strcat(cpu_model, "DX"); 298 break; 299 case 0x20: 300 strcat(cpu_model, "SX"); 301 break; 302 case 0x30: 303 strcat(cpu_model, "DX2"); 304 break; 305 case 0x40: 306 strcat(cpu_model, "SL"); 307 break; 308 case 0x50: 309 strcat(cpu_model, "SX2"); 310 break; 311 case 0x70: 312 strcat(cpu_model, 313 "DX2 Write-Back Enhanced"); 314 break; 315 case 0x80: 316 strcat(cpu_model, "DX4"); 317 break; 318 } 319 break; 320 case 0x500: 321 /* Check the particular flavor of 586 */ 322 strcat(cpu_model, "Pentium"); 323 switch (cpu_id & 0xf0) { 324 case 0x00: 325 strcat(cpu_model, " A-step"); 326 break; 327 case 0x10: 328 strcat(cpu_model, "/P5"); 329 break; 330 case 0x20: 331 strcat(cpu_model, "/P54C"); 332 break; 333 case 0x30: 334 strcat(cpu_model, "/P24T"); 335 break; 336 case 0x40: 337 strcat(cpu_model, "/P55C"); 338 break; 339 case 0x70: 340 strcat(cpu_model, "/P54C"); 341 break; 342 case 0x80: 343 strcat(cpu_model, "/P55C (quarter-micron)"); 344 break; 345 default: 346 /* nothing */ 347 break; 348 } 349 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 350 /* 351 * XXX - If/when Intel fixes the bug, this 352 * should also check the version of the 353 * CPU, not just that it's a Pentium. 354 */ 355 has_f00f_bug = 1; 356 #endif 357 break; 358 case 0x600: 359 /* Check the particular flavor of 686 */ 360 switch (cpu_id & 0xf0) { 361 case 0x00: 362 strcat(cpu_model, "Pentium Pro A-step"); 363 break; 364 case 0x10: 365 strcat(cpu_model, "Pentium Pro"); 366 break; 367 case 0x30: 368 case 0x50: 369 case 0x60: 370 strcat(cpu_model, 371 "Pentium II/Pentium II Xeon/Celeron"); 372 cpu = CPU_PII; 373 break; 374 case 0x70: 375 case 0x80: 376 case 0xa0: 377 case 0xb0: 378 strcat(cpu_model, 379 "Pentium III/Pentium III Xeon/Celeron"); 380 cpu = CPU_PIII; 381 break; 382 default: 383 strcat(cpu_model, "Unknown 80686"); 384 break; 385 } 386 break; 387 case 0xf00: 388 strcat(cpu_model, "Pentium 4"); 389 cpu = CPU_P4; 390 break; 391 default: 392 strcat(cpu_model, "unknown"); 393 break; 394 } 395 396 /* 397 * If we didn't get a brand name from the extended 398 * CPUID, try to look it up in the brand table. 399 */ 400 if (cpu_high > 0 && *cpu_brand == '\0') { 401 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 402 if (brand_index <= MAX_BRAND_INDEX && 403 cpu_brandtable[brand_index] != NULL) 404 strcpy(cpu_brand, 405 cpu_brandtable[brand_index]); 406 } 407 } 408 #else 409 /* Please make up your mind folks! */ 410 strcat(cpu_model, "EM64T"); 411 #endif 412 break; 413 case CPU_VENDOR_AMD: 414 /* 415 * Values taken from AMD Processor Recognition 416 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 417 * (also describes ``Features'' encodings. 418 */ 419 strcpy(cpu_model, "AMD "); 420 #ifdef __i386__ 421 switch (cpu_id & 0xFF0) { 422 case 0x410: 423 strcat(cpu_model, "Standard Am486DX"); 424 break; 425 case 0x430: 426 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 427 break; 428 case 0x470: 429 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 430 break; 431 case 0x480: 432 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 433 break; 434 case 0x490: 435 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 436 break; 437 case 0x4E0: 438 strcat(cpu_model, "Am5x86 Write-Through"); 439 break; 440 case 0x4F0: 441 strcat(cpu_model, "Am5x86 Write-Back"); 442 break; 443 case 0x500: 444 strcat(cpu_model, "K5 model 0"); 445 break; 446 case 0x510: 447 strcat(cpu_model, "K5 model 1"); 448 break; 449 case 0x520: 450 strcat(cpu_model, "K5 PR166 (model 2)"); 451 break; 452 case 0x530: 453 strcat(cpu_model, "K5 PR200 (model 3)"); 454 break; 455 case 0x560: 456 strcat(cpu_model, "K6"); 457 break; 458 case 0x570: 459 strcat(cpu_model, "K6 266 (model 1)"); 460 break; 461 case 0x580: 462 strcat(cpu_model, "K6-2"); 463 break; 464 case 0x590: 465 strcat(cpu_model, "K6-III"); 466 break; 467 case 0x5a0: 468 strcat(cpu_model, "Geode LX"); 469 break; 470 default: 471 strcat(cpu_model, "Unknown"); 472 break; 473 } 474 #else 475 if ((cpu_id & 0xf00) == 0xf00) 476 strcat(cpu_model, "AMD64 Processor"); 477 else 478 strcat(cpu_model, "Unknown"); 479 #endif 480 break; 481 #ifdef __i386__ 482 case CPU_VENDOR_CYRIX: 483 strcpy(cpu_model, "Cyrix "); 484 switch (cpu_id & 0xff0) { 485 case 0x440: 486 strcat(cpu_model, "MediaGX"); 487 break; 488 case 0x520: 489 strcat(cpu_model, "6x86"); 490 break; 491 case 0x540: 492 cpu_class = CPUCLASS_586; 493 strcat(cpu_model, "GXm"); 494 break; 495 case 0x600: 496 strcat(cpu_model, "6x86MX"); 497 break; 498 default: 499 /* 500 * Even though CPU supports the cpuid 501 * instruction, it can be disabled. 502 * Therefore, this routine supports all Cyrix 503 * CPUs. 504 */ 505 switch (cyrix_did & 0xf0) { 506 case 0x00: 507 switch (cyrix_did & 0x0f) { 508 case 0x00: 509 strcat(cpu_model, "486SLC"); 510 break; 511 case 0x01: 512 strcat(cpu_model, "486DLC"); 513 break; 514 case 0x02: 515 strcat(cpu_model, "486SLC2"); 516 break; 517 case 0x03: 518 strcat(cpu_model, "486DLC2"); 519 break; 520 case 0x04: 521 strcat(cpu_model, "486SRx"); 522 break; 523 case 0x05: 524 strcat(cpu_model, "486DRx"); 525 break; 526 case 0x06: 527 strcat(cpu_model, "486SRx2"); 528 break; 529 case 0x07: 530 strcat(cpu_model, "486DRx2"); 531 break; 532 case 0x08: 533 strcat(cpu_model, "486SRu"); 534 break; 535 case 0x09: 536 strcat(cpu_model, "486DRu"); 537 break; 538 case 0x0a: 539 strcat(cpu_model, "486SRu2"); 540 break; 541 case 0x0b: 542 strcat(cpu_model, "486DRu2"); 543 break; 544 default: 545 strcat(cpu_model, "Unknown"); 546 break; 547 } 548 break; 549 case 0x10: 550 switch (cyrix_did & 0x0f) { 551 case 0x00: 552 strcat(cpu_model, "486S"); 553 break; 554 case 0x01: 555 strcat(cpu_model, "486S2"); 556 break; 557 case 0x02: 558 strcat(cpu_model, "486Se"); 559 break; 560 case 0x03: 561 strcat(cpu_model, "486S2e"); 562 break; 563 case 0x0a: 564 strcat(cpu_model, "486DX"); 565 break; 566 case 0x0b: 567 strcat(cpu_model, "486DX2"); 568 break; 569 case 0x0f: 570 strcat(cpu_model, "486DX4"); 571 break; 572 default: 573 strcat(cpu_model, "Unknown"); 574 break; 575 } 576 break; 577 case 0x20: 578 if ((cyrix_did & 0x0f) < 8) 579 strcat(cpu_model, "6x86"); /* Where did you get it? */ 580 else 581 strcat(cpu_model, "5x86"); 582 break; 583 case 0x30: 584 strcat(cpu_model, "6x86"); 585 break; 586 case 0x40: 587 if ((cyrix_did & 0xf000) == 0x3000) { 588 cpu_class = CPUCLASS_586; 589 strcat(cpu_model, "GXm"); 590 } else 591 strcat(cpu_model, "MediaGX"); 592 break; 593 case 0x50: 594 strcat(cpu_model, "6x86MX"); 595 break; 596 case 0xf0: 597 switch (cyrix_did & 0x0f) { 598 case 0x0d: 599 strcat(cpu_model, "Overdrive CPU"); 600 break; 601 case 0x0e: 602 strcpy(cpu_model, "Texas Instruments 486SXL"); 603 break; 604 case 0x0f: 605 strcat(cpu_model, "486SLC/DLC"); 606 break; 607 default: 608 strcat(cpu_model, "Unknown"); 609 break; 610 } 611 break; 612 default: 613 strcat(cpu_model, "Unknown"); 614 break; 615 } 616 break; 617 } 618 break; 619 case CPU_VENDOR_RISE: 620 strcpy(cpu_model, "Rise "); 621 switch (cpu_id & 0xff0) { 622 case 0x500: /* 6401 and 6441 (Kirin) */ 623 case 0x520: /* 6510 (Lynx) */ 624 strcat(cpu_model, "mP6"); 625 break; 626 default: 627 strcat(cpu_model, "Unknown"); 628 } 629 break; 630 #endif 631 case CPU_VENDOR_CENTAUR: 632 #ifdef __i386__ 633 switch (cpu_id & 0xff0) { 634 case 0x540: 635 strcpy(cpu_model, "IDT WinChip C6"); 636 break; 637 case 0x580: 638 strcpy(cpu_model, "IDT WinChip 2"); 639 break; 640 case 0x590: 641 strcpy(cpu_model, "IDT WinChip 3"); 642 break; 643 case 0x660: 644 strcpy(cpu_model, "VIA C3 Samuel"); 645 break; 646 case 0x670: 647 if (cpu_id & 0x8) 648 strcpy(cpu_model, "VIA C3 Ezra"); 649 else 650 strcpy(cpu_model, "VIA C3 Samuel 2"); 651 break; 652 case 0x680: 653 strcpy(cpu_model, "VIA C3 Ezra-T"); 654 break; 655 case 0x690: 656 strcpy(cpu_model, "VIA C3 Nehemiah"); 657 break; 658 case 0x6a0: 659 case 0x6d0: 660 strcpy(cpu_model, "VIA C7 Esther"); 661 break; 662 case 0x6f0: 663 strcpy(cpu_model, "VIA Nano"); 664 break; 665 default: 666 strcpy(cpu_model, "VIA/IDT Unknown"); 667 } 668 #else 669 strcpy(cpu_model, "VIA "); 670 if ((cpu_id & 0xff0) == 0x6f0) 671 strcat(cpu_model, "Nano Processor"); 672 else 673 strcat(cpu_model, "Unknown"); 674 #endif 675 break; 676 #ifdef __i386__ 677 case CPU_VENDOR_IBM: 678 strcpy(cpu_model, "Blue Lightning CPU"); 679 break; 680 case CPU_VENDOR_NSC: 681 switch (cpu_id & 0xff0) { 682 case 0x540: 683 strcpy(cpu_model, "Geode SC1100"); 684 cpu = CPU_GEODE1100; 685 break; 686 default: 687 strcpy(cpu_model, "Geode/NSC unknown"); 688 break; 689 } 690 break; 691 #endif 692 case CPU_VENDOR_HYGON: 693 strcpy(cpu_model, "Hygon "); 694 #ifdef __i386__ 695 strcat(cpu_model, "Unknown"); 696 #else 697 if ((cpu_id & 0xf00) == 0xf00) 698 strcat(cpu_model, "AMD64 Processor"); 699 else 700 strcat(cpu_model, "Unknown"); 701 #endif 702 break; 703 704 default: 705 strcat(cpu_model, "Unknown"); 706 break; 707 } 708 709 /* 710 * Replace cpu_model with cpu_brand minus leading spaces if 711 * we have one. 712 */ 713 brand = cpu_brand; 714 while (*brand == ' ') 715 ++brand; 716 if (*brand != '\0') 717 strcpy(cpu_model, brand); 718 719 printf("%s (", cpu_model); 720 if (tsc_freq != 0) { 721 hw_clockrate = (tsc_freq + 5000) / 1000000; 722 printf("%jd.%02d-MHz ", 723 (intmax_t)(tsc_freq + 4999) / 1000000, 724 (u_int)((tsc_freq + 4999) / 10000) % 100); 725 } 726 #ifdef __i386__ 727 switch(cpu_class) { 728 case CPUCLASS_286: 729 printf("286"); 730 break; 731 case CPUCLASS_386: 732 printf("386"); 733 break; 734 #if defined(I486_CPU) 735 case CPUCLASS_486: 736 printf("486"); 737 break; 738 #endif 739 #if defined(I586_CPU) 740 case CPUCLASS_586: 741 printf("586"); 742 break; 743 #endif 744 #if defined(I686_CPU) 745 case CPUCLASS_686: 746 printf("686"); 747 break; 748 #endif 749 default: 750 printf("Unknown"); /* will panic below... */ 751 } 752 #else 753 printf("K8"); 754 #endif 755 printf("-class CPU)\n"); 756 if (*cpu_vendor) 757 printf(" Origin=\"%s\"", cpu_vendor); 758 if (cpu_id) 759 printf(" Id=0x%x", cpu_id); 760 761 if (cpu_vendor_id == CPU_VENDOR_INTEL || 762 cpu_vendor_id == CPU_VENDOR_AMD || 763 cpu_vendor_id == CPU_VENDOR_HYGON || 764 cpu_vendor_id == CPU_VENDOR_CENTAUR || 765 #ifdef __i386__ 766 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 767 cpu_vendor_id == CPU_VENDOR_RISE || 768 cpu_vendor_id == CPU_VENDOR_NSC || 769 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 770 #endif 771 0) { 772 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 773 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 774 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 775 #ifdef __i386__ 776 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 777 printf("\n DIR=0x%04x", cyrix_did); 778 #endif 779 780 /* 781 * AMD CPUID Specification 782 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 783 * 784 * Intel Processor Identification and CPUID Instruction 785 * http://www.intel.com/assets/pdf/appnote/241618.pdf 786 */ 787 if (cpu_high > 0) { 788 /* 789 * Here we should probably set up flags indicating 790 * whether or not various features are available. 791 * The interesting ones are probably VME, PSE, PAE, 792 * and PGE. The code already assumes without bothering 793 * to check that all CPUs >= Pentium have a TSC and 794 * MSRs. 795 */ 796 printf("\n Features=0x%b", cpu_feature, 797 "\020" 798 "\001FPU" /* Integral FPU */ 799 "\002VME" /* Extended VM86 mode support */ 800 "\003DE" /* Debugging Extensions (CR4.DE) */ 801 "\004PSE" /* 4MByte page tables */ 802 "\005TSC" /* Timestamp counter */ 803 "\006MSR" /* Machine specific registers */ 804 "\007PAE" /* Physical address extension */ 805 "\010MCE" /* Machine Check support */ 806 "\011CX8" /* CMPEXCH8 instruction */ 807 "\012APIC" /* SMP local APIC */ 808 "\013oldMTRR" /* Previous implementation of MTRR */ 809 "\014SEP" /* Fast System Call */ 810 "\015MTRR" /* Memory Type Range Registers */ 811 "\016PGE" /* PG_G (global bit) support */ 812 "\017MCA" /* Machine Check Architecture */ 813 "\020CMOV" /* CMOV instruction */ 814 "\021PAT" /* Page attributes table */ 815 "\022PSE36" /* 36 bit address space support */ 816 "\023PN" /* Processor Serial number */ 817 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 818 "\025<b20>" 819 "\026DTS" /* Debug Trace Store */ 820 "\027ACPI" /* ACPI support */ 821 "\030MMX" /* MMX instructions */ 822 "\031FXSR" /* FXSAVE/FXRSTOR */ 823 "\032SSE" /* Streaming SIMD Extensions */ 824 "\033SSE2" /* Streaming SIMD Extensions #2 */ 825 "\034SS" /* Self snoop */ 826 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 827 "\036TM" /* Thermal Monitor clock slowdown */ 828 "\037IA64" /* CPU can execute IA64 instructions */ 829 "\040PBE" /* Pending Break Enable */ 830 ); 831 832 if (cpu_feature2 != 0) { 833 printf("\n Features2=0x%b", cpu_feature2, 834 "\020" 835 "\001SSE3" /* SSE3 */ 836 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 837 "\003DTES64" /* 64-bit Debug Trace */ 838 "\004MON" /* MONITOR/MWAIT Instructions */ 839 "\005DS_CPL" /* CPL Qualified Debug Store */ 840 "\006VMX" /* Virtual Machine Extensions */ 841 "\007SMX" /* Safer Mode Extensions */ 842 "\010EST" /* Enhanced SpeedStep */ 843 "\011TM2" /* Thermal Monitor 2 */ 844 "\012SSSE3" /* SSSE3 */ 845 "\013CNXT-ID" /* L1 context ID available */ 846 "\014SDBG" /* IA32 silicon debug */ 847 "\015FMA" /* Fused Multiply Add */ 848 "\016CX16" /* CMPXCHG16B Instruction */ 849 "\017xTPR" /* Send Task Priority Messages*/ 850 "\020PDCM" /* Perf/Debug Capability MSR */ 851 "\021<b16>" 852 "\022PCID" /* Process-context Identifiers*/ 853 "\023DCA" /* Direct Cache Access */ 854 "\024SSE4.1" /* SSE 4.1 */ 855 "\025SSE4.2" /* SSE 4.2 */ 856 "\026x2APIC" /* xAPIC Extensions */ 857 "\027MOVBE" /* MOVBE Instruction */ 858 "\030POPCNT" /* POPCNT Instruction */ 859 "\031TSCDLT" /* TSC-Deadline Timer */ 860 "\032AESNI" /* AES Crypto */ 861 "\033XSAVE" /* XSAVE/XRSTOR States */ 862 "\034OSXSAVE" /* OS-Enabled State Management*/ 863 "\035AVX" /* Advanced Vector Extensions */ 864 "\036F16C" /* Half-precision conversions */ 865 "\037RDRAND" /* RDRAND Instruction */ 866 "\040HV" /* Hypervisor */ 867 ); 868 } 869 870 if (amd_feature != 0) { 871 printf("\n AMD Features=0x%b", amd_feature, 872 "\020" /* in hex */ 873 "\001<s0>" /* Same */ 874 "\002<s1>" /* Same */ 875 "\003<s2>" /* Same */ 876 "\004<s3>" /* Same */ 877 "\005<s4>" /* Same */ 878 "\006<s5>" /* Same */ 879 "\007<s6>" /* Same */ 880 "\010<s7>" /* Same */ 881 "\011<s8>" /* Same */ 882 "\012<s9>" /* Same */ 883 "\013<b10>" /* Undefined */ 884 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 885 "\015<s12>" /* Same */ 886 "\016<s13>" /* Same */ 887 "\017<s14>" /* Same */ 888 "\020<s15>" /* Same */ 889 "\021<s16>" /* Same */ 890 "\022<s17>" /* Same */ 891 "\023<b18>" /* Reserved, unknown */ 892 "\024MP" /* Multiprocessor Capable */ 893 "\025NX" /* Has EFER.NXE, NX */ 894 "\026<b21>" /* Undefined */ 895 "\027MMX+" /* AMD MMX Extensions */ 896 "\030<s23>" /* Same */ 897 "\031<s24>" /* Same */ 898 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 899 "\033Page1GB" /* 1-GB large page support */ 900 "\034RDTSCP" /* RDTSCP */ 901 "\035<b28>" /* Undefined */ 902 "\036LM" /* 64 bit long mode */ 903 "\0373DNow!+" /* AMD 3DNow! Extensions */ 904 "\0403DNow!" /* AMD 3DNow! */ 905 ); 906 } 907 908 if (amd_feature2 != 0) { 909 printf("\n AMD Features2=0x%b", amd_feature2, 910 "\020" 911 "\001LAHF" /* LAHF/SAHF in long mode */ 912 "\002CMP" /* CMP legacy */ 913 "\003SVM" /* Secure Virtual Mode */ 914 "\004ExtAPIC" /* Extended APIC register */ 915 "\005CR8" /* CR8 in legacy mode */ 916 "\006ABM" /* LZCNT instruction */ 917 "\007SSE4A" /* SSE4A */ 918 "\010MAS" /* Misaligned SSE mode */ 919 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 920 "\012OSVW" /* OS visible workaround */ 921 "\013IBS" /* Instruction based sampling */ 922 "\014XOP" /* XOP extended instructions */ 923 "\015SKINIT" /* SKINIT/STGI */ 924 "\016WDT" /* Watchdog timer */ 925 "\017<b14>" 926 "\020LWP" /* Lightweight Profiling */ 927 "\021FMA4" /* 4-operand FMA instructions */ 928 "\022TCE" /* Translation Cache Extension */ 929 "\023<b18>" 930 "\024NodeId" /* NodeId MSR support */ 931 "\025<b20>" 932 "\026TBM" /* Trailing Bit Manipulation */ 933 "\027Topology" /* Topology Extensions */ 934 "\030PCXC" /* Core perf count */ 935 "\031PNXC" /* NB perf count */ 936 "\032<b25>" 937 "\033DBE" /* Data Breakpoint extension */ 938 "\034PTSC" /* Performance TSC */ 939 "\035PL2I" /* L2I perf count */ 940 "\036MWAITX" /* MONITORX/MWAITX instructions */ 941 "\037ADMSKX" /* Address mask extension */ 942 "\040<b31>" 943 ); 944 } 945 946 if (cpu_stdext_feature != 0) { 947 printf("\n Structured Extended Features=0x%b", 948 cpu_stdext_feature, 949 "\020" 950 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 951 "\001FSGSBASE" 952 "\002TSCADJ" 953 "\003SGX" 954 /* Bit Manipulation Instructions */ 955 "\004BMI1" 956 /* Hardware Lock Elision */ 957 "\005HLE" 958 /* Advanced Vector Instructions 2 */ 959 "\006AVX2" 960 /* FDP_EXCPTN_ONLY */ 961 "\007FDPEXC" 962 /* Supervisor Mode Execution Prot. */ 963 "\010SMEP" 964 /* Bit Manipulation Instructions */ 965 "\011BMI2" 966 "\012ERMS" 967 /* Invalidate Processor Context ID */ 968 "\013INVPCID" 969 /* Restricted Transactional Memory */ 970 "\014RTM" 971 "\015PQM" 972 "\016NFPUSG" 973 /* Intel Memory Protection Extensions */ 974 "\017MPX" 975 "\020PQE" 976 /* AVX512 Foundation */ 977 "\021AVX512F" 978 "\022AVX512DQ" 979 /* Enhanced NRBG */ 980 "\023RDSEED" 981 /* ADCX + ADOX */ 982 "\024ADX" 983 /* Supervisor Mode Access Prevention */ 984 "\025SMAP" 985 "\026AVX512IFMA" 986 /* Formerly PCOMMIT */ 987 "\027<b22>" 988 "\030CLFLUSHOPT" 989 "\031CLWB" 990 "\032PROCTRACE" 991 "\033AVX512PF" 992 "\034AVX512ER" 993 "\035AVX512CD" 994 "\036SHA" 995 "\037AVX512BW" 996 "\040AVX512VL" 997 ); 998 } 999 1000 if (cpu_stdext_feature2 != 0) { 1001 printf("\n Structured Extended Features2=0x%b", 1002 cpu_stdext_feature2, 1003 "\020" 1004 "\001PREFETCHWT1" 1005 "\002AVX512VBMI" 1006 "\003UMIP" 1007 "\004PKU" 1008 "\005OSPKE" 1009 "\006WAITPKG" 1010 "\007AVX512VBMI2" 1011 "\011GFNI" 1012 "\012VAES" 1013 "\013VPCLMULQDQ" 1014 "\014AVX512VNNI" 1015 "\015AVX512BITALG" 1016 "\016TME" 1017 "\017AVX512VPOPCNTDQ" 1018 "\021LA57" 1019 "\027RDPID" 1020 "\032CLDEMOTE" 1021 "\034MOVDIRI" 1022 "\035MOVDIR64B" 1023 "\036ENQCMD" 1024 "\037SGXLC" 1025 ); 1026 } 1027 1028 if (cpu_stdext_feature3 != 0) { 1029 printf("\n Structured Extended Features3=0x%b", 1030 cpu_stdext_feature3, 1031 "\020" 1032 "\003AVX512_4VNNIW" 1033 "\004AVX512_4FMAPS" 1034 "\005FSRM" 1035 "\011AVX512VP2INTERSECT" 1036 "\012MCUOPT" 1037 "\013MD_CLEAR" 1038 "\016TSXFA" 1039 "\023PCONFIG" 1040 "\025IBT" 1041 "\033IBPB" 1042 "\034STIBP" 1043 "\035L1DFL" 1044 "\036ARCH_CAP" 1045 "\037CORE_CAP" 1046 "\040SSBD" 1047 ); 1048 } 1049 #define STDEXT4_MASK (CPUID_STDEXT4_LASS | CPUID_STDEXT4_LAM) 1050 if ((cpu_stdext_feature4 & STDEXT4_MASK) != 0) { 1051 printf("\n Structured Extended Features4=0x%b", 1052 cpu_stdext_feature4 & STDEXT4_MASK, 1053 "\020" 1054 "\007LASS" 1055 "\033LAM" 1056 ); 1057 } 1058 #undef STDEXT4_MASK 1059 1060 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1061 cpuid_count(0xd, 0x1, regs); 1062 if (regs[0] != 0) { 1063 printf("\n XSAVE Features=0x%b", 1064 regs[0], 1065 "\020" 1066 "\001XSAVEOPT" 1067 "\002XSAVEC" 1068 "\003XINUSE" 1069 "\004XSAVES"); 1070 } 1071 } 1072 1073 if (cpu_ia32_arch_caps != 0) { 1074 printf("\n IA32_ARCH_CAPS=0x%b", 1075 (u_int)cpu_ia32_arch_caps, 1076 "\020" 1077 "\001RDCL_NO" 1078 "\002IBRS_ALL" 1079 "\003RSBA" 1080 "\004SKIP_L1DFL_VME" 1081 "\005SSB_NO" 1082 "\006MDS_NO" 1083 "\010TSX_CTRL" 1084 "\011TAA_NO" 1085 ); 1086 } 1087 1088 if (amd_extended_feature_extensions != 0) { 1089 u_int amd_fe_masked; 1090 1091 amd_fe_masked = amd_extended_feature_extensions; 1092 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1093 amd_fe_masked &= 1094 ~(AMDFEID_IBRS_ALWAYSON | 1095 AMDFEID_PREFER_IBRS); 1096 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1097 amd_fe_masked &= 1098 ~AMDFEID_STIBP_ALWAYSON; 1099 1100 printf("\n " 1101 "AMD Extended Feature Extensions ID EBX=" 1102 "0x%b", amd_fe_masked, 1103 "\020" 1104 "\001CLZERO" 1105 "\002IRPerf" 1106 "\003XSaveErPtr" 1107 "\004INVLPGB" 1108 "\005RDPRU" 1109 "\007BE" 1110 "\011MCOMMIT" 1111 "\012WBNOINVD" 1112 "\015IBPB" 1113 "\016INT_WBINVD" 1114 "\017IBRS" 1115 "\020STIBP" 1116 "\021IBRS_ALWAYSON" 1117 "\022STIBP_ALWAYSON" 1118 "\023PREFER_IBRS" 1119 "\024SAMEMODE_IBRS" 1120 "\025NOLMSLE" 1121 "\026INVLPGBNEST" 1122 "\030PPIN" 1123 "\031SSBD" 1124 "\032VIRT_SSBD" 1125 "\033SSB_NO" 1126 "\034CPPC" 1127 "\035PSFD" 1128 "\036BTC_NO" 1129 "\037IBPB_RET" 1130 ); 1131 } 1132 1133 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1134 print_via_padlock_info(); 1135 1136 if (cpu_feature2 & CPUID2_VMX) 1137 print_vmx_info(); 1138 1139 if (amd_feature2 & AMDID2_SVM) 1140 print_svm_info(); 1141 1142 if ((cpu_feature & CPUID_HTT) && 1143 (cpu_vendor_id == CPU_VENDOR_AMD || 1144 cpu_vendor_id == CPU_VENDOR_HYGON)) 1145 cpu_feature &= ~CPUID_HTT; 1146 1147 /* 1148 * If this CPU supports P-state invariant TSC then 1149 * mention the capability. 1150 */ 1151 if (tsc_is_invariant) { 1152 printf("\n TSC: P-state invariant"); 1153 if (tsc_perf_stat) 1154 printf(", performance statistics"); 1155 } 1156 } 1157 #ifdef __i386__ 1158 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1159 printf(" DIR=0x%04x", cyrix_did); 1160 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1161 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1162 #ifndef CYRIX_CACHE_REALLY_WORKS 1163 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1164 printf("\n CPU cache: write-through mode"); 1165 #endif 1166 #endif 1167 } 1168 1169 /* Avoid ugly blank lines: only print newline when we have to. */ 1170 if (*cpu_vendor || cpu_id) 1171 printf("\n"); 1172 1173 if (bootverbose) { 1174 if (cpu_vendor_id == CPU_VENDOR_AMD || 1175 cpu_vendor_id == CPU_VENDOR_HYGON) 1176 print_AMD_info(); 1177 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1178 print_INTEL_info(); 1179 #ifdef __i386__ 1180 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1181 print_transmeta_info(); 1182 #endif 1183 } 1184 1185 print_hypervisor_info(); 1186 } 1187 1188 #ifdef __i386__ 1189 void 1190 panicifcpuunsupported(void) 1191 { 1192 1193 #if !defined(lint) 1194 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1195 #error This kernel is not configured for one of the supported CPUs 1196 #endif 1197 #else /* lint */ 1198 #endif /* lint */ 1199 /* 1200 * Now that we have told the user what they have, 1201 * let them know if that machine type isn't configured. 1202 */ 1203 switch (cpu_class) { 1204 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1205 case CPUCLASS_386: 1206 #if !defined(I486_CPU) 1207 case CPUCLASS_486: 1208 #endif 1209 #if !defined(I586_CPU) 1210 case CPUCLASS_586: 1211 #endif 1212 #if !defined(I686_CPU) 1213 case CPUCLASS_686: 1214 #endif 1215 panic("CPU class not configured"); 1216 default: 1217 break; 1218 } 1219 } 1220 1221 static volatile u_int trap_by_rdmsr; 1222 1223 /* 1224 * Special exception 6 handler. 1225 * The rdmsr instruction generates invalid opcodes fault on 486-class 1226 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1227 * function identblue() when this handler is called. Stacked eip should 1228 * be advanced. 1229 */ 1230 inthand_t bluetrap6; 1231 __asm 1232 (" \n\ 1233 .text \n\ 1234 .p2align 2,0x90 \n\ 1235 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1236 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1237 ss \n\ 1238 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1239 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1240 iret \n\ 1241 "); 1242 1243 /* 1244 * Special exception 13 handler. 1245 * Accessing non-existent MSR generates general protection fault. 1246 */ 1247 inthand_t bluetrap13; 1248 __asm 1249 (" \n\ 1250 .text \n\ 1251 .p2align 2,0x90 \n\ 1252 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1253 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1254 ss \n\ 1255 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1256 popl %eax /* discard error code */ \n\ 1257 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1258 iret \n\ 1259 "); 1260 1261 /* 1262 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1263 * support cpuid instruction. This function should be called after 1264 * loading interrupt descriptor table register. 1265 * 1266 * I don't like this method that handles fault, but I couldn't get 1267 * information for any other methods. Does blue giant know? 1268 */ 1269 static int 1270 identblue(void) 1271 { 1272 1273 trap_by_rdmsr = 0; 1274 1275 /* 1276 * Cyrix 486-class CPU does not support rdmsr instruction. 1277 * The rdmsr instruction generates invalid opcode fault, and exception 1278 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1279 * bluetrap6() set the magic number to trap_by_rdmsr. 1280 */ 1281 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1282 GSEL(GCODE_SEL, SEL_KPL)); 1283 1284 /* 1285 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1286 * In this case, rdmsr generates general protection fault, and 1287 * exception will be trapped by bluetrap13(). 1288 */ 1289 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1290 GSEL(GCODE_SEL, SEL_KPL)); 1291 1292 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1293 1294 if (trap_by_rdmsr == 0xa8c1d) 1295 return IDENTBLUE_CYRIX486; 1296 else if (trap_by_rdmsr == 0xa89c4) 1297 return IDENTBLUE_CYRIXM2; 1298 return IDENTBLUE_IBMCPU; 1299 } 1300 1301 /* 1302 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1303 * 1304 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1305 * +-------+-------+---------------+ 1306 * | SID | RID | Device ID | 1307 * | (DIR 1) | (DIR 0) | 1308 * +-------+-------+---------------+ 1309 */ 1310 static void 1311 identifycyrix(void) 1312 { 1313 register_t saveintr; 1314 int ccr2_test = 0, dir_test = 0; 1315 u_char ccr2, ccr3; 1316 1317 saveintr = intr_disable(); 1318 1319 ccr2 = read_cyrix_reg(CCR2); 1320 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1321 read_cyrix_reg(CCR2); 1322 if (read_cyrix_reg(CCR2) != ccr2) 1323 ccr2_test = 1; 1324 write_cyrix_reg(CCR2, ccr2); 1325 1326 ccr3 = read_cyrix_reg(CCR3); 1327 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1328 read_cyrix_reg(CCR3); 1329 if (read_cyrix_reg(CCR3) != ccr3) 1330 dir_test = 1; /* CPU supports DIRs. */ 1331 write_cyrix_reg(CCR3, ccr3); 1332 1333 if (dir_test) { 1334 /* Device ID registers are available. */ 1335 cyrix_did = read_cyrix_reg(DIR1) << 8; 1336 cyrix_did += read_cyrix_reg(DIR0); 1337 } else if (ccr2_test) 1338 cyrix_did = 0x0010; /* 486S A-step */ 1339 else 1340 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1341 1342 intr_restore(saveintr); 1343 } 1344 #endif 1345 1346 /* Update TSC freq with the value indicated by the caller. */ 1347 static void 1348 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1349 { 1350 1351 /* If there was an error during the transition, don't do anything. */ 1352 if (status != 0) 1353 return; 1354 1355 /* Total setting for this level gives the new frequency in MHz. */ 1356 hw_clockrate = level->total_set.freq; 1357 } 1358 1359 static void 1360 hook_tsc_freq(void *arg __unused) 1361 { 1362 1363 if (tsc_is_invariant) 1364 return; 1365 1366 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1367 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1368 } 1369 1370 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1371 1372 static struct { 1373 const char *vm_cpuid; 1374 int vm_guest; 1375 void (*init)(void); 1376 } vm_cpuids[] = { 1377 { "XenVMMXenVMM", VM_GUEST_XEN, 1378 #ifdef XENHVM 1379 &xen_early_init, 1380 #endif 1381 }, /* XEN */ 1382 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */ 1383 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */ 1384 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */ 1385 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */ 1386 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */ 1387 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */ 1388 }; 1389 1390 static void 1391 identify_hypervisor_cpuid_base(void) 1392 { 1393 void (*init_fn)(void) = NULL; 1394 u_int leaf, regs[4]; 1395 int i; 1396 1397 /* 1398 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1399 * http://lkml.org/lkml/2008/10/1/246 1400 * 1401 * KB1009458: Mechanisms to determine if software is running in 1402 * a VMware virtual machine 1403 * http://kb.vmware.com/kb/1009458 1404 * 1405 * Search for a hypervisor that we recognize. If we cannot find 1406 * a specific hypervisor, return the first information about the 1407 * hypervisor that we found, as others may be able to use. 1408 */ 1409 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { 1410 do_cpuid(leaf, regs); 1411 1412 /* 1413 * KVM from Linux kernels prior to commit 1414 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1415 * to 0 rather than a valid hv_high value. Check for 1416 * the KVM signature bytes and fixup %eax to the 1417 * highest supported leaf in that case. 1418 */ 1419 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1420 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1421 regs[0] = leaf + 1; 1422 1423 if (regs[0] >= leaf) { 1424 enum VM_GUEST prev_vm_guest = vm_guest; 1425 1426 for (i = 0; i < nitems(vm_cpuids); i++) 1427 if (strncmp((const char *)®s[1], 1428 vm_cpuids[i].vm_cpuid, 12) == 0) { 1429 vm_guest = vm_cpuids[i].vm_guest; 1430 init_fn = vm_cpuids[i].init; 1431 break; 1432 } 1433 1434 /* 1435 * If this is the first entry or we found a 1436 * specific hypervisor, record the base, high value, 1437 * and vendor identifier. 1438 */ 1439 if (vm_guest != prev_vm_guest || leaf == 0x40000000) { 1440 hv_base = leaf; 1441 hv_high = regs[0]; 1442 ((u_int *)&hv_vendor)[0] = regs[1]; 1443 ((u_int *)&hv_vendor)[1] = regs[2]; 1444 ((u_int *)&hv_vendor)[2] = regs[3]; 1445 hv_vendor[12] = '\0'; 1446 1447 /* 1448 * If we found a specific hypervisor, then 1449 * we are finished. 1450 */ 1451 if (vm_guest != VM_GUEST_VM && 1452 /* 1453 * Xen and other hypervisors can expose the 1454 * HyperV signature in addition to the 1455 * native one in order to support Viridian 1456 * extensions for Windows guests. 1457 * 1458 * Do the full cpuid scan if HyperV is 1459 * detected, as the native hypervisor is 1460 * preferred. 1461 */ 1462 vm_guest != VM_GUEST_HV) 1463 break; 1464 } 1465 } 1466 } 1467 1468 if (init_fn != NULL) 1469 init_fn(); 1470 } 1471 1472 void 1473 identify_hypervisor(void) 1474 { 1475 u_int regs[4]; 1476 char *p; 1477 1478 TSENTER(); 1479 /* 1480 * If CPUID2_HV is set, we are running in a hypervisor environment. 1481 */ 1482 if (cpu_feature2 & CPUID2_HV) { 1483 vm_guest = VM_GUEST_VM; 1484 identify_hypervisor_cpuid_base(); 1485 1486 /* If we have a definitive vendor, we can return now. */ 1487 if (*hv_vendor != '\0') { 1488 TSEXIT(); 1489 return; 1490 } 1491 } 1492 1493 /* 1494 * Examine SMBIOS strings for older hypervisors. 1495 */ 1496 p = kern_getenv("smbios.system.serial"); 1497 if (p != NULL) { 1498 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1499 vmware_hvcall(0, VMW_HVCMD_GETVERSION, 1500 VMW_HVCMD_DEFAULT_PARAM, regs); 1501 if (regs[1] == VMW_HVMAGIC) { 1502 vm_guest = VM_GUEST_VMWARE; 1503 freeenv(p); 1504 TSEXIT(); 1505 return; 1506 } 1507 } 1508 freeenv(p); 1509 } 1510 TSEXIT(); 1511 } 1512 1513 bool 1514 fix_cpuid(void) 1515 { 1516 uint64_t msr; 1517 1518 /* 1519 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1520 * get the largest standard CPUID function number again if it is set 1521 * from BIOS. It is necessary for probing correct CPU topology later 1522 * and for the correct operation of the AVX-aware userspace. 1523 */ 1524 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1525 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1526 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1527 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1528 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1529 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1530 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1531 msr &= ~IA32_MISC_EN_LIMCPUID; 1532 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1533 return (true); 1534 } 1535 } 1536 1537 /* 1538 * Re-enable AMD Topology Extension that could be disabled by BIOS 1539 * on some notebook processors. Without the extension it's really 1540 * hard to determine the correct CPU cache topology. 1541 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1542 * Models 60h-6Fh Processors, Publication # 50742. 1543 */ 1544 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1545 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1546 msr = rdmsr(MSR_EXTFEATURES); 1547 if ((msr & ((uint64_t)1 << 54)) == 0) { 1548 msr |= (uint64_t)1 << 54; 1549 wrmsr(MSR_EXTFEATURES, msr); 1550 return (true); 1551 } 1552 } 1553 return (false); 1554 } 1555 1556 void 1557 identify_cpu1(void) 1558 { 1559 u_int regs[4]; 1560 1561 do_cpuid(0, regs); 1562 cpu_high = regs[0]; 1563 ((u_int *)&cpu_vendor)[0] = regs[1]; 1564 ((u_int *)&cpu_vendor)[1] = regs[3]; 1565 ((u_int *)&cpu_vendor)[2] = regs[2]; 1566 cpu_vendor[12] = '\0'; 1567 1568 do_cpuid(1, regs); 1569 cpu_id = regs[0]; 1570 cpu_procinfo = regs[1]; 1571 cpu_feature = regs[3]; 1572 cpu_feature2 = regs[2]; 1573 } 1574 1575 void 1576 identify_cpu2(void) 1577 { 1578 u_int regs[4], cpu_stdext_disable, max_eax_l7; 1579 1580 if (cpu_high >= 6) { 1581 cpuid_count(6, 0, regs); 1582 cpu_power_eax = regs[0]; 1583 cpu_power_ebx = regs[1]; 1584 cpu_power_ecx = regs[2]; 1585 cpu_power_edx = regs[3]; 1586 } 1587 1588 if (cpu_high >= 7) { 1589 cpuid_count(7, 0, regs); 1590 cpu_stdext_feature = regs[1]; 1591 max_eax_l7 = regs[0]; 1592 1593 /* 1594 * Some hypervisors failed to filter out unsupported 1595 * extended features. Allow to disable the 1596 * extensions, activation of which requires setting a 1597 * bit in CR4, and which VM monitors do not support. 1598 */ 1599 cpu_stdext_disable = 0; 1600 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1601 cpu_stdext_feature &= ~cpu_stdext_disable; 1602 1603 cpu_stdext_feature2 = regs[2]; 1604 cpu_stdext_feature3 = regs[3]; 1605 1606 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1607 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1608 1609 if (max_eax_l7 >= 1) { 1610 cpuid_count(7, 1, regs); 1611 cpu_stdext_feature4 = regs[0]; 1612 } 1613 } 1614 } 1615 1616 void 1617 identify_cpu_ext_features(void) 1618 { 1619 u_int regs[4]; 1620 1621 if (cpu_high >= 7) { 1622 cpuid_count(7, 0, regs); 1623 cpu_stdext_feature2 = regs[2]; 1624 cpu_stdext_feature3 = regs[3]; 1625 } 1626 } 1627 1628 void 1629 identify_cpu_fixup_bsp(void) 1630 { 1631 u_int regs[4]; 1632 1633 cpu_vendor_id = find_cpu_vendor_id(); 1634 1635 if (fix_cpuid()) { 1636 do_cpuid(0, regs); 1637 cpu_high = regs[0]; 1638 } 1639 } 1640 1641 /* 1642 * Final stage of CPU identification. 1643 */ 1644 void 1645 finishidentcpu(void) 1646 { 1647 u_int regs[4]; 1648 #ifdef __i386__ 1649 u_char ccr3; 1650 #endif 1651 1652 identify_cpu_fixup_bsp(); 1653 1654 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1655 do_cpuid(5, regs); 1656 cpu_mon_mwait_flags = regs[2]; 1657 cpu_mon_mwait_edx = regs[3]; 1658 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1659 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1660 } 1661 1662 identify_cpu2(); 1663 1664 #ifdef __i386__ 1665 if (cpu_high > 0 && 1666 (cpu_vendor_id == CPU_VENDOR_INTEL || 1667 cpu_vendor_id == CPU_VENDOR_AMD || 1668 cpu_vendor_id == CPU_VENDOR_HYGON || 1669 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1670 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1671 cpu_vendor_id == CPU_VENDOR_NSC)) { 1672 do_cpuid(0x80000000, regs); 1673 if (regs[0] >= 0x80000000) 1674 cpu_exthigh = regs[0]; 1675 } 1676 #else 1677 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1678 cpu_vendor_id == CPU_VENDOR_AMD || 1679 cpu_vendor_id == CPU_VENDOR_HYGON || 1680 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1681 do_cpuid(0x80000000, regs); 1682 cpu_exthigh = regs[0]; 1683 } 1684 #endif 1685 if (cpu_exthigh >= 0x80000001) { 1686 do_cpuid(0x80000001, regs); 1687 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1688 amd_feature2 = regs[2]; 1689 } 1690 if (cpu_exthigh >= 0x80000007) { 1691 do_cpuid(0x80000007, regs); 1692 amd_rascap = regs[1]; 1693 amd_pminfo = regs[3]; 1694 } 1695 if (cpu_exthigh >= 0x80000008) { 1696 do_cpuid(0x80000008, regs); 1697 cpu_maxphyaddr = regs[0] & 0xff; 1698 amd_extended_feature_extensions = regs[1]; 1699 cpu_procinfo2 = regs[2]; 1700 cpu_procinfo3 = regs[3]; 1701 } else { 1702 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1703 } 1704 1705 #ifdef __i386__ 1706 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1707 if (cpu == CPU_486) { 1708 /* 1709 * These conditions are equivalent to: 1710 * - CPU does not support cpuid instruction. 1711 * - Cyrix/IBM CPU is detected. 1712 */ 1713 if (identblue() == IDENTBLUE_IBMCPU) { 1714 strcpy(cpu_vendor, "IBM"); 1715 cpu_vendor_id = CPU_VENDOR_IBM; 1716 cpu = CPU_BLUE; 1717 return; 1718 } 1719 } 1720 switch (cpu_id & 0xf00) { 1721 case 0x600: 1722 /* 1723 * Cyrix's datasheet does not describe DIRs. 1724 * Therefor, I assume it does not have them 1725 * and use the result of the cpuid instruction. 1726 * XXX they seem to have it for now at least. -Peter 1727 */ 1728 identifycyrix(); 1729 cpu = CPU_M2; 1730 break; 1731 default: 1732 identifycyrix(); 1733 /* 1734 * This routine contains a trick. 1735 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1736 */ 1737 switch (cyrix_did & 0x00f0) { 1738 case 0x00: 1739 case 0xf0: 1740 cpu = CPU_486DLC; 1741 break; 1742 case 0x10: 1743 cpu = CPU_CY486DX; 1744 break; 1745 case 0x20: 1746 if ((cyrix_did & 0x000f) < 8) 1747 cpu = CPU_M1; 1748 else 1749 cpu = CPU_M1SC; 1750 break; 1751 case 0x30: 1752 cpu = CPU_M1; 1753 break; 1754 case 0x40: 1755 /* MediaGX CPU */ 1756 cpu = CPU_M1SC; 1757 break; 1758 default: 1759 /* M2 and later CPUs are treated as M2. */ 1760 cpu = CPU_M2; 1761 1762 /* 1763 * enable cpuid instruction. 1764 */ 1765 ccr3 = read_cyrix_reg(CCR3); 1766 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1767 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1768 write_cyrix_reg(CCR3, ccr3); 1769 1770 do_cpuid(0, regs); 1771 cpu_high = regs[0]; /* eax */ 1772 do_cpuid(1, regs); 1773 cpu_id = regs[0]; /* eax */ 1774 cpu_feature = regs[3]; /* edx */ 1775 break; 1776 } 1777 } 1778 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1779 /* 1780 * There are BlueLightning CPUs that do not change 1781 * undefined flags by dividing 5 by 2. In this case, 1782 * the CPU identification routine in locore.s leaves 1783 * cpu_vendor null string and puts CPU_486 into the 1784 * cpu. 1785 */ 1786 if (identblue() == IDENTBLUE_IBMCPU) { 1787 strcpy(cpu_vendor, "IBM"); 1788 cpu_vendor_id = CPU_VENDOR_IBM; 1789 cpu = CPU_BLUE; 1790 return; 1791 } 1792 } 1793 #endif 1794 } 1795 1796 int 1797 pti_get_default(void) 1798 { 1799 1800 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || 1801 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) 1802 return (0); 1803 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1804 return (0); 1805 return (1); 1806 } 1807 1808 static u_int 1809 find_cpu_vendor_id(void) 1810 { 1811 int i; 1812 1813 for (i = 0; i < nitems(cpu_vendors); i++) 1814 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1815 return (cpu_vendors[i].vendor_id); 1816 return (0); 1817 } 1818 1819 static void 1820 print_AMD_assoc(int i) 1821 { 1822 if (i == 255) 1823 printf(", fully associative\n"); 1824 else 1825 printf(", %d-way associative\n", i); 1826 } 1827 1828 static void 1829 print_AMD_l2_assoc(int i) 1830 { 1831 switch (i & 0x0f) { 1832 case 0: printf(", disabled/not present\n"); break; 1833 case 1: printf(", direct mapped\n"); break; 1834 case 2: printf(", 2-way associative\n"); break; 1835 case 4: printf(", 4-way associative\n"); break; 1836 case 6: printf(", 8-way associative\n"); break; 1837 case 8: printf(", 16-way associative\n"); break; 1838 case 15: printf(", fully associative\n"); break; 1839 default: printf(", reserved configuration\n"); break; 1840 } 1841 } 1842 1843 static void 1844 print_AMD_info(void) 1845 { 1846 #ifdef __i386__ 1847 uint64_t amd_whcr; 1848 #endif 1849 u_int regs[4]; 1850 1851 if (cpu_exthigh >= 0x80000005) { 1852 do_cpuid(0x80000005, regs); 1853 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1854 print_AMD_assoc(regs[0] >> 24); 1855 1856 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1857 print_AMD_assoc((regs[0] >> 8) & 0xff); 1858 1859 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1860 print_AMD_assoc(regs[1] >> 24); 1861 1862 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1863 print_AMD_assoc((regs[1] >> 8) & 0xff); 1864 1865 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1866 printf(", %d bytes/line", regs[2] & 0xff); 1867 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1868 print_AMD_assoc((regs[2] >> 16) & 0xff); 1869 1870 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1871 printf(", %d bytes/line", regs[3] & 0xff); 1872 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1873 print_AMD_assoc((regs[3] >> 16) & 0xff); 1874 } 1875 1876 if (cpu_exthigh >= 0x80000006) { 1877 do_cpuid(0x80000006, regs); 1878 if ((regs[0] >> 16) != 0) { 1879 printf("L2 2MB data TLB: %d entries", 1880 (regs[0] >> 16) & 0xfff); 1881 print_AMD_l2_assoc(regs[0] >> 28); 1882 printf("L2 2MB instruction TLB: %d entries", 1883 regs[0] & 0xfff); 1884 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1885 } else { 1886 printf("L2 2MB unified TLB: %d entries", 1887 regs[0] & 0xfff); 1888 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1889 } 1890 if ((regs[1] >> 16) != 0) { 1891 printf("L2 4KB data TLB: %d entries", 1892 (regs[1] >> 16) & 0xfff); 1893 print_AMD_l2_assoc(regs[1] >> 28); 1894 1895 printf("L2 4KB instruction TLB: %d entries", 1896 (regs[1] >> 16) & 0xfff); 1897 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1898 } else { 1899 printf("L2 4KB unified TLB: %d entries", 1900 (regs[1] >> 16) & 0xfff); 1901 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1902 } 1903 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1904 printf(", %d bytes/line", regs[2] & 0xff); 1905 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1906 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1907 } 1908 1909 #ifdef __i386__ 1910 if (((cpu_id & 0xf00) == 0x500) 1911 && (((cpu_id & 0x0f0) > 0x80) 1912 || (((cpu_id & 0x0f0) == 0x80) 1913 && (cpu_id & 0x00f) > 0x07))) { 1914 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1915 amd_whcr = rdmsr(0xc0000082); 1916 if (!(amd_whcr & (0x3ff << 22))) { 1917 printf("Write Allocate Disable\n"); 1918 } else { 1919 printf("Write Allocate Enable Limit: %dM bytes\n", 1920 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1921 printf("Write Allocate 15-16M bytes: %s\n", 1922 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1923 } 1924 } else if (((cpu_id & 0xf00) == 0x500) 1925 && ((cpu_id & 0x0f0) > 0x50)) { 1926 /* K6, K6-2(old core) */ 1927 amd_whcr = rdmsr(0xc0000082); 1928 if (!(amd_whcr & (0x7f << 1))) { 1929 printf("Write Allocate Disable\n"); 1930 } else { 1931 printf("Write Allocate Enable Limit: %dM bytes\n", 1932 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1933 printf("Write Allocate 15-16M bytes: %s\n", 1934 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1935 printf("Hardware Write Allocate Control: %s\n", 1936 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1937 } 1938 } 1939 #endif 1940 /* 1941 * Opteron Rev E shows a bug as in very rare occasions a read memory 1942 * barrier is not performed as expected if it is followed by a 1943 * non-atomic read-modify-write instruction. 1944 * As long as that bug pops up very rarely (intensive machine usage 1945 * on other operating systems generally generates one unexplainable 1946 * crash any 2 months) and as long as a model specific fix would be 1947 * impractical at this stage, print out a warning string if the broken 1948 * model and family are identified. 1949 */ 1950 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1951 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1952 printf("WARNING: This architecture revision has known SMP " 1953 "hardware bugs which may cause random instability\n"); 1954 } 1955 1956 static void 1957 print_INTEL_info(void) 1958 { 1959 u_int regs[4]; 1960 u_int rounds, regnum; 1961 u_int nwaycode, nway; 1962 1963 if (cpu_high >= 2) { 1964 rounds = 0; 1965 do { 1966 do_cpuid(0x2, regs); 1967 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1968 break; /* we have a buggy CPU */ 1969 1970 for (regnum = 0; regnum <= 3; ++regnum) { 1971 if (regs[regnum] & (1<<31)) 1972 continue; 1973 if (regnum != 0) 1974 print_INTEL_TLB(regs[regnum] & 0xff); 1975 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1976 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1977 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1978 } 1979 } while (--rounds > 0); 1980 } 1981 1982 if (cpu_exthigh >= 0x80000006) { 1983 do_cpuid(0x80000006, regs); 1984 nwaycode = (regs[2] >> 12) & 0x0f; 1985 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1986 nway = 1 << (nwaycode / 2); 1987 else 1988 nway = 0; 1989 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1990 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1991 } 1992 } 1993 1994 static void 1995 print_INTEL_TLB(u_int data) 1996 { 1997 switch (data) { 1998 case 0x0: 1999 case 0x40: 2000 default: 2001 break; 2002 case 0x1: 2003 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 2004 break; 2005 case 0x2: 2006 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 2007 break; 2008 case 0x3: 2009 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 2010 break; 2011 case 0x4: 2012 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 2013 break; 2014 case 0x6: 2015 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 2016 break; 2017 case 0x8: 2018 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2019 break; 2020 case 0x9: 2021 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 2022 break; 2023 case 0xa: 2024 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 2025 break; 2026 case 0xb: 2027 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 2028 break; 2029 case 0xc: 2030 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2031 break; 2032 case 0xd: 2033 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 2034 break; 2035 case 0xe: 2036 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 2037 break; 2038 case 0x1d: 2039 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 2040 break; 2041 case 0x21: 2042 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 2043 break; 2044 case 0x22: 2045 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2046 break; 2047 case 0x23: 2048 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2049 break; 2050 case 0x24: 2051 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 2052 break; 2053 case 0x25: 2054 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2055 break; 2056 case 0x29: 2057 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2058 break; 2059 case 0x2c: 2060 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2061 break; 2062 case 0x30: 2063 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2064 break; 2065 case 0x39: /* De-listed in SDM rev. 54 */ 2066 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2067 break; 2068 case 0x3b: /* De-listed in SDM rev. 54 */ 2069 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 2070 break; 2071 case 0x3c: /* De-listed in SDM rev. 54 */ 2072 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2073 break; 2074 case 0x41: 2075 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 2076 break; 2077 case 0x42: 2078 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 2079 break; 2080 case 0x43: 2081 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 2082 break; 2083 case 0x44: 2084 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 2085 break; 2086 case 0x45: 2087 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 2088 break; 2089 case 0x46: 2090 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 2091 break; 2092 case 0x47: 2093 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 2094 break; 2095 case 0x48: 2096 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 2097 break; 2098 case 0x49: 2099 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 2100 CPUID_TO_MODEL(cpu_id) == 0x6) 2101 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 2102 else 2103 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 2104 break; 2105 case 0x4a: 2106 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 2107 break; 2108 case 0x4b: 2109 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 2110 break; 2111 case 0x4c: 2112 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 2113 break; 2114 case 0x4d: 2115 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 2116 break; 2117 case 0x4e: 2118 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 2119 break; 2120 case 0x4f: 2121 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 2122 break; 2123 case 0x50: 2124 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 2125 break; 2126 case 0x51: 2127 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 2128 break; 2129 case 0x52: 2130 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2131 break; 2132 case 0x55: 2133 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2134 break; 2135 case 0x56: 2136 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2137 break; 2138 case 0x57: 2139 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2140 break; 2141 case 0x59: 2142 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2143 break; 2144 case 0x5a: 2145 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2146 break; 2147 case 0x5b: 2148 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2149 break; 2150 case 0x5c: 2151 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2152 break; 2153 case 0x5d: 2154 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2155 break; 2156 case 0x60: 2157 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2158 break; 2159 case 0x61: 2160 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2161 break; 2162 case 0x63: 2163 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2164 break; 2165 case 0x64: 2166 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2167 break; 2168 case 0x66: 2169 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2170 break; 2171 case 0x67: 2172 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2173 break; 2174 case 0x68: 2175 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2176 break; 2177 case 0x6a: 2178 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2179 break; 2180 case 0x6b: 2181 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2182 break; 2183 case 0x6c: 2184 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2185 break; 2186 case 0x6d: 2187 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2188 break; 2189 case 0x70: 2190 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2191 break; 2192 case 0x71: 2193 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2194 break; 2195 case 0x72: 2196 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2197 break; 2198 case 0x76: 2199 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2200 break; 2201 case 0x78: 2202 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2203 break; 2204 case 0x79: 2205 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2206 break; 2207 case 0x7a: 2208 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2209 break; 2210 case 0x7b: 2211 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2212 break; 2213 case 0x7c: 2214 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2215 break; 2216 case 0x7d: 2217 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2218 break; 2219 case 0x7f: 2220 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2221 break; 2222 case 0x80: 2223 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2224 break; 2225 case 0x82: 2226 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2227 break; 2228 case 0x83: 2229 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2230 break; 2231 case 0x84: 2232 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2233 break; 2234 case 0x85: 2235 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2236 break; 2237 case 0x86: 2238 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2239 break; 2240 case 0x87: 2241 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2242 break; 2243 case 0xa0: 2244 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2245 break; 2246 case 0xb0: 2247 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2248 break; 2249 case 0xb1: 2250 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2251 break; 2252 case 0xb2: 2253 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2254 break; 2255 case 0xb3: 2256 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2257 break; 2258 case 0xb4: 2259 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2260 break; 2261 case 0xb5: 2262 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2263 break; 2264 case 0xb6: 2265 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2266 break; 2267 case 0xba: 2268 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2269 break; 2270 case 0xc0: 2271 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2272 break; 2273 case 0xc1: 2274 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2275 break; 2276 case 0xc2: 2277 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2278 break; 2279 case 0xc3: 2280 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2281 break; 2282 case 0xc4: 2283 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2284 break; 2285 case 0xca: 2286 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2287 break; 2288 case 0xd0: 2289 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2290 break; 2291 case 0xd1: 2292 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2293 break; 2294 case 0xd2: 2295 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2296 break; 2297 case 0xd6: 2298 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2299 break; 2300 case 0xd7: 2301 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2302 break; 2303 case 0xd8: 2304 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2305 break; 2306 case 0xdc: 2307 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2308 break; 2309 case 0xdd: 2310 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2311 break; 2312 case 0xde: 2313 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2314 break; 2315 case 0xe2: 2316 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2317 break; 2318 case 0xe3: 2319 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2320 break; 2321 case 0xe4: 2322 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2323 break; 2324 case 0xea: 2325 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2326 break; 2327 case 0xeb: 2328 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2329 break; 2330 case 0xec: 2331 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2332 break; 2333 case 0xf0: 2334 printf("64-Byte prefetching\n"); 2335 break; 2336 case 0xf1: 2337 printf("128-Byte prefetching\n"); 2338 break; 2339 } 2340 } 2341 2342 static void 2343 print_svm_info(void) 2344 { 2345 u_int features, regs[4]; 2346 uint64_t msr; 2347 int comma; 2348 2349 printf("\n SVM: "); 2350 do_cpuid(0x8000000A, regs); 2351 features = regs[3]; 2352 2353 msr = rdmsr(MSR_VM_CR); 2354 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2355 printf("(disabled in BIOS) "); 2356 2357 if (!bootverbose) { 2358 comma = 0; 2359 if (features & (1 << 0)) { 2360 printf("%sNP", comma ? "," : ""); 2361 comma = 1; 2362 } 2363 if (features & (1 << 3)) { 2364 printf("%sNRIP", comma ? "," : ""); 2365 comma = 1; 2366 } 2367 if (features & (1 << 5)) { 2368 printf("%sVClean", comma ? "," : ""); 2369 comma = 1; 2370 } 2371 if (features & (1 << 6)) { 2372 printf("%sAFlush", comma ? "," : ""); 2373 comma = 1; 2374 } 2375 if (features & (1 << 7)) { 2376 printf("%sDAssist", comma ? "," : ""); 2377 comma = 1; 2378 } 2379 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2380 return; 2381 } 2382 2383 printf("Features=0x%b", features, 2384 "\020" 2385 "\001NP" /* Nested paging */ 2386 "\002LbrVirt" /* LBR virtualization */ 2387 "\003SVML" /* SVM lock */ 2388 "\004NRIPS" /* NRIP save */ 2389 "\005TscRateMsr" /* MSR based TSC rate control */ 2390 "\006VmcbClean" /* VMCB clean bits */ 2391 "\007FlushByAsid" /* Flush by ASID */ 2392 "\010DecodeAssist" /* Decode assist */ 2393 "\011<b8>" 2394 "\012<b9>" 2395 "\013PauseFilter" /* PAUSE intercept filter */ 2396 "\014EncryptedMcodePatch" 2397 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2398 "\016AVIC" /* virtual interrupt controller */ 2399 "\017<b14>" 2400 "\020V_VMSAVE_VMLOAD" 2401 "\021vGIF" 2402 "\022GMET" /* Guest Mode Execute Trap */ 2403 "\023<b18>" 2404 "\024<b19>" 2405 "\025GuesSpecCtl" /* Guest Spec_ctl */ 2406 "\026<b21>" 2407 "\027<b22>" 2408 "\030<b23>" 2409 "\031<b24>" 2410 "\032<b25>" 2411 "\033<b26>" 2412 "\034<b27>" 2413 "\035<b28>" 2414 "\036<b29>" 2415 "\037<b30>" 2416 "\040<b31>" 2417 ); 2418 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2419 } 2420 2421 #ifdef __i386__ 2422 static void 2423 print_transmeta_info(void) 2424 { 2425 u_int regs[4], nreg = 0; 2426 2427 do_cpuid(0x80860000, regs); 2428 nreg = regs[0]; 2429 if (nreg >= 0x80860001) { 2430 do_cpuid(0x80860001, regs); 2431 printf(" Processor revision %u.%u.%u.%u\n", 2432 (regs[1] >> 24) & 0xff, 2433 (regs[1] >> 16) & 0xff, 2434 (regs[1] >> 8) & 0xff, 2435 regs[1] & 0xff); 2436 } 2437 if (nreg >= 0x80860002) { 2438 do_cpuid(0x80860002, regs); 2439 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2440 (regs[1] >> 24) & 0xff, 2441 (regs[1] >> 16) & 0xff, 2442 (regs[1] >> 8) & 0xff, 2443 regs[1] & 0xff, 2444 regs[2]); 2445 } 2446 if (nreg >= 0x80860006) { 2447 char info[65]; 2448 do_cpuid(0x80860003, (u_int*) &info[0]); 2449 do_cpuid(0x80860004, (u_int*) &info[16]); 2450 do_cpuid(0x80860005, (u_int*) &info[32]); 2451 do_cpuid(0x80860006, (u_int*) &info[48]); 2452 info[64] = 0; 2453 printf(" %s\n", info); 2454 } 2455 } 2456 #endif 2457 2458 static void 2459 print_via_padlock_info(void) 2460 { 2461 u_int regs[4]; 2462 2463 do_cpuid(0xc0000001, regs); 2464 printf("\n VIA Padlock Features=0x%b", regs[3], 2465 "\020" 2466 "\003RNG" /* RNG */ 2467 "\007AES" /* ACE */ 2468 "\011AES-CTR" /* ACE2 */ 2469 "\013SHA1,SHA256" /* PHE */ 2470 "\015RSA" /* PMM */ 2471 ); 2472 } 2473 2474 static uint32_t 2475 vmx_settable(uint64_t basic, int msr, int true_msr) 2476 { 2477 uint64_t val; 2478 2479 if (basic & (1ULL << 55)) 2480 val = rdmsr(true_msr); 2481 else 2482 val = rdmsr(msr); 2483 2484 /* Just report the controls that can be set to 1. */ 2485 return (val >> 32); 2486 } 2487 2488 static void 2489 print_vmx_info(void) 2490 { 2491 uint64_t basic, msr; 2492 uint32_t entry, exit, mask, pin, proc, proc2; 2493 int comma; 2494 2495 printf("\n VT-x: "); 2496 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2497 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2498 printf("(disabled in BIOS) "); 2499 basic = rdmsr(MSR_VMX_BASIC); 2500 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2501 MSR_VMX_TRUE_PINBASED_CTLS); 2502 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2503 MSR_VMX_TRUE_PROCBASED_CTLS); 2504 if (proc & PROCBASED_SECONDARY_CONTROLS) 2505 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2506 MSR_VMX_PROCBASED_CTLS2); 2507 else 2508 proc2 = 0; 2509 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2510 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2511 2512 if (!bootverbose) { 2513 comma = 0; 2514 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2515 entry & VM_ENTRY_LOAD_PAT) { 2516 printf("%sPAT", comma ? "," : ""); 2517 comma = 1; 2518 } 2519 if (proc & PROCBASED_HLT_EXITING) { 2520 printf("%sHLT", comma ? "," : ""); 2521 comma = 1; 2522 } 2523 if (proc & PROCBASED_MTF) { 2524 printf("%sMTF", comma ? "," : ""); 2525 comma = 1; 2526 } 2527 if (proc & PROCBASED_PAUSE_EXITING) { 2528 printf("%sPAUSE", comma ? "," : ""); 2529 comma = 1; 2530 } 2531 if (proc2 & PROCBASED2_ENABLE_EPT) { 2532 printf("%sEPT", comma ? "," : ""); 2533 comma = 1; 2534 } 2535 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2536 printf("%sUG", comma ? "," : ""); 2537 comma = 1; 2538 } 2539 if (proc2 & PROCBASED2_ENABLE_VPID) { 2540 printf("%sVPID", comma ? "," : ""); 2541 comma = 1; 2542 } 2543 if (proc & PROCBASED_USE_TPR_SHADOW && 2544 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2545 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2546 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2547 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2548 printf("%sVID", comma ? "," : ""); 2549 comma = 1; 2550 if (pin & PINBASED_POSTED_INTERRUPT) 2551 printf(",PostIntr"); 2552 } 2553 return; 2554 } 2555 2556 mask = basic >> 32; 2557 printf("Basic Features=0x%b", mask, 2558 "\020" 2559 "\02132PA" /* 32-bit physical addresses */ 2560 "\022SMM" /* SMM dual-monitor */ 2561 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2562 "\030TRUE" /* TRUE_CTLS MSRs */ 2563 ); 2564 printf("\n Pin-Based Controls=0x%b", pin, 2565 "\020" 2566 "\001ExtINT" /* External-interrupt exiting */ 2567 "\004NMI" /* NMI exiting */ 2568 "\006VNMI" /* Virtual NMIs */ 2569 "\007PreTmr" /* Activate VMX-preemption timer */ 2570 "\010PostIntr" /* Process posted interrupts */ 2571 ); 2572 printf("\n Primary Processor Controls=0x%b", proc, 2573 "\020" 2574 "\003INTWIN" /* Interrupt-window exiting */ 2575 "\004TSCOff" /* Use TSC offsetting */ 2576 "\010HLT" /* HLT exiting */ 2577 "\012INVLPG" /* INVLPG exiting */ 2578 "\013MWAIT" /* MWAIT exiting */ 2579 "\014RDPMC" /* RDPMC exiting */ 2580 "\015RDTSC" /* RDTSC exiting */ 2581 "\020CR3-LD" /* CR3-load exiting */ 2582 "\021CR3-ST" /* CR3-store exiting */ 2583 "\024CR8-LD" /* CR8-load exiting */ 2584 "\025CR8-ST" /* CR8-store exiting */ 2585 "\026TPR" /* Use TPR shadow */ 2586 "\027NMIWIN" /* NMI-window exiting */ 2587 "\030MOV-DR" /* MOV-DR exiting */ 2588 "\031IO" /* Unconditional I/O exiting */ 2589 "\032IOmap" /* Use I/O bitmaps */ 2590 "\034MTF" /* Monitor trap flag */ 2591 "\035MSRmap" /* Use MSR bitmaps */ 2592 "\036MONITOR" /* MONITOR exiting */ 2593 "\037PAUSE" /* PAUSE exiting */ 2594 ); 2595 if (proc & PROCBASED_SECONDARY_CONTROLS) 2596 printf("\n Secondary Processor Controls=0x%b", proc2, 2597 "\020" 2598 "\001APIC" /* Virtualize APIC accesses */ 2599 "\002EPT" /* Enable EPT */ 2600 "\003DT" /* Descriptor-table exiting */ 2601 "\004RDTSCP" /* Enable RDTSCP */ 2602 "\005x2APIC" /* Virtualize x2APIC mode */ 2603 "\006VPID" /* Enable VPID */ 2604 "\007WBINVD" /* WBINVD exiting */ 2605 "\010UG" /* Unrestricted guest */ 2606 "\011APIC-reg" /* APIC-register virtualization */ 2607 "\012VID" /* Virtual-interrupt delivery */ 2608 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2609 "\014RDRAND" /* RDRAND exiting */ 2610 "\015INVPCID" /* Enable INVPCID */ 2611 "\016VMFUNC" /* Enable VM functions */ 2612 "\017VMCS" /* VMCS shadowing */ 2613 "\020EPT#VE" /* EPT-violation #VE */ 2614 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2615 ); 2616 printf("\n Exit Controls=0x%b", mask, 2617 "\020" 2618 "\003DR" /* Save debug controls */ 2619 /* Ignore Host address-space size */ 2620 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2621 "\020AckInt" /* Acknowledge interrupt on exit */ 2622 "\023PAT-SV" /* Save MSR_PAT */ 2623 "\024PAT-LD" /* Load MSR_PAT */ 2624 "\025EFER-SV" /* Save MSR_EFER */ 2625 "\026EFER-LD" /* Load MSR_EFER */ 2626 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2627 ); 2628 printf("\n Entry Controls=0x%b", mask, 2629 "\020" 2630 "\003DR" /* Save debug controls */ 2631 /* Ignore IA-32e mode guest */ 2632 /* Ignore Entry to SMM */ 2633 /* Ignore Deactivate dual-monitor treatment */ 2634 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2635 "\017PAT" /* Load MSR_PAT */ 2636 "\020EFER" /* Load MSR_EFER */ 2637 ); 2638 if (proc & PROCBASED_SECONDARY_CONTROLS && 2639 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2640 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2641 mask = msr; 2642 printf("\n EPT Features=0x%b", mask, 2643 "\020" 2644 "\001XO" /* Execute-only translations */ 2645 "\007PW4" /* Page-walk length of 4 */ 2646 "\011UC" /* EPT paging-structure mem can be UC */ 2647 "\017WB" /* EPT paging-structure mem can be WB */ 2648 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2649 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2650 "\025INVEPT" /* INVEPT is supported */ 2651 "\026AD" /* Accessed and dirty flags for EPT */ 2652 "\032single" /* INVEPT single-context type */ 2653 "\033all" /* INVEPT all-context type */ 2654 ); 2655 mask = msr >> 32; 2656 printf("\n VPID Features=0x%b", mask, 2657 "\020" 2658 "\001INVVPID" /* INVVPID is supported */ 2659 "\011individual" /* INVVPID individual-address type */ 2660 "\012single" /* INVVPID single-context type */ 2661 "\013all" /* INVVPID all-context type */ 2662 /* INVVPID single-context-retaining-globals type */ 2663 "\014single-globals" 2664 ); 2665 } 2666 } 2667 2668 static void 2669 print_hypervisor_info(void) 2670 { 2671 2672 if (*hv_vendor != '\0') 2673 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2674 } 2675 2676 /* 2677 * Returns the maximum physical address that can be used with the 2678 * current system. 2679 */ 2680 vm_paddr_t 2681 cpu_getmaxphyaddr(void) 2682 { 2683 2684 #if defined(__i386__) 2685 if (!pae_mode) 2686 return (0xffffffff); 2687 #endif 2688 return ((1ULL << cpu_maxphyaddr) - 1); 2689 } 2690