1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 #include "opt_cpu.h" 43 44 #include <sys/param.h> 45 #include <sys/bus.h> 46 #include <sys/cpu.h> 47 #include <sys/eventhandler.h> 48 #include <sys/limits.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/sysctl.h> 52 #include <sys/power.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include <machine/asmacros.h> 58 #include <machine/clock.h> 59 #include <machine/cputypes.h> 60 #include <machine/frame.h> 61 #include <machine/intr_machdep.h> 62 #include <machine/md_var.h> 63 #include <machine/segments.h> 64 #include <machine/specialreg.h> 65 66 #include <amd64/vmm/intel/vmx_controls.h> 67 #include <x86/cputypes.h> 68 #include <x86/isa/icu.h> 69 #include <x86/vmware.h> 70 71 #ifdef XENHVM 72 #include <xen/xen-os.h> 73 #endif 74 75 #ifdef __i386__ 76 #define IDENTBLUE_CYRIX486 0 77 #define IDENTBLUE_IBMCPU 1 78 #define IDENTBLUE_CYRIXM2 2 79 80 static void identifycyrix(void); 81 static void print_transmeta_info(void); 82 #endif 83 static u_int find_cpu_vendor_id(void); 84 static void print_AMD_info(void); 85 static void print_INTEL_info(void); 86 static void print_INTEL_TLB(u_int data); 87 static void print_hypervisor_info(void); 88 static void print_svm_info(void); 89 static void print_via_padlock_info(void); 90 static void print_vmx_info(void); 91 92 #ifdef __i386__ 93 int cpu; /* Are we 386, 386sx, 486, etc? */ 94 int cpu_class; 95 #endif 96 u_int cpu_feature; /* Feature flags */ 97 u_int cpu_feature2; /* Feature flags */ 98 u_int amd_feature; /* AMD feature flags */ 99 u_int amd_feature2; /* AMD feature flags */ 100 u_int amd_rascap; /* AMD RAS capabilities */ 101 u_int amd_pminfo; /* AMD advanced power management info */ 102 u_int amd_extended_feature_extensions; 103 u_int via_feature_rng; /* VIA RNG features */ 104 u_int via_feature_xcrypt; /* VIA ACE features */ 105 u_int cpu_high; /* Highest arg to CPUID */ 106 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 107 u_int cpu_id; /* Stepping ID */ 108 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 109 u_int cpu_procinfo2; /* Multicore info */ 110 u_int cpu_procinfo3; 111 char cpu_vendor[20]; /* CPU Origin code */ 112 u_int cpu_vendor_id; /* CPU vendor ID */ 113 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 114 u_int cpu_clflush_line_size = 32; 115 /* leaf 7 %ecx = 0 */ 116 u_int cpu_stdext_feature; /* %ebx */ 117 u_int cpu_stdext_feature2; /* %ecx */ 118 u_int cpu_stdext_feature3; /* %edx */ 119 /* leaf 7 %ecx = 1 */ 120 u_int cpu_stdext_feature4; /* %eax */ 121 u_int cpu_stdext_feature5; /* %ecx */ 122 uint64_t cpu_ia32_arch_caps; 123 u_int cpu_max_ext_state_size; 124 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 125 u_int cpu_mon_mwait_edx; /* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */ 126 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 127 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 128 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 129 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */ 130 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */ 131 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */ 132 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */ 133 const char machine[] = MACHINE; 134 135 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 136 &via_feature_rng, 0, 137 "VIA RNG feature available in CPU"); 138 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 139 &via_feature_xcrypt, 0, 140 "VIA xcrypt feature available in CPU"); 141 142 #ifdef __amd64__ 143 #ifdef SCTL_MASK32 144 extern int adaptive_machine_arch; 145 #endif 146 147 static int 148 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 149 { 150 #ifdef SCTL_MASK32 151 static const char machine32[] = "i386"; 152 #endif 153 int error; 154 155 #ifdef SCTL_MASK32 156 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 157 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 158 else 159 #endif 160 error = SYSCTL_OUT(req, machine, sizeof(machine)); 161 return (error); 162 163 } 164 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 165 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 166 #else 167 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD, 168 machine, "Machine class"); 169 #endif 170 171 char cpu_model[128]; 172 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD, 173 cpu_model, 0, "Machine model"); 174 175 static int hw_clockrate; 176 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 177 &hw_clockrate, 0, "CPU instruction clock rate"); 178 179 u_int hv_base; 180 u_int hv_high; 181 char hv_vendor[16]; 182 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 183 0, "Hypervisor vendor"); 184 185 static eventhandler_tag tsc_post_tag; 186 187 static char cpu_brand[48]; 188 189 #ifdef __i386__ 190 #define MAX_BRAND_INDEX 8 191 192 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 193 NULL, /* No brand */ 194 "Intel Celeron", 195 "Intel Pentium III", 196 "Intel Pentium III Xeon", 197 NULL, 198 NULL, 199 NULL, 200 NULL, 201 "Intel Pentium 4" 202 }; 203 204 static struct { 205 char *cpu_name; 206 int cpu_class; 207 } cpus[] = { 208 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 209 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 210 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 211 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 212 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 213 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 214 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 215 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 216 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 217 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 218 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 219 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 220 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 221 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 222 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 223 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 224 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 225 }; 226 #endif 227 228 static struct { 229 char *vendor; 230 u_int vendor_id; 231 } cpu_vendors[] = { 232 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 233 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 234 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */ 235 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 236 #ifdef __i386__ 237 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 238 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 239 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 240 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 241 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 242 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 243 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 244 #if 0 245 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 246 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 247 #endif 248 #endif 249 }; 250 251 void 252 printcpuinfo(void) 253 { 254 u_int regs[4], i; 255 char *brand; 256 257 printf("CPU: "); 258 #ifdef __i386__ 259 cpu_class = cpus[cpu].cpu_class; 260 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 261 #else 262 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 263 #endif 264 265 /* Check for extended CPUID information and a processor name. */ 266 if (cpu_exthigh >= 0x80000004) { 267 brand = cpu_brand; 268 for (i = 0x80000002; i < 0x80000005; i++) { 269 do_cpuid(i, regs); 270 memcpy(brand, regs, sizeof(regs)); 271 brand += sizeof(regs); 272 } 273 } 274 275 switch (cpu_vendor_id) { 276 case CPU_VENDOR_INTEL: 277 #ifdef __i386__ 278 if ((cpu_id & 0xf00) > 0x300) { 279 u_int brand_index; 280 281 cpu_model[0] = '\0'; 282 283 switch (cpu_id & 0x3000) { 284 case 0x1000: 285 strcpy(cpu_model, "Overdrive "); 286 break; 287 case 0x2000: 288 strcpy(cpu_model, "Dual "); 289 break; 290 } 291 292 switch (cpu_id & 0xf00) { 293 case 0x400: 294 strcat(cpu_model, "i486 "); 295 /* Check the particular flavor of 486 */ 296 switch (cpu_id & 0xf0) { 297 case 0x00: 298 case 0x10: 299 strcat(cpu_model, "DX"); 300 break; 301 case 0x20: 302 strcat(cpu_model, "SX"); 303 break; 304 case 0x30: 305 strcat(cpu_model, "DX2"); 306 break; 307 case 0x40: 308 strcat(cpu_model, "SL"); 309 break; 310 case 0x50: 311 strcat(cpu_model, "SX2"); 312 break; 313 case 0x70: 314 strcat(cpu_model, 315 "DX2 Write-Back Enhanced"); 316 break; 317 case 0x80: 318 strcat(cpu_model, "DX4"); 319 break; 320 } 321 break; 322 case 0x500: 323 /* Check the particular flavor of 586 */ 324 strcat(cpu_model, "Pentium"); 325 switch (cpu_id & 0xf0) { 326 case 0x00: 327 strcat(cpu_model, " A-step"); 328 break; 329 case 0x10: 330 strcat(cpu_model, "/P5"); 331 break; 332 case 0x20: 333 strcat(cpu_model, "/P54C"); 334 break; 335 case 0x30: 336 strcat(cpu_model, "/P24T"); 337 break; 338 case 0x40: 339 strcat(cpu_model, "/P55C"); 340 break; 341 case 0x70: 342 strcat(cpu_model, "/P54C"); 343 break; 344 case 0x80: 345 strcat(cpu_model, "/P55C (quarter-micron)"); 346 break; 347 default: 348 /* nothing */ 349 break; 350 } 351 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 352 /* 353 * XXX - If/when Intel fixes the bug, this 354 * should also check the version of the 355 * CPU, not just that it's a Pentium. 356 */ 357 has_f00f_bug = 1; 358 #endif 359 break; 360 case 0x600: 361 /* Check the particular flavor of 686 */ 362 switch (cpu_id & 0xf0) { 363 case 0x00: 364 strcat(cpu_model, "Pentium Pro A-step"); 365 break; 366 case 0x10: 367 strcat(cpu_model, "Pentium Pro"); 368 break; 369 case 0x30: 370 case 0x50: 371 case 0x60: 372 strcat(cpu_model, 373 "Pentium II/Pentium II Xeon/Celeron"); 374 cpu = CPU_PII; 375 break; 376 case 0x70: 377 case 0x80: 378 case 0xa0: 379 case 0xb0: 380 strcat(cpu_model, 381 "Pentium III/Pentium III Xeon/Celeron"); 382 cpu = CPU_PIII; 383 break; 384 default: 385 strcat(cpu_model, "Unknown 80686"); 386 break; 387 } 388 break; 389 case 0xf00: 390 strcat(cpu_model, "Pentium 4"); 391 cpu = CPU_P4; 392 break; 393 default: 394 strcat(cpu_model, "unknown"); 395 break; 396 } 397 398 /* 399 * If we didn't get a brand name from the extended 400 * CPUID, try to look it up in the brand table. 401 */ 402 if (cpu_high > 0 && *cpu_brand == '\0') { 403 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 404 if (brand_index <= MAX_BRAND_INDEX && 405 cpu_brandtable[brand_index] != NULL) 406 strcpy(cpu_brand, 407 cpu_brandtable[brand_index]); 408 } 409 } 410 #else 411 /* Please make up your mind folks! */ 412 strcat(cpu_model, "EM64T"); 413 #endif 414 break; 415 case CPU_VENDOR_AMD: 416 /* 417 * Values taken from AMD Processor Recognition 418 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 419 * (also describes ``Features'' encodings. 420 */ 421 strcpy(cpu_model, "AMD "); 422 #ifdef __i386__ 423 switch (cpu_id & 0xFF0) { 424 case 0x410: 425 strcat(cpu_model, "Standard Am486DX"); 426 break; 427 case 0x430: 428 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 429 break; 430 case 0x470: 431 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 432 break; 433 case 0x480: 434 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 435 break; 436 case 0x490: 437 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 438 break; 439 case 0x4E0: 440 strcat(cpu_model, "Am5x86 Write-Through"); 441 break; 442 case 0x4F0: 443 strcat(cpu_model, "Am5x86 Write-Back"); 444 break; 445 case 0x500: 446 strcat(cpu_model, "K5 model 0"); 447 break; 448 case 0x510: 449 strcat(cpu_model, "K5 model 1"); 450 break; 451 case 0x520: 452 strcat(cpu_model, "K5 PR166 (model 2)"); 453 break; 454 case 0x530: 455 strcat(cpu_model, "K5 PR200 (model 3)"); 456 break; 457 case 0x560: 458 strcat(cpu_model, "K6"); 459 break; 460 case 0x570: 461 strcat(cpu_model, "K6 266 (model 1)"); 462 break; 463 case 0x580: 464 strcat(cpu_model, "K6-2"); 465 break; 466 case 0x590: 467 strcat(cpu_model, "K6-III"); 468 break; 469 case 0x5a0: 470 strcat(cpu_model, "Geode LX"); 471 break; 472 default: 473 strcat(cpu_model, "Unknown"); 474 break; 475 } 476 #else 477 if ((cpu_id & 0xf00) == 0xf00) 478 strcat(cpu_model, "AMD64 Processor"); 479 else 480 strcat(cpu_model, "Unknown"); 481 #endif 482 break; 483 #ifdef __i386__ 484 case CPU_VENDOR_CYRIX: 485 strcpy(cpu_model, "Cyrix "); 486 switch (cpu_id & 0xff0) { 487 case 0x440: 488 strcat(cpu_model, "MediaGX"); 489 break; 490 case 0x520: 491 strcat(cpu_model, "6x86"); 492 break; 493 case 0x540: 494 cpu_class = CPUCLASS_586; 495 strcat(cpu_model, "GXm"); 496 break; 497 case 0x600: 498 strcat(cpu_model, "6x86MX"); 499 break; 500 default: 501 /* 502 * Even though CPU supports the cpuid 503 * instruction, it can be disabled. 504 * Therefore, this routine supports all Cyrix 505 * CPUs. 506 */ 507 switch (cyrix_did & 0xf0) { 508 case 0x00: 509 switch (cyrix_did & 0x0f) { 510 case 0x00: 511 strcat(cpu_model, "486SLC"); 512 break; 513 case 0x01: 514 strcat(cpu_model, "486DLC"); 515 break; 516 case 0x02: 517 strcat(cpu_model, "486SLC2"); 518 break; 519 case 0x03: 520 strcat(cpu_model, "486DLC2"); 521 break; 522 case 0x04: 523 strcat(cpu_model, "486SRx"); 524 break; 525 case 0x05: 526 strcat(cpu_model, "486DRx"); 527 break; 528 case 0x06: 529 strcat(cpu_model, "486SRx2"); 530 break; 531 case 0x07: 532 strcat(cpu_model, "486DRx2"); 533 break; 534 case 0x08: 535 strcat(cpu_model, "486SRu"); 536 break; 537 case 0x09: 538 strcat(cpu_model, "486DRu"); 539 break; 540 case 0x0a: 541 strcat(cpu_model, "486SRu2"); 542 break; 543 case 0x0b: 544 strcat(cpu_model, "486DRu2"); 545 break; 546 default: 547 strcat(cpu_model, "Unknown"); 548 break; 549 } 550 break; 551 case 0x10: 552 switch (cyrix_did & 0x0f) { 553 case 0x00: 554 strcat(cpu_model, "486S"); 555 break; 556 case 0x01: 557 strcat(cpu_model, "486S2"); 558 break; 559 case 0x02: 560 strcat(cpu_model, "486Se"); 561 break; 562 case 0x03: 563 strcat(cpu_model, "486S2e"); 564 break; 565 case 0x0a: 566 strcat(cpu_model, "486DX"); 567 break; 568 case 0x0b: 569 strcat(cpu_model, "486DX2"); 570 break; 571 case 0x0f: 572 strcat(cpu_model, "486DX4"); 573 break; 574 default: 575 strcat(cpu_model, "Unknown"); 576 break; 577 } 578 break; 579 case 0x20: 580 if ((cyrix_did & 0x0f) < 8) 581 strcat(cpu_model, "6x86"); /* Where did you get it? */ 582 else 583 strcat(cpu_model, "5x86"); 584 break; 585 case 0x30: 586 strcat(cpu_model, "6x86"); 587 break; 588 case 0x40: 589 if ((cyrix_did & 0xf000) == 0x3000) { 590 cpu_class = CPUCLASS_586; 591 strcat(cpu_model, "GXm"); 592 } else 593 strcat(cpu_model, "MediaGX"); 594 break; 595 case 0x50: 596 strcat(cpu_model, "6x86MX"); 597 break; 598 case 0xf0: 599 switch (cyrix_did & 0x0f) { 600 case 0x0d: 601 strcat(cpu_model, "Overdrive CPU"); 602 break; 603 case 0x0e: 604 strcpy(cpu_model, "Texas Instruments 486SXL"); 605 break; 606 case 0x0f: 607 strcat(cpu_model, "486SLC/DLC"); 608 break; 609 default: 610 strcat(cpu_model, "Unknown"); 611 break; 612 } 613 break; 614 default: 615 strcat(cpu_model, "Unknown"); 616 break; 617 } 618 break; 619 } 620 break; 621 case CPU_VENDOR_RISE: 622 strcpy(cpu_model, "Rise "); 623 switch (cpu_id & 0xff0) { 624 case 0x500: /* 6401 and 6441 (Kirin) */ 625 case 0x520: /* 6510 (Lynx) */ 626 strcat(cpu_model, "mP6"); 627 break; 628 default: 629 strcat(cpu_model, "Unknown"); 630 } 631 break; 632 #endif 633 case CPU_VENDOR_CENTAUR: 634 #ifdef __i386__ 635 switch (cpu_id & 0xff0) { 636 case 0x540: 637 strcpy(cpu_model, "IDT WinChip C6"); 638 break; 639 case 0x580: 640 strcpy(cpu_model, "IDT WinChip 2"); 641 break; 642 case 0x590: 643 strcpy(cpu_model, "IDT WinChip 3"); 644 break; 645 case 0x660: 646 strcpy(cpu_model, "VIA C3 Samuel"); 647 break; 648 case 0x670: 649 if (cpu_id & 0x8) 650 strcpy(cpu_model, "VIA C3 Ezra"); 651 else 652 strcpy(cpu_model, "VIA C3 Samuel 2"); 653 break; 654 case 0x680: 655 strcpy(cpu_model, "VIA C3 Ezra-T"); 656 break; 657 case 0x690: 658 strcpy(cpu_model, "VIA C3 Nehemiah"); 659 break; 660 case 0x6a0: 661 case 0x6d0: 662 strcpy(cpu_model, "VIA C7 Esther"); 663 break; 664 case 0x6f0: 665 strcpy(cpu_model, "VIA Nano"); 666 break; 667 default: 668 strcpy(cpu_model, "VIA/IDT Unknown"); 669 } 670 #else 671 strcpy(cpu_model, "VIA "); 672 if ((cpu_id & 0xff0) == 0x6f0) 673 strcat(cpu_model, "Nano Processor"); 674 else 675 strcat(cpu_model, "Unknown"); 676 #endif 677 break; 678 #ifdef __i386__ 679 case CPU_VENDOR_IBM: 680 strcpy(cpu_model, "Blue Lightning CPU"); 681 break; 682 case CPU_VENDOR_NSC: 683 switch (cpu_id & 0xff0) { 684 case 0x540: 685 strcpy(cpu_model, "Geode SC1100"); 686 cpu = CPU_GEODE1100; 687 break; 688 default: 689 strcpy(cpu_model, "Geode/NSC unknown"); 690 break; 691 } 692 break; 693 #endif 694 case CPU_VENDOR_HYGON: 695 strcpy(cpu_model, "Hygon "); 696 #ifdef __i386__ 697 strcat(cpu_model, "Unknown"); 698 #else 699 if ((cpu_id & 0xf00) == 0xf00) 700 strcat(cpu_model, "AMD64 Processor"); 701 else 702 strcat(cpu_model, "Unknown"); 703 #endif 704 break; 705 706 default: 707 strcat(cpu_model, "Unknown"); 708 break; 709 } 710 711 /* 712 * Replace cpu_model with cpu_brand minus leading spaces if 713 * we have one. 714 */ 715 brand = cpu_brand; 716 while (*brand == ' ') 717 ++brand; 718 if (*brand != '\0') 719 strcpy(cpu_model, brand); 720 721 printf("%s (", cpu_model); 722 if (tsc_freq != 0) { 723 hw_clockrate = (tsc_freq + 5000) / 1000000; 724 printf("%jd.%02d-MHz ", 725 (intmax_t)(tsc_freq + 4999) / 1000000, 726 (u_int)((tsc_freq + 4999) / 10000) % 100); 727 } 728 #ifdef __i386__ 729 switch(cpu_class) { 730 case CPUCLASS_286: 731 printf("286"); 732 break; 733 case CPUCLASS_386: 734 printf("386"); 735 break; 736 #if defined(I486_CPU) 737 case CPUCLASS_486: 738 printf("486"); 739 break; 740 #endif 741 #if defined(I586_CPU) 742 case CPUCLASS_586: 743 printf("586"); 744 break; 745 #endif 746 #if defined(I686_CPU) 747 case CPUCLASS_686: 748 printf("686"); 749 break; 750 #endif 751 default: 752 printf("Unknown"); /* will panic below... */ 753 } 754 #else 755 printf("K8"); 756 #endif 757 printf("-class CPU)\n"); 758 if (*cpu_vendor) 759 printf(" Origin=\"%s\"", cpu_vendor); 760 if (cpu_id) 761 printf(" Id=0x%x", cpu_id); 762 763 if (cpu_vendor_id == CPU_VENDOR_INTEL || 764 cpu_vendor_id == CPU_VENDOR_AMD || 765 cpu_vendor_id == CPU_VENDOR_HYGON || 766 cpu_vendor_id == CPU_VENDOR_CENTAUR || 767 #ifdef __i386__ 768 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 769 cpu_vendor_id == CPU_VENDOR_RISE || 770 cpu_vendor_id == CPU_VENDOR_NSC || 771 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 772 #endif 773 0) { 774 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 775 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 776 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 777 #ifdef __i386__ 778 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 779 printf("\n DIR=0x%04x", cyrix_did); 780 #endif 781 782 /* 783 * AMD CPUID Specification 784 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 785 * 786 * Intel Processor Identification and CPUID Instruction 787 * http://www.intel.com/assets/pdf/appnote/241618.pdf 788 */ 789 if (cpu_high > 0) { 790 /* 791 * Here we should probably set up flags indicating 792 * whether or not various features are available. 793 * The interesting ones are probably VME, PSE, PAE, 794 * and PGE. The code already assumes without bothering 795 * to check that all CPUs >= Pentium have a TSC and 796 * MSRs. 797 */ 798 printf("\n Features=0x%b", cpu_feature, 799 "\020" 800 "\001FPU" /* Integral FPU */ 801 "\002VME" /* Extended VM86 mode support */ 802 "\003DE" /* Debugging Extensions (CR4.DE) */ 803 "\004PSE" /* 4MByte page tables */ 804 "\005TSC" /* Timestamp counter */ 805 "\006MSR" /* Machine specific registers */ 806 "\007PAE" /* Physical address extension */ 807 "\010MCE" /* Machine Check support */ 808 "\011CX8" /* CMPEXCH8 instruction */ 809 "\012APIC" /* SMP local APIC */ 810 "\013oldMTRR" /* Previous implementation of MTRR */ 811 "\014SEP" /* Fast System Call */ 812 "\015MTRR" /* Memory Type Range Registers */ 813 "\016PGE" /* PG_G (global bit) support */ 814 "\017MCA" /* Machine Check Architecture */ 815 "\020CMOV" /* CMOV instruction */ 816 "\021PAT" /* Page attributes table */ 817 "\022PSE36" /* 36 bit address space support */ 818 "\023PN" /* Processor Serial number */ 819 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 820 "\025<b20>" 821 "\026DTS" /* Debug Trace Store */ 822 "\027ACPI" /* ACPI support */ 823 "\030MMX" /* MMX instructions */ 824 "\031FXSR" /* FXSAVE/FXRSTOR */ 825 "\032SSE" /* Streaming SIMD Extensions */ 826 "\033SSE2" /* Streaming SIMD Extensions #2 */ 827 "\034SS" /* Self snoop */ 828 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 829 "\036TM" /* Thermal Monitor clock slowdown */ 830 "\037IA64" /* CPU can execute IA64 instructions */ 831 "\040PBE" /* Pending Break Enable */ 832 ); 833 834 if (cpu_feature2 != 0) { 835 printf("\n Features2=0x%b", cpu_feature2, 836 "\020" 837 "\001SSE3" /* SSE3 */ 838 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 839 "\003DTES64" /* 64-bit Debug Trace */ 840 "\004MON" /* MONITOR/MWAIT Instructions */ 841 "\005DS_CPL" /* CPL Qualified Debug Store */ 842 "\006VMX" /* Virtual Machine Extensions */ 843 "\007SMX" /* Safer Mode Extensions */ 844 "\010EST" /* Enhanced SpeedStep */ 845 "\011TM2" /* Thermal Monitor 2 */ 846 "\012SSSE3" /* SSSE3 */ 847 "\013CNXT-ID" /* L1 context ID available */ 848 "\014SDBG" /* IA32 silicon debug */ 849 "\015FMA" /* Fused Multiply Add */ 850 "\016CX16" /* CMPXCHG16B Instruction */ 851 "\017xTPR" /* Send Task Priority Messages*/ 852 "\020PDCM" /* Perf/Debug Capability MSR */ 853 "\021<b16>" 854 "\022PCID" /* Process-context Identifiers*/ 855 "\023DCA" /* Direct Cache Access */ 856 "\024SSE4.1" /* SSE 4.1 */ 857 "\025SSE4.2" /* SSE 4.2 */ 858 "\026x2APIC" /* xAPIC Extensions */ 859 "\027MOVBE" /* MOVBE Instruction */ 860 "\030POPCNT" /* POPCNT Instruction */ 861 "\031TSCDLT" /* TSC-Deadline Timer */ 862 "\032AESNI" /* AES Crypto */ 863 "\033XSAVE" /* XSAVE/XRSTOR States */ 864 "\034OSXSAVE" /* OS-Enabled State Management*/ 865 "\035AVX" /* Advanced Vector Extensions */ 866 "\036F16C" /* Half-precision conversions */ 867 "\037RDRAND" /* RDRAND Instruction */ 868 "\040HV" /* Hypervisor */ 869 ); 870 } 871 872 if (amd_feature != 0) { 873 printf("\n AMD Features=0x%b", amd_feature, 874 "\020" /* in hex */ 875 "\001<s0>" /* Same */ 876 "\002<s1>" /* Same */ 877 "\003<s2>" /* Same */ 878 "\004<s3>" /* Same */ 879 "\005<s4>" /* Same */ 880 "\006<s5>" /* Same */ 881 "\007<s6>" /* Same */ 882 "\010<s7>" /* Same */ 883 "\011<s8>" /* Same */ 884 "\012<s9>" /* Same */ 885 "\013<b10>" /* Undefined */ 886 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 887 "\015<s12>" /* Same */ 888 "\016<s13>" /* Same */ 889 "\017<s14>" /* Same */ 890 "\020<s15>" /* Same */ 891 "\021<s16>" /* Same */ 892 "\022<s17>" /* Same */ 893 "\023<b18>" /* Reserved, unknown */ 894 "\024MP" /* Multiprocessor Capable */ 895 "\025NX" /* Has EFER.NXE, NX */ 896 "\026<b21>" /* Undefined */ 897 "\027MMX+" /* AMD MMX Extensions */ 898 "\030<s23>" /* Same */ 899 "\031<s24>" /* Same */ 900 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 901 "\033Page1GB" /* 1-GB large page support */ 902 "\034RDTSCP" /* RDTSCP */ 903 "\035<b28>" /* Undefined */ 904 "\036LM" /* 64 bit long mode */ 905 "\0373DNow!+" /* AMD 3DNow! Extensions */ 906 "\0403DNow!" /* AMD 3DNow! */ 907 ); 908 } 909 910 if (amd_feature2 != 0) { 911 printf("\n AMD Features2=0x%b", amd_feature2, 912 "\020" 913 "\001LAHF" /* LAHF/SAHF in long mode */ 914 "\002CMP" /* CMP legacy */ 915 "\003SVM" /* Secure Virtual Mode */ 916 "\004ExtAPIC" /* Extended APIC register */ 917 "\005CR8" /* CR8 in legacy mode */ 918 "\006ABM" /* LZCNT instruction */ 919 "\007SSE4A" /* SSE4A */ 920 "\010MAS" /* Misaligned SSE mode */ 921 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 922 "\012OSVW" /* OS visible workaround */ 923 "\013IBS" /* Instruction based sampling */ 924 "\014XOP" /* XOP extended instructions */ 925 "\015SKINIT" /* SKINIT/STGI */ 926 "\016WDT" /* Watchdog timer */ 927 "\017<b14>" 928 "\020LWP" /* Lightweight Profiling */ 929 "\021FMA4" /* 4-operand FMA instructions */ 930 "\022TCE" /* Translation Cache Extension */ 931 "\023<b18>" 932 "\024NodeId" /* NodeId MSR support */ 933 "\025<b20>" 934 "\026TBM" /* Trailing Bit Manipulation */ 935 "\027Topology" /* Topology Extensions */ 936 "\030PCXC" /* Core perf count */ 937 "\031PNXC" /* NB perf count */ 938 "\032<b25>" 939 "\033DBE" /* Data Breakpoint extension */ 940 "\034PTSC" /* Performance TSC */ 941 "\035PL2I" /* L2I perf count */ 942 "\036MWAITX" /* MONITORX/MWAITX instructions */ 943 "\037ADMSKX" /* Address mask extension */ 944 "\040<b31>" 945 ); 946 } 947 948 if (cpu_stdext_feature != 0) { 949 printf("\n Structured Extended Features=0x%b", 950 cpu_stdext_feature, 951 "\020" 952 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 953 "\001FSGSBASE" 954 "\002TSCADJ" 955 "\003SGX" 956 /* Bit Manipulation Instructions */ 957 "\004BMI1" 958 /* Hardware Lock Elision */ 959 "\005HLE" 960 /* Advanced Vector Instructions 2 */ 961 "\006AVX2" 962 /* FDP_EXCPTN_ONLY */ 963 "\007FDPEXC" 964 /* Supervisor Mode Execution Prot. */ 965 "\010SMEP" 966 /* Bit Manipulation Instructions */ 967 "\011BMI2" 968 "\012ERMS" 969 /* Invalidate Processor Context ID */ 970 "\013INVPCID" 971 /* Restricted Transactional Memory */ 972 "\014RTM" 973 "\015PQM" 974 "\016NFPUSG" 975 /* Intel Memory Protection Extensions */ 976 "\017MPX" 977 "\020PQE" 978 /* AVX512 Foundation */ 979 "\021AVX512F" 980 "\022AVX512DQ" 981 /* Enhanced NRBG */ 982 "\023RDSEED" 983 /* ADCX + ADOX */ 984 "\024ADX" 985 /* Supervisor Mode Access Prevention */ 986 "\025SMAP" 987 "\026AVX512IFMA" 988 /* Formerly PCOMMIT */ 989 "\027<b22>" 990 "\030CLFLUSHOPT" 991 "\031CLWB" 992 "\032PROCTRACE" 993 "\033AVX512PF" 994 "\034AVX512ER" 995 "\035AVX512CD" 996 "\036SHA" 997 "\037AVX512BW" 998 "\040AVX512VL" 999 ); 1000 } 1001 1002 if (cpu_stdext_feature2 != 0) { 1003 printf("\n Structured Extended Features2=0x%b", 1004 cpu_stdext_feature2, 1005 "\020" 1006 "\001PREFETCHWT1" 1007 "\002AVX512VBMI" 1008 "\003UMIP" 1009 "\004PKU" 1010 "\005OSPKE" 1011 "\006WAITPKG" 1012 "\007AVX512VBMI2" 1013 "\011GFNI" 1014 "\012VAES" 1015 "\013VPCLMULQDQ" 1016 "\014AVX512VNNI" 1017 "\015AVX512BITALG" 1018 "\016TME" 1019 "\017AVX512VPOPCNTDQ" 1020 "\021LA57" 1021 "\027RDPID" 1022 "\032CLDEMOTE" 1023 "\034MOVDIRI" 1024 "\035MOVDIR64B" 1025 "\036ENQCMD" 1026 "\037SGXLC" 1027 ); 1028 } 1029 1030 if (cpu_stdext_feature3 != 0) { 1031 printf("\n Structured Extended Features3=0x%b", 1032 cpu_stdext_feature3, 1033 "\020" 1034 "\003AVX512_4VNNIW" 1035 "\004AVX512_4FMAPS" 1036 "\005FSRM" 1037 "\011AVX512VP2INTERSECT" 1038 "\012MCUOPT" 1039 "\013MD_CLEAR" 1040 "\016TSXFA" 1041 "\023PCONFIG" 1042 "\025IBT" 1043 "\033IBPB" 1044 "\034STIBP" 1045 "\035L1DFL" 1046 "\036ARCH_CAP" 1047 "\037CORE_CAP" 1048 "\040SSBD" 1049 ); 1050 } 1051 1052 if (cpu_stdext_feature4 != 0) { 1053 printf("\n Structured Extended Features4=0x%b", 1054 cpu_stdext_feature4, 1055 "\020" 1056 "\001SHA512" 1057 "\002SM3" 1058 "\003SM4" 1059 "\007LASS" 1060 "\022FRED" 1061 "\023LKGS" 1062 "\024WRMSRNS" 1063 "\025NMISRC" 1064 "\033LAM" 1065 ); 1066 } 1067 1068 if (cpu_stdext_feature5 != 0) { 1069 printf("\n Structured Extended Features5=0x%b", 1070 cpu_stdext_feature5, 1071 "\020" 1072 "\006MSR_IMM" 1073 ); 1074 } 1075 1076 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1077 cpuid_count(0xd, 0x1, regs); 1078 if (regs[0] != 0) { 1079 printf("\n XSAVE Features=0x%b", 1080 regs[0], 1081 "\020" 1082 "\001XSAVEOPT" 1083 "\002XSAVEC" 1084 "\003XINUSE" 1085 "\004XSAVES"); 1086 } 1087 } 1088 1089 if (cpu_ia32_arch_caps != 0) { 1090 printf("\n IA32_ARCH_CAPS=0x%b", 1091 (u_int)cpu_ia32_arch_caps, 1092 "\020" 1093 "\001RDCL_NO" 1094 "\002IBRS_ALL" 1095 "\003RSBA" 1096 "\004SKIP_L1DFL_VME" 1097 "\005SSB_NO" 1098 "\006MDS_NO" 1099 "\010TSX_CTRL" 1100 "\011TAA_NO" 1101 ); 1102 } 1103 1104 if (amd_extended_feature_extensions != 0) { 1105 u_int amd_fe_masked; 1106 1107 amd_fe_masked = amd_extended_feature_extensions; 1108 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1109 amd_fe_masked &= 1110 ~(AMDFEID_IBRS_ALWAYSON | 1111 AMDFEID_PREFER_IBRS); 1112 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1113 amd_fe_masked &= 1114 ~AMDFEID_STIBP_ALWAYSON; 1115 1116 printf("\n " 1117 "AMD Extended Feature Extensions ID EBX=" 1118 "0x%b", amd_fe_masked, 1119 "\020" 1120 "\001CLZERO" 1121 "\002IRPerf" 1122 "\003XSaveErPtr" 1123 "\004INVLPGB" 1124 "\005RDPRU" 1125 "\007BE" 1126 "\011MCOMMIT" 1127 "\012WBNOINVD" 1128 "\015IBPB" 1129 "\016INT_WBINVD" 1130 "\017IBRS" 1131 "\020STIBP" 1132 "\021IBRS_ALWAYSON" 1133 "\022STIBP_ALWAYSON" 1134 "\023PREFER_IBRS" 1135 "\024SAMEMODE_IBRS" 1136 "\025NOLMSLE" 1137 "\026INVLPGBNEST" 1138 "\030PPIN" 1139 "\031SSBD" 1140 "\032VIRT_SSBD" 1141 "\033SSB_NO" 1142 "\034CPPC" 1143 "\035PSFD" 1144 "\036BTC_NO" 1145 "\037IBPB_RET" 1146 ); 1147 } 1148 1149 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1150 print_via_padlock_info(); 1151 1152 if (cpu_feature2 & CPUID2_VMX) 1153 print_vmx_info(); 1154 1155 if (amd_feature2 & AMDID2_SVM) 1156 print_svm_info(); 1157 1158 if ((cpu_feature & CPUID_HTT) && 1159 (cpu_vendor_id == CPU_VENDOR_AMD || 1160 cpu_vendor_id == CPU_VENDOR_HYGON)) 1161 cpu_feature &= ~CPUID_HTT; 1162 1163 /* 1164 * If this CPU supports P-state invariant TSC then 1165 * mention the capability. 1166 */ 1167 if (tsc_is_invariant) { 1168 printf("\n TSC: P-state invariant"); 1169 if (tsc_perf_stat) 1170 printf(", performance statistics"); 1171 } 1172 } 1173 #ifdef __i386__ 1174 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1175 printf(" DIR=0x%04x", cyrix_did); 1176 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1177 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1178 #ifndef CYRIX_CACHE_REALLY_WORKS 1179 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1180 printf("\n CPU cache: write-through mode"); 1181 #endif 1182 #endif 1183 } 1184 1185 /* Avoid ugly blank lines: only print newline when we have to. */ 1186 if (*cpu_vendor || cpu_id) 1187 printf("\n"); 1188 1189 if (bootverbose) { 1190 if (cpu_vendor_id == CPU_VENDOR_AMD || 1191 cpu_vendor_id == CPU_VENDOR_HYGON) 1192 print_AMD_info(); 1193 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1194 print_INTEL_info(); 1195 #ifdef __i386__ 1196 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1197 print_transmeta_info(); 1198 #endif 1199 } 1200 1201 print_hypervisor_info(); 1202 } 1203 1204 #ifdef __i386__ 1205 void 1206 panicifcpuunsupported(void) 1207 { 1208 1209 #if !defined(lint) 1210 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1211 #error This kernel is not configured for one of the supported CPUs 1212 #endif 1213 #else /* lint */ 1214 #endif /* lint */ 1215 /* 1216 * Now that we have told the user what they have, 1217 * let them know if that machine type isn't configured. 1218 */ 1219 switch (cpu_class) { 1220 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1221 case CPUCLASS_386: 1222 #if !defined(I486_CPU) 1223 case CPUCLASS_486: 1224 #endif 1225 #if !defined(I586_CPU) 1226 case CPUCLASS_586: 1227 #endif 1228 #if !defined(I686_CPU) 1229 case CPUCLASS_686: 1230 #endif 1231 panic("CPU class not configured"); 1232 default: 1233 break; 1234 } 1235 } 1236 1237 static volatile u_int trap_by_rdmsr; 1238 1239 /* 1240 * Special exception 6 handler. 1241 * The rdmsr instruction generates invalid opcodes fault on 486-class 1242 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1243 * function identblue() when this handler is called. Stacked eip should 1244 * be advanced. 1245 */ 1246 inthand_t bluetrap6; 1247 __asm 1248 (" \n\ 1249 .text \n\ 1250 .p2align 2,0x90 \n\ 1251 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1252 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1253 ss \n\ 1254 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1255 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1256 iret \n\ 1257 "); 1258 1259 /* 1260 * Special exception 13 handler. 1261 * Accessing non-existent MSR generates general protection fault. 1262 */ 1263 inthand_t bluetrap13; 1264 __asm 1265 (" \n\ 1266 .text \n\ 1267 .p2align 2,0x90 \n\ 1268 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1269 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1270 ss \n\ 1271 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1272 popl %eax /* discard error code */ \n\ 1273 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1274 iret \n\ 1275 "); 1276 1277 /* 1278 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1279 * support cpuid instruction. This function should be called after 1280 * loading interrupt descriptor table register. 1281 * 1282 * I don't like this method that handles fault, but I couldn't get 1283 * information for any other methods. Does blue giant know? 1284 */ 1285 static int 1286 identblue(void) 1287 { 1288 1289 trap_by_rdmsr = 0; 1290 1291 /* 1292 * Cyrix 486-class CPU does not support rdmsr instruction. 1293 * The rdmsr instruction generates invalid opcode fault, and exception 1294 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1295 * bluetrap6() set the magic number to trap_by_rdmsr. 1296 */ 1297 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1298 GSEL(GCODE_SEL, SEL_KPL)); 1299 1300 /* 1301 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1302 * In this case, rdmsr generates general protection fault, and 1303 * exception will be trapped by bluetrap13(). 1304 */ 1305 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1306 GSEL(GCODE_SEL, SEL_KPL)); 1307 1308 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1309 1310 if (trap_by_rdmsr == 0xa8c1d) 1311 return IDENTBLUE_CYRIX486; 1312 else if (trap_by_rdmsr == 0xa89c4) 1313 return IDENTBLUE_CYRIXM2; 1314 return IDENTBLUE_IBMCPU; 1315 } 1316 1317 /* 1318 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1319 * 1320 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1321 * +-------+-------+---------------+ 1322 * | SID | RID | Device ID | 1323 * | (DIR 1) | (DIR 0) | 1324 * +-------+-------+---------------+ 1325 */ 1326 static void 1327 identifycyrix(void) 1328 { 1329 register_t saveintr; 1330 int ccr2_test = 0, dir_test = 0; 1331 u_char ccr2, ccr3; 1332 1333 saveintr = intr_disable(); 1334 1335 ccr2 = read_cyrix_reg(CCR2); 1336 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1337 read_cyrix_reg(CCR2); 1338 if (read_cyrix_reg(CCR2) != ccr2) 1339 ccr2_test = 1; 1340 write_cyrix_reg(CCR2, ccr2); 1341 1342 ccr3 = read_cyrix_reg(CCR3); 1343 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1344 read_cyrix_reg(CCR3); 1345 if (read_cyrix_reg(CCR3) != ccr3) 1346 dir_test = 1; /* CPU supports DIRs. */ 1347 write_cyrix_reg(CCR3, ccr3); 1348 1349 if (dir_test) { 1350 /* Device ID registers are available. */ 1351 cyrix_did = read_cyrix_reg(DIR1) << 8; 1352 cyrix_did += read_cyrix_reg(DIR0); 1353 } else if (ccr2_test) 1354 cyrix_did = 0x0010; /* 486S A-step */ 1355 else 1356 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1357 1358 intr_restore(saveintr); 1359 } 1360 #endif 1361 1362 /* Update TSC freq with the value indicated by the caller. */ 1363 static void 1364 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1365 { 1366 1367 /* If there was an error during the transition, don't do anything. */ 1368 if (status != 0) 1369 return; 1370 1371 /* Total setting for this level gives the new frequency in MHz. */ 1372 hw_clockrate = level->total_set.freq; 1373 } 1374 1375 static void 1376 hook_tsc_freq(void *arg __unused) 1377 { 1378 1379 if (tsc_is_invariant) 1380 return; 1381 1382 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1383 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1384 } 1385 1386 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1387 1388 static struct { 1389 const char *vm_cpuid; 1390 int vm_guest; 1391 void (*init)(void); 1392 } vm_cpuids[] = { 1393 { "XenVMMXenVMM", VM_GUEST_XEN, 1394 #ifdef XENHVM 1395 &xen_early_init, 1396 #endif 1397 }, /* XEN */ 1398 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */ 1399 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */ 1400 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */ 1401 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */ 1402 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */ 1403 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */ 1404 }; 1405 1406 static void 1407 identify_hypervisor_cpuid_base(void) 1408 { 1409 void (*init_fn)(void) = NULL; 1410 u_int leaf, regs[4]; 1411 int i; 1412 1413 /* 1414 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1415 * http://lkml.org/lkml/2008/10/1/246 1416 * 1417 * KB1009458: Mechanisms to determine if software is running in 1418 * a VMware virtual machine 1419 * http://kb.vmware.com/kb/1009458 1420 * 1421 * Search for a hypervisor that we recognize. If we cannot find 1422 * a specific hypervisor, return the first information about the 1423 * hypervisor that we found, as others may be able to use. 1424 */ 1425 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { 1426 do_cpuid(leaf, regs); 1427 1428 /* 1429 * KVM from Linux kernels prior to commit 1430 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1431 * to 0 rather than a valid hv_high value. Check for 1432 * the KVM signature bytes and fixup %eax to the 1433 * highest supported leaf in that case. 1434 */ 1435 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1436 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1437 regs[0] = leaf + 1; 1438 1439 if (regs[0] >= leaf) { 1440 enum VM_GUEST prev_vm_guest = vm_guest; 1441 1442 for (i = 0; i < nitems(vm_cpuids); i++) 1443 if (strncmp((const char *)®s[1], 1444 vm_cpuids[i].vm_cpuid, 12) == 0) { 1445 vm_guest = vm_cpuids[i].vm_guest; 1446 init_fn = vm_cpuids[i].init; 1447 break; 1448 } 1449 1450 /* 1451 * If this is the first entry or we found a 1452 * specific hypervisor, record the base, high value, 1453 * and vendor identifier. 1454 */ 1455 if (vm_guest != prev_vm_guest || leaf == 0x40000000) { 1456 hv_base = leaf; 1457 hv_high = regs[0]; 1458 ((u_int *)&hv_vendor)[0] = regs[1]; 1459 ((u_int *)&hv_vendor)[1] = regs[2]; 1460 ((u_int *)&hv_vendor)[2] = regs[3]; 1461 hv_vendor[12] = '\0'; 1462 1463 /* 1464 * If we found a specific hypervisor, then 1465 * we are finished. 1466 */ 1467 if (vm_guest != VM_GUEST_VM && 1468 /* 1469 * Xen and other hypervisors can expose the 1470 * HyperV signature in addition to the 1471 * native one in order to support Viridian 1472 * extensions for Windows guests. 1473 * 1474 * Do the full cpuid scan if HyperV is 1475 * detected, as the native hypervisor is 1476 * preferred. 1477 */ 1478 vm_guest != VM_GUEST_HV) 1479 break; 1480 } 1481 } 1482 } 1483 1484 if (init_fn != NULL) 1485 init_fn(); 1486 } 1487 1488 void 1489 identify_hypervisor(void) 1490 { 1491 u_int regs[4]; 1492 char *p; 1493 1494 TSENTER(); 1495 /* 1496 * If CPUID2_HV is set, we are running in a hypervisor environment. 1497 */ 1498 if (cpu_feature2 & CPUID2_HV) { 1499 vm_guest = VM_GUEST_VM; 1500 identify_hypervisor_cpuid_base(); 1501 1502 /* If we have a definitive vendor, we can return now. */ 1503 if (*hv_vendor != '\0') { 1504 TSEXIT(); 1505 return; 1506 } 1507 } 1508 1509 /* 1510 * Examine SMBIOS strings for older hypervisors. 1511 */ 1512 p = kern_getenv("smbios.system.serial"); 1513 if (p != NULL) { 1514 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1515 vmware_hvcall(0, VMW_HVCMD_GETVERSION, 1516 VMW_HVCMD_DEFAULT_PARAM, regs); 1517 if (regs[1] == VMW_HVMAGIC) { 1518 vm_guest = VM_GUEST_VMWARE; 1519 freeenv(p); 1520 TSEXIT(); 1521 return; 1522 } 1523 } 1524 freeenv(p); 1525 } 1526 TSEXIT(); 1527 } 1528 1529 bool 1530 fix_cpuid(void) 1531 { 1532 uint64_t msr; 1533 1534 /* 1535 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1536 * get the largest standard CPUID function number again if it is set 1537 * from BIOS. It is necessary for probing correct CPU topology later 1538 * and for the correct operation of the AVX-aware userspace. 1539 */ 1540 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1541 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1542 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1543 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1544 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1545 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1546 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1547 msr &= ~IA32_MISC_EN_LIMCPUID; 1548 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1549 return (true); 1550 } 1551 } 1552 1553 /* 1554 * Re-enable AMD Topology Extension that could be disabled by BIOS 1555 * on some notebook processors. Without the extension it's really 1556 * hard to determine the correct CPU cache topology. 1557 * See BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h 1558 * Models 60h-6Fh Processors, Publication # 50742. 1559 */ 1560 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1561 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1562 msr = rdmsr(MSR_EXTFEATURES); 1563 if ((msr & ((uint64_t)1 << 54)) == 0) { 1564 msr |= (uint64_t)1 << 54; 1565 wrmsr(MSR_EXTFEATURES, msr); 1566 return (true); 1567 } 1568 } 1569 return (false); 1570 } 1571 1572 void 1573 identify_cpu1(void) 1574 { 1575 u_int regs[4]; 1576 1577 do_cpuid(0, regs); 1578 cpu_high = regs[0]; 1579 ((u_int *)&cpu_vendor)[0] = regs[1]; 1580 ((u_int *)&cpu_vendor)[1] = regs[3]; 1581 ((u_int *)&cpu_vendor)[2] = regs[2]; 1582 cpu_vendor[12] = '\0'; 1583 1584 do_cpuid(1, regs); 1585 cpu_id = regs[0]; 1586 cpu_procinfo = regs[1]; 1587 cpu_feature = regs[3]; 1588 cpu_feature2 = regs[2]; 1589 } 1590 1591 void 1592 identify_cpu2(void) 1593 { 1594 u_int regs[4], cpu_stdext_disable, max_eax_l7; 1595 1596 if (cpu_high >= 6) { 1597 cpuid_count(6, 0, regs); 1598 cpu_power_eax = regs[0]; 1599 cpu_power_ebx = regs[1]; 1600 cpu_power_ecx = regs[2]; 1601 cpu_power_edx = regs[3]; 1602 } 1603 1604 if (cpu_high >= 7) { 1605 cpuid_count(7, 0, regs); 1606 cpu_stdext_feature = regs[1]; 1607 max_eax_l7 = regs[0]; 1608 1609 /* 1610 * Some hypervisors failed to filter out unsupported 1611 * extended features. Allow to disable the 1612 * extensions, activation of which requires setting a 1613 * bit in CR4, and which VM monitors do not support. 1614 */ 1615 cpu_stdext_disable = 0; 1616 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1617 cpu_stdext_feature &= ~cpu_stdext_disable; 1618 1619 cpu_stdext_feature2 = regs[2]; 1620 cpu_stdext_feature3 = regs[3]; 1621 1622 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1623 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1624 1625 if (max_eax_l7 >= 1) { 1626 cpuid_count(7, 1, regs); 1627 cpu_stdext_feature4 = regs[0]; 1628 cpu_stdext_feature5 = regs[2]; 1629 } 1630 } 1631 } 1632 1633 void 1634 identify_cpu_ext_features(void) 1635 { 1636 u_int regs[4]; 1637 1638 if (cpu_high >= 7) { 1639 cpuid_count(7, 0, regs); 1640 cpu_stdext_feature2 = regs[2]; 1641 cpu_stdext_feature3 = regs[3]; 1642 } 1643 } 1644 1645 void 1646 identify_cpu_fixup_bsp(void) 1647 { 1648 u_int regs[4]; 1649 1650 cpu_vendor_id = find_cpu_vendor_id(); 1651 1652 if (fix_cpuid()) { 1653 do_cpuid(0, regs); 1654 cpu_high = regs[0]; 1655 } 1656 } 1657 1658 /* 1659 * Final stage of CPU identification. 1660 */ 1661 void 1662 finishidentcpu(void) 1663 { 1664 u_int regs[4]; 1665 #ifdef __i386__ 1666 u_char ccr3; 1667 #endif 1668 1669 identify_cpu_fixup_bsp(); 1670 1671 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1672 do_cpuid(5, regs); 1673 cpu_mon_mwait_flags = regs[2]; 1674 cpu_mon_mwait_edx = regs[3]; 1675 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1676 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1677 } 1678 1679 identify_cpu2(); 1680 1681 #ifdef __i386__ 1682 if (cpu_high > 0 && 1683 (cpu_vendor_id == CPU_VENDOR_INTEL || 1684 cpu_vendor_id == CPU_VENDOR_AMD || 1685 cpu_vendor_id == CPU_VENDOR_HYGON || 1686 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1687 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1688 cpu_vendor_id == CPU_VENDOR_NSC)) { 1689 do_cpuid(0x80000000, regs); 1690 if (regs[0] >= 0x80000000) 1691 cpu_exthigh = regs[0]; 1692 } 1693 #else 1694 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1695 cpu_vendor_id == CPU_VENDOR_AMD || 1696 cpu_vendor_id == CPU_VENDOR_HYGON || 1697 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1698 do_cpuid(0x80000000, regs); 1699 cpu_exthigh = regs[0]; 1700 } 1701 #endif 1702 if (cpu_exthigh >= 0x80000001) { 1703 do_cpuid(0x80000001, regs); 1704 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1705 amd_feature2 = regs[2]; 1706 } 1707 if (cpu_exthigh >= 0x80000007) { 1708 do_cpuid(0x80000007, regs); 1709 amd_rascap = regs[1]; 1710 amd_pminfo = regs[3]; 1711 } 1712 if (cpu_exthigh >= 0x80000008) { 1713 do_cpuid(0x80000008, regs); 1714 cpu_maxphyaddr = regs[0] & 0xff; 1715 amd_extended_feature_extensions = regs[1]; 1716 cpu_procinfo2 = regs[2]; 1717 cpu_procinfo3 = regs[3]; 1718 } else { 1719 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1720 } 1721 1722 #ifdef __i386__ 1723 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1724 if (cpu == CPU_486) { 1725 /* 1726 * These conditions are equivalent to: 1727 * - CPU does not support cpuid instruction. 1728 * - Cyrix/IBM CPU is detected. 1729 */ 1730 if (identblue() == IDENTBLUE_IBMCPU) { 1731 strcpy(cpu_vendor, "IBM"); 1732 cpu_vendor_id = CPU_VENDOR_IBM; 1733 cpu = CPU_BLUE; 1734 return; 1735 } 1736 } 1737 switch (cpu_id & 0xf00) { 1738 case 0x600: 1739 /* 1740 * Cyrix's datasheet does not describe DIRs. 1741 * Therefor, I assume it does not have them 1742 * and use the result of the cpuid instruction. 1743 * XXX they seem to have it for now at least. -Peter 1744 */ 1745 identifycyrix(); 1746 cpu = CPU_M2; 1747 break; 1748 default: 1749 identifycyrix(); 1750 /* 1751 * This routine contains a trick. 1752 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1753 */ 1754 switch (cyrix_did & 0x00f0) { 1755 case 0x00: 1756 case 0xf0: 1757 cpu = CPU_486DLC; 1758 break; 1759 case 0x10: 1760 cpu = CPU_CY486DX; 1761 break; 1762 case 0x20: 1763 if ((cyrix_did & 0x000f) < 8) 1764 cpu = CPU_M1; 1765 else 1766 cpu = CPU_M1SC; 1767 break; 1768 case 0x30: 1769 cpu = CPU_M1; 1770 break; 1771 case 0x40: 1772 /* MediaGX CPU */ 1773 cpu = CPU_M1SC; 1774 break; 1775 default: 1776 /* M2 and later CPUs are treated as M2. */ 1777 cpu = CPU_M2; 1778 1779 /* 1780 * enable cpuid instruction. 1781 */ 1782 ccr3 = read_cyrix_reg(CCR3); 1783 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1784 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1785 write_cyrix_reg(CCR3, ccr3); 1786 1787 do_cpuid(0, regs); 1788 cpu_high = regs[0]; /* eax */ 1789 do_cpuid(1, regs); 1790 cpu_id = regs[0]; /* eax */ 1791 cpu_feature = regs[3]; /* edx */ 1792 break; 1793 } 1794 } 1795 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1796 /* 1797 * There are BlueLightning CPUs that do not change 1798 * undefined flags by dividing 5 by 2. In this case, 1799 * the CPU identification routine in locore.s leaves 1800 * cpu_vendor null string and puts CPU_486 into the 1801 * cpu. 1802 */ 1803 if (identblue() == IDENTBLUE_IBMCPU) { 1804 strcpy(cpu_vendor, "IBM"); 1805 cpu_vendor_id = CPU_VENDOR_IBM; 1806 cpu = CPU_BLUE; 1807 return; 1808 } 1809 } 1810 #endif 1811 } 1812 1813 int 1814 pti_get_default(void) 1815 { 1816 1817 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || 1818 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) 1819 return (0); 1820 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1821 return (0); 1822 return (1); 1823 } 1824 1825 static u_int 1826 find_cpu_vendor_id(void) 1827 { 1828 int i; 1829 1830 for (i = 0; i < nitems(cpu_vendors); i++) 1831 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1832 return (cpu_vendors[i].vendor_id); 1833 return (0); 1834 } 1835 1836 static void 1837 print_AMD_assoc(int i) 1838 { 1839 if (i == 255) 1840 printf(", fully associative\n"); 1841 else 1842 printf(", %d-way associative\n", i); 1843 } 1844 1845 static void 1846 print_AMD_l2_assoc(int i) 1847 { 1848 switch (i & 0x0f) { 1849 case 0: printf(", disabled/not present\n"); break; 1850 case 1: printf(", direct mapped\n"); break; 1851 case 2: printf(", 2-way associative\n"); break; 1852 case 4: printf(", 4-way associative\n"); break; 1853 case 6: printf(", 8-way associative\n"); break; 1854 case 8: printf(", 16-way associative\n"); break; 1855 case 15: printf(", fully associative\n"); break; 1856 default: printf(", reserved configuration\n"); break; 1857 } 1858 } 1859 1860 static void 1861 print_AMD_info(void) 1862 { 1863 #ifdef __i386__ 1864 uint64_t amd_whcr; 1865 #endif 1866 u_int regs[4]; 1867 1868 if (cpu_exthigh >= 0x80000005) { 1869 do_cpuid(0x80000005, regs); 1870 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1871 print_AMD_assoc(regs[0] >> 24); 1872 1873 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1874 print_AMD_assoc((regs[0] >> 8) & 0xff); 1875 1876 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1877 print_AMD_assoc(regs[1] >> 24); 1878 1879 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1880 print_AMD_assoc((regs[1] >> 8) & 0xff); 1881 1882 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1883 printf(", %d bytes/line", regs[2] & 0xff); 1884 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1885 print_AMD_assoc((regs[2] >> 16) & 0xff); 1886 1887 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1888 printf(", %d bytes/line", regs[3] & 0xff); 1889 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1890 print_AMD_assoc((regs[3] >> 16) & 0xff); 1891 } 1892 1893 if (cpu_exthigh >= 0x80000006) { 1894 do_cpuid(0x80000006, regs); 1895 if ((regs[0] >> 16) != 0) { 1896 printf("L2 2MB data TLB: %d entries", 1897 (regs[0] >> 16) & 0xfff); 1898 print_AMD_l2_assoc(regs[0] >> 28); 1899 printf("L2 2MB instruction TLB: %d entries", 1900 regs[0] & 0xfff); 1901 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1902 } else { 1903 printf("L2 2MB unified TLB: %d entries", 1904 regs[0] & 0xfff); 1905 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1906 } 1907 if ((regs[1] >> 16) != 0) { 1908 printf("L2 4KB data TLB: %d entries", 1909 (regs[1] >> 16) & 0xfff); 1910 print_AMD_l2_assoc(regs[1] >> 28); 1911 1912 printf("L2 4KB instruction TLB: %d entries", 1913 (regs[1] >> 16) & 0xfff); 1914 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1915 } else { 1916 printf("L2 4KB unified TLB: %d entries", 1917 (regs[1] >> 16) & 0xfff); 1918 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1919 } 1920 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1921 printf(", %d bytes/line", regs[2] & 0xff); 1922 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1923 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1924 } 1925 1926 #ifdef __i386__ 1927 if (((cpu_id & 0xf00) == 0x500) 1928 && (((cpu_id & 0x0f0) > 0x80) 1929 || (((cpu_id & 0x0f0) == 0x80) 1930 && (cpu_id & 0x00f) > 0x07))) { 1931 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1932 amd_whcr = rdmsr(0xc0000082); 1933 if (!(amd_whcr & (0x3ff << 22))) { 1934 printf("Write Allocate Disable\n"); 1935 } else { 1936 printf("Write Allocate Enable Limit: %dM bytes\n", 1937 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1938 printf("Write Allocate 15-16M bytes: %s\n", 1939 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1940 } 1941 } else if (((cpu_id & 0xf00) == 0x500) 1942 && ((cpu_id & 0x0f0) > 0x50)) { 1943 /* K6, K6-2(old core) */ 1944 amd_whcr = rdmsr(0xc0000082); 1945 if (!(amd_whcr & (0x7f << 1))) { 1946 printf("Write Allocate Disable\n"); 1947 } else { 1948 printf("Write Allocate Enable Limit: %dM bytes\n", 1949 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1950 printf("Write Allocate 15-16M bytes: %s\n", 1951 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1952 printf("Hardware Write Allocate Control: %s\n", 1953 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1954 } 1955 } 1956 #endif 1957 /* 1958 * Opteron Rev E shows a bug as in very rare occasions a read memory 1959 * barrier is not performed as expected if it is followed by a 1960 * non-atomic read-modify-write instruction. 1961 * As long as that bug pops up very rarely (intensive machine usage 1962 * on other operating systems generally generates one unexplainable 1963 * crash any 2 months) and as long as a model specific fix would be 1964 * impractical at this stage, print out a warning string if the broken 1965 * model and family are identified. 1966 */ 1967 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1968 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1969 printf("WARNING: This architecture revision has known SMP " 1970 "hardware bugs which may cause random instability\n"); 1971 } 1972 1973 static void 1974 print_INTEL_info(void) 1975 { 1976 u_int regs[4]; 1977 u_int rounds, regnum; 1978 u_int nwaycode, nway; 1979 1980 if (cpu_high >= 2) { 1981 rounds = 0; 1982 do { 1983 do_cpuid(0x2, regs); 1984 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1985 break; /* we have a buggy CPU */ 1986 1987 for (regnum = 0; regnum <= 3; ++regnum) { 1988 if (regs[regnum] & (1<<31)) 1989 continue; 1990 if (regnum != 0) 1991 print_INTEL_TLB(regs[regnum] & 0xff); 1992 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1993 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1994 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1995 } 1996 } while (--rounds > 0); 1997 } 1998 1999 if (cpu_exthigh >= 0x80000006) { 2000 do_cpuid(0x80000006, regs); 2001 nwaycode = (regs[2] >> 12) & 0x0f; 2002 if (nwaycode >= 0x02 && nwaycode <= 0x08) 2003 nway = 1 << (nwaycode / 2); 2004 else 2005 nway = 0; 2006 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 2007 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 2008 } 2009 } 2010 2011 static void 2012 print_INTEL_TLB(u_int data) 2013 { 2014 switch (data) { 2015 case 0x0: 2016 case 0x40: 2017 default: 2018 break; 2019 case 0x1: 2020 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 2021 break; 2022 case 0x2: 2023 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 2024 break; 2025 case 0x3: 2026 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 2027 break; 2028 case 0x4: 2029 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 2030 break; 2031 case 0x6: 2032 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 2033 break; 2034 case 0x8: 2035 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2036 break; 2037 case 0x9: 2038 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 2039 break; 2040 case 0xa: 2041 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 2042 break; 2043 case 0xb: 2044 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 2045 break; 2046 case 0xc: 2047 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2048 break; 2049 case 0xd: 2050 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 2051 break; 2052 case 0xe: 2053 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 2054 break; 2055 case 0x1d: 2056 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 2057 break; 2058 case 0x21: 2059 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 2060 break; 2061 case 0x22: 2062 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2063 break; 2064 case 0x23: 2065 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2066 break; 2067 case 0x24: 2068 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 2069 break; 2070 case 0x25: 2071 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2072 break; 2073 case 0x29: 2074 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2075 break; 2076 case 0x2c: 2077 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2078 break; 2079 case 0x30: 2080 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2081 break; 2082 case 0x39: /* De-listed in SDM rev. 54 */ 2083 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2084 break; 2085 case 0x3b: /* De-listed in SDM rev. 54 */ 2086 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 2087 break; 2088 case 0x3c: /* De-listed in SDM rev. 54 */ 2089 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2090 break; 2091 case 0x41: 2092 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 2093 break; 2094 case 0x42: 2095 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 2096 break; 2097 case 0x43: 2098 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 2099 break; 2100 case 0x44: 2101 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 2102 break; 2103 case 0x45: 2104 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 2105 break; 2106 case 0x46: 2107 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 2108 break; 2109 case 0x47: 2110 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 2111 break; 2112 case 0x48: 2113 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 2114 break; 2115 case 0x49: 2116 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 2117 CPUID_TO_MODEL(cpu_id) == 0x6) 2118 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 2119 else 2120 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 2121 break; 2122 case 0x4a: 2123 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 2124 break; 2125 case 0x4b: 2126 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 2127 break; 2128 case 0x4c: 2129 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 2130 break; 2131 case 0x4d: 2132 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 2133 break; 2134 case 0x4e: 2135 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 2136 break; 2137 case 0x4f: 2138 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 2139 break; 2140 case 0x50: 2141 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 2142 break; 2143 case 0x51: 2144 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 2145 break; 2146 case 0x52: 2147 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2148 break; 2149 case 0x55: 2150 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2151 break; 2152 case 0x56: 2153 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2154 break; 2155 case 0x57: 2156 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2157 break; 2158 case 0x59: 2159 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2160 break; 2161 case 0x5a: 2162 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2163 break; 2164 case 0x5b: 2165 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2166 break; 2167 case 0x5c: 2168 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2169 break; 2170 case 0x5d: 2171 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2172 break; 2173 case 0x60: 2174 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2175 break; 2176 case 0x61: 2177 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2178 break; 2179 case 0x63: 2180 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2181 break; 2182 case 0x64: 2183 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2184 break; 2185 case 0x66: 2186 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2187 break; 2188 case 0x67: 2189 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2190 break; 2191 case 0x68: 2192 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2193 break; 2194 case 0x6a: 2195 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2196 break; 2197 case 0x6b: 2198 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2199 break; 2200 case 0x6c: 2201 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2202 break; 2203 case 0x6d: 2204 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2205 break; 2206 case 0x70: 2207 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2208 break; 2209 case 0x71: 2210 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2211 break; 2212 case 0x72: 2213 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2214 break; 2215 case 0x76: 2216 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2217 break; 2218 case 0x78: 2219 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2220 break; 2221 case 0x79: 2222 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2223 break; 2224 case 0x7a: 2225 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2226 break; 2227 case 0x7b: 2228 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2229 break; 2230 case 0x7c: 2231 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2232 break; 2233 case 0x7d: 2234 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2235 break; 2236 case 0x7f: 2237 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2238 break; 2239 case 0x80: 2240 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2241 break; 2242 case 0x82: 2243 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2244 break; 2245 case 0x83: 2246 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2247 break; 2248 case 0x84: 2249 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2250 break; 2251 case 0x85: 2252 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2253 break; 2254 case 0x86: 2255 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2256 break; 2257 case 0x87: 2258 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2259 break; 2260 case 0xa0: 2261 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2262 break; 2263 case 0xb0: 2264 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2265 break; 2266 case 0xb1: 2267 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2268 break; 2269 case 0xb2: 2270 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2271 break; 2272 case 0xb3: 2273 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2274 break; 2275 case 0xb4: 2276 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2277 break; 2278 case 0xb5: 2279 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2280 break; 2281 case 0xb6: 2282 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2283 break; 2284 case 0xba: 2285 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2286 break; 2287 case 0xc0: 2288 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2289 break; 2290 case 0xc1: 2291 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2292 break; 2293 case 0xc2: 2294 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2295 break; 2296 case 0xc3: 2297 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2298 break; 2299 case 0xc4: 2300 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2301 break; 2302 case 0xca: 2303 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2304 break; 2305 case 0xd0: 2306 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2307 break; 2308 case 0xd1: 2309 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2310 break; 2311 case 0xd2: 2312 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2313 break; 2314 case 0xd6: 2315 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2316 break; 2317 case 0xd7: 2318 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2319 break; 2320 case 0xd8: 2321 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2322 break; 2323 case 0xdc: 2324 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2325 break; 2326 case 0xdd: 2327 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2328 break; 2329 case 0xde: 2330 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2331 break; 2332 case 0xe2: 2333 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2334 break; 2335 case 0xe3: 2336 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2337 break; 2338 case 0xe4: 2339 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2340 break; 2341 case 0xea: 2342 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2343 break; 2344 case 0xeb: 2345 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2346 break; 2347 case 0xec: 2348 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2349 break; 2350 case 0xf0: 2351 printf("64-Byte prefetching\n"); 2352 break; 2353 case 0xf1: 2354 printf("128-Byte prefetching\n"); 2355 break; 2356 } 2357 } 2358 2359 static void 2360 print_svm_info(void) 2361 { 2362 u_int features, regs[4]; 2363 uint64_t msr; 2364 int comma; 2365 2366 printf("\n SVM: "); 2367 do_cpuid(0x8000000A, regs); 2368 features = regs[3]; 2369 2370 msr = rdmsr(MSR_VM_CR); 2371 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2372 printf("(disabled in BIOS) "); 2373 2374 if (!bootverbose) { 2375 comma = 0; 2376 if (features & (1 << 0)) { 2377 printf("%sNP", comma ? "," : ""); 2378 comma = 1; 2379 } 2380 if (features & (1 << 3)) { 2381 printf("%sNRIP", comma ? "," : ""); 2382 comma = 1; 2383 } 2384 if (features & (1 << 5)) { 2385 printf("%sVClean", comma ? "," : ""); 2386 comma = 1; 2387 } 2388 if (features & (1 << 6)) { 2389 printf("%sAFlush", comma ? "," : ""); 2390 comma = 1; 2391 } 2392 if (features & (1 << 7)) { 2393 printf("%sDAssist", comma ? "," : ""); 2394 comma = 1; 2395 } 2396 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2397 return; 2398 } 2399 2400 printf("Features=0x%b", features, 2401 "\020" 2402 "\001NP" /* Nested paging */ 2403 "\002LbrVirt" /* LBR virtualization */ 2404 "\003SVML" /* SVM lock */ 2405 "\004NRIPS" /* NRIP save */ 2406 "\005TscRateMsr" /* MSR based TSC rate control */ 2407 "\006VmcbClean" /* VMCB clean bits */ 2408 "\007FlushByAsid" /* Flush by ASID */ 2409 "\010DecodeAssist" /* Decode assist */ 2410 "\011<b8>" 2411 "\012<b9>" 2412 "\013PauseFilter" /* PAUSE intercept filter */ 2413 "\014EncryptedMcodePatch" 2414 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2415 "\016AVIC" /* virtual interrupt controller */ 2416 "\017<b14>" 2417 "\020V_VMSAVE_VMLOAD" 2418 "\021vGIF" 2419 "\022GMET" /* Guest Mode Execute Trap */ 2420 "\023<b18>" 2421 "\024<b19>" 2422 "\025GuesSpecCtl" /* Guest Spec_ctl */ 2423 "\026<b21>" 2424 "\027<b22>" 2425 "\030<b23>" 2426 "\031<b24>" 2427 "\032<b25>" 2428 "\033<b26>" 2429 "\034<b27>" 2430 "\035<b28>" 2431 "\036<b29>" 2432 "\037<b30>" 2433 "\040<b31>" 2434 ); 2435 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2436 } 2437 2438 #ifdef __i386__ 2439 static void 2440 print_transmeta_info(void) 2441 { 2442 u_int regs[4], nreg = 0; 2443 2444 do_cpuid(0x80860000, regs); 2445 nreg = regs[0]; 2446 if (nreg >= 0x80860001) { 2447 do_cpuid(0x80860001, regs); 2448 printf(" Processor revision %u.%u.%u.%u\n", 2449 (regs[1] >> 24) & 0xff, 2450 (regs[1] >> 16) & 0xff, 2451 (regs[1] >> 8) & 0xff, 2452 regs[1] & 0xff); 2453 } 2454 if (nreg >= 0x80860002) { 2455 do_cpuid(0x80860002, regs); 2456 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2457 (regs[1] >> 24) & 0xff, 2458 (regs[1] >> 16) & 0xff, 2459 (regs[1] >> 8) & 0xff, 2460 regs[1] & 0xff, 2461 regs[2]); 2462 } 2463 if (nreg >= 0x80860006) { 2464 char info[65]; 2465 do_cpuid(0x80860003, (u_int*) &info[0]); 2466 do_cpuid(0x80860004, (u_int*) &info[16]); 2467 do_cpuid(0x80860005, (u_int*) &info[32]); 2468 do_cpuid(0x80860006, (u_int*) &info[48]); 2469 info[64] = 0; 2470 printf(" %s\n", info); 2471 } 2472 } 2473 #endif 2474 2475 static void 2476 print_via_padlock_info(void) 2477 { 2478 u_int regs[4]; 2479 2480 do_cpuid(0xc0000001, regs); 2481 printf("\n VIA Padlock Features=0x%b", regs[3], 2482 "\020" 2483 "\003RNG" /* RNG */ 2484 "\007AES" /* ACE */ 2485 "\011AES-CTR" /* ACE2 */ 2486 "\013SHA1,SHA256" /* PHE */ 2487 "\015RSA" /* PMM */ 2488 ); 2489 } 2490 2491 static uint32_t 2492 vmx_settable(uint64_t basic, int msr, int true_msr) 2493 { 2494 uint64_t val; 2495 2496 if (basic & (1ULL << 55)) 2497 val = rdmsr(true_msr); 2498 else 2499 val = rdmsr(msr); 2500 2501 /* Just report the controls that can be set to 1. */ 2502 return (val >> 32); 2503 } 2504 2505 static void 2506 print_vmx_info(void) 2507 { 2508 uint64_t basic, msr; 2509 uint32_t entry, exit, mask, pin, proc, proc2; 2510 int comma; 2511 2512 printf("\n VT-x: "); 2513 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2514 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2515 printf("(disabled in BIOS) "); 2516 basic = rdmsr(MSR_VMX_BASIC); 2517 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2518 MSR_VMX_TRUE_PINBASED_CTLS); 2519 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2520 MSR_VMX_TRUE_PROCBASED_CTLS); 2521 if (proc & PROCBASED_SECONDARY_CONTROLS) 2522 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2523 MSR_VMX_PROCBASED_CTLS2); 2524 else 2525 proc2 = 0; 2526 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2527 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2528 2529 if (!bootverbose) { 2530 comma = 0; 2531 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2532 entry & VM_ENTRY_LOAD_PAT) { 2533 printf("%sPAT", comma ? "," : ""); 2534 comma = 1; 2535 } 2536 if (proc & PROCBASED_HLT_EXITING) { 2537 printf("%sHLT", comma ? "," : ""); 2538 comma = 1; 2539 } 2540 if (proc & PROCBASED_MTF) { 2541 printf("%sMTF", comma ? "," : ""); 2542 comma = 1; 2543 } 2544 if (proc & PROCBASED_PAUSE_EXITING) { 2545 printf("%sPAUSE", comma ? "," : ""); 2546 comma = 1; 2547 } 2548 if (proc2 & PROCBASED2_ENABLE_EPT) { 2549 printf("%sEPT", comma ? "," : ""); 2550 comma = 1; 2551 } 2552 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2553 printf("%sUG", comma ? "," : ""); 2554 comma = 1; 2555 } 2556 if (proc2 & PROCBASED2_ENABLE_VPID) { 2557 printf("%sVPID", comma ? "," : ""); 2558 comma = 1; 2559 } 2560 if (proc & PROCBASED_USE_TPR_SHADOW && 2561 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2562 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2563 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2564 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2565 printf("%sVID", comma ? "," : ""); 2566 comma = 1; 2567 if (pin & PINBASED_POSTED_INTERRUPT) 2568 printf(",PostIntr"); 2569 } 2570 return; 2571 } 2572 2573 mask = basic >> 32; 2574 printf("Basic Features=0x%b", mask, 2575 "\020" 2576 "\02132PA" /* 32-bit physical addresses */ 2577 "\022SMM" /* SMM dual-monitor */ 2578 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2579 "\030TRUE" /* TRUE_CTLS MSRs */ 2580 ); 2581 printf("\n Pin-Based Controls=0x%b", pin, 2582 "\020" 2583 "\001ExtINT" /* External-interrupt exiting */ 2584 "\004NMI" /* NMI exiting */ 2585 "\006VNMI" /* Virtual NMIs */ 2586 "\007PreTmr" /* Activate VMX-preemption timer */ 2587 "\010PostIntr" /* Process posted interrupts */ 2588 ); 2589 printf("\n Primary Processor Controls=0x%b", proc, 2590 "\020" 2591 "\003INTWIN" /* Interrupt-window exiting */ 2592 "\004TSCOff" /* Use TSC offsetting */ 2593 "\010HLT" /* HLT exiting */ 2594 "\012INVLPG" /* INVLPG exiting */ 2595 "\013MWAIT" /* MWAIT exiting */ 2596 "\014RDPMC" /* RDPMC exiting */ 2597 "\015RDTSC" /* RDTSC exiting */ 2598 "\020CR3-LD" /* CR3-load exiting */ 2599 "\021CR3-ST" /* CR3-store exiting */ 2600 "\024CR8-LD" /* CR8-load exiting */ 2601 "\025CR8-ST" /* CR8-store exiting */ 2602 "\026TPR" /* Use TPR shadow */ 2603 "\027NMIWIN" /* NMI-window exiting */ 2604 "\030MOV-DR" /* MOV-DR exiting */ 2605 "\031IO" /* Unconditional I/O exiting */ 2606 "\032IOmap" /* Use I/O bitmaps */ 2607 "\034MTF" /* Monitor trap flag */ 2608 "\035MSRmap" /* Use MSR bitmaps */ 2609 "\036MONITOR" /* MONITOR exiting */ 2610 "\037PAUSE" /* PAUSE exiting */ 2611 ); 2612 if (proc & PROCBASED_SECONDARY_CONTROLS) 2613 printf("\n Secondary Processor Controls=0x%b", proc2, 2614 "\020" 2615 "\001APIC" /* Virtualize APIC accesses */ 2616 "\002EPT" /* Enable EPT */ 2617 "\003DT" /* Descriptor-table exiting */ 2618 "\004RDTSCP" /* Enable RDTSCP */ 2619 "\005x2APIC" /* Virtualize x2APIC mode */ 2620 "\006VPID" /* Enable VPID */ 2621 "\007WBINVD" /* WBINVD exiting */ 2622 "\010UG" /* Unrestricted guest */ 2623 "\011APIC-reg" /* APIC-register virtualization */ 2624 "\012VID" /* Virtual-interrupt delivery */ 2625 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2626 "\014RDRAND" /* RDRAND exiting */ 2627 "\015INVPCID" /* Enable INVPCID */ 2628 "\016VMFUNC" /* Enable VM functions */ 2629 "\017VMCS" /* VMCS shadowing */ 2630 "\020EPT#VE" /* EPT-violation #VE */ 2631 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2632 ); 2633 printf("\n Exit Controls=0x%b", exit, 2634 "\020" 2635 "\003DR" /* Save debug controls */ 2636 /* Ignore Host address-space size */ 2637 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2638 "\020AckInt" /* Acknowledge interrupt on exit */ 2639 "\023PAT-SV" /* Save MSR_PAT */ 2640 "\024PAT-LD" /* Load MSR_PAT */ 2641 "\025EFER-SV" /* Save MSR_EFER */ 2642 "\026EFER-LD" /* Load MSR_EFER */ 2643 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2644 ); 2645 printf("\n Entry Controls=0x%b", entry, 2646 "\020" 2647 "\003DR" /* Save debug controls */ 2648 /* Ignore IA-32e mode guest */ 2649 /* Ignore Entry to SMM */ 2650 /* Ignore Deactivate dual-monitor treatment */ 2651 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2652 "\017PAT" /* Load MSR_PAT */ 2653 "\020EFER" /* Load MSR_EFER */ 2654 ); 2655 if (proc & PROCBASED_SECONDARY_CONTROLS && 2656 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2657 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2658 mask = msr; 2659 printf("\n EPT Features=0x%b", mask, 2660 "\020" 2661 "\001XO" /* Execute-only translations */ 2662 "\007PW4" /* Page-walk length of 4 */ 2663 "\011UC" /* EPT paging-structure mem can be UC */ 2664 "\017WB" /* EPT paging-structure mem can be WB */ 2665 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2666 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2667 "\025INVEPT" /* INVEPT is supported */ 2668 "\026AD" /* Accessed and dirty flags for EPT */ 2669 "\032single" /* INVEPT single-context type */ 2670 "\033all" /* INVEPT all-context type */ 2671 ); 2672 mask = msr >> 32; 2673 printf("\n VPID Features=0x%b", mask, 2674 "\020" 2675 "\001INVVPID" /* INVVPID is supported */ 2676 "\011individual" /* INVVPID individual-address type */ 2677 "\012single" /* INVVPID single-context type */ 2678 "\013all" /* INVVPID all-context type */ 2679 /* INVVPID single-context-retaining-globals type */ 2680 "\014single-globals" 2681 ); 2682 } 2683 } 2684 2685 static void 2686 print_hypervisor_info(void) 2687 { 2688 2689 if (*hv_vendor != '\0') 2690 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2691 } 2692 2693 /* 2694 * Returns the maximum physical address that can be used with the 2695 * current system. 2696 */ 2697 vm_paddr_t 2698 cpu_getmaxphyaddr(void) 2699 { 2700 2701 #if defined(__i386__) 2702 if (!pae_mode) 2703 return (0xffffffff); 2704 #endif 2705 return ((1ULL << cpu_maxphyaddr) - 1); 2706 } 2707 2708 const static struct { 2709 u_int family; 2710 u_int model_min; 2711 u_int model_max; 2712 u_int generation; 2713 } zen_idents[] = { 2714 { .family = 0x17, .model_min = 0x00, .model_max = 0x2f, .generation = CPU_AMD_ZEN1 }, 2715 { .family = 0x17, .model_min = 0x50, .model_max = 0x5f, .generation = CPU_AMD_ZEN1 }, 2716 { .family = 0x17, .model_min = 0x30, .model_max = 0x4f, .generation = CPU_AMD_ZEN2 }, 2717 { .family = 0x17, .model_min = 0x60, .model_max = 0x7f, .generation = CPU_AMD_ZEN2 }, 2718 { .family = 0x17, .model_min = 0x90, .model_max = 0x91, .generation = CPU_AMD_ZEN2 }, 2719 { .family = 0x17, .model_min = 0xa0, .model_max = 0xaf, .generation = CPU_AMD_ZEN2 }, 2720 { .family = 0x19, .model_min = 0x00, .model_max = 0x0f, .generation = CPU_AMD_ZEN3 }, 2721 { .family = 0x19, .model_min = 0x20, .model_max = 0x5f, .generation = CPU_AMD_ZEN3 }, 2722 { .family = 0x19, .model_min = 0x10, .model_max = 0x1f, .generation = CPU_AMD_ZEN4 }, 2723 { .family = 0x19, .model_min = 0x60, .model_max = 0xaf, .generation = CPU_AMD_ZEN4 }, 2724 { .family = 0x1a, .model_min = 0x00, .model_max = 0x2f, .generation = CPU_AMD_ZEN5 }, 2725 { .family = 0x1a, .model_min = 0x40, .model_max = 0x4f, .generation = CPU_AMD_ZEN5 }, 2726 { .family = 0x1a, .model_min = 0x60, .model_max = 0x7f, .generation = CPU_AMD_ZEN5 }, 2727 { .family = 0x1a, .model_min = 0x50, .model_max = 0x5f, .generation = CPU_AMD_ZEN6 }, 2728 { .family = 0x1a, .model_min = 0x80, .model_max = 0xaf, .generation = CPU_AMD_ZEN6 }, 2729 { .family = 0x1a, .model_min = 0xc0, .model_max = 0xcf, .generation = CPU_AMD_ZEN6 }, 2730 }; 2731 2732 u_int 2733 ident_zen_cpu(void) 2734 { 2735 u_int family = CPUID_TO_FAMILY(cpu_id); 2736 u_int model = CPUID_TO_MODEL(cpu_id); 2737 int i; 2738 2739 if (cpu_vendor_id != CPU_VENDOR_AMD) 2740 return (CPU_AMD_UNKNOWN); 2741 2742 for (i = 0; i < nitems(zen_idents); i++) { 2743 if (family != zen_idents[i].family) 2744 continue; 2745 if (model < zen_idents[i].model_min || 2746 model > zen_idents[i].model_max) 2747 continue; 2748 return (zen_idents[i].generation); 2749 } 2750 2751 return (CPU_AMD_UNKNOWN); 2752 } 2753