xref: /titanic_52/usr/src/uts/sun4v/sys/machcpuvar.h (revision 9d0d62ad2e60e8f742a2e723d06e88352ee6a1f3)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_MACHCPUVAR_H
27 #define	_SYS_MACHCPUVAR_H
28 
29 #include <sys/intr.h>
30 #include <sys/clock.h>
31 #include <sys/machparam.h>
32 #include <sys/machpcb.h>
33 #include <sys/privregs.h>
34 #include <sys/machlock.h>
35 #include <sys/async.h>
36 #include <sys/error.h>
37 
38 #ifdef	__cplusplus
39 extern "C" {
40 #endif
41 
42 #ifndef	_ASM
43 
44 #include <sys/obpdefs.h>
45 #include <sys/async.h>
46 #include <sys/fm/protocol.h>
47 
48 /*
49  * CPU state ptl1_panic save.
50  */
51 typedef struct ptl1_trapregs {
52 	uint32_t	ptl1_tl;
53 	uint32_t	ptl1_tt;
54 	uint64_t	ptl1_tstate;
55 	uint64_t	ptl1_tpc;
56 	uint64_t	ptl1_tnpc;
57 } ptl1_trapregs_t;
58 
59 typedef struct ptl1_gregs {
60 	uint64_t	ptl1_gl;
61 	uint64_t	ptl1_g1;
62 	uint64_t	ptl1_g2;
63 	uint64_t	ptl1_g3;
64 	uint64_t	ptl1_g4;
65 	uint64_t	ptl1_g5;
66 	uint64_t	ptl1_g6;
67 	uint64_t	ptl1_g7;
68 } ptl1_gregs_t;
69 
70 typedef struct ptl1_regs {
71 	ptl1_trapregs_t	ptl1_trap_regs[PTL1_MAXTL];
72 	ptl1_gregs_t	ptl1_gregs[PTL1_MAXGL + 1];
73 	uint64_t	ptl1_tick;
74 	uint64_t	ptl1_dmmu_type;
75 	uint64_t	ptl1_dmmu_addr;
76 	uint64_t	ptl1_dmmu_ctx;
77 	uint64_t	ptl1_immu_type;
78 	uint64_t	ptl1_immu_addr;
79 	uint64_t	ptl1_immu_ctx;
80 	struct rwindow	ptl1_rwindow[MAXWIN];
81 	uint32_t	ptl1_softint;
82 	uint16_t	ptl1_pstate;
83 	uint8_t		ptl1_pil;
84 	uint8_t		ptl1_cwp;
85 	uint8_t		ptl1_wstate;
86 	uint8_t		ptl1_otherwin;
87 	uint8_t		ptl1_cleanwin;
88 	uint8_t		ptl1_cansave;
89 	uint8_t		ptl1_canrestore;
90 } ptl1_regs_t;
91 
92 typedef struct ptl1_state {
93 	ptl1_regs_t	ptl1_regs;
94 	uint32_t	ptl1_entry_count;
95 	uintptr_t	ptl1_stktop;
96 	ulong_t		ptl1_stk[1];
97 } ptl1_state_t;
98 
99 /*
100  * For cpu_chip and cpu_core in machcpu structure if we cannot get
101  * any chip id or core id information from MD.
102  */
103 #define	CPU_CHIPID_INVALID	-1
104 #define	CPU_COREID_INVALID	-1
105 #define	CPU_L2_CACHEID_INVALID	-1
106 
107 /*
108  * Machine specific fields of the cpu struct
109  * defined in common/sys/cpuvar.h.
110  */
111 struct	machcpu {
112 	struct machpcb	*mpcb;
113 	uint64_t	mpcb_pa;
114 	int		mutex_ready;
115 	int		in_prom;
116 	int		tl1_hdlr;
117 	char		cpu_tstat_flags;	/* tstat flags */
118 	uint16_t	divisor;	/* Estar %tick clock ratio */
119 	uint8_t		intrcnt;	/* number of back-to-back interrupts */
120 	u_longlong_t	tmp1;		/* per-cpu tmps */
121 	u_longlong_t	tmp2;		/*  used in trap processing */
122 	u_longlong_t	tmp3;
123 	u_longlong_t	tmp4;
124 
125 	label_t		*ofd[HIGH_LEVELS];	/* saved pil ofd */
126 	uintptr_t	lfd[HIGH_LEVELS];	/* saved ret PC */
127 	struct on_trap_data *otd[HIGH_LEVELS];	/* saved pil otd */
128 
129 	struct intr_vec	*intr_head[PIL_LEVELS];	/* intr queue heads per pil */
130 	struct intr_vec	*intr_tail[PIL_LEVELS];	/* intr queue tails per pil */
131 	boolean_t	poke_cpu_outstanding;
132 	/*
133 	 * The cpu module allocates a private data structure for the
134 	 * E$ data, which is needed for the specific cpu type.
135 	 */
136 	void		*cpu_private;		/* ptr to cpu private data */
137 	/*
138 	 * per-MMU ctxdom CPU data.
139 	 */
140 	uint_t		cpu_mmu_idx;
141 	struct mmu_ctx	*cpu_mmu_ctxp;
142 
143 	ptl1_state_t	ptl1_state;
144 
145 	uint64_t	pil_high_start[HIGH_LEVELS];	/* high-level intrs */
146 
147 	/*
148 	 * intrstat[][] is used to keep track of ticks used at a given pil
149 	 * level. intrstat[pil][0] is cumulative and exported via kstats.
150 	 * intrstat[pil][1] is used in intr_get_time() and is private.
151 	 * 2-dimensional array improves cache locality.
152 	 */
153 
154 	uint64_t	intrstat[PIL_MAX+1][2];
155 
156 	int		kwbuf_full;
157 	caddr_t		kwbuf_sp;
158 	struct rwindow	kwbuf;
159 
160 	caddr_t		cpu_q_va;	/* cpu intrq base VA */
161 	caddr_t		dev_q_va;	/* dev intrq base VA */
162 	uint64_t	cpu_q_base_pa;	/* cpu intrq base PA */
163 	uint64_t	cpu_q_size;
164 	uint64_t	dev_q_base_pa;	/* dev intrq base PA */
165 	uint64_t	dev_q_size;
166 	caddr_t		cpu_rq_va;	/* resumable Q base VA */
167 	caddr_t		cpu_nrq_va;	/* nonresumable Q base VA */
168 	uint64_t	cpu_rq_base_pa;	/* resumable Q base PA */
169 	uint64_t	cpu_rq_size;	/* resumable Q size */
170 	uint64_t	cpu_nrq_base_pa;	/* nonresumable Q base PA */
171 	uint64_t	cpu_nrq_size;		/* nonresumable Q size */
172 	errh_er_t	*cpu_rq_lastre;		/* most recent RE */
173 	errh_er_t	*cpu_nrq_lastnre;	/* most recent NRE */
174 	caddr_t		mondo_data;		/* send mondo data */
175 	uint64_t	mondo_data_ra;		/* mono data pa */
176 	uint16_t	*cpu_list;		/* uint16_t [NCPU] */
177 	uint64_t	cpu_list_ra;		/* cpu list ra */
178 	id_t		cpu_ipipe;		/* cpu int exec unit id */
179 	id_t		cpu_mpipe;		/* cpu memory pipe id */
180 	id_t		cpu_fpu;		/* cpu fpu unit id */
181 	id_t		cpu_core;		/* cpu core id */
182 	id_t		cpu_chip;		/* cpu chip id */
183 	kthread_t	*startup_thread;
184 };
185 
186 typedef	struct machcpu	machcpu_t;
187 
188 #define	cpu_startup_thread	cpu_m.startup_thread
189 #define	CPU_MMU_IDX(cp)		((cp)->cpu_m.cpu_mmu_idx)
190 #define	CPU_MMU_CTXP(cp)	((cp)->cpu_m.cpu_mmu_ctxp)
191 #define	NINTR_THREADS	(LOCK_LEVEL)	/* number of interrupt threads */
192 
193 /*
194  * Macro to access the "cpu private" data structure.
195  */
196 #define	CPU_PRIVATE(cp)		((cp)->cpu_m.cpu_private)
197 
198 /*
199  * The OpenBoot Standalone Interface supplies the kernel with
200  * implementation dependent parameters through the devinfo/property mechanism
201  */
202 #define	MAXSYSNAME	20
203 
204 /*
205  * Used to indicate busy/idle state of a cpu.
206  * msram field will be set with ECACHE_CPU_MIRROR if we are on
207  * mirrored sram module.
208  */
209 #define	ECACHE_CPU_IDLE		0x0		/* CPU is idle */
210 #define	ECACHE_CPU_BUSY		0x1		/* CPU is busy */
211 #define	ECACHE_CPU_MIRROR 	0x2		/* E$ is mirrored */
212 #define	ECACHE_CPU_NON_MIRROR	0x3		/* E$ is not mirrored */
213 
214 /*
215  * A CPU FRU FMRI string minus the unum component.
216  */
217 #define	CPU_FRU_FMRI		FM_FMRI_SCHEME_HC":///" \
218     FM_FMRI_LEGACY_HC"="
219 
220 struct cpu_node {
221 	char	name[MAXSYSNAME];
222 	char	fru_fmri[sizeof (CPU_FRU_FMRI) + UNUM_NAMLEN];
223 	int	cpuid;
224 	pnode_t	nodeid;
225 	uint64_t	clock_freq;
226 	uint_t	tick_nsec_scale;
227 	union {
228 		int	dummy;
229 	}	u_info;
230 	int	ecache_size;
231 	int	ecache_linesize;
232 	int	ecache_associativity;
233 	int	ecache_setsize;
234 	uint64_t	device_id;
235 	id_t	exec_unit_mapping;
236 	id_t	fpu_mapping;
237 	id_t	l2_cache_mapping;
238 	id_t	core_mapping;
239 };
240 
241 extern struct cpu_node cpunodes[];
242 
243 #endif	/* _ASM */
244 
245 #ifdef	__cplusplus
246 }
247 #endif
248 
249 #endif	/* _SYS_MACHCPUVAR_H */
250