1 /*-
2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2014 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Semihalf
7 * under sponsorship of the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/proc.h>
36 #include <sys/pcpu.h>
37 #include <sys/sbuf.h>
38 #include <sys/smp.h>
39 #include <sys/sysctl.h>
40 #include <sys/sysent.h>
41 #include <sys/systm.h>
42
43 #include <machine/atomic.h>
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/elf.h>
47 #include <machine/md_var.h>
48 #include <machine/undefined.h>
49
50 static MALLOC_DEFINE(M_IDENTCPU, "CPU ID", "arm64 CPU identification memory");
51
52 struct cpu_desc;
53
54 static void print_cpu_midr(struct sbuf *sb, u_int cpu);
55 static void print_cpu_features(u_int cpu, struct cpu_desc *desc,
56 struct cpu_desc *prev_desc);
57 static void print_cpu_caches(struct sbuf *sb, struct cpu_desc *desc);
58 #ifdef COMPAT_FREEBSD32
59 static u_long parse_cpu_features_hwcap32(void);
60 #endif
61
62 const char machine[] = "arm64";
63
64 #ifdef SCTL_MASK32
65 extern int adaptive_machine_arch;
66 #endif
67
68 static SYSCTL_NODE(_machdep, OID_AUTO, cache, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
69 "Cache management tuning");
70
71 static int allow_dic = 1;
72 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_dic, CTLFLAG_RDTUN, &allow_dic, 0,
73 "Allow optimizations based on the DIC cache bit");
74
75 static int allow_idc = 1;
76 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_idc, CTLFLAG_RDTUN, &allow_idc, 0,
77 "Allow optimizations based on the IDC cache bit");
78
79 static void check_cpu_regs(u_int cpu, struct cpu_desc *desc,
80 struct cpu_desc *prev_desc);
81 static uint64_t update_special_reg_field(uint64_t user_reg, u_int type,
82 uint64_t value, u_int width, u_int shift, bool sign);
83
84 /*
85 * The default implementation of I-cache sync assumes we have an
86 * aliasing cache until we know otherwise.
87 */
88 void (*arm64_icache_sync_range)(void *, vm_size_t) =
89 &arm64_aliasing_icache_sync_range;
90
91 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)92 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
93 {
94 #ifdef SCTL_MASK32
95 static const char machine32[] = "arm";
96 #endif
97 int error;
98
99 #ifdef SCTL_MASK32
100 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
101 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
102 else
103 #endif
104 error = SYSCTL_OUT(req, machine, sizeof(machine));
105 return (error);
106 }
107
108 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
109 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A",
110 "Machine class");
111
112 static char cpu_model[64];
113 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
114 cpu_model, sizeof(cpu_model), "Machine model");
115
116 #define MAX_CACHES 8 /* Maximum number of caches supported
117 architecturally. */
118 /*
119 * Per-CPU affinity as provided in MPIDR_EL1
120 * Indexed by CPU number in logical order selected by the system.
121 * Relevant fields can be extracted using CPU_AFFn macros,
122 * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system.
123 *
124 * Fields used by us:
125 * Aff1 - Cluster number
126 * Aff0 - CPU number in Aff1 cluster
127 */
128 uint64_t __cpu_affinity[MAXCPU];
129 static u_int cpu_aff_levels;
130
131 struct cpu_desc {
132 uint64_t mpidr;
133 uint64_t id_aa64afr0;
134 uint64_t id_aa64afr1;
135 uint64_t id_aa64dfr0;
136 uint64_t id_aa64dfr1;
137 uint64_t id_aa64isar0;
138 uint64_t id_aa64isar1;
139 uint64_t id_aa64isar2;
140 uint64_t id_aa64mmfr0;
141 uint64_t id_aa64mmfr1;
142 uint64_t id_aa64mmfr2;
143 uint64_t id_aa64mmfr3;
144 uint64_t id_aa64mmfr4;
145 uint64_t id_aa64pfr0;
146 uint64_t id_aa64pfr1;
147 uint64_t id_aa64pfr2;
148 uint64_t id_aa64zfr0;
149 uint64_t ctr;
150 #ifdef COMPAT_FREEBSD32
151 uint64_t id_isar5;
152 uint64_t mvfr0;
153 uint64_t mvfr1;
154 #endif
155 uint64_t clidr;
156 uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */
157 bool have_sve;
158 };
159
160 static struct cpu_desc cpu_desc0;
161 static struct cpu_desc *cpu_desc;
162 static struct cpu_desc kern_cpu_desc;
163 static struct cpu_desc user_cpu_desc;
164 static struct cpu_desc l_user_cpu_desc;
165
166 static struct cpu_desc *
get_cpu_desc(u_int cpu)167 get_cpu_desc(u_int cpu)
168 {
169 /* The cpu_desc for CPU 0 is used before the allocator is ready. */
170 if (cpu == 0)
171 return (&cpu_desc0);
172
173 MPASS(cpu_desc != NULL);
174 return (&cpu_desc[cpu - 1]);
175 }
176
177 struct cpu_parts {
178 u_int part_id;
179 const char *part_name;
180 };
181 #define CPU_PART_NONE { 0, NULL }
182
183 struct cpu_implementers {
184 u_int impl_id;
185 const char *impl_name;
186 /*
187 * Part number is implementation defined
188 * so each vendor will have its own set of values and names.
189 */
190 const struct cpu_parts *cpu_parts;
191 };
192 #define CPU_IMPLEMENTER_NONE { 0, NULL, NULL }
193
194 /*
195 * Per-implementer table of (PartNum, CPU Name) pairs.
196 */
197 /* ARM Ltd. */
198 static const struct cpu_parts cpu_parts_arm[] = {
199 { CPU_PART_AEM_V8, "AEMv8" },
200 { CPU_PART_FOUNDATION, "Foundation-Model" },
201 { CPU_PART_CORTEX_A34, "Cortex-A34" },
202 { CPU_PART_CORTEX_A35, "Cortex-A35" },
203 { CPU_PART_CORTEX_A53, "Cortex-A53" },
204 { CPU_PART_CORTEX_A55, "Cortex-A55" },
205 { CPU_PART_CORTEX_A57, "Cortex-A57" },
206 { CPU_PART_CORTEX_A65, "Cortex-A65" },
207 { CPU_PART_CORTEX_A65AE, "Cortex-A65AE" },
208 { CPU_PART_CORTEX_A72, "Cortex-A72" },
209 { CPU_PART_CORTEX_A73, "Cortex-A73" },
210 { CPU_PART_CORTEX_A75, "Cortex-A75" },
211 { CPU_PART_CORTEX_A76, "Cortex-A76" },
212 { CPU_PART_CORTEX_A76AE, "Cortex-A76AE" },
213 { CPU_PART_CORTEX_A77, "Cortex-A77" },
214 { CPU_PART_CORTEX_A78, "Cortex-A78" },
215 { CPU_PART_CORTEX_A78C, "Cortex-A78C" },
216 { CPU_PART_CORTEX_A510, "Cortex-A510" },
217 { CPU_PART_CORTEX_A710, "Cortex-A710" },
218 { CPU_PART_CORTEX_A715, "Cortex-A715" },
219 { CPU_PART_CORTEX_X1, "Cortex-X1" },
220 { CPU_PART_CORTEX_X1C, "Cortex-X1C" },
221 { CPU_PART_CORTEX_X2, "Cortex-X2" },
222 { CPU_PART_CORTEX_X3, "Cortex-X3" },
223 { CPU_PART_NEOVERSE_E1, "Neoverse-E1" },
224 { CPU_PART_NEOVERSE_N1, "Neoverse-N1" },
225 { CPU_PART_NEOVERSE_N2, "Neoverse-N2" },
226 { CPU_PART_NEOVERSE_V1, "Neoverse-V1" },
227 { CPU_PART_NEOVERSE_V2, "Neoverse-V2" },
228 CPU_PART_NONE,
229 };
230
231 /* Cavium */
232 static const struct cpu_parts cpu_parts_cavium[] = {
233 { CPU_PART_THUNDERX, "ThunderX" },
234 { CPU_PART_THUNDERX2, "ThunderX2" },
235 CPU_PART_NONE,
236 };
237
238 /* APM / Ampere */
239 static const struct cpu_parts cpu_parts_apm[] = {
240 { CPU_PART_EMAG8180, "eMAG 8180" },
241 CPU_PART_NONE,
242 };
243
244 /* Qualcomm */
245 static const struct cpu_parts cpu_parts_qcom[] = {
246 { CPU_PART_KRYO400_GOLD, "Kryo 400 Gold" },
247 { CPU_PART_KRYO400_SILVER, "Kryo 400 Silver" },
248 CPU_PART_NONE,
249 };
250
251 /* Apple */
252 static const struct cpu_parts cpu_parts_apple[] = {
253 { CPU_PART_M1_ICESTORM, "M1 Icestorm" },
254 { CPU_PART_M1_FIRESTORM, "M1 Firestorm" },
255 { CPU_PART_M1_ICESTORM_PRO, "M1 Pro Icestorm" },
256 { CPU_PART_M1_FIRESTORM_PRO, "M1 Pro Firestorm" },
257 { CPU_PART_M1_ICESTORM_MAX, "M1 Max Icestorm" },
258 { CPU_PART_M1_FIRESTORM_MAX, "M1 Max Firestorm" },
259 { CPU_PART_M2_BLIZZARD, "M2 Blizzard" },
260 { CPU_PART_M2_AVALANCHE, "M2 Avalanche" },
261 { CPU_PART_M2_BLIZZARD_PRO, "M2 Pro Blizzard" },
262 { CPU_PART_M2_AVALANCHE_PRO, "M2 Pro Avalanche" },
263 { CPU_PART_M2_BLIZZARD_MAX, "M2 Max Blizzard" },
264 { CPU_PART_M2_AVALANCHE_MAX, "M2 Max Avalanche" },
265 CPU_PART_NONE,
266 };
267
268 /* Unknown */
269 static const struct cpu_parts cpu_parts_none[] = {
270 CPU_PART_NONE,
271 };
272
273 /*
274 * Implementers table.
275 */
276 const struct cpu_implementers cpu_implementers[] = {
277 { CPU_IMPL_AMPERE, "Ampere", cpu_parts_none },
278 { CPU_IMPL_APPLE, "Apple", cpu_parts_apple },
279 { CPU_IMPL_APM, "APM", cpu_parts_apm },
280 { CPU_IMPL_ARM, "ARM", cpu_parts_arm },
281 { CPU_IMPL_BROADCOM, "Broadcom", cpu_parts_none },
282 { CPU_IMPL_CAVIUM, "Cavium", cpu_parts_cavium },
283 { CPU_IMPL_DEC, "DEC", cpu_parts_none },
284 { CPU_IMPL_FREESCALE, "Freescale", cpu_parts_none },
285 { CPU_IMPL_FUJITSU, "Fujitsu", cpu_parts_none },
286 { CPU_IMPL_INFINEON, "IFX", cpu_parts_none },
287 { CPU_IMPL_INTEL, "Intel", cpu_parts_none },
288 { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none },
289 { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none },
290 { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_qcom },
291 CPU_IMPLEMENTER_NONE,
292 };
293
294 #define MRS_TYPE_MASK 0xf
295 #define MRS_INVALID 0
296 #define MRS_EXACT 1
297 #define MRS_EXACT_IF_DIFFERENT 2
298 #define MRS_LOWER 3
299 #define MRS_HIGHER_OR_ZERO 4
300 #define MRS_HIGHER 5
301 #define MRS_SAFE_SHIFT 4
302 #define MRS_SAFE_MASK (0xfu << MRS_SAFE_SHIFT)
303 #define MRS_SAFE(x) (((x) << MRS_SAFE_SHIFT) & MRS_SAFE_MASK)
304 #define MRS_SAFE_VAL(x) (((x) & MRS_SAFE_MASK) >> MRS_SAFE_SHIFT)
305 #define MRS_FREEBSD (1u << 8)
306 #define MRS_LINUX (1u << 9)
307 #define MRS_USERSPACE (MRS_FREEBSD | MRS_LINUX)
308
309 struct mrs_field_value {
310 uint64_t value;
311 const char *desc;
312 };
313
314 #define MRS_FIELD_VALUE(_value, _desc) \
315 { \
316 .value = (_value), \
317 .desc = (_desc), \
318 }
319
320 #define MRS_FIELD_VALUE_NONE_IMPL(_reg, _field, _none, _impl) \
321 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _none, ""), \
322 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _impl, #_field)
323
324 #define MRS_FIELD_VALUE_COUNT(_reg, _field, _desc) \
325 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, "1 " _desc), \
326 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "2 " _desc "s"), \
327 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "3 " _desc "s"), \
328 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "4 " _desc "s"), \
329 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "5 " _desc "s"), \
330 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "6 " _desc "s"), \
331 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "7 " _desc "s"), \
332 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc "s"), \
333 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "9 " _desc "s"), \
334 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "10 "_desc "s"), \
335 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "11 "_desc "s"), \
336 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "12 "_desc "s"), \
337 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "13 "_desc "s"), \
338 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "14 "_desc "s"), \
339 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "15 "_desc "s"), \
340 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s")
341
342 /*
343 * Used for printing I/D cache line sizes & CWG/ERG, as 0 is a special case
344 * in some cases the decoded string needs to be passed in.
345 */
346 #define MRS_FIELD_VALUE_CACHE(_reg, _field, _0desc, _desc) \
347 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, _0desc), \
348 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc), \
349 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "16 " _desc), \
350 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "32 " _desc), \
351 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "64 " _desc), \
352 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "128 " _desc), \
353 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "256 " _desc), \
354 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "512 " _desc), \
355 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "1k " _desc), \
356 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "2k " _desc), \
357 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "4k " _desc), \
358 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "8k " _desc), \
359 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "16k " _desc), \
360 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "32k " _desc), \
361 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "64k " _desc), \
362 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "128k "_desc)
363
364 #define MRS_FIELD_VALUE_END { .desc = NULL }
365
366 struct mrs_field_hwcap {
367 uint64_t min;
368 u_long hwcap_val;
369 u_int hwcap_id;
370 };
371
372 #define MRS_HWCAP(_hwcap_id, _val, _min) \
373 { \
374 .hwcap_id = (_hwcap_id), \
375 .hwcap_val = (_val), \
376 .min = (_min), \
377 }
378
379 #define MRS_HWCAP_END { .hwcap_id = 0 }
380
381 struct mrs_field {
382 const char *name;
383 const struct mrs_field_value *values;
384 const struct mrs_field_hwcap *hwcaps;
385 uint64_t mask;
386 bool sign;
387 u_int type;
388 u_int width;
389 u_int shift;
390 };
391
392 #define MRS_FIELD_RES1(_width, _shift) \
393 { \
394 .sign = false, \
395 .type = MRS_EXACT | MRS_SAFE((1u << (_width)) - 1) | \
396 MRS_USERSPACE, \
397 .width = (_width), \
398 .shift = (_shift), \
399 }
400
401 #define MRS_FIELD_HWCAP(_register, _name, _sign, _type, _visibility, \
402 _values, _hwcap) \
403 { \
404 .name = #_name, \
405 .sign = (_sign), \
406 .type = ((_type) | (_visibility)), \
407 .width = _register ## _ ## _name ## _WIDTH, \
408 .shift = _register ## _ ## _name ## _SHIFT, \
409 .mask = _register ## _ ## _name ## _MASK, \
410 .values = (_values), \
411 .hwcaps = (_hwcap), \
412 }
413
414 #define MRS_FIELD(_register, _name, _sign, _type, _visibility, _values) \
415 MRS_FIELD_HWCAP(_register, _name, _sign, _type, _visibility, \
416 _values, NULL)
417
418 #define MRS_FIELD_END { .type = MRS_INVALID, }
419
420 /* CTR_EL0 */
421 static const struct mrs_field_value ctr_dic[] = {
422 MRS_FIELD_VALUE_NONE_IMPL(CTR, DIC, NONE, IMPL),
423 MRS_FIELD_VALUE_END,
424 };
425
426 static const struct mrs_field_value ctr_idc[] = {
427 MRS_FIELD_VALUE_NONE_IMPL(CTR, IDC, NONE, IMPL),
428 MRS_FIELD_VALUE_END,
429 };
430
431 static const struct mrs_field_value ctr_cwg[] = {
432 MRS_FIELD_VALUE_CACHE(CTR, CWG, "Unknown CWG",
433 "byte CWG"),
434 MRS_FIELD_VALUE_END,
435 };
436
437 static const struct mrs_field_value ctr_erg[] = {
438 MRS_FIELD_VALUE_CACHE(CTR, ERG, "Unknown ERG",
439 "byte ERG"),
440 MRS_FIELD_VALUE_END,
441 };
442
443 static const struct mrs_field_value ctr_dline[] = {
444 MRS_FIELD_VALUE_CACHE(CTR, DLINE, "4 byte D-cacheline",
445 "byte D-cacheline"),
446 MRS_FIELD_VALUE_END,
447 };
448
449 static const struct mrs_field_value ctr_l1ip[] = {
450 MRS_FIELD_VALUE(CTR_L1IP_VIPT, "VIPT I-cache"),
451 MRS_FIELD_VALUE(CTR_L1IP_PIPT, "PIPT I-cache"),
452 MRS_FIELD_VALUE_END,
453 };
454
455 static const struct mrs_field_value ctr_iline[] = {
456 MRS_FIELD_VALUE_CACHE(CTR, ILINE, "4 byte I-cacheline",
457 "byte I-cacheline"),
458 MRS_FIELD_VALUE_END,
459 };
460
461 static const struct mrs_field ctr_fields[] = {
462 /* Bit 31 is RES1 */
463 MRS_FIELD_RES1(1, 31),
464 MRS_FIELD(CTR, DIC, false, MRS_LOWER, MRS_USERSPACE, ctr_dic),
465 MRS_FIELD(CTR, IDC, false, MRS_LOWER, MRS_USERSPACE, ctr_idc),
466 MRS_FIELD(CTR, CWG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_cwg),
467 MRS_FIELD(CTR, ERG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_erg),
468 MRS_FIELD(CTR, DLINE, false, MRS_LOWER, MRS_USERSPACE, ctr_dline),
469 /* If the ICache types are different report the safe option */
470 MRS_FIELD(CTR, L1IP, false, MRS_EXACT_IF_DIFFERENT |
471 MRS_SAFE(CTR_L1IP_VIPT >> CTR_L1IP_SHIFT), MRS_USERSPACE,
472 ctr_l1ip),
473 MRS_FIELD(CTR, ILINE, false, MRS_LOWER, MRS_USERSPACE, ctr_iline),
474 MRS_FIELD_END,
475 };
476
477 /* ID_AA64AFR0_EL1 */
478 static const struct mrs_field id_aa64afr0_fields[] = {
479 MRS_FIELD_END,
480 };
481
482
483 /* ID_AA64AFR1_EL1 */
484 static const struct mrs_field id_aa64afr1_fields[] = {
485 MRS_FIELD_END,
486 };
487
488
489 /* ID_AA64DFR0_EL1 */
490 static const struct mrs_field_value id_aa64dfr0_hpmn0[] = {
491 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, HPMN0, CONSTR, DEFINED),
492 MRS_FIELD_VALUE_END,
493 };
494
495 static const struct mrs_field_value id_aa64dfr0_brbe[] = {
496 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, BRBE, NONE, IMPL),
497 MRS_FIELD_VALUE(ID_AA64DFR0_BRBE_EL3, "BRBE EL3"),
498 MRS_FIELD_VALUE_END,
499 };
500
501 static const struct mrs_field_value id_aa64dfr0_mtpmu[] = {
502 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, MTPMU, NONE, IMPL),
503 MRS_FIELD_VALUE(ID_AA64DFR0_MTPMU_NONE_MT_RES0, "MTPMU res0"),
504 MRS_FIELD_VALUE_END,
505 };
506
507 static const struct mrs_field_value id_aa64dfr0_tracebuffer[] = {
508 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, TraceBuffer, NONE, IMPL),
509 MRS_FIELD_VALUE_END,
510 };
511
512 static const struct mrs_field_value id_aa64dfr0_tracefilt[] = {
513 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""),
514 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"),
515 MRS_FIELD_VALUE_END,
516 };
517
518 static const struct mrs_field_value id_aa64dfr0_doublelock[] = {
519 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_IMPL, "DoubleLock"),
520 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_NONE, ""),
521 MRS_FIELD_VALUE_END,
522 };
523
524 static const struct mrs_field_value id_aa64dfr0_pmsver[] = {
525 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""),
526 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"),
527 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_1, "SPEv1p1"),
528 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_2, "SPEv1p2"),
529 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_3, "SPEv1p3"),
530 MRS_FIELD_VALUE_END,
531 };
532
533 static const struct mrs_field_value id_aa64dfr0_ctx_cmps[] = {
534 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, CTX_CMPs, "CTX BKPT"),
535 MRS_FIELD_VALUE_END,
536 };
537
538 static const struct mrs_field_value id_aa64dfr0_wrps[] = {
539 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, WRPs, "Watchpoint"),
540 MRS_FIELD_VALUE_END,
541 };
542
543 static const struct mrs_field_value id_aa64dfr0_brps[] = {
544 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, BRPs, "Breakpoint"),
545 MRS_FIELD_VALUE_END,
546 };
547
548 static const struct mrs_field_value id_aa64dfr0_pmuver[] = {
549 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""),
550 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"),
551 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3p1"),
552 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3p4"),
553 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3p5"),
554 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_7, "PMUv3p7"),
555 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_8, "PMUv3p8"),
556 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"),
557 MRS_FIELD_VALUE_END,
558 };
559
560 static const struct mrs_field_value id_aa64dfr0_tracever[] = {
561 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_NONE, ""),
562 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_IMPL, "Trace"),
563 MRS_FIELD_VALUE_END,
564 };
565
566 static const struct mrs_field_value id_aa64dfr0_debugver[] = {
567 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"),
568 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"),
569 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8p2"),
570 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8p4"),
571 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_8, "Debugv8p8"),
572 MRS_FIELD_VALUE_END,
573 };
574
575 static const struct mrs_field id_aa64dfr0_fields[] = {
576 MRS_FIELD(ID_AA64DFR0, HPMN0, false, MRS_LOWER, 0, id_aa64dfr0_hpmn0),
577 MRS_FIELD(ID_AA64DFR0, BRBE, false, MRS_LOWER, 0, id_aa64dfr0_brbe),
578 MRS_FIELD(ID_AA64DFR0, MTPMU, true, MRS_LOWER, 0, id_aa64dfr0_mtpmu),
579 MRS_FIELD(ID_AA64DFR0, TraceBuffer, false, MRS_LOWER, 0,
580 id_aa64dfr0_tracebuffer),
581 MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_LOWER, 0,
582 id_aa64dfr0_tracefilt),
583 MRS_FIELD(ID_AA64DFR0, DoubleLock, false, MRS_LOWER, 0,
584 id_aa64dfr0_doublelock),
585 MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_LOWER, 0, id_aa64dfr0_pmsver),
586 MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_LOWER, 0,
587 id_aa64dfr0_ctx_cmps),
588 MRS_FIELD(ID_AA64DFR0, WRPs, false, MRS_LOWER, MRS_USERSPACE,
589 id_aa64dfr0_wrps),
590 MRS_FIELD(ID_AA64DFR0, BRPs, false, MRS_LOWER, MRS_USERSPACE,
591 id_aa64dfr0_brps),
592 MRS_FIELD(ID_AA64DFR0, PMUVer, false, MRS_LOWER, 0, id_aa64dfr0_pmuver),
593 MRS_FIELD(ID_AA64DFR0, TraceVer, false, MRS_LOWER, 0,
594 id_aa64dfr0_tracever),
595 MRS_FIELD(ID_AA64DFR0, DebugVer, false, MRS_LOWER | MRS_SAFE(0x6), 0,
596 id_aa64dfr0_debugver),
597 MRS_FIELD_END,
598 };
599
600
601 /* ID_AA64DFR1_EL1 */
602 static const struct mrs_field id_aa64dfr1_fields[] = {
603 MRS_FIELD_END,
604 };
605
606
607 /* ID_AA64ISAR0_EL1 */
608 static const struct mrs_field_value id_aa64isar0_rndr[] = {
609 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""),
610 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"),
611 MRS_FIELD_VALUE_END,
612 };
613
614 static const struct mrs_field_hwcap id_aa64isar0_rndr_caps[] = {
615 MRS_HWCAP(2, HWCAP2_RNG, ID_AA64ISAR0_RNDR_IMPL),
616 MRS_HWCAP_END
617 };
618
619 static const struct mrs_field_value id_aa64isar0_tlb[] = {
620 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""),
621 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOS, "TLBI-OS"),
622 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOSR, "TLBI-OSR"),
623 MRS_FIELD_VALUE_END,
624 };
625
626 static const struct mrs_field_value id_aa64isar0_ts[] = {
627 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""),
628 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_4, "CondM-8.4"),
629 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_5, "CondM-8.5"),
630 MRS_FIELD_VALUE_END,
631 };
632
633 static const struct mrs_field_hwcap id_aa64isar0_ts_caps[] = {
634 MRS_HWCAP(1, HWCAP_FLAGM, ID_AA64ISAR0_TS_CondM_8_4),
635 MRS_HWCAP(2, HWCAP2_FLAGM2, ID_AA64ISAR0_TS_CondM_8_5),
636 MRS_HWCAP_END
637 };
638
639 static const struct mrs_field_value id_aa64isar0_fhm[] = {
640 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL),
641 MRS_FIELD_VALUE_END,
642 };
643
644 static const struct mrs_field_hwcap id_aa64isar0_fhm_caps[] = {
645 MRS_HWCAP(1, HWCAP_ASIMDFHM, ID_AA64ISAR0_FHM_IMPL),
646 MRS_HWCAP_END
647 };
648
649 static const struct mrs_field_value id_aa64isar0_dp[] = {
650 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL),
651 MRS_FIELD_VALUE_END,
652 };
653
654 static const struct mrs_field_hwcap id_aa64isar0_dp_caps[] = {
655 MRS_HWCAP(1, HWCAP_ASIMDDP, ID_AA64ISAR0_DP_IMPL),
656 MRS_HWCAP_END
657 };
658
659 static const struct mrs_field_value id_aa64isar0_sm4[] = {
660 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL),
661 MRS_FIELD_VALUE_END,
662 };
663
664 static const struct mrs_field_hwcap id_aa64isar0_sm4_caps[] = {
665 MRS_HWCAP(1, HWCAP_SM4, ID_AA64ISAR0_SM4_IMPL),
666 MRS_HWCAP_END
667 };
668
669 static const struct mrs_field_value id_aa64isar0_sm3[] = {
670 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM3, NONE, IMPL),
671 MRS_FIELD_VALUE_END,
672 };
673
674 static const struct mrs_field_hwcap id_aa64isar0_sm3_caps[] = {
675 MRS_HWCAP(1, HWCAP_SM3, ID_AA64ISAR0_SM3_IMPL),
676 MRS_HWCAP_END
677 };
678
679 static const struct mrs_field_value id_aa64isar0_sha3[] = {
680 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA3, NONE, IMPL),
681 MRS_FIELD_VALUE_END,
682 };
683
684 static const struct mrs_field_hwcap id_aa64isar0_sha3_caps[] = {
685 MRS_HWCAP(1, HWCAP_SHA3, ID_AA64ISAR0_SHA3_IMPL),
686 MRS_HWCAP_END
687 };
688
689 static const struct mrs_field_value id_aa64isar0_rdm[] = {
690 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, RDM, NONE, IMPL),
691 MRS_FIELD_VALUE_END,
692 };
693
694 static const struct mrs_field_hwcap id_aa64isar0_rdm_caps[] = {
695 MRS_HWCAP(1, HWCAP_ASIMDRDM, ID_AA64ISAR0_RDM_IMPL),
696 MRS_HWCAP_END
697 };
698
699 static const struct mrs_field_value id_aa64isar0_tme[] = {
700 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, TME, NONE, IMPL),
701 MRS_FIELD_VALUE_END,
702 };
703
704 static const struct mrs_field_value id_aa64isar0_atomic[] = {
705 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, Atomic, NONE, IMPL),
706 MRS_FIELD_VALUE_END,
707 };
708
709 static const struct mrs_field_hwcap id_aa64isar0_atomic_caps[] = {
710 MRS_HWCAP(1, HWCAP_ATOMICS, ID_AA64ISAR0_Atomic_IMPL),
711 MRS_HWCAP_END
712 };
713
714 static const struct mrs_field_value id_aa64isar0_crc32[] = {
715 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, CRC32, NONE, BASE),
716 MRS_FIELD_VALUE_END,
717 };
718
719 static const struct mrs_field_hwcap id_aa64isar0_crc32_caps[] = {
720 MRS_HWCAP(1, HWCAP_CRC32, ID_AA64ISAR0_CRC32_BASE),
721 MRS_HWCAP_END
722 };
723
724 static const struct mrs_field_value id_aa64isar0_sha2[] = {
725 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA2, NONE, BASE),
726 MRS_FIELD_VALUE(ID_AA64ISAR0_SHA2_512, "SHA2+SHA512"),
727 MRS_FIELD_VALUE_END,
728 };
729
730 static const struct mrs_field_hwcap id_aa64isar0_sha2_caps[] = {
731 MRS_HWCAP(1, HWCAP_SHA2, ID_AA64ISAR0_SHA2_BASE),
732 MRS_HWCAP(1, HWCAP_SHA512, ID_AA64ISAR0_SHA2_512),
733 MRS_HWCAP_END
734 };
735
736 static const struct mrs_field_value id_aa64isar0_sha1[] = {
737 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA1, NONE, BASE),
738 MRS_FIELD_VALUE_END,
739 };
740
741 static const struct mrs_field_hwcap id_aa64isar0_sha1_caps[] = {
742 MRS_HWCAP(1, HWCAP_SHA1, ID_AA64ISAR0_SHA1_BASE),
743 MRS_HWCAP_END
744 };
745
746 static const struct mrs_field_value id_aa64isar0_aes[] = {
747 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE),
748 MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"),
749 MRS_FIELD_VALUE_END,
750 };
751
752 static const struct mrs_field_hwcap id_aa64isar0_aes_caps[] = {
753 MRS_HWCAP(1, HWCAP_AES, ID_AA64ISAR0_AES_BASE),
754 MRS_HWCAP(1, HWCAP_PMULL, ID_AA64ISAR0_AES_PMULL),
755 MRS_HWCAP_END
756 };
757
758 static const struct mrs_field id_aa64isar0_fields[] = {
759 MRS_FIELD_HWCAP(ID_AA64ISAR0, RNDR, false, MRS_LOWER, MRS_USERSPACE,
760 id_aa64isar0_rndr, id_aa64isar0_rndr_caps),
761 MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_LOWER, 0, id_aa64isar0_tlb),
762 MRS_FIELD_HWCAP(ID_AA64ISAR0, TS, false, MRS_LOWER, MRS_USERSPACE,
763 id_aa64isar0_ts, id_aa64isar0_ts_caps),
764 MRS_FIELD_HWCAP(ID_AA64ISAR0, FHM, false, MRS_LOWER, MRS_USERSPACE,
765 id_aa64isar0_fhm, id_aa64isar0_fhm_caps),
766 MRS_FIELD_HWCAP(ID_AA64ISAR0, DP, false, MRS_LOWER, MRS_USERSPACE,
767 id_aa64isar0_dp, id_aa64isar0_dp_caps),
768 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM4, false, MRS_LOWER, MRS_USERSPACE,
769 id_aa64isar0_sm4, id_aa64isar0_sm4_caps),
770 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM3, false, MRS_LOWER, MRS_USERSPACE,
771 id_aa64isar0_sm3, id_aa64isar0_sm3_caps),
772 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA3, false, MRS_LOWER, MRS_USERSPACE,
773 id_aa64isar0_sha3, id_aa64isar0_sha3_caps),
774 MRS_FIELD_HWCAP(ID_AA64ISAR0, RDM, false, MRS_LOWER, MRS_USERSPACE,
775 id_aa64isar0_rdm, id_aa64isar0_rdm_caps),
776 MRS_FIELD(ID_AA64ISAR0, TME, false, MRS_LOWER, 0, id_aa64isar0_tme),
777 MRS_FIELD_HWCAP(ID_AA64ISAR0, Atomic, false, MRS_LOWER, MRS_USERSPACE,
778 id_aa64isar0_atomic, id_aa64isar0_atomic_caps),
779 MRS_FIELD_HWCAP(ID_AA64ISAR0, CRC32, false, MRS_LOWER, MRS_USERSPACE,
780 id_aa64isar0_crc32, id_aa64isar0_crc32_caps),
781 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA2, false, MRS_LOWER, MRS_USERSPACE,
782 id_aa64isar0_sha2, id_aa64isar0_sha2_caps),
783 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA1, false, MRS_LOWER, MRS_USERSPACE,
784 id_aa64isar0_sha1, id_aa64isar0_sha1_caps),
785 MRS_FIELD_HWCAP(ID_AA64ISAR0, AES, false, MRS_LOWER, MRS_USERSPACE,
786 id_aa64isar0_aes, id_aa64isar0_aes_caps),
787 MRS_FIELD_END,
788 };
789
790
791 /* ID_AA64ISAR1_EL1 */
792 static const struct mrs_field_value id_aa64isar1_ls64[] = {
793 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LS64, NONE, IMPL),
794 MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_V, "LS64v"),
795 MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_ACCDATA, "LS64+ACCDATA"),
796 MRS_FIELD_VALUE_END,
797 };
798
799 static const struct mrs_field_value id_aa64isar1_xs[] = {
800 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, XS, NONE, IMPL),
801 MRS_FIELD_VALUE_END,
802 };
803
804 static const struct mrs_field_value id_aa64isar1_i8mm[] = {
805 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
806 MRS_FIELD_VALUE_END,
807 };
808
809 static const struct mrs_field_hwcap id_aa64isar1_i8mm_caps[] = {
810 MRS_HWCAP(2, HWCAP2_I8MM, ID_AA64ISAR1_I8MM_IMPL),
811 MRS_HWCAP_END
812 };
813
814 static const struct mrs_field_value id_aa64isar1_dgh[] = {
815 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL),
816 MRS_FIELD_VALUE_END,
817 };
818
819 static const struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = {
820 MRS_HWCAP(2, HWCAP2_DGH, ID_AA64ISAR1_DGH_IMPL),
821 MRS_HWCAP_END
822 };
823
824 static const struct mrs_field_value id_aa64isar1_bf16[] = {
825 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
826 MRS_FIELD_VALUE(ID_AA64ISAR1_BF16_EBF, "EBF16"),
827 MRS_FIELD_VALUE_END,
828 };
829
830 static const struct mrs_field_hwcap id_aa64isar1_bf16_caps[] = {
831 MRS_HWCAP(2, HWCAP2_BF16, ID_AA64ISAR1_BF16_IMPL),
832 MRS_HWCAP_END
833 };
834
835 static const struct mrs_field_value id_aa64isar1_specres[] = {
836 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""),
837 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_IMPL, "PredInv"),
838 MRS_FIELD_VALUE_END,
839 };
840
841 static const struct mrs_field_value id_aa64isar1_sb[] = {
842 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL),
843 MRS_FIELD_VALUE_END,
844 };
845
846 static const struct mrs_field_hwcap id_aa64isar1_sb_caps[] = {
847 MRS_HWCAP(1, HWCAP_SB, ID_AA64ISAR1_SB_IMPL),
848 MRS_HWCAP_END
849 };
850
851 static const struct mrs_field_value id_aa64isar1_frintts[] = {
852 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL),
853 MRS_FIELD_VALUE_END,
854 };
855
856 static const struct mrs_field_hwcap id_aa64isar1_frintts_caps[] = {
857 MRS_HWCAP(2, HWCAP2_FRINT, ID_AA64ISAR1_FRINTTS_IMPL),
858 MRS_HWCAP_END
859 };
860
861 static const struct mrs_field_value id_aa64isar1_gpi[] = {
862 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL),
863 MRS_FIELD_VALUE_END,
864 };
865
866 static const struct mrs_field_hwcap id_aa64isar1_gpi_caps[] = {
867 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR1_GPI_IMPL),
868 MRS_HWCAP_END
869 };
870
871 static const struct mrs_field_value id_aa64isar1_gpa[] = {
872 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL),
873 MRS_FIELD_VALUE_END,
874 };
875
876 static const struct mrs_field_hwcap id_aa64isar1_gpa_caps[] = {
877 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR1_GPA_IMPL),
878 MRS_HWCAP_END
879 };
880
881 static const struct mrs_field_value id_aa64isar1_lrcpc[] = {
882 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_NONE, ""),
883 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_3, "RCPC-8.3"),
884 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_4, "RCPC-8.4"),
885 MRS_FIELD_VALUE_END,
886 };
887
888 static const struct mrs_field_hwcap id_aa64isar1_lrcpc_caps[] = {
889 MRS_HWCAP(1, HWCAP_LRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_3),
890 MRS_HWCAP(1, HWCAP_ILRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_4),
891 MRS_HWCAP_END
892 };
893
894 static const struct mrs_field_value id_aa64isar1_fcma[] = {
895 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL),
896 MRS_FIELD_VALUE_END,
897 };
898
899 static const struct mrs_field_hwcap id_aa64isar1_fcma_caps[] = {
900 MRS_HWCAP(1, HWCAP_FCMA, ID_AA64ISAR1_FCMA_IMPL),
901 MRS_HWCAP_END
902 };
903
904 static const struct mrs_field_value id_aa64isar1_jscvt[] = {
905 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL),
906 MRS_FIELD_VALUE_END,
907 };
908
909 static const struct mrs_field_hwcap id_aa64isar1_jscvt_caps[] = {
910 MRS_HWCAP(1, HWCAP_JSCVT, ID_AA64ISAR1_JSCVT_IMPL),
911 MRS_HWCAP_END
912 };
913
914 static const struct mrs_field_value id_aa64isar1_api[] = {
915 MRS_FIELD_VALUE(ID_AA64ISAR1_API_NONE, ""),
916 MRS_FIELD_VALUE(ID_AA64ISAR1_API_PAC, "API PAC"),
917 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC, "API EPAC"),
918 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC2, "Impl PAuth+EPAC2"),
919 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC, "Impl PAuth+FPAC"),
920 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC_COMBINED,
921 "Impl PAuth+FPAC+Combined"),
922 MRS_FIELD_VALUE_END,
923 };
924
925 static const struct mrs_field_hwcap id_aa64isar1_api_caps[] = {
926 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR1_API_PAC),
927 MRS_HWCAP_END
928 };
929
930 static const struct mrs_field_value id_aa64isar1_apa[] = {
931 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""),
932 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"),
933 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"),
934 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "APA EPAC2"),
935 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "APA FPAC"),
936 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED,
937 "APA FPAC+Combined"),
938 MRS_FIELD_VALUE_END,
939 };
940
941 static const struct mrs_field_hwcap id_aa64isar1_apa_caps[] = {
942 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR1_APA_PAC),
943 MRS_HWCAP_END
944 };
945
946 static const struct mrs_field_value id_aa64isar1_dpb[] = {
947 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""),
948 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"),
949 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"),
950 MRS_FIELD_VALUE_END,
951 };
952
953 static const struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = {
954 MRS_HWCAP(1, HWCAP_DCPOP, ID_AA64ISAR1_DPB_DCCVAP),
955 MRS_HWCAP(2, HWCAP2_DCPODP, ID_AA64ISAR1_DPB_DCCVADP),
956 MRS_HWCAP_END
957 };
958
959 static const struct mrs_field id_aa64isar1_fields[] = {
960 MRS_FIELD(ID_AA64ISAR1, LS64, false, MRS_LOWER, 0, id_aa64isar1_ls64),
961 MRS_FIELD(ID_AA64ISAR1, XS, false, MRS_LOWER, 0, id_aa64isar1_xs),
962 MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, MRS_USERSPACE,
963 id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps),
964 MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, MRS_USERSPACE,
965 id_aa64isar1_dgh, id_aa64isar1_dgh_caps),
966 MRS_FIELD_HWCAP(ID_AA64ISAR1, BF16, false, MRS_LOWER, MRS_USERSPACE,
967 id_aa64isar1_bf16, id_aa64isar1_bf16_caps),
968 MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_LOWER, 0,
969 id_aa64isar1_specres),
970 MRS_FIELD_HWCAP(ID_AA64ISAR1, SB, false, MRS_LOWER, MRS_USERSPACE,
971 id_aa64isar1_sb, id_aa64isar1_sb_caps),
972 MRS_FIELD_HWCAP(ID_AA64ISAR1, FRINTTS, false, MRS_LOWER, MRS_USERSPACE,
973 id_aa64isar1_frintts, id_aa64isar1_frintts_caps),
974 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPI, false, MRS_LOWER, 0,
975 id_aa64isar1_gpi, id_aa64isar1_gpi_caps),
976 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPA, false, MRS_LOWER, 0,
977 id_aa64isar1_gpa, id_aa64isar1_gpa_caps),
978 MRS_FIELD_HWCAP(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, MRS_USERSPACE,
979 id_aa64isar1_lrcpc, id_aa64isar1_lrcpc_caps),
980 MRS_FIELD_HWCAP(ID_AA64ISAR1, FCMA, false, MRS_LOWER, MRS_USERSPACE,
981 id_aa64isar1_fcma, id_aa64isar1_fcma_caps),
982 MRS_FIELD_HWCAP(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, MRS_USERSPACE,
983 id_aa64isar1_jscvt, id_aa64isar1_jscvt_caps),
984 MRS_FIELD_HWCAP(ID_AA64ISAR1, API, false, MRS_LOWER, 0,
985 id_aa64isar1_api, id_aa64isar1_api_caps),
986 MRS_FIELD_HWCAP(ID_AA64ISAR1, APA, false, MRS_LOWER, 0,
987 id_aa64isar1_apa, id_aa64isar1_apa_caps),
988 MRS_FIELD_HWCAP(ID_AA64ISAR1, DPB, false, MRS_LOWER, MRS_USERSPACE,
989 id_aa64isar1_dpb, id_aa64isar1_dpb_caps),
990 MRS_FIELD_END,
991 };
992
993
994 /* ID_AA64ISAR2_EL1 */
995 static const struct mrs_field_value id_aa64isar2_pac_frac[] = {
996 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PAC_frac, NONE, IMPL),
997 MRS_FIELD_VALUE_END,
998 };
999
1000 static const struct mrs_field_value id_aa64isar2_bc[] = {
1001 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, BC, NONE, IMPL),
1002 MRS_FIELD_VALUE_END,
1003 };
1004
1005 static const struct mrs_field_value id_aa64isar2_mops[] = {
1006 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, MOPS, NONE, IMPL),
1007 MRS_FIELD_VALUE_END,
1008 };
1009
1010 static const struct mrs_field_value id_aa64isar2_apa3[] = {
1011 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_NONE, ""),
1012 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_PAC, "APA3 PAC"),
1013 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC, "APA3 EPAC"),
1014 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC2, "APA3 EPAC2"),
1015 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC, "APA3 FPAC"),
1016 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC_COMBINED,
1017 "APA3 FPAC+Combined"),
1018 MRS_FIELD_VALUE_END,
1019 };
1020
1021 static const struct mrs_field_hwcap id_aa64isar2_apa3_caps[] = {
1022 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR2_APA3_PAC),
1023 MRS_HWCAP_END
1024 };
1025
1026 static const struct mrs_field_value id_aa64isar2_gpa3[] = {
1027 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, GPA3, NONE, IMPL),
1028 MRS_FIELD_VALUE_END,
1029 };
1030
1031 static const struct mrs_field_hwcap id_aa64isar2_gpa3_caps[] = {
1032 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR2_GPA3_IMPL),
1033 MRS_HWCAP_END
1034 };
1035
1036 static const struct mrs_field_value id_aa64isar2_rpres[] = {
1037 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRES, NONE, IMPL),
1038 MRS_FIELD_VALUE_END,
1039 };
1040
1041 static const struct mrs_field_hwcap id_aa64isar2_rpres_caps[] = {
1042 MRS_HWCAP(2, HWCAP2_RPRES, ID_AA64ISAR2_RPRES_IMPL),
1043 MRS_HWCAP_END
1044 };
1045
1046 static const struct mrs_field_value id_aa64isar2_wfxt[] = {
1047 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, WFxT, NONE, IMPL),
1048 MRS_FIELD_VALUE_END,
1049 };
1050
1051 static const struct mrs_field id_aa64isar2_fields[] = {
1052 MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_LOWER, 0,
1053 id_aa64isar2_pac_frac),
1054 MRS_FIELD(ID_AA64ISAR2, BC, false, MRS_LOWER, 0, id_aa64isar2_bc),
1055 MRS_FIELD(ID_AA64ISAR2, MOPS, false, MRS_LOWER, 0, id_aa64isar2_mops),
1056 MRS_FIELD_HWCAP(ID_AA64ISAR2, APA3, false, MRS_LOWER, 0,
1057 id_aa64isar2_apa3, id_aa64isar2_apa3_caps),
1058 MRS_FIELD_HWCAP(ID_AA64ISAR2, GPA3, false, MRS_LOWER, 0,
1059 id_aa64isar2_gpa3, id_aa64isar2_gpa3_caps),
1060 MRS_FIELD_HWCAP(ID_AA64ISAR2, RPRES, false, MRS_LOWER, MRS_USERSPACE,
1061 id_aa64isar2_rpres, id_aa64isar2_rpres_caps),
1062 MRS_FIELD(ID_AA64ISAR2, WFxT, false, MRS_LOWER, 0, id_aa64isar2_wfxt),
1063 MRS_FIELD_END,
1064 };
1065
1066
1067 /* ID_AA64MMFR0_EL1 */
1068 static const struct mrs_field_value id_aa64mmfr0_ecv[] = {
1069 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ECV, NONE, IMPL),
1070 MRS_FIELD_VALUE(ID_AA64MMFR0_ECV_CNTHCTL, "ECV+CNTHCTL"),
1071 MRS_FIELD_VALUE_END,
1072 };
1073
1074 static const struct mrs_field_value id_aa64mmfr0_fgt[] = {
1075 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, FGT, NONE, IMPL),
1076 MRS_FIELD_VALUE_END,
1077 };
1078
1079 static const struct mrs_field_value id_aa64mmfr0_exs[] = {
1080 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
1081 MRS_FIELD_VALUE_END,
1082 };
1083
1084 static const struct mrs_field_value id_aa64mmfr0_tgran4_2[] = {
1085 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""),
1086 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"),
1087 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"),
1088 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_LPA2, "S2 TGran4+LPA2"),
1089 MRS_FIELD_VALUE_END,
1090 };
1091
1092 static const struct mrs_field_value id_aa64mmfr0_tgran64_2[] = {
1093 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_TGran64, ""),
1094 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_NONE, "No S2 TGran64"),
1095 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_IMPL, "S2 TGran64"),
1096 MRS_FIELD_VALUE_END,
1097 };
1098
1099 static const struct mrs_field_value id_aa64mmfr0_tgran16_2[] = {
1100 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""),
1101 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"),
1102 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"),
1103 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_LPA2, "S2 TGran16+LPA2"),
1104 MRS_FIELD_VALUE_END,
1105 };
1106
1107 static const struct mrs_field_value id_aa64mmfr0_tgran4[] = {
1108 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
1109 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_LPA2, "TGran4+LPA2"),
1110 MRS_FIELD_VALUE_END,
1111 };
1112
1113 static const struct mrs_field_value id_aa64mmfr0_tgran64[] = {
1114 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran64, NONE, IMPL),
1115 MRS_FIELD_VALUE_END,
1116 };
1117
1118 static const struct mrs_field_value id_aa64mmfr0_tgran16[] = {
1119 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL),
1120 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_LPA2, "TGran16+LPA2"),
1121 MRS_FIELD_VALUE_END,
1122 };
1123
1124 static const struct mrs_field_value id_aa64mmfr0_bigendel0[] = {
1125 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEndEL0, FIXED, MIXED),
1126 MRS_FIELD_VALUE_END,
1127 };
1128
1129 static const struct mrs_field_value id_aa64mmfr0_snsmem[] = {
1130 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, SNSMem, NONE, DISTINCT),
1131 MRS_FIELD_VALUE_END,
1132 };
1133
1134 static const struct mrs_field_value id_aa64mmfr0_bigend[] = {
1135 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEnd, FIXED, MIXED),
1136 MRS_FIELD_VALUE_END,
1137 };
1138
1139 static const struct mrs_field_value id_aa64mmfr0_asidbits[] = {
1140 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_8, "8bit ASID"),
1141 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_16, "16bit ASID"),
1142 MRS_FIELD_VALUE_END,
1143 };
1144
1145 static const struct mrs_field_value id_aa64mmfr0_parange[] = {
1146 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4G, "4GB PA"),
1147 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_64G, "64GB PA"),
1148 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_1T, "1TB PA"),
1149 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4T, "4TB PA"),
1150 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_16T, "16TB PA"),
1151 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_256T, "256TB PA"),
1152 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4P, "4PB PA"),
1153 MRS_FIELD_VALUE_END,
1154 };
1155
1156 static const struct mrs_field id_aa64mmfr0_fields[] = {
1157 MRS_FIELD(ID_AA64MMFR0, ECV, false, MRS_LOWER, 0, id_aa64mmfr0_ecv),
1158 MRS_FIELD(ID_AA64MMFR0, FGT, false, MRS_LOWER, 0, id_aa64mmfr0_fgt),
1159 MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_LOWER, 0, id_aa64mmfr0_exs),
1160 MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_LOWER, 0,
1161 id_aa64mmfr0_tgran4_2),
1162 MRS_FIELD(ID_AA64MMFR0, TGran64_2, false, MRS_LOWER, 0,
1163 id_aa64mmfr0_tgran64_2),
1164 MRS_FIELD(ID_AA64MMFR0, TGran16_2, false, MRS_LOWER, 0,
1165 id_aa64mmfr0_tgran16_2),
1166 MRS_FIELD(ID_AA64MMFR0, TGran4, false, MRS_LOWER, 0,
1167 id_aa64mmfr0_tgran4),
1168 MRS_FIELD(ID_AA64MMFR0, TGran64, false, MRS_LOWER, 0,
1169 id_aa64mmfr0_tgran64),
1170 MRS_FIELD(ID_AA64MMFR0, TGran16, false, MRS_LOWER, 0,
1171 id_aa64mmfr0_tgran16),
1172 MRS_FIELD(ID_AA64MMFR0, BigEndEL0, false, MRS_LOWER, 0,
1173 id_aa64mmfr0_bigendel0),
1174 MRS_FIELD(ID_AA64MMFR0, SNSMem, false, MRS_LOWER, 0,
1175 id_aa64mmfr0_snsmem),
1176 MRS_FIELD(ID_AA64MMFR0, BigEnd, false, MRS_LOWER, 0,
1177 id_aa64mmfr0_bigend),
1178 MRS_FIELD(ID_AA64MMFR0, ASIDBits, false, MRS_LOWER, 0,
1179 id_aa64mmfr0_asidbits),
1180 MRS_FIELD(ID_AA64MMFR0, PARange, false, MRS_LOWER, 0,
1181 id_aa64mmfr0_parange),
1182 MRS_FIELD_END,
1183 };
1184
1185
1186 /* ID_AA64MMFR1_EL1 */
1187 static const struct mrs_field_value id_aa64mmfr1_cmovw[] = {
1188 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, CMOVW, NONE, IMPL),
1189 MRS_FIELD_VALUE_END,
1190 };
1191
1192 static const struct mrs_field_value id_aa64mmfr1_tidcp1[] = {
1193 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TIDCP1, NONE, IMPL),
1194 MRS_FIELD_VALUE_END,
1195 };
1196
1197 static const struct mrs_field_value id_aa64mmfr1_ntlbpa[] = {
1198 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, nTLBPA, NONE, IMPL),
1199 MRS_FIELD_VALUE_END,
1200 };
1201
1202 static const struct mrs_field_value id_aa64mmfr1_afp[] = {
1203 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, AFP, NONE, IMPL),
1204 MRS_FIELD_VALUE_END,
1205 };
1206
1207 static const struct mrs_field_hwcap id_aa64mmfr1_afp_caps[] = {
1208 MRS_HWCAP(2, HWCAP2_AFP, ID_AA64MMFR1_AFP_IMPL),
1209 MRS_HWCAP_END
1210 };
1211
1212 static const struct mrs_field_value id_aa64mmfr1_hcx[] = {
1213 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, HCX, NONE, IMPL),
1214 MRS_FIELD_VALUE_END,
1215 };
1216
1217 static const struct mrs_field_value id_aa64mmfr1_ets[] = {
1218 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, ETS, NONE, IMPL),
1219 MRS_FIELD_VALUE_END,
1220 };
1221
1222 static const struct mrs_field_value id_aa64mmfr1_twed[] = {
1223 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TWED, NONE, IMPL),
1224 MRS_FIELD_VALUE_END,
1225 };
1226
1227 static const struct mrs_field_value id_aa64mmfr1_xnx[] = {
1228 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL),
1229 MRS_FIELD_VALUE_END,
1230 };
1231
1232 static const struct mrs_field_value id_aa64mmfr1_specsei[] = {
1233 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, SpecSEI, NONE, IMPL),
1234 MRS_FIELD_VALUE_END,
1235 };
1236
1237 static const struct mrs_field_value id_aa64mmfr1_pan[] = {
1238 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, PAN, NONE, IMPL),
1239 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_ATS1E1, "PAN+ATS1E1"),
1240 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_EPAN, "EPAN"),
1241 MRS_FIELD_VALUE_END,
1242 };
1243
1244 static const struct mrs_field_value id_aa64mmfr1_lo[] = {
1245 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, LO, NONE, IMPL),
1246 MRS_FIELD_VALUE_END,
1247 };
1248
1249 static const struct mrs_field_value id_aa64mmfr1_hpds[] = {
1250 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_NONE, ""),
1251 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_HPD, "HPD"),
1252 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_TTPBHA, "HPD+TTPBHA"),
1253 MRS_FIELD_VALUE_END,
1254 };
1255
1256 static const struct mrs_field_value id_aa64mmfr1_vh[] = {
1257 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, VH, NONE, IMPL),
1258 MRS_FIELD_VALUE_END,
1259 };
1260
1261 static const struct mrs_field_value id_aa64mmfr1_vmidbits[] = {
1262 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_8, "8bit VMID"),
1263 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_16, "16bit VMID"),
1264 MRS_FIELD_VALUE_END,
1265 };
1266
1267 static const struct mrs_field_value id_aa64mmfr1_hafdbs[] = {
1268 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_NONE, ""),
1269 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF, "HAF"),
1270 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF_DBS, "HAF+DS"),
1271 MRS_FIELD_VALUE_END,
1272 };
1273
1274 static const struct mrs_field id_aa64mmfr1_fields[] = {
1275 MRS_FIELD(ID_AA64MMFR1, CMOVW, false, MRS_LOWER, 0, id_aa64mmfr1_cmovw),
1276 MRS_FIELD(ID_AA64MMFR1, TIDCP1, false, MRS_LOWER, 0,
1277 id_aa64mmfr1_tidcp1),
1278 MRS_FIELD(ID_AA64MMFR1, nTLBPA, false, MRS_LOWER, 0,
1279 id_aa64mmfr1_ntlbpa),
1280 MRS_FIELD_HWCAP(ID_AA64MMFR1, AFP, false, MRS_LOWER, 0,
1281 id_aa64mmfr1_afp, id_aa64mmfr1_afp_caps),
1282 MRS_FIELD(ID_AA64MMFR1, HCX, false, MRS_LOWER, 0, id_aa64mmfr1_hcx),
1283 MRS_FIELD(ID_AA64MMFR1, ETS, false, MRS_LOWER, 0, id_aa64mmfr1_ets),
1284 MRS_FIELD(ID_AA64MMFR1, TWED, false, MRS_LOWER, 0, id_aa64mmfr1_twed),
1285 MRS_FIELD(ID_AA64MMFR1, XNX, false, MRS_LOWER, 0, id_aa64mmfr1_xnx),
1286 /*
1287 * SpecSEI != 0 indicates the CPU might generate an external abort
1288 * under speculation, while 0 indicates it can't happen. It's safer
1289 * to incorrectly indicate it might happen when it can't rather than
1290 * say it can't happen when it could. As such use the largest value
1291 * found in the system.
1292 */
1293 MRS_FIELD(ID_AA64MMFR1, SpecSEI, false, MRS_HIGHER, 0,
1294 id_aa64mmfr1_specsei),
1295 MRS_FIELD(ID_AA64MMFR1, PAN, false, MRS_LOWER, 0, id_aa64mmfr1_pan),
1296 MRS_FIELD(ID_AA64MMFR1, LO, false, MRS_LOWER, 0, id_aa64mmfr1_lo),
1297 MRS_FIELD(ID_AA64MMFR1, HPDS, false, MRS_LOWER, 0, id_aa64mmfr1_hpds),
1298 MRS_FIELD(ID_AA64MMFR1, VH, false, MRS_LOWER, 0, id_aa64mmfr1_vh),
1299 MRS_FIELD(ID_AA64MMFR1, VMIDBits, false, MRS_LOWER, 0,
1300 id_aa64mmfr1_vmidbits),
1301 MRS_FIELD(ID_AA64MMFR1, HAFDBS, false, MRS_LOWER, 0, id_aa64mmfr1_hafdbs),
1302 MRS_FIELD_END,
1303 };
1304
1305
1306 /* ID_AA64MMFR2_EL1 */
1307 static const struct mrs_field_value id_aa64mmfr2_e0pd[] = {
1308 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, E0PD, NONE, IMPL),
1309 MRS_FIELD_VALUE_END,
1310 };
1311
1312 static const struct mrs_field_value id_aa64mmfr2_evt[] = {
1313 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_NONE, ""),
1314 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_2, "EVT-8.2"),
1315 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_5, "EVT-8.5"),
1316 MRS_FIELD_VALUE_END,
1317 };
1318
1319 static const struct mrs_field_value id_aa64mmfr2_bbm[] = {
1320 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL0, ""),
1321 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL1, "BBM level 1"),
1322 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL2, "BBM level 2"),
1323 MRS_FIELD_VALUE_END,
1324 };
1325
1326 static const struct mrs_field_value id_aa64mmfr2_ttl[] = {
1327 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, TTL, NONE, IMPL),
1328 MRS_FIELD_VALUE_END,
1329 };
1330
1331 static const struct mrs_field_value id_aa64mmfr2_fwb[] = {
1332 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, FWB, NONE, IMPL),
1333 MRS_FIELD_VALUE_END,
1334 };
1335
1336 static const struct mrs_field_value id_aa64mmfr2_ids[] = {
1337 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IDS, NONE, IMPL),
1338 MRS_FIELD_VALUE_END,
1339 };
1340
1341 static const struct mrs_field_value id_aa64mmfr2_at[] = {
1342 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, AT, NONE, IMPL),
1343 MRS_FIELD_VALUE_END,
1344 };
1345
1346 static const struct mrs_field_hwcap id_aa64mmfr2_at_caps[] = {
1347 MRS_HWCAP(1, HWCAP_USCAT, ID_AA64MMFR2_AT_IMPL),
1348 MRS_HWCAP_END
1349 };
1350
1351 static const struct mrs_field_value id_aa64mmfr2_st[] = {
1352 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, ST, NONE, IMPL),
1353 MRS_FIELD_VALUE_END,
1354 };
1355
1356 static const struct mrs_field_value id_aa64mmfr2_nv[] = {
1357 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, 8_3),
1358 MRS_FIELD_VALUE(ID_AA64MMFR2_NV_8_4, "NV v8.4"),
1359 MRS_FIELD_VALUE_END,
1360 };
1361
1362 static const struct mrs_field_value id_aa64mmfr2_ccidx[] = {
1363 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_32, "32bit CCIDX"),
1364 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_64, "64bit CCIDX"),
1365 MRS_FIELD_VALUE_END,
1366 };
1367
1368 static const struct mrs_field_value id_aa64mmfr2_varange[] = {
1369 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_48, "48bit VA"),
1370 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_52, "52bit VA"),
1371 MRS_FIELD_VALUE_END,
1372 };
1373
1374 static const struct mrs_field_value id_aa64mmfr2_iesb[] = {
1375 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IESB, NONE, IMPL),
1376 MRS_FIELD_VALUE_END,
1377 };
1378
1379 static const struct mrs_field_value id_aa64mmfr2_lsm[] = {
1380 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, LSM, NONE, IMPL),
1381 MRS_FIELD_VALUE_END,
1382 };
1383
1384 static const struct mrs_field_value id_aa64mmfr2_uao[] = {
1385 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, UAO, NONE, IMPL),
1386 MRS_FIELD_VALUE_END,
1387 };
1388
1389 static const struct mrs_field_value id_aa64mmfr2_cnp[] = {
1390 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, CnP, NONE, IMPL),
1391 MRS_FIELD_VALUE_END,
1392 };
1393
1394 static const struct mrs_field id_aa64mmfr2_fields[] = {
1395 MRS_FIELD(ID_AA64MMFR2, E0PD, false, MRS_LOWER, 0, id_aa64mmfr2_e0pd),
1396 MRS_FIELD(ID_AA64MMFR2, EVT, false, MRS_LOWER, 0, id_aa64mmfr2_evt),
1397 MRS_FIELD(ID_AA64MMFR2, BBM, false, MRS_LOWER, 0, id_aa64mmfr2_bbm),
1398 MRS_FIELD(ID_AA64MMFR2, TTL, false, MRS_LOWER, 0, id_aa64mmfr2_ttl),
1399 MRS_FIELD(ID_AA64MMFR2, FWB, false, MRS_LOWER, 0, id_aa64mmfr2_fwb),
1400 MRS_FIELD(ID_AA64MMFR2, IDS, false, MRS_LOWER, 0, id_aa64mmfr2_ids),
1401 MRS_FIELD_HWCAP(ID_AA64MMFR2, AT, false, MRS_LOWER, MRS_USERSPACE,
1402 id_aa64mmfr2_at, id_aa64mmfr2_at_caps),
1403 MRS_FIELD(ID_AA64MMFR2, ST, false, MRS_LOWER, 0, id_aa64mmfr2_st),
1404 MRS_FIELD(ID_AA64MMFR2, NV, false, MRS_LOWER, 0, id_aa64mmfr2_nv),
1405 MRS_FIELD(ID_AA64MMFR2, CCIDX, false, MRS_LOWER, 0, id_aa64mmfr2_ccidx),
1406 MRS_FIELD(ID_AA64MMFR2, VARange, false, MRS_LOWER, 0,
1407 id_aa64mmfr2_varange),
1408 MRS_FIELD(ID_AA64MMFR2, IESB, false, MRS_LOWER, 0, id_aa64mmfr2_iesb),
1409 MRS_FIELD(ID_AA64MMFR2, LSM, false, MRS_LOWER, 0, id_aa64mmfr2_lsm),
1410 MRS_FIELD(ID_AA64MMFR2, UAO, false, MRS_LOWER, 0, id_aa64mmfr2_uao),
1411 MRS_FIELD(ID_AA64MMFR2, CnP, false, MRS_LOWER, 0, id_aa64mmfr2_cnp),
1412 MRS_FIELD_END,
1413 };
1414
1415
1416 /* ID_AA64MMFR2_EL1 */
1417 static const struct mrs_field_value id_aa64mmfr3_spec_fpacc[] = {
1418 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, Spec_FPACC, NONE, IMPL),
1419 MRS_FIELD_VALUE_END,
1420 };
1421
1422 static const struct mrs_field_value id_aa64mmfr3_mec[] = {
1423 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, MEC, NONE, IMPL),
1424 MRS_FIELD_VALUE_END,
1425 };
1426
1427 static const struct mrs_field_value id_aa64mmfr3_sctlrx[] = {
1428 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SCTLRX, NONE, IMPL),
1429 MRS_FIELD_VALUE_END,
1430 };
1431
1432 static const struct mrs_field_value id_aa64mmfr3_tcrx[] = {
1433 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, TCRX, NONE, IMPL),
1434 MRS_FIELD_VALUE_END,
1435 };
1436
1437 static const struct mrs_field id_aa64mmfr3_fields[] = {
1438 MRS_FIELD(ID_AA64MMFR3, Spec_FPACC, false, MRS_LOWER, 0,
1439 id_aa64mmfr3_spec_fpacc),
1440 MRS_FIELD(ID_AA64MMFR3, MEC, false, MRS_LOWER, 0, id_aa64mmfr3_mec),
1441 MRS_FIELD(ID_AA64MMFR3, SCTLRX, false, MRS_LOWER, 0,
1442 id_aa64mmfr3_sctlrx),
1443 MRS_FIELD(ID_AA64MMFR3, TCRX, false, MRS_LOWER, 0, id_aa64mmfr3_tcrx),
1444 MRS_FIELD_END,
1445 };
1446
1447
1448 /* ID_AA64MMFR4_EL1 */
1449 static const struct mrs_field id_aa64mmfr4_fields[] = {
1450 MRS_FIELD_END,
1451 };
1452
1453
1454 /* ID_AA64PFR0_EL1 */
1455 static const struct mrs_field_value id_aa64pfr0_csv3[] = {
1456 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
1457 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"),
1458 MRS_FIELD_VALUE_END,
1459 };
1460
1461 static const struct mrs_field_value id_aa64pfr0_csv2[] = {
1462 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""),
1463 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"),
1464 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "CSV2_2"),
1465 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_3, "CSV2_3"),
1466 MRS_FIELD_VALUE_END,
1467 };
1468
1469 static const struct mrs_field_value id_aa64pfr0_rme[] = {
1470 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, RME, NONE, IMPL),
1471 MRS_FIELD_VALUE_END,
1472 };
1473
1474 static const struct mrs_field_value id_aa64pfr0_dit[] = {
1475 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""),
1476 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"),
1477 MRS_FIELD_VALUE_END,
1478 };
1479
1480 static const struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = {
1481 MRS_HWCAP(1, HWCAP_DIT, ID_AA64PFR0_DIT_PSTATE),
1482 MRS_HWCAP_END
1483 };
1484
1485 static const struct mrs_field_value id_aa64pfr0_amu[] = {
1486 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""),
1487 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"),
1488 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1_1, "AMUv1p1"),
1489 MRS_FIELD_VALUE_END,
1490 };
1491
1492 static const struct mrs_field_value id_aa64pfr0_mpam[] = {
1493 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL),
1494 MRS_FIELD_VALUE_END,
1495 };
1496
1497 static const struct mrs_field_value id_aa64pfr0_sel2[] = {
1498 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL),
1499 MRS_FIELD_VALUE_END,
1500 };
1501
1502 static const struct mrs_field_value id_aa64pfr0_sve[] = {
1503 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL),
1504 MRS_FIELD_VALUE_END,
1505 };
1506
1507 static const struct mrs_field_hwcap id_aa64pfr0_sve_caps[] = {
1508 MRS_HWCAP(1, HWCAP_SVE, ID_AA64PFR0_SVE_IMPL),
1509 MRS_HWCAP_END
1510 };
1511
1512 static const struct mrs_field_value id_aa64pfr0_ras[] = {
1513 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_NONE, ""),
1514 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_IMPL, "RAS"),
1515 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_4, "RAS v8.4"),
1516 MRS_FIELD_VALUE_END,
1517 };
1518
1519 static const struct mrs_field_value id_aa64pfr0_gic[] = {
1520 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN),
1521 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""),
1522 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"),
1523 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"),
1524 MRS_FIELD_VALUE_END,
1525 };
1526
1527 static const struct mrs_field_value id_aa64pfr0_advsimd[] = {
1528 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, AdvSIMD, NONE, IMPL),
1529 MRS_FIELD_VALUE(ID_AA64PFR0_AdvSIMD_HP, "AdvSIMD+HP"),
1530 MRS_FIELD_VALUE_END,
1531 };
1532
1533 static const struct mrs_field_hwcap id_aa64pfr0_advsimd_caps[] = {
1534 MRS_HWCAP(1, HWCAP_ASIMD, ID_AA64PFR0_AdvSIMD_IMPL),
1535 MRS_HWCAP(1, HWCAP_ASIMDHP, ID_AA64PFR0_AdvSIMD_HP),
1536 MRS_HWCAP_END
1537 };
1538
1539 static const struct mrs_field_value id_aa64pfr0_fp[] = {
1540 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, FP, NONE, IMPL),
1541 MRS_FIELD_VALUE(ID_AA64PFR0_FP_HP, "FP+HP"),
1542 MRS_FIELD_VALUE_END,
1543 };
1544
1545 static const struct mrs_field_hwcap id_aa64pfr0_fp_caps[] = {
1546 MRS_HWCAP(1, HWCAP_FP, ID_AA64PFR0_FP_IMPL),
1547 MRS_HWCAP(1, HWCAP_FPHP, ID_AA64PFR0_FP_HP),
1548 MRS_HWCAP_END
1549 };
1550
1551 static const struct mrs_field_value id_aa64pfr0_el3[] = {
1552 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL3, NONE, 64),
1553 MRS_FIELD_VALUE(ID_AA64PFR0_EL3_64_32, "EL3 32"),
1554 MRS_FIELD_VALUE_END,
1555 };
1556
1557 static const struct mrs_field_value id_aa64pfr0_el2[] = {
1558 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL2, NONE, 64),
1559 MRS_FIELD_VALUE(ID_AA64PFR0_EL2_64_32, "EL2 32"),
1560 MRS_FIELD_VALUE_END,
1561 };
1562
1563 static const struct mrs_field_value id_aa64pfr0_el1[] = {
1564 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64, "EL1"),
1565 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64_32, "EL1 32"),
1566 MRS_FIELD_VALUE_END,
1567 };
1568
1569 static const struct mrs_field_value id_aa64pfr0_el0[] = {
1570 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64, "EL0"),
1571 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64_32, "EL0 32"),
1572 MRS_FIELD_VALUE_END,
1573 };
1574
1575 static const struct mrs_field id_aa64pfr0_fields[] = {
1576 MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_LOWER, 0, id_aa64pfr0_csv3),
1577 MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_LOWER, 0, id_aa64pfr0_csv2),
1578 MRS_FIELD(ID_AA64PFR0, RME, false, MRS_LOWER, 0, id_aa64pfr0_rme),
1579 MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, MRS_USERSPACE,
1580 id_aa64pfr0_dit, id_aa64pfr0_dit_caps),
1581 MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_LOWER, 0, id_aa64pfr0_amu),
1582 MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_LOWER, 0, id_aa64pfr0_mpam),
1583 MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_LOWER, 0, id_aa64pfr0_sel2),
1584 MRS_FIELD_HWCAP(ID_AA64PFR0, SVE, false, MRS_LOWER,
1585 MRS_FREEBSD, id_aa64pfr0_sve, id_aa64pfr0_sve_caps),
1586 MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_LOWER, 0, id_aa64pfr0_ras),
1587 MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_LOWER, 0, id_aa64pfr0_gic),
1588 MRS_FIELD_HWCAP(ID_AA64PFR0, AdvSIMD, true, MRS_LOWER, MRS_USERSPACE,
1589 id_aa64pfr0_advsimd, id_aa64pfr0_advsimd_caps),
1590 MRS_FIELD_HWCAP(ID_AA64PFR0, FP, true, MRS_LOWER, MRS_USERSPACE,
1591 id_aa64pfr0_fp, id_aa64pfr0_fp_caps),
1592 MRS_FIELD(ID_AA64PFR0, EL3, false, MRS_LOWER, 0, id_aa64pfr0_el3),
1593 MRS_FIELD(ID_AA64PFR0, EL2, false, MRS_LOWER, 0, id_aa64pfr0_el2),
1594 MRS_FIELD(ID_AA64PFR0, EL1, false, MRS_LOWER, MRS_USERSPACE,
1595 id_aa64pfr0_el1),
1596 MRS_FIELD(ID_AA64PFR0, EL0, false, MRS_LOWER, MRS_USERSPACE,
1597 id_aa64pfr0_el0),
1598 MRS_FIELD_END,
1599 };
1600
1601
1602 /* ID_AA64PFR1_EL1 */
1603 static const struct mrs_field_value id_aa64pfr1_nmi[] = {
1604 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, NMI, NONE, IMPL),
1605 MRS_FIELD_VALUE_END,
1606 };
1607
1608 static const struct mrs_field_value id_aa64pfr1_csv2_frac[] = {
1609 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p0, ""),
1610 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p1, "CSV2 p1"),
1611 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p2, "CSV2 p2"),
1612 MRS_FIELD_VALUE_END,
1613 };
1614
1615 static const struct mrs_field_value id_aa64pfr1_rndr_trap[] = {
1616 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, RNDR_trap, NONE, IMPL),
1617 MRS_FIELD_VALUE_END,
1618 };
1619
1620 static const struct mrs_field_value id_aa64pfr1_sme[] = {
1621 MRS_FIELD_VALUE(ID_AA64PFR1_SME_NONE, ""),
1622 MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME, "SME"),
1623 MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME2, "SME2"),
1624 MRS_FIELD_VALUE_END,
1625 };
1626
1627 static const struct mrs_field_value id_aa64pfr1_mpam_frac[] = {
1628 MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p0, ""),
1629 MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p1, "MPAM p1"),
1630 MRS_FIELD_VALUE_END,
1631 };
1632
1633 static const struct mrs_field_value id_aa64pfr1_ras_frac[] = {
1634 MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p0, ""),
1635 MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p1, "RAS p1"),
1636 MRS_FIELD_VALUE_END,
1637 };
1638
1639 static const struct mrs_field_value id_aa64pfr1_mte[] = {
1640 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""),
1641 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE, "MTE"),
1642 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE2, "MTE2"),
1643 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE3, "MTE3"),
1644 MRS_FIELD_VALUE_END,
1645 };
1646
1647 static const struct mrs_field_value id_aa64pfr1_ssbs[] = {
1648 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""),
1649 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"),
1650 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"),
1651 MRS_FIELD_VALUE_END,
1652 };
1653
1654 static const struct mrs_field_hwcap id_aa64pfr1_ssbs_caps[] = {
1655 MRS_HWCAP(1, HWCAP_SSBS, ID_AA64PFR1_SSBS_PSTATE),
1656 MRS_HWCAP_END
1657 };
1658
1659 static const struct mrs_field_value id_aa64pfr1_bt[] = {
1660 MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""),
1661 MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"),
1662 MRS_FIELD_VALUE_END,
1663 };
1664
1665 static const struct mrs_field_hwcap id_aa64pfr1_bt_caps[] = {
1666 MRS_HWCAP(2, HWCAP2_BTI, ID_AA64PFR1_BT_IMPL),
1667 MRS_HWCAP_END
1668 };
1669
1670 static const struct mrs_field id_aa64pfr1_fields[] = {
1671 MRS_FIELD(ID_AA64PFR1, NMI, false, MRS_LOWER, 0, id_aa64pfr1_nmi),
1672 MRS_FIELD(ID_AA64PFR1, CSV2_frac, false, MRS_LOWER, 0,
1673 id_aa64pfr1_csv2_frac),
1674 MRS_FIELD(ID_AA64PFR1, RNDR_trap, false, MRS_LOWER, 0,
1675 id_aa64pfr1_rndr_trap),
1676 MRS_FIELD(ID_AA64PFR1, SME, false, MRS_LOWER, 0, id_aa64pfr1_sme),
1677 MRS_FIELD(ID_AA64PFR1, MPAM_frac, false, MRS_LOWER, 0,
1678 id_aa64pfr1_mpam_frac),
1679 MRS_FIELD(ID_AA64PFR1, RAS_frac, false, MRS_LOWER, 0,
1680 id_aa64pfr1_ras_frac),
1681 MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_LOWER, 0, id_aa64pfr1_mte),
1682 MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, MRS_USERSPACE,
1683 id_aa64pfr1_ssbs, id_aa64pfr1_ssbs_caps),
1684 MRS_FIELD_HWCAP(ID_AA64PFR1, BT, false, MRS_LOWER,
1685 MRS_FREEBSD, id_aa64pfr1_bt, id_aa64pfr1_bt_caps),
1686 MRS_FIELD_END,
1687 };
1688
1689
1690 /* ID_AA64PFR2_EL1 */
1691 static const struct mrs_field id_aa64pfr2_fields[] = {
1692 MRS_FIELD_END,
1693 };
1694
1695
1696 /* ID_AA64ZFR0_EL1 */
1697 static const struct mrs_field_value id_aa64zfr0_f64mm[] = {
1698 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F64MM, NONE, IMPL),
1699 MRS_FIELD_VALUE_END,
1700 };
1701
1702 static const struct mrs_field_hwcap id_aa64zfr0_f64mm_caps[] = {
1703 MRS_HWCAP(2, HWCAP2_SVEF64MM, ID_AA64ZFR0_F64MM_IMPL),
1704 MRS_HWCAP_END,
1705 };
1706
1707 static const struct mrs_field_value id_aa64zfr0_f32mm[] = {
1708 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F32MM, NONE, IMPL),
1709 MRS_FIELD_VALUE_END,
1710 };
1711
1712 static const struct mrs_field_hwcap id_aa64zfr0_f32mm_caps[] = {
1713 MRS_HWCAP(2, HWCAP2_SVEF32MM, ID_AA64ZFR0_F32MM_IMPL),
1714 MRS_HWCAP_END,
1715 };
1716
1717 static const struct mrs_field_value id_aa64zfr0_i8mm[] = {
1718 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, I8MM, NONE, IMPL),
1719 MRS_FIELD_VALUE_END,
1720 };
1721
1722 static const struct mrs_field_hwcap id_aa64zfr0_i8mm_caps[] = {
1723 MRS_HWCAP(2, HWCAP2_SVEI8MM, ID_AA64ZFR0_I8MM_IMPL),
1724 MRS_HWCAP_END,
1725 };
1726
1727 static const struct mrs_field_value id_aa64zfr0_sm4[] = {
1728 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SM4, NONE, IMPL),
1729 MRS_FIELD_VALUE_END,
1730 };
1731
1732 static const struct mrs_field_hwcap id_aa64zfr0_sm4_caps[] = {
1733 MRS_HWCAP(2, HWCAP2_SVESM4, ID_AA64ZFR0_SM4_IMPL),
1734 MRS_HWCAP_END,
1735 };
1736
1737 static const struct mrs_field_value id_aa64zfr0_sha3[] = {
1738 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SHA3, NONE, IMPL),
1739 MRS_FIELD_VALUE_END,
1740 };
1741
1742 static const struct mrs_field_hwcap id_aa64zfr0_sha3_caps[] = {
1743 MRS_HWCAP(2, HWCAP2_SVESHA3, ID_AA64ZFR0_SHA3_IMPL),
1744 MRS_HWCAP_END,
1745 };
1746
1747 static const struct mrs_field_value id_aa64zfr0_bf16[] = {
1748 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BF16, NONE, BASE),
1749 MRS_FIELD_VALUE(ID_AA64ZFR0_BF16_EBF, "BF16+EBF"),
1750 MRS_FIELD_VALUE_END,
1751 };
1752
1753 static const struct mrs_field_hwcap id_aa64zfr0_bf16_caps[] = {
1754 MRS_HWCAP(2, HWCAP2_SVEBF16, ID_AA64ZFR0_BF16_BASE),
1755 MRS_HWCAP(2, HWCAP2_SVE_EBF16, ID_AA64ZFR0_BF16_EBF),
1756 MRS_HWCAP_END,
1757 };
1758
1759 static const struct mrs_field_value id_aa64zfr0_bitperm[] = {
1760 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BitPerm, NONE, IMPL),
1761 MRS_FIELD_VALUE_END,
1762 };
1763
1764 static const struct mrs_field_hwcap id_aa64zfr0_bitperm_caps[] = {
1765 MRS_HWCAP(2, HWCAP2_SVEBITPERM, ID_AA64ZFR0_BitPerm_IMPL),
1766 MRS_HWCAP_END,
1767 };
1768
1769 static const struct mrs_field_value id_aa64zfr0_aes[] = {
1770 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, AES, NONE, BASE),
1771 MRS_FIELD_VALUE(ID_AA64ZFR0_AES_PMULL, "AES+PMULL"),
1772 MRS_FIELD_VALUE_END,
1773 };
1774
1775 static const struct mrs_field_hwcap id_aa64zfr0_aes_caps[] = {
1776 MRS_HWCAP(2, HWCAP2_SVEAES, ID_AA64ZFR0_AES_BASE),
1777 MRS_HWCAP(2, HWCAP2_SVEPMULL, ID_AA64ZFR0_AES_PMULL),
1778 MRS_HWCAP_END,
1779 };
1780
1781 static const struct mrs_field_value id_aa64zfr0_svever[] = {
1782 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE1, "SVE1"),
1783 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2, "SVE2"),
1784 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2P1, "SVE2P1"),
1785 MRS_FIELD_VALUE_END,
1786 };
1787
1788 static const struct mrs_field_hwcap id_aa64zfr0_svever_caps[] = {
1789 MRS_HWCAP(2, HWCAP2_SVE2, ID_AA64ZFR0_SVEver_SVE2),
1790 MRS_HWCAP(2, HWCAP2_SVE2P1, ID_AA64ZFR0_SVEver_SVE2P1),
1791 MRS_HWCAP_END,
1792 };
1793
1794 static const struct mrs_field id_aa64zfr0_fields[] = {
1795 MRS_FIELD_HWCAP(ID_AA64ZFR0, F64MM, false, MRS_LOWER, MRS_USERSPACE,
1796 id_aa64zfr0_f64mm, id_aa64zfr0_f64mm_caps),
1797 MRS_FIELD_HWCAP(ID_AA64ZFR0, F32MM, false, MRS_LOWER, MRS_USERSPACE,
1798 id_aa64zfr0_f32mm, id_aa64zfr0_f32mm_caps),
1799 MRS_FIELD_HWCAP(ID_AA64ZFR0, I8MM, false, MRS_LOWER, MRS_USERSPACE,
1800 id_aa64zfr0_i8mm, id_aa64zfr0_i8mm_caps),
1801 MRS_FIELD_HWCAP(ID_AA64ZFR0, SM4, false, MRS_LOWER, MRS_USERSPACE,
1802 id_aa64zfr0_sm4, id_aa64zfr0_sm4_caps),
1803 MRS_FIELD_HWCAP(ID_AA64ZFR0, SHA3, false, MRS_LOWER, MRS_USERSPACE,
1804 id_aa64zfr0_sha3, id_aa64zfr0_sha3_caps),
1805 MRS_FIELD_HWCAP(ID_AA64ZFR0, BF16, false, MRS_LOWER, MRS_USERSPACE,
1806 id_aa64zfr0_bf16, id_aa64zfr0_bf16_caps),
1807 MRS_FIELD_HWCAP(ID_AA64ZFR0, BitPerm, false, MRS_LOWER, MRS_USERSPACE,
1808 id_aa64zfr0_bitperm, id_aa64zfr0_bitperm_caps),
1809 MRS_FIELD_HWCAP(ID_AA64ZFR0, AES, false, MRS_LOWER, MRS_USERSPACE,
1810 id_aa64zfr0_aes, id_aa64zfr0_aes_caps),
1811 MRS_FIELD_HWCAP(ID_AA64ZFR0, SVEver, false, MRS_LOWER, MRS_USERSPACE,
1812 id_aa64zfr0_svever, id_aa64zfr0_svever_caps),
1813 MRS_FIELD_END,
1814 };
1815
1816
1817 #ifdef COMPAT_FREEBSD32
1818 /* ID_ISAR5_EL1 */
1819 static const struct mrs_field_value id_isar5_vcma[] = {
1820 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, VCMA, NONE, IMPL),
1821 MRS_FIELD_VALUE_END,
1822 };
1823
1824 static const struct mrs_field_value id_isar5_rdm[] = {
1825 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, RDM, NONE, IMPL),
1826 MRS_FIELD_VALUE_END,
1827 };
1828
1829 static const struct mrs_field_value id_isar5_crc32[] = {
1830 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, CRC32, NONE, IMPL),
1831 MRS_FIELD_VALUE_END,
1832 };
1833
1834 static const struct mrs_field_hwcap id_isar5_crc32_caps[] = {
1835 MRS_HWCAP(2, HWCAP32_2_CRC32, ID_ISAR5_CRC32_IMPL),
1836 MRS_HWCAP_END
1837 };
1838
1839 static const struct mrs_field_value id_isar5_sha2[] = {
1840 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA2, NONE, IMPL),
1841 MRS_FIELD_VALUE_END,
1842 };
1843
1844 static const struct mrs_field_hwcap id_isar5_sha2_caps[] = {
1845 MRS_HWCAP(2, HWCAP32_2_SHA2, ID_ISAR5_SHA2_IMPL),
1846 MRS_HWCAP_END
1847 };
1848
1849 static const struct mrs_field_value id_isar5_sha1[] = {
1850 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA1, NONE, IMPL),
1851 MRS_FIELD_VALUE_END,
1852 };
1853
1854 static const struct mrs_field_hwcap id_isar5_sha1_caps[] = {
1855 MRS_HWCAP(2, HWCAP32_2_SHA1, ID_ISAR5_SHA1_IMPL),
1856 MRS_HWCAP_END
1857 };
1858
1859 static const struct mrs_field_value id_isar5_aes[] = {
1860 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, AES, NONE, BASE),
1861 MRS_FIELD_VALUE(ID_ISAR5_AES_VMULL, "AES+VMULL"),
1862 MRS_FIELD_VALUE_END,
1863 };
1864
1865 static const struct mrs_field_hwcap id_isar5_aes_caps[] = {
1866 MRS_HWCAP(2, HWCAP32_2_AES, ID_ISAR5_AES_BASE),
1867 MRS_HWCAP(2, HWCAP32_2_PMULL, ID_ISAR5_AES_VMULL),
1868 MRS_HWCAP_END
1869 };
1870
1871 static const struct mrs_field_value id_isar5_sevl[] = {
1872 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SEVL, NOP, IMPL),
1873 MRS_FIELD_VALUE_END,
1874 };
1875
1876 static const struct mrs_field id_isar5_fields[] = {
1877 MRS_FIELD(ID_ISAR5, VCMA, false, MRS_LOWER,MRS_USERSPACE,
1878 id_isar5_vcma),
1879 MRS_FIELD(ID_ISAR5, RDM, false, MRS_LOWER, MRS_USERSPACE, id_isar5_rdm),
1880 MRS_FIELD_HWCAP(ID_ISAR5, CRC32, false, MRS_LOWER, MRS_USERSPACE,
1881 id_isar5_crc32, id_isar5_crc32_caps),
1882 MRS_FIELD_HWCAP(ID_ISAR5, SHA2, false, MRS_LOWER, MRS_USERSPACE,
1883 id_isar5_sha2, id_isar5_sha2_caps),
1884 MRS_FIELD_HWCAP(ID_ISAR5, SHA1, false, MRS_LOWER, MRS_USERSPACE,
1885 id_isar5_sha1, id_isar5_sha1_caps),
1886 MRS_FIELD_HWCAP(ID_ISAR5, AES, false, MRS_LOWER, MRS_USERSPACE,
1887 id_isar5_aes, id_isar5_aes_caps),
1888 MRS_FIELD(ID_ISAR5, SEVL, false, MRS_LOWER, MRS_USERSPACE,
1889 id_isar5_sevl),
1890 MRS_FIELD_END,
1891 };
1892
1893 /* MVFR0 */
1894 static const struct mrs_field_value mvfr0_fpround[] = {
1895 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPRound, NONE, IMPL),
1896 MRS_FIELD_VALUE_END,
1897 };
1898
1899 static const struct mrs_field_value mvfr0_fpsqrt[] = {
1900 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPSqrt, NONE, IMPL),
1901 MRS_FIELD_VALUE_END,
1902 };
1903
1904 static const struct mrs_field_value mvfr0_fpdivide[] = {
1905 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPDivide, NONE, IMPL),
1906 MRS_FIELD_VALUE_END,
1907 };
1908
1909 static const struct mrs_field_value mvfr0_fptrap[] = {
1910 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPTrap, NONE, IMPL),
1911 MRS_FIELD_VALUE_END,
1912 };
1913
1914 static const struct mrs_field_value mvfr0_fpdp[] = {
1915 MRS_FIELD_VALUE(MVFR0_FPDP_NONE, ""),
1916 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v2, "DP VFPv2"),
1917 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v3_v4, "DP VFPv3+v4"),
1918 MRS_FIELD_VALUE_END,
1919 };
1920
1921 static const struct mrs_field_hwcap mvfr0_fpdp_caps[] = {
1922 MRS_HWCAP(1, HWCAP32_VFP, MVFR0_FPDP_VFP_v2),
1923 MRS_HWCAP(1, HWCAP32_VFPv3, MVFR0_FPDP_VFP_v3_v4),
1924 MRS_HWCAP_END
1925 };
1926
1927 static const struct mrs_field_value mvfr0_fpsp[] = {
1928 MRS_FIELD_VALUE(MVFR0_FPSP_NONE, ""),
1929 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v2, "SP VFPv2"),
1930 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v3_v4, "SP VFPv3+v4"),
1931 MRS_FIELD_VALUE_END,
1932 };
1933
1934 static const struct mrs_field_value mvfr0_simdreg[] = {
1935 MRS_FIELD_VALUE(MVFR0_SIMDReg_NONE, ""),
1936 MRS_FIELD_VALUE(MVFR0_SIMDReg_FP, "FP 16x64"),
1937 MRS_FIELD_VALUE(MVFR0_SIMDReg_AdvSIMD, "AdvSIMD"),
1938 MRS_FIELD_VALUE_END,
1939 };
1940
1941 static const struct mrs_field mvfr0_fields[] = {
1942 MRS_FIELD(MVFR0, FPRound, false, MRS_LOWER, MRS_USERSPACE,
1943 mvfr0_fpround),
1944 MRS_FIELD(MVFR0, FPSqrt, false, MRS_LOWER, MRS_USERSPACE,
1945 mvfr0_fpsqrt),
1946 MRS_FIELD(MVFR0, FPDivide, false, MRS_LOWER, MRS_USERSPACE,
1947 mvfr0_fpdivide),
1948 MRS_FIELD(MVFR0, FPTrap, false, MRS_LOWER, MRS_USERSPACE,
1949 mvfr0_fptrap),
1950 MRS_FIELD_HWCAP(MVFR0, FPDP, false, MRS_LOWER, MRS_USERSPACE,
1951 mvfr0_fpdp, mvfr0_fpdp_caps),
1952 MRS_FIELD(MVFR0, FPSP, false, MRS_LOWER, MRS_USERSPACE, mvfr0_fpsp),
1953 MRS_FIELD(MVFR0, SIMDReg, false, MRS_LOWER, MRS_USERSPACE,
1954 mvfr0_simdreg),
1955 MRS_FIELD_END,
1956 };
1957
1958 /* MVFR1 */
1959 static const struct mrs_field_value mvfr1_simdfmac[] = {
1960 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDFMAC, NONE, IMPL),
1961 MRS_FIELD_VALUE_END,
1962 };
1963
1964 static const struct mrs_field_hwcap mvfr1_simdfmac_caps[] = {
1965 MRS_HWCAP(1, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL),
1966 MRS_HWCAP_END
1967 };
1968
1969 static const struct mrs_field_value mvfr1_fphp[] = {
1970 MRS_FIELD_VALUE(MVFR1_FPHP_NONE, ""),
1971 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_SP, "FPHP SP Conv"),
1972 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_DP, "FPHP DP Conv"),
1973 MRS_FIELD_VALUE(MVFR1_FPHP_ARITH, "FPHP Arith"),
1974 MRS_FIELD_VALUE_END,
1975 };
1976
1977 static const struct mrs_field_value mvfr1_simdhp[] = {
1978 MRS_FIELD_VALUE(MVFR1_SIMDHP_NONE, ""),
1979 MRS_FIELD_VALUE(MVFR1_SIMDHP_CONV_SP, "SIMDHP SP Conv"),
1980 MRS_FIELD_VALUE(MVFR1_SIMDHP_ARITH, "SIMDHP Arith"),
1981 MRS_FIELD_VALUE_END,
1982 };
1983
1984 static const struct mrs_field_value mvfr1_simdsp[] = {
1985 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDSP, NONE, IMPL),
1986 MRS_FIELD_VALUE_END,
1987 };
1988
1989 static const struct mrs_field_value mvfr1_simdint[] = {
1990 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDInt, NONE, IMPL),
1991 MRS_FIELD_VALUE_END,
1992 };
1993
1994 static const struct mrs_field_value mvfr1_simdls[] = {
1995 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDLS, NONE, IMPL),
1996 MRS_FIELD_VALUE_END,
1997 };
1998
1999 static const struct mrs_field_hwcap mvfr1_simdls_caps[] = {
2000 MRS_HWCAP(1, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL),
2001 MRS_HWCAP_END
2002 };
2003
2004 static const struct mrs_field_value mvfr1_fpdnan[] = {
2005 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPDNaN, NONE, IMPL),
2006 MRS_FIELD_VALUE_END,
2007 };
2008
2009 static const struct mrs_field_value mvfr1_fpftz[] = {
2010 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPFtZ, NONE, IMPL),
2011 MRS_FIELD_VALUE_END,
2012 };
2013
2014 static const struct mrs_field mvfr1_fields[] = {
2015 MRS_FIELD_HWCAP(MVFR1, SIMDFMAC, false, MRS_LOWER, MRS_USERSPACE,
2016 mvfr1_simdfmac, mvfr1_simdfmac_caps),
2017 MRS_FIELD(MVFR1, FPHP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_fphp),
2018 MRS_FIELD(MVFR1, SIMDHP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_simdhp),
2019 MRS_FIELD(MVFR1, SIMDSP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_simdsp),
2020 MRS_FIELD(MVFR1, SIMDInt, false, MRS_LOWER, MRS_USERSPACE,
2021 mvfr1_simdint),
2022 MRS_FIELD_HWCAP(MVFR1, SIMDLS, false, MRS_LOWER, MRS_USERSPACE,
2023 mvfr1_simdls, mvfr1_simdls_caps),
2024 MRS_FIELD(MVFR1, FPDNaN, false, MRS_LOWER, MRS_USERSPACE,
2025 mvfr1_fpdnan),
2026 MRS_FIELD(MVFR1, FPFtZ, false, MRS_LOWER, MRS_USERSPACE,
2027 mvfr1_fpftz),
2028 MRS_FIELD_END,
2029 };
2030 #endif /* COMPAT_FREEBSD32 */
2031
2032 struct mrs_user_reg {
2033 u_int reg;
2034 u_int CRm;
2035 u_int Op2;
2036 bool is64bit;
2037 size_t offset;
2038 const struct mrs_field *fields;
2039 };
2040
2041 #define USER_REG(name, field_name, _is64bit) \
2042 { \
2043 .reg = name, \
2044 .CRm = name##_CRm, \
2045 .Op2 = name##_op2, \
2046 .offset = __offsetof(struct cpu_desc, field_name), \
2047 .fields = field_name##_fields, \
2048 .is64bit = _is64bit, \
2049 }
2050 static const struct mrs_user_reg user_regs[] = {
2051 USER_REG(ID_AA64AFR0_EL1, id_aa64afr0, true),
2052 USER_REG(ID_AA64AFR1_EL1, id_aa64afr1, true),
2053
2054 USER_REG(ID_AA64DFR0_EL1, id_aa64dfr0, true),
2055 USER_REG(ID_AA64DFR1_EL1, id_aa64dfr1, true),
2056
2057 USER_REG(ID_AA64ISAR0_EL1, id_aa64isar0, true),
2058 USER_REG(ID_AA64ISAR1_EL1, id_aa64isar1, true),
2059 USER_REG(ID_AA64ISAR2_EL1, id_aa64isar2, true),
2060
2061 USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0, true),
2062 USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1, true),
2063 USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2, true),
2064 USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3, true),
2065 USER_REG(ID_AA64MMFR4_EL1, id_aa64mmfr4, true),
2066
2067 USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0, true),
2068 USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1, true),
2069 USER_REG(ID_AA64PFR2_EL1, id_aa64pfr2, true),
2070
2071 USER_REG(ID_AA64ZFR0_EL1, id_aa64zfr0, true),
2072
2073 #ifdef COMPAT_FREEBSD32
2074 USER_REG(ID_ISAR5_EL1, id_isar5, false),
2075
2076 USER_REG(MVFR0_EL1, mvfr0, false),
2077 USER_REG(MVFR1_EL1, mvfr1, false),
2078 #endif /* COMPAT_FREEBSD32 */
2079 };
2080
2081 #define CPU_DESC_FIELD(desc, idx) \
2082 *(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset)
2083
2084 static int
user_mrs_handler(vm_offset_t va,uint32_t insn,struct trapframe * frame,uint32_t esr)2085 user_mrs_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
2086 uint32_t esr)
2087 {
2088 uint64_t value;
2089 int CRm, Op2, i, reg;
2090
2091 if ((insn & MRS_MASK) != MRS_VALUE)
2092 return (0);
2093
2094 /*
2095 * We only emulate Op0 == 3, Op1 == 0, CRn == 0, CRm == {0, 4-7}.
2096 * These are in the EL1 CPU identification space.
2097 * CRm == 0 holds MIDR_EL1, MPIDR_EL1, and REVID_EL1.
2098 * CRm == {4-7} holds the ID_AA64 registers.
2099 *
2100 * For full details see the ARMv8 ARM (ARM DDI 0487C.a)
2101 * Table D9-2 System instruction encodings for non-Debug System
2102 * register accesses.
2103 */
2104 if (mrs_Op0(insn) != 3 || mrs_Op1(insn) != 0 || mrs_CRn(insn) != 0)
2105 return (0);
2106
2107 CRm = mrs_CRm(insn);
2108 if (CRm > 7 || (CRm < 4 && CRm != 0))
2109 return (0);
2110
2111 Op2 = mrs_Op2(insn);
2112 value = 0;
2113
2114 for (i = 0; i < nitems(user_regs); i++) {
2115 if (user_regs[i].CRm == CRm && user_regs[i].Op2 == Op2) {
2116 if (SV_CURPROC_ABI() == SV_ABI_FREEBSD)
2117 value = CPU_DESC_FIELD(user_cpu_desc, i);
2118 else
2119 value = CPU_DESC_FIELD(l_user_cpu_desc, i);
2120 break;
2121 }
2122 }
2123
2124 if (CRm == 0) {
2125 switch (Op2) {
2126 case 0:
2127 value = READ_SPECIALREG(midr_el1);
2128 break;
2129 case 5:
2130 value = READ_SPECIALREG(mpidr_el1);
2131 break;
2132 case 6:
2133 value = READ_SPECIALREG(revidr_el1);
2134 break;
2135 default:
2136 return (0);
2137 }
2138 }
2139
2140 /*
2141 * We will handle this instruction, move to the next so we
2142 * don't trap here again.
2143 */
2144 frame->tf_elr += INSN_SIZE;
2145
2146 reg = MRS_REGISTER(insn);
2147 /* If reg is 31 then write to xzr, i.e. do nothing */
2148 if (reg == 31)
2149 return (1);
2150
2151 if (reg < nitems(frame->tf_x))
2152 frame->tf_x[reg] = value;
2153 else if (reg == 30)
2154 frame->tf_lr = value;
2155
2156 return (1);
2157 }
2158
2159 /*
2160 * Compares two field values that may be signed or unsigned.
2161 * Returns:
2162 * < 0 when a is less than b
2163 * = 0 when a equals b
2164 * > 0 when a is greater than b
2165 */
2166 static int
mrs_field_cmp(uint64_t a,uint64_t b,u_int shift,int width,bool sign)2167 mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign)
2168 {
2169 uint64_t mask;
2170
2171 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__,
2172 width));
2173
2174 mask = (1ul << width) - 1;
2175 /* Move the field to the lower bits */
2176 a = (a >> shift) & mask;
2177 b = (b >> shift) & mask;
2178
2179 if (sign) {
2180 /*
2181 * The field is signed. Toggle the upper bit so the comparison
2182 * works on unsigned values as this makes positive numbers,
2183 * i.e. those with a 0 bit, larger than negative numbers,
2184 * i.e. those with a 1 bit, in an unsigned comparison.
2185 */
2186 a ^= 1ul << (width - 1);
2187 b ^= 1ul << (width - 1);
2188 }
2189
2190 return (a - b);
2191 }
2192
2193 bool
extract_user_id_field(u_int reg,u_int field_shift,uint8_t * val)2194 extract_user_id_field(u_int reg, u_int field_shift, uint8_t *val)
2195 {
2196 uint64_t value;
2197 int i;
2198
2199 for (i = 0; i < nitems(user_regs); i++) {
2200 if (user_regs[i].reg == reg) {
2201 value = CPU_DESC_FIELD(user_cpu_desc, i);
2202 *val = value >> field_shift;
2203 return (true);
2204 }
2205 }
2206
2207 return (false);
2208 }
2209
2210 bool
get_kernel_reg(u_int reg,uint64_t * val)2211 get_kernel_reg(u_int reg, uint64_t *val)
2212 {
2213 int i;
2214
2215 for (i = 0; i < nitems(user_regs); i++) {
2216 if (user_regs[i].reg == reg) {
2217 *val = CPU_DESC_FIELD(kern_cpu_desc, i);
2218 return (true);
2219 }
2220 }
2221
2222 return (false);
2223 }
2224
2225 /*
2226 * Fetch the specified register's value, ensuring that individual field values
2227 * do not exceed those in the mask.
2228 */
2229 bool
get_kernel_reg_masked(u_int reg,uint64_t * valp,uint64_t mask)2230 get_kernel_reg_masked(u_int reg, uint64_t *valp, uint64_t mask)
2231 {
2232 const struct mrs_field *fields;
2233 uint64_t val;
2234
2235 for (int i = 0; i < nitems(user_regs); i++) {
2236 if (user_regs[i].reg == reg) {
2237 val = CPU_DESC_FIELD(kern_cpu_desc, i);
2238 fields = user_regs[i].fields;
2239 for (int j = 0; fields[j].type != 0; j++) {
2240 mask = update_special_reg_field(mask,
2241 fields[j].type, val, fields[j].width,
2242 fields[j].shift, fields[j].sign);
2243 }
2244 *valp = mask;
2245 return (true);
2246 }
2247 }
2248
2249 return (false);
2250 }
2251
2252 static uint64_t
update_special_reg_field(uint64_t user_reg,u_int type,uint64_t value,u_int width,u_int shift,bool sign)2253 update_special_reg_field(uint64_t user_reg, u_int type, uint64_t value,
2254 u_int width, u_int shift, bool sign)
2255 {
2256 uint64_t cur, mask, new_val;
2257
2258 mask = ((1ul << width) - 1) << shift;
2259 cur = user_reg & mask;
2260 new_val = value & mask;
2261
2262 switch (type & MRS_TYPE_MASK) {
2263 case MRS_EXACT_IF_DIFFERENT:
2264 if (mrs_field_cmp(new_val, cur, shift, width, sign) != 0)
2265 break;
2266 /* FALLTHROUGH */
2267 case MRS_EXACT:
2268 cur = (uint64_t)MRS_SAFE_VAL(type) << shift;
2269 break;
2270 case MRS_LOWER:
2271 if (mrs_field_cmp(new_val, cur, shift, width, sign) < 0)
2272 cur = new_val;
2273 break;
2274 case MRS_HIGHER_OR_ZERO:
2275 if (cur == 0 || new_val == 0) {
2276 cur = 0;
2277 break;
2278 }
2279 /* FALLTHROUGH */
2280 case MRS_HIGHER:
2281 if (mrs_field_cmp(new_val, cur, shift, width, sign) > 0)
2282 cur = new_val;
2283 break;
2284 default:
2285 panic("Invalid field type: %d", type);
2286 }
2287
2288 user_reg &= ~mask;
2289 user_reg |= cur;
2290
2291 return (user_reg);
2292 }
2293
2294 void
update_special_regs(u_int cpu)2295 update_special_regs(u_int cpu)
2296 {
2297 struct cpu_desc *desc;
2298 const struct mrs_field *fields;
2299 uint64_t l_user_reg, user_reg, kern_reg, value;
2300 int i, j;
2301
2302 if (cpu == 0) {
2303 /* Create a user visible cpu description with safe values */
2304 memset(&user_cpu_desc, 0, sizeof(user_cpu_desc));
2305 /* Safe values for these registers */
2306 user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE |
2307 ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 |
2308 ID_AA64PFR0_EL0_64;
2309 user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8;
2310 /* Create the Linux user visible cpu description */
2311 memcpy(&l_user_cpu_desc, &user_cpu_desc, sizeof(user_cpu_desc));
2312 }
2313
2314 desc = get_cpu_desc(cpu);
2315 for (i = 0; i < nitems(user_regs); i++) {
2316 value = CPU_DESC_FIELD(*desc, i);
2317 if (cpu == 0) {
2318 kern_reg = value;
2319 user_reg = value;
2320 l_user_reg = value;
2321 } else {
2322 kern_reg = CPU_DESC_FIELD(kern_cpu_desc, i);
2323 user_reg = CPU_DESC_FIELD(user_cpu_desc, i);
2324 l_user_reg = CPU_DESC_FIELD(l_user_cpu_desc, i);
2325 }
2326
2327 fields = user_regs[i].fields;
2328 for (j = 0; fields[j].type != 0; j++) {
2329 u_int type;
2330
2331 /* Update the FreeBSD userspace ID register view */
2332 type = ((fields[j].type & MRS_FREEBSD) != 0) ?
2333 fields[j].type :
2334 (MRS_EXACT | (fields[j].type & MRS_SAFE_MASK));
2335 user_reg = update_special_reg_field(user_reg,
2336 type, value, fields[j].width, fields[j].shift,
2337 fields[j].sign);
2338
2339 /* Update the Linux userspace ID register view */
2340 type = ((fields[j].type & MRS_LINUX) != 0) ?
2341 fields[j].type :
2342 (MRS_EXACT | (fields[j].type & MRS_SAFE_MASK));
2343 l_user_reg = update_special_reg_field(l_user_reg,
2344 type, value, fields[j].width, fields[j].shift,
2345 fields[j].sign);
2346
2347 /* Update the kernel ID register view */
2348 kern_reg = update_special_reg_field(kern_reg,
2349 fields[j].type, value, fields[j].width,
2350 fields[j].shift, fields[j].sign);
2351 }
2352
2353 CPU_DESC_FIELD(kern_cpu_desc, i) = kern_reg;
2354 CPU_DESC_FIELD(user_cpu_desc, i) = user_reg;
2355 CPU_DESC_FIELD(l_user_cpu_desc, i) = l_user_reg;
2356 }
2357 }
2358
2359 void
cpu_desc_init(void)2360 cpu_desc_init(void)
2361 {
2362 if (mp_ncpus == 1)
2363 return;
2364
2365 /*
2366 * Allocate memory for the non-boot CPUs to store their registers.
2367 * As this is indexed by CPU ID we need to allocate space for CPUs
2368 * 1 to mp_maxid. Because of this mp_maxid is already the correct
2369 * number of elements.
2370 */
2371 cpu_desc = mallocarray(mp_maxid, sizeof(*cpu_desc), M_IDENTCPU,
2372 M_ZERO | M_WAITOK);
2373 }
2374
2375 /* HWCAP */
2376 bool __read_frequently lse_supported = false;
2377
2378 bool __read_frequently icache_aliasing = false;
2379 bool __read_frequently icache_vmid = false;
2380
2381 int64_t dcache_line_size; /* The minimum D cache line size */
2382 int64_t icache_line_size; /* The minimum I cache line size */
2383 int64_t idcache_line_size; /* The minimum cache line size */
2384
2385 /*
2386 * Find the values to export to userspace as AT_HWCAP and AT_HWCAP2.
2387 */
2388 static void
parse_cpu_features(bool is64bit,struct cpu_desc * cpu_desc,u_long * hwcap,u_long * hwcap2)2389 parse_cpu_features(bool is64bit, struct cpu_desc *cpu_desc, u_long *hwcap,
2390 u_long *hwcap2)
2391 {
2392 const struct mrs_field_hwcap *hwcaps;
2393 const struct mrs_field *fields;
2394 uint64_t min, reg;
2395 u_long *cur_hwcap;
2396 int i, j, k;
2397
2398 for (i = 0; i < nitems(user_regs); i++) {
2399 if (user_regs[i].is64bit != is64bit)
2400 continue;
2401
2402 reg = CPU_DESC_FIELD(*cpu_desc, i);
2403 fields = user_regs[i].fields;
2404 for (j = 0; fields[j].type != 0; j++) {
2405 hwcaps = fields[j].hwcaps;
2406 if (hwcaps == NULL)
2407 continue;
2408
2409 for (k = 0; hwcaps[k].hwcap_id != 0; k++) {
2410 KASSERT(hwcaps[k].hwcap_id == 1 ||
2411 hwcaps[k].hwcap_id == 2,
2412 ("%s: Invalid HWCAP ID %d", __func__,
2413 hwcaps[k].hwcap_id));
2414
2415 cur_hwcap = hwcaps[k].hwcap_id == 1 ?
2416 hwcap : hwcap2;
2417 min = hwcaps[k].min;
2418
2419 /*
2420 * If the field is greater than the minimum
2421 * value we can set the hwcap;
2422 */
2423 if (mrs_field_cmp(reg, min, fields[j].shift,
2424 4, fields[j].sign) >= 0) {
2425 *cur_hwcap |= hwcaps[k].hwcap_val;
2426 }
2427 }
2428 }
2429 }
2430 }
2431
2432 static void
identify_cpu_sysinit(void * dummy __unused)2433 identify_cpu_sysinit(void *dummy __unused)
2434 {
2435 struct cpu_desc *desc, *prev_desc;
2436 int cpu;
2437 bool dic, idc;
2438
2439 dic = (allow_dic != 0);
2440 idc = (allow_idc != 0);
2441
2442 prev_desc = NULL;
2443 CPU_FOREACH(cpu) {
2444 desc = get_cpu_desc(cpu);
2445 if (cpu != 0) {
2446 check_cpu_regs(cpu, desc, prev_desc);
2447 update_special_regs(cpu);
2448 }
2449
2450 if (CTR_DIC_VAL(desc->ctr) == 0)
2451 dic = false;
2452 if (CTR_IDC_VAL(desc->ctr) == 0)
2453 idc = false;
2454 prev_desc = desc;
2455 }
2456
2457 /* Find the values to export to userspace as AT_HWCAP and AT_HWCAP2 */
2458 parse_cpu_features(true, &user_cpu_desc, &elf_hwcap, &elf_hwcap2);
2459 parse_cpu_features(true, &l_user_cpu_desc, &linux_elf_hwcap,
2460 &linux_elf_hwcap2);
2461 #ifdef COMPAT_FREEBSD32
2462 parse_cpu_features(false, &user_cpu_desc, &elf32_hwcap, &elf32_hwcap2);
2463 #endif
2464
2465 /* We export the CPUID registers */
2466 elf_hwcap |= HWCAP_CPUID;
2467 linux_elf_hwcap |= HWCAP_CPUID;
2468
2469 #ifdef COMPAT_FREEBSD32
2470 /* Set the default caps and any that need to check multiple fields */
2471 elf32_hwcap |= parse_cpu_features_hwcap32();
2472 #endif
2473
2474 if (dic && idc) {
2475 arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range;
2476 if (bootverbose)
2477 printf("Enabling DIC & IDC ICache sync\n");
2478 } else if (idc) {
2479 arm64_icache_sync_range = &arm64_idc_aliasing_icache_sync_range;
2480 if (bootverbose)
2481 printf("Enabling IDC ICache sync\n");
2482 }
2483
2484 if ((elf_hwcap & HWCAP_ATOMICS) != 0) {
2485 lse_supported = true;
2486 if (bootverbose)
2487 printf("Enabling LSE atomics in the kernel\n");
2488 }
2489 #ifdef LSE_ATOMICS
2490 if (!lse_supported)
2491 panic("CPU does not support LSE atomic instructions");
2492 #endif
2493
2494 install_undef_handler(true, user_mrs_handler);
2495 }
2496 SYSINIT(identify_cpu, SI_SUB_CPU, SI_ORDER_MIDDLE, identify_cpu_sysinit, NULL);
2497
2498 static void
cpu_features_sysinit(void * dummy __unused)2499 cpu_features_sysinit(void *dummy __unused)
2500 {
2501 struct sbuf sb;
2502 struct cpu_desc *desc, *prev_desc;
2503 u_int cpu;
2504
2505 prev_desc = NULL;
2506 CPU_FOREACH(cpu) {
2507 desc = get_cpu_desc(cpu);
2508 print_cpu_features(cpu, desc, prev_desc);
2509 prev_desc = desc;
2510 }
2511
2512 /* Fill in cpu_model for the hw.model sysctl */
2513 sbuf_new(&sb, cpu_model, sizeof(cpu_model), SBUF_FIXEDLEN);
2514 print_cpu_midr(&sb, 0);
2515
2516 sbuf_finish(&sb);
2517 sbuf_delete(&sb);
2518
2519 free(cpu_desc, M_IDENTCPU);
2520 }
2521 /* Log features before APs are released and start printing to the dmesg. */
2522 SYSINIT(cpu_features, SI_SUB_SMP - 1, SI_ORDER_ANY, cpu_features_sysinit, NULL);
2523
2524 static void
tcr_set_e0pd1(void * arg __unused)2525 tcr_set_e0pd1(void *arg __unused)
2526 {
2527 uint64_t tcr;
2528
2529 tcr = READ_SPECIALREG(tcr_el1);
2530 tcr |= TCR_E0PD1;
2531 WRITE_SPECIALREG(tcr_el1, tcr);
2532 isb();
2533 }
2534
2535 /* Enable support for more recent architecture features */
2536 static void
cpu_feat_support(void * arg __unused)2537 cpu_feat_support(void *arg __unused)
2538 {
2539 /*
2540 * If FEAT_E0PD is supported use it to cause faults without a page
2541 * table walk if userspace tries to access kernel memory.
2542 */
2543 if (ID_AA64MMFR2_E0PD_VAL(kern_cpu_desc.id_aa64mmfr2) !=
2544 ID_AA64MMFR2_E0PD_NONE)
2545 smp_rendezvous(NULL, tcr_set_e0pd1, NULL, NULL);
2546 }
2547 SYSINIT(cpu_feat_support, SI_SUB_SMP, SI_ORDER_ANY, cpu_feat_support, NULL);
2548
2549 #ifdef COMPAT_FREEBSD32
2550 static u_long
parse_cpu_features_hwcap32(void)2551 parse_cpu_features_hwcap32(void)
2552 {
2553 u_long hwcap = HWCAP32_DEFAULT;
2554
2555 if ((MVFR1_SIMDLS_VAL(user_cpu_desc.mvfr1) >=
2556 MVFR1_SIMDLS_IMPL) &&
2557 (MVFR1_SIMDInt_VAL(user_cpu_desc.mvfr1) >=
2558 MVFR1_SIMDInt_IMPL) &&
2559 (MVFR1_SIMDSP_VAL(user_cpu_desc.mvfr1) >=
2560 MVFR1_SIMDSP_IMPL))
2561 hwcap |= HWCAP32_NEON;
2562
2563 return (hwcap);
2564 }
2565 #endif /* COMPAT_FREEBSD32 */
2566
2567 static void
print_register(struct sbuf * sb,const char * reg_name,uint64_t reg,void (* print_fields)(struct sbuf *,uint64_t,const void *),const void * arg)2568 print_register(struct sbuf *sb, const char *reg_name, uint64_t reg,
2569 void (*print_fields)(struct sbuf *, uint64_t, const void *),
2570 const void *arg)
2571 {
2572
2573 sbuf_printf(sb, "%29s = <", reg_name);
2574
2575 print_fields(sb, reg, arg);
2576
2577 sbuf_finish(sb);
2578 printf("%s>\n", sbuf_data(sb));
2579 sbuf_clear(sb);
2580 }
2581
2582 static void
print_id_fields(struct sbuf * sb,uint64_t reg,const void * arg)2583 print_id_fields(struct sbuf *sb, uint64_t reg, const void *arg)
2584 {
2585 const struct mrs_field *fields = arg;
2586 const struct mrs_field_value *fv;
2587 int field, i, j, printed;
2588
2589 #define SEP_STR ((printed++) == 0) ? "" : ","
2590 printed = 0;
2591 for (i = 0; fields[i].type != 0; i++) {
2592 fv = fields[i].values;
2593
2594 if (fv == NULL)
2595 goto next;
2596
2597 field = (reg & fields[i].mask) >> fields[i].shift;
2598 for (j = 0; fv[j].desc != NULL; j++) {
2599 if ((fv[j].value >> fields[i].shift) != field)
2600 continue;
2601
2602 if (fv[j].desc[0] != '\0')
2603 sbuf_printf(sb, "%s%s", SEP_STR, fv[j].desc);
2604 break;
2605 }
2606 if (fv[j].desc == NULL)
2607 sbuf_printf(sb, "%sUnknown %s(%x)", SEP_STR,
2608 fields[i].name, field);
2609
2610 next:
2611 reg &= ~(((1ul << fields[i].width) - 1) << fields[i].shift);
2612 }
2613
2614 if (reg != 0)
2615 sbuf_printf(sb, "%s%#lx", SEP_STR, reg);
2616 #undef SEP_STR
2617 }
2618
2619 static void
print_id_register(struct sbuf * sb,const char * reg_name,uint64_t reg,const struct mrs_field * fields)2620 print_id_register(struct sbuf *sb, const char *reg_name, uint64_t reg,
2621 const struct mrs_field *fields)
2622 {
2623
2624 print_register(sb, reg_name, reg, print_id_fields, fields);
2625 }
2626
2627 static void
print_cpu_midr(struct sbuf * sb,u_int cpu)2628 print_cpu_midr(struct sbuf *sb, u_int cpu)
2629 {
2630 const struct cpu_parts *cpu_partsp;
2631 const char *cpu_impl_name;
2632 const char *cpu_part_name;
2633 u_int midr;
2634 u_int impl_id;
2635 u_int part_id;
2636
2637 midr = pcpu_find(cpu)->pc_midr;
2638
2639 cpu_impl_name = NULL;
2640 cpu_partsp = NULL;
2641 impl_id = CPU_IMPL(midr);
2642 for (int i = 0; cpu_implementers[i].impl_name != NULL; i++) {
2643 if (impl_id == cpu_implementers[i].impl_id) {
2644 cpu_impl_name = cpu_implementers[i].impl_name;
2645 cpu_partsp = cpu_implementers[i].cpu_parts;
2646 break;
2647 }
2648 }
2649 /* Unknown implementer, so unknown part */
2650 if (cpu_impl_name == NULL) {
2651 sbuf_printf(sb, "Unknown Implementer (midr: %08x)", midr);
2652 return;
2653 }
2654
2655 KASSERT(cpu_partsp != NULL, ("%s: No parts table for implementer %s",
2656 __func__, cpu_impl_name));
2657
2658 cpu_part_name = NULL;
2659 part_id = CPU_PART(midr);
2660 for (int i = 0; cpu_partsp[i].part_name != NULL; i++) {
2661 if (part_id == cpu_partsp[i].part_id) {
2662 cpu_part_name = cpu_partsp[i].part_name;
2663 break;
2664 }
2665 }
2666 /* Known Implementer, Unknown part */
2667 if (cpu_part_name == NULL) {
2668 sbuf_printf(sb, "%s Unknown CPU r%dp%d (midr: %08x)",
2669 cpu_impl_name, CPU_VAR(midr), CPU_REV(midr), midr);
2670 return;
2671 }
2672
2673 sbuf_printf(sb, "%s %s r%dp%d", cpu_impl_name,
2674 cpu_part_name, CPU_VAR(midr), CPU_REV(midr));
2675 }
2676
2677 static void
print_cpu_cache(struct cpu_desc * desc,struct sbuf * sb,uint64_t ccs,bool icache,bool unified)2678 print_cpu_cache(struct cpu_desc *desc, struct sbuf *sb, uint64_t ccs,
2679 bool icache, bool unified)
2680 {
2681 size_t cache_size;
2682 size_t line_size;
2683
2684 /* LineSize is Log2(S) - 4. */
2685 line_size = 1 << ((ccs & CCSIDR_LineSize_MASK) + 4);
2686 /*
2687 * Calculate cache size (sets * ways * line size). There are different
2688 * formats depending on the FEAT_CCIDX bit in ID_AA64MMFR2 feature
2689 * register.
2690 */
2691 if ((desc->id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64))
2692 cache_size = (CCSIDR_NSETS_64(ccs) + 1) *
2693 (CCSIDR_ASSOC_64(ccs) + 1);
2694 else
2695 cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1);
2696
2697 cache_size *= line_size;
2698 sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024,
2699 icache ? "instruction" : unified ? "unified" : "data");
2700 }
2701
2702 static void
print_cpu_caches(struct sbuf * sb,struct cpu_desc * desc)2703 print_cpu_caches(struct sbuf *sb, struct cpu_desc *desc)
2704 {
2705 /* Print out each cache combination */
2706 uint64_t clidr;
2707 int i = 1;
2708 clidr = desc->clidr;
2709
2710 for (i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
2711 int j = 0;
2712 int ctype_m = (clidr & CLIDR_CTYPE_MASK);
2713
2714 sbuf_printf(sb, " L%d cache: ", i + 1);
2715 if ((clidr & CLIDR_CTYPE_IO)) {
2716 print_cpu_cache(desc, sb, desc->ccsidr[i][j++], true,
2717 false);
2718 /* If there's more, add to the line. */
2719 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0)
2720 sbuf_printf(sb, ", ");
2721 }
2722 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) {
2723 print_cpu_cache(desc, sb, desc->ccsidr[i][j], false,
2724 (clidr & CLIDR_CTYPE_UNIFIED));
2725 }
2726 sbuf_printf(sb, "\n");
2727
2728 }
2729 sbuf_finish(sb);
2730 printf("%s", sbuf_data(sb));
2731 }
2732
2733 static void
print_cpu_features(u_int cpu,struct cpu_desc * desc,struct cpu_desc * prev_desc)2734 print_cpu_features(u_int cpu, struct cpu_desc *desc,
2735 struct cpu_desc *prev_desc)
2736 {
2737 struct sbuf *sb;
2738
2739 sb = sbuf_new_auto();
2740 sbuf_printf(sb, "CPU%3u: ", cpu);
2741 print_cpu_midr(sb, cpu);
2742
2743 sbuf_cat(sb, " affinity:");
2744 switch(cpu_aff_levels) {
2745 default:
2746 case 4:
2747 sbuf_printf(sb, " %2d", CPU_AFF3(desc->mpidr));
2748 /* FALLTHROUGH */
2749 case 3:
2750 sbuf_printf(sb, " %2d", CPU_AFF2(desc->mpidr));
2751 /* FALLTHROUGH */
2752 case 2:
2753 sbuf_printf(sb, " %2d", CPU_AFF1(desc->mpidr));
2754 /* FALLTHROUGH */
2755 case 1:
2756 case 0: /* On UP this will be zero */
2757 sbuf_printf(sb, " %2d", CPU_AFF0(desc->mpidr));
2758 break;
2759 }
2760 sbuf_finish(sb);
2761 printf("%s\n", sbuf_data(sb));
2762 sbuf_clear(sb);
2763
2764 /*
2765 * There is a hardware errata where, if one CPU is performing a TLB
2766 * invalidation while another is performing a store-exclusive the
2767 * store-exclusive may return the wrong status. A workaround seems
2768 * to be to use an IPI to invalidate on each CPU, however given the
2769 * limited number of affected units (pass 1.1 is the evaluation
2770 * hardware revision), and the lack of information from Cavium
2771 * this has not been implemented.
2772 *
2773 * At the time of writing this the only information is from:
2774 * https://lkml.org/lkml/2016/8/4/722
2775 */
2776 /*
2777 * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also
2778 * triggers on pass 2.0+.
2779 */
2780 if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 &&
2781 CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1)
2782 printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known "
2783 "hardware bugs that may cause the incorrect operation of "
2784 "atomic operations.\n");
2785
2786 #define SHOULD_PRINT_REG(_reg) \
2787 (prev_desc == NULL || desc->_reg != prev_desc->_reg)
2788
2789 /* Cache Type Register */
2790 if (SHOULD_PRINT_REG(ctr))
2791 print_id_register(sb, "Cache Type", desc->ctr, ctr_fields);
2792
2793 /* AArch64 Instruction Set Attribute Register 0 */
2794 if (SHOULD_PRINT_REG(id_aa64isar0))
2795 print_id_register(sb, "Instruction Set Attributes 0",
2796 desc->id_aa64isar0, id_aa64isar0_fields);
2797
2798 /* AArch64 Instruction Set Attribute Register 1 */
2799 if (SHOULD_PRINT_REG(id_aa64isar1))
2800 print_id_register(sb, "Instruction Set Attributes 1",
2801 desc->id_aa64isar1, id_aa64isar1_fields);
2802
2803 /* AArch64 Instruction Set Attribute Register 2 */
2804 if (SHOULD_PRINT_REG(id_aa64isar2))
2805 print_id_register(sb, "Instruction Set Attributes 2",
2806 desc->id_aa64isar2, id_aa64isar2_fields);
2807
2808 /* AArch64 Processor Feature Register 0 */
2809 if (SHOULD_PRINT_REG(id_aa64pfr0))
2810 print_id_register(sb, "Processor Features 0",
2811 desc->id_aa64pfr0, id_aa64pfr0_fields);
2812
2813 /* AArch64 Processor Feature Register 1 */
2814 if (SHOULD_PRINT_REG(id_aa64pfr1))
2815 print_id_register(sb, "Processor Features 1",
2816 desc->id_aa64pfr1, id_aa64pfr1_fields);
2817
2818 /* AArch64 Processor Feature Register 2 */
2819 if (SHOULD_PRINT_REG(id_aa64pfr2))
2820 print_id_register(sb, "Processor Features 2",
2821 desc->id_aa64pfr2, id_aa64pfr2_fields);
2822
2823 /* AArch64 Memory Model Feature Register 0 */
2824 if (SHOULD_PRINT_REG(id_aa64mmfr0))
2825 print_id_register(sb, "Memory Model Features 0",
2826 desc->id_aa64mmfr0, id_aa64mmfr0_fields);
2827
2828 /* AArch64 Memory Model Feature Register 1 */
2829 if (SHOULD_PRINT_REG(id_aa64mmfr1))
2830 print_id_register(sb, "Memory Model Features 1",
2831 desc->id_aa64mmfr1, id_aa64mmfr1_fields);
2832
2833 /* AArch64 Memory Model Feature Register 2 */
2834 if (SHOULD_PRINT_REG(id_aa64mmfr2))
2835 print_id_register(sb, "Memory Model Features 2",
2836 desc->id_aa64mmfr2, id_aa64mmfr2_fields);
2837
2838 /* AArch64 Memory Model Feature Register 3 */
2839 if (SHOULD_PRINT_REG(id_aa64mmfr3))
2840 print_id_register(sb, "Memory Model Features 3",
2841 desc->id_aa64mmfr3, id_aa64mmfr3_fields);
2842
2843 /* AArch64 Memory Model Feature Register 4 */
2844 if (SHOULD_PRINT_REG(id_aa64mmfr4))
2845 print_id_register(sb, "Memory Model Features 4",
2846 desc->id_aa64mmfr4, id_aa64mmfr4_fields);
2847
2848 /* AArch64 Debug Feature Register 0 */
2849 if (SHOULD_PRINT_REG(id_aa64dfr0))
2850 print_id_register(sb, "Debug Features 0",
2851 desc->id_aa64dfr0, id_aa64dfr0_fields);
2852
2853 /* AArch64 Memory Model Feature Register 1 */
2854 if (SHOULD_PRINT_REG(id_aa64dfr1))
2855 print_id_register(sb, "Debug Features 1",
2856 desc->id_aa64dfr1, id_aa64dfr1_fields);
2857
2858 /* AArch64 Auxiliary Feature Register 0 */
2859 if (SHOULD_PRINT_REG(id_aa64afr0))
2860 print_id_register(sb, "Auxiliary Features 0",
2861 desc->id_aa64afr0, id_aa64afr0_fields);
2862
2863 /* AArch64 Auxiliary Feature Register 1 */
2864 if (SHOULD_PRINT_REG(id_aa64afr1))
2865 print_id_register(sb, "Auxiliary Features 1",
2866 desc->id_aa64afr1, id_aa64afr1_fields);
2867
2868 /* AArch64 SVE Feature Register 0 */
2869 if (desc->have_sve) {
2870 if (SHOULD_PRINT_REG(id_aa64zfr0) ||
2871 !prev_desc->have_sve) {
2872 print_id_register(sb, "SVE Features 0",
2873 desc->id_aa64zfr0, id_aa64zfr0_fields);
2874 }
2875 }
2876
2877 #ifdef COMPAT_FREEBSD32
2878 /* AArch32 Instruction Set Attribute Register 5 */
2879 if (SHOULD_PRINT_REG(id_isar5))
2880 print_id_register(sb, "AArch32 Instruction Set Attributes 5",
2881 desc->id_isar5, id_isar5_fields);
2882
2883 /* AArch32 Media and VFP Feature Register 0 */
2884 if (SHOULD_PRINT_REG(mvfr0))
2885 print_id_register(sb, "AArch32 Media and VFP Features 0",
2886 desc->mvfr0, mvfr0_fields);
2887
2888 /* AArch32 Media and VFP Feature Register 1 */
2889 if (SHOULD_PRINT_REG(mvfr1))
2890 print_id_register(sb, "AArch32 Media and VFP Features 1",
2891 desc->mvfr1, mvfr1_fields);
2892 #endif
2893 if (bootverbose)
2894 print_cpu_caches(sb, desc);
2895
2896 sbuf_delete(sb);
2897 sb = NULL;
2898 #undef SHOULD_PRINT_REG
2899 #undef SEP_STR
2900 }
2901
2902 void
identify_cache(uint64_t ctr)2903 identify_cache(uint64_t ctr)
2904 {
2905
2906 /* Identify the L1 cache type */
2907 switch (CTR_L1IP_VAL(ctr)) {
2908 case CTR_L1IP_PIPT:
2909 break;
2910 default:
2911 case CTR_L1IP_VIPT:
2912 icache_aliasing = true;
2913 break;
2914 }
2915
2916 if (dcache_line_size == 0) {
2917 KASSERT(icache_line_size == 0, ("%s: i-cacheline size set: %ld",
2918 __func__, icache_line_size));
2919
2920 /* Get the D cache line size */
2921 dcache_line_size = CTR_DLINE_SIZE(ctr);
2922 /* And the same for the I cache */
2923 icache_line_size = CTR_ILINE_SIZE(ctr);
2924
2925 idcache_line_size = MIN(dcache_line_size, icache_line_size);
2926 }
2927
2928 if (dcache_line_size != CTR_DLINE_SIZE(ctr)) {
2929 printf("WARNING: D-cacheline size mismatch %ld != %d\n",
2930 dcache_line_size, CTR_DLINE_SIZE(ctr));
2931 }
2932
2933 if (icache_line_size != CTR_ILINE_SIZE(ctr)) {
2934 printf("WARNING: I-cacheline size mismatch %ld != %d\n",
2935 icache_line_size, CTR_ILINE_SIZE(ctr));
2936 }
2937 }
2938
2939 void
identify_cpu(u_int cpu)2940 identify_cpu(u_int cpu)
2941 {
2942 struct cpu_desc *desc;
2943 uint64_t clidr;
2944
2945 desc = get_cpu_desc(cpu);
2946 /* Save affinity for current CPU */
2947 desc->mpidr = get_mpidr();
2948 CPU_AFFINITY(cpu) = desc->mpidr & CPU_AFF_MASK;
2949
2950 desc->ctr = READ_SPECIALREG(ctr_el0);
2951 desc->id_aa64dfr0 = READ_SPECIALREG(ID_AA64DFR0_EL1_REG);
2952 desc->id_aa64dfr1 = READ_SPECIALREG(ID_AA64DFR1_EL1_REG);
2953 desc->id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1_REG);
2954 desc->id_aa64isar1 = READ_SPECIALREG(ID_AA64ISAR1_EL1_REG);
2955 desc->id_aa64isar2 = READ_SPECIALREG(ID_AA64ISAR2_EL1_REG);
2956 desc->id_aa64mmfr0 = READ_SPECIALREG(ID_AA64MMFR0_EL1_REG);
2957 desc->id_aa64mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1_REG);
2958 desc->id_aa64mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1_REG);
2959 desc->id_aa64mmfr3 = READ_SPECIALREG(ID_AA64MMFR3_EL1_REG);
2960 desc->id_aa64mmfr4 = READ_SPECIALREG(ID_AA64MMFR4_EL1_REG);
2961 desc->id_aa64pfr0 = READ_SPECIALREG(ID_AA64PFR0_EL1_REG);
2962 desc->id_aa64pfr1 = READ_SPECIALREG(ID_AA64PFR1_EL1_REG);
2963 desc->id_aa64pfr2 = READ_SPECIALREG(ID_AA64PFR2_EL1_REG);
2964
2965 /*
2966 * ID_AA64ZFR0_EL1 is only valid when at least one of:
2967 * - ID_AA64PFR0_EL1.SVE is non-zero
2968 * - ID_AA64PFR1_EL1.SME is non-zero
2969 * In other cases it is zero, but still safe to read
2970 */
2971 desc->have_sve =
2972 (ID_AA64PFR0_SVE_VAL(desc->id_aa64pfr0) != 0);
2973 desc->id_aa64zfr0 = READ_SPECIALREG(ID_AA64ZFR0_EL1_REG);
2974
2975 desc->clidr = READ_SPECIALREG(clidr_el1);
2976
2977 clidr = desc->clidr;
2978
2979 for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
2980 int j = 0;
2981 if ((clidr & CLIDR_CTYPE_IO)) {
2982 WRITE_SPECIALREG(csselr_el1,
2983 CSSELR_Level(i) | CSSELR_InD);
2984 desc->ccsidr[i][j++] =
2985 READ_SPECIALREG(ccsidr_el1);
2986 }
2987 if ((clidr & ~CLIDR_CTYPE_IO) == 0)
2988 continue;
2989 WRITE_SPECIALREG(csselr_el1, CSSELR_Level(i));
2990 desc->ccsidr[i][j] = READ_SPECIALREG(ccsidr_el1);
2991 }
2992
2993 #ifdef COMPAT_FREEBSD32
2994 /* Only read aarch32 SRs if EL0-32 is available */
2995 if (ID_AA64PFR0_EL0_VAL(desc->id_aa64pfr0) == ID_AA64PFR0_EL0_64_32) {
2996 desc->id_isar5 = READ_SPECIALREG(id_isar5_el1);
2997 desc->mvfr0 = READ_SPECIALREG(mvfr0_el1);
2998 desc->mvfr1 = READ_SPECIALREG(mvfr1_el1);
2999 }
3000 #endif
3001 }
3002
3003 static void
check_cpu_regs(u_int cpu,struct cpu_desc * desc,struct cpu_desc * prev_desc)3004 check_cpu_regs(u_int cpu, struct cpu_desc *desc, struct cpu_desc *prev_desc)
3005 {
3006 switch (cpu_aff_levels) {
3007 case 0:
3008 if (CPU_AFF0(desc->mpidr) != CPU_AFF0(prev_desc->mpidr))
3009 cpu_aff_levels = 1;
3010 /* FALLTHROUGH */
3011 case 1:
3012 if (CPU_AFF1(desc->mpidr) != CPU_AFF1(prev_desc->mpidr))
3013 cpu_aff_levels = 2;
3014 /* FALLTHROUGH */
3015 case 2:
3016 if (CPU_AFF2(desc->mpidr) != CPU_AFF2(prev_desc->mpidr))
3017 cpu_aff_levels = 3;
3018 /* FALLTHROUGH */
3019 case 3:
3020 if (CPU_AFF3(desc->mpidr) != CPU_AFF3(prev_desc->mpidr))
3021 cpu_aff_levels = 4;
3022 break;
3023 }
3024
3025 if (desc->ctr != prev_desc->ctr) {
3026 /*
3027 * If the cache type register is different we may
3028 * have a different l1 cache type.
3029 */
3030 identify_cache(desc->ctr);
3031 }
3032 }
3033