xref: /titanic_41/usr/src/uts/common/sys/ib/adapters/tavor/tavor_cfg.h (revision 9e39c5ba00a55fa05777cc94b148296af305e135)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_IB_ADAPTERS_TAVOR_CFG_H
28 #define	_SYS_IB_ADAPTERS_TAVOR_CFG_H
29 
30 /*
31  * tavor_cfg.h
32  *    Contains some prototypes and the structure needed to provided the
33  *    Tavor Configuration Profile variables.
34  */
35 
36 #include <sys/types.h>
37 #include <sys/conf.h>
38 #include <sys/ddi.h>
39 #include <sys/sunddi.h>
40 
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 
45 /*
46  * The following define specifies the number of ports provided by the Tavor
47  * hardware.  While the Tavor hardware does have two ports, it is not always
48  * necessary to use both (and in some cases it may be desirable not to).
49  * This define is used to set the "tavor_num_ports" configuration variable.
50  * The only other legal value for "tavor_num_ports" (besides two) is one.  If
51  * that variable is set to one, then only port number 1 will be active and
52  * usable.  This define, however, should not be changed.
53  */
54 #define	TAVOR_NUM_PORTS			2
55 
56 /*
57  * DDR Sizes.  We support 256MB / 128MB DIMMs. These defines give us the
58  * size to check against in the cfg_profile_init.
59  */
60 #define	TAVOR_DDR_SIZE_256	(1 << 28)
61 #define	TAVOR_DDR_SIZE_128	(1 << 27)
62 
63 /*
64  * Minimal configuration value.
65  */
66 #define	TAVOR_DDR_SIZE_MIN	(1 << 25)
67 
68 /*
69  * The tavor_cfg_profile_t structure is used internally by the Tavor driver
70  * to hold all of the configuration information for the driver.  It contains
71  * information such as the maximum number (and size) of Tavor's queue pairs.
72  * completion queues, translation tables, etc.  It also contains configuration
73  * information such as whether the device is using agents in the Tavor
74  * firmware (i.e. SMA, PMA, BMA) or whether it must register with the IBMF
75  * for management requests.  Each of the fields is described below.
76  */
77 typedef struct tavor_cfg_profile_s {
78 	/* Number of supported QPs and their maximum size */
79 	uint32_t	cp_log_num_qp;
80 	uint32_t	cp_log_max_qp_sz;
81 
82 	/* Number of supported SGL per WQE */
83 	uint32_t	cp_wqe_max_sgl;
84 	uint32_t	cp_wqe_real_max_sgl;
85 
86 	/* Number of supported CQs and their maximum size */
87 	uint32_t	cp_log_num_cq;
88 	uint32_t	cp_log_max_cq_sz;
89 
90 	/* Select to enable SRQ or not; overrides the firmware setting */
91 	uint32_t	cp_srq_enable;
92 	uint32_t	cp_srq_wq_inddr;
93 
94 	/* Number of supported SRQs and their maximum size */
95 	uint32_t	cp_log_num_srq;
96 	uint32_t	cp_log_max_srq_sz;
97 	uint32_t	cp_srq_max_sgl;
98 
99 	/* Select to enable FMR or not */
100 	uint32_t	cp_fmr_enable;
101 
102 	/* The max remaps of a particular fmr */
103 	uint32_t	cp_fmr_max_remaps;
104 
105 	/* Default size for all EQs */
106 	uint32_t	cp_log_default_eq_sz;
107 
108 	/* Number of supported RDB (for incoming RDMA Read/Atomic) */
109 	uint32_t	cp_log_num_rdb;
110 
111 	/*
112 	 * Number of support multicast groups, number of QP per multicast
113 	 * group, and the number of entries (from the total number) in
114 	 * the multicast group "hash table"
115 	 */
116 	uint32_t	cp_log_num_mcg;
117 	uint32_t	cp_num_qp_per_mcg;
118 	uint32_t	cp_log_num_mcg_hash;
119 
120 	/*
121 	 * Number of supported MPTs (memory regions and windows) and their
122 	 * maximum size.  Also the number of MTT per "MTT segment" (see
123 	 * tavor_mr.h for more details)
124 	 */
125 	uint32_t	cp_log_num_mpt;
126 	uint32_t	cp_log_max_mrw_sz;
127 	uint32_t	cp_log_num_mttseg;
128 
129 	/*
130 	 * Number of supported Tavor mailboxes ("In" and "Out") and their
131 	 * maximum sizes, respectively
132 	 */
133 	uint32_t	cp_log_num_inmbox;
134 	uint32_t	cp_log_num_outmbox;
135 	uint32_t	cp_log_num_intr_inmbox;
136 	uint32_t	cp_log_num_intr_outmbox;
137 	uint32_t	cp_log_inmbox_size;
138 	uint32_t	cp_log_outmbox_size;
139 
140 	/* Number of supported UAR pages */
141 	uint32_t	cp_log_num_uar;
142 
143 	/* Number of supported Protection Domains (PD) */
144 	uint32_t	cp_log_num_pd;
145 
146 	/* Number of supported Address Handles (AH) */
147 	uint32_t	cp_log_num_ah;
148 
149 	/*
150 	 * Number of supported PKeys per PKey table (i.e. per port).  Also the
151 	 * number of SGID per GID table.
152 	 */
153 	uint32_t	cp_log_max_pkeytbl;
154 	uint32_t	cp_log_max_gidtbl;
155 
156 	/* Maximum "responder resources" and "initiator depth" per QP */
157 	uint32_t	cp_hca_max_rdma_in_qp;
158 	uint32_t	cp_hca_max_rdma_out_qp;
159 
160 	/* Maximum supported MTU and port width */
161 	uint32_t	cp_max_mtu;
162 	uint32_t	cp_max_port_width;
163 
164 	/* Number of supported Virtual Lanes (VL) */
165 	uint32_t	cp_max_vlcap;
166 
167 	/* Number of supported ports (1 or 2) */
168 	uint32_t	cp_num_ports;
169 
170 	/*
171 	 * Whether or not to use the built-in (i.e. in firmware) agents
172 	 * for QP0 and QP1, respectively
173 	 */
174 	uint32_t	cp_qp0_agents_in_fw;
175 	uint32_t	cp_qp1_agents_in_fw;
176 
177 	/*
178 	 * Whether DMA mappings should be made with DDI_DMA_STREAMING or
179 	 * with DDI_DMA_CONSISTENT mode
180 	 */
181 	uint32_t	cp_streaming_consistent;
182 
183 	/*
184 	 * Whether to override the necessity for ddi_dma_sync() calls on system
185 	 * memory which has been mapped DDI_DMA_CONSISTENT
186 	 */
187 	uint32_t	cp_consistent_syncoverride;
188 
189 	/* Whether DMA mappings should bypass the PCI IOMMU or not */
190 	uint32_t	cp_iommu_bypass;
191 	uint32_t	cp_disable_streaming_on_bypass;
192 
193 	/*
194 	 * Whether QP work queues should be allocated from system memory or
195 	 * from Tavor DDR memory
196 	 */
197 	uint32_t	cp_qp_wq_inddr;
198 
199 	/* Delay after software reset */
200 	uint32_t	cp_sw_reset_delay;
201 
202 	/* Time to wait in-between attempts to poll the 'go' bit */
203 	uint32_t	cp_cmd_poll_delay;
204 
205 	/* Max time to continue to poll the 'go bit */
206 	uint32_t	cp_cmd_poll_max;
207 
208 	/* Default AckReq frequency */
209 	uint32_t	cp_ackreq_freq;
210 
211 	/* Default maximum number of outstanding split transations */
212 	uint32_t	cp_max_out_splt_trans;
213 
214 	/* Default maximum number of bytes per read burst */
215 	uint32_t	cp_max_mem_rd_byte_cnt;
216 
217 	/* Specify whether to use MSI (if available) */
218 	uint32_t	cp_use_msi_if_avail;
219 
220 	/*
221 	 * Used to override SystemImageGUID, NodeGUID and PortGUID(s) as
222 	 * specified by the Tavor device node properties
223 	 */
224 	uint64_t	cp_sysimgguid;
225 	uint64_t	cp_nodeguid;
226 	uint64_t	cp_portguid[TAVOR_NUM_PORTS];
227 
228 } tavor_cfg_profile_t;
229 
230 int tavor_cfg_profile_init_phase1(tavor_state_t *state);
231 int tavor_cfg_profile_init_phase2(tavor_state_t *state);
232 void tavor_cfg_profile_fini(tavor_state_t *state);
233 
234 #ifdef __cplusplus
235 }
236 #endif
237 
238 #endif	/* _SYS_IB_ADAPTERS_TAVOR_CFG_H */
239