1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2001-2024, Intel Corporation
5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30
31 #ifndef _EM_H_DEFINED_
32 #define _EM_H_DEFINED_
33
34 #include "opt_ddb.h"
35 #include "opt_inet.h"
36 #include "opt_inet6.h"
37 #include "opt_rss.h"
38
39 #ifdef HAVE_KERNEL_OPTION_HEADERS
40 #include "opt_device_polling.h"
41 #endif
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #ifdef DDB
46 #include <sys/types.h>
47 #include <ddb/ddb.h>
48 #endif
49 #include <sys/buf_ring.h>
50 #include <sys/bus.h>
51 #include <sys/callout.h>
52 #include <sys/endian.h>
53 #include <sys/kernel.h>
54 #include <sys/kthread.h>
55 #include <sys/malloc.h>
56 #include <sys/mbuf.h>
57 #include <sys/module.h>
58 #include <sys/rman.h>
59 #include <sys/smp.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/sysctl.h>
63 #include <sys/taskqueue.h>
64 #include <sys/eventhandler.h>
65 #include <machine/bus.h>
66 #include <machine/resource.h>
67
68 #include <net/bpf.h>
69 #include <net/ethernet.h>
70 #include <net/if.h>
71 #include <net/if_var.h>
72 #include <net/if_arp.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
75 #include <net/iflib.h>
76 #include <net/rss_config.h>
77 #include <netinet/in_rss.h>
78
79 #include <net/if_types.h>
80 #include <net/if_vlan_var.h>
81
82 #include <netinet/in_systm.h>
83 #include <netinet/in.h>
84 #include <netinet/if_ether.h>
85 #include <netinet/ip.h>
86 #include <netinet/ip6.h>
87 #include <netinet/tcp.h>
88 #include <netinet/udp.h>
89
90 #include <machine/in_cksum.h>
91 #include <dev/led/led.h>
92 #include <dev/pci/pcivar.h>
93 #include <dev/pci/pcireg.h>
94
95 #include "e1000_api.h"
96 #include "e1000_82571.h"
97 #include "ifdi_if.h"
98
99 struct igb_vf;
100 struct igb_vf_mac_filter;
101
102 /* Tunables */
103
104 /*
105 * EM_MAX_TXD: Maximum number of Transmit Descriptors
106 * Valid Range: 80-256 for 82542 and 82543-based adapters
107 * 80-4096 for others
108 * Default Value: 1024
109 * This value is the number of transmit descriptors allocated by the driver.
110 * Increasing this value allows the driver to queue more transmits. Each
111 * descriptor is 16 bytes.
112 * Since TDLEN should be multiple of 128bytes, the number of transmit
113 * desscriptors should meet the following condition.
114 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
115 */
116 #define EM_MIN_TXD 128
117 #define EM_MAX_TXD 4096
118 #define EM_DEFAULT_TXD 1024
119 #define EM_DEFAULT_MULTI_TXD 4096
120 #define IGB_MAX_TXD 4096
121
122 /*
123 * EM_MAX_RXD - Maximum number of receive Descriptors
124 * Valid Range: 80-256 for 82542 and 82543-based adapters
125 * 80-4096 for others
126 * Default Value: 1024
127 * This value is the number of receive descriptors allocated by the driver.
128 * Increasing this value allows the driver to buffer more incoming packets.
129 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
130 * descriptor. The maximum MTU size is 16110.
131 * Since TDLEN should be multiple of 128bytes, the number of transmit
132 * desscriptors should meet the following condition.
133 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
134 */
135 #define EM_MIN_RXD 128
136 #define EM_MAX_RXD 4096
137 #define EM_DEFAULT_RXD 1024
138 #define EM_DEFAULT_MULTI_RXD 4096
139 #define IGB_MAX_RXD 4096
140 #define IGB_MAX_FRAME_SIZE 9234
141
142 /*
143 * EM_TIDV - Transmit Interrupt Delay Value
144 * Valid Range: 0-65535 (0=off)
145 * Default Value: 64
146 * This value delays the generation of transmit interrupts in units of
147 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
148 * efficiency if properly tuned for specific network traffic. If the
149 * system is reporting dropped transmits, this value may be set too high
150 * causing the driver to run out of available transmit descriptors.
151 */
152 #define EM_TIDV 64
153
154 /*
155 * EM_TADV - Transmit Absolute Interrupt Delay Value
156 * (Not valid for 82542/82543/82544)
157 * Valid Range: 0-65535 (0=off)
158 * Default Value: 64
159 * This value, in units of 1.024 microseconds, limits the delay in which a
160 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
161 * this value ensures that an interrupt is generated after the initial
162 * packet is sent on the wire within the set amount of time. Proper tuning,
163 * along with EM_TIDV, may improve traffic throughput in specific
164 * network conditions.
165 */
166 #define EM_TADV 64
167
168 /*
169 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
170 * Valid Range: 0-65535 (0=off)
171 * Default Value: 0
172 * This value delays the generation of receive interrupts in units of 1.024
173 * microseconds. Receive interrupt reduction can improve CPU efficiency if
174 * properly tuned for specific network traffic. Increasing this value adds
175 * extra latency to frame reception and can end up decreasing the throughput
176 * of TCP traffic. If the system is reporting dropped receives, this value
177 * may be set too high, causing the driver to run out of available receive
178 * descriptors.
179 *
180 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
181 * may hang (stop transmitting) under certain network conditions.
182 * If this occurs a WATCHDOG message is logged in the system
183 * event log. In addition, the controller is automatically reset,
184 * restoring the network connection. To eliminate the potential
185 * for the hang ensure that EM_RDTR is set to 0.
186 */
187 #define EM_RDTR 0
188
189 /*
190 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
191 * Valid Range: 0-65535 (0=off)
192 * Default Value: 64
193 * This value, in units of 1.024 microseconds, limits the delay in which a
194 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
195 * this value ensures that an interrupt is generated after the initial
196 * packet is received within the set amount of time. Proper tuning,
197 * along with EM_RDTR, may improve traffic throughput in specific network
198 * conditions.
199 */
200 #define EM_RADV 64
201
202 /*
203 * This parameter controls whether or not autonegotiation is enabled.
204 * 0 - Disable autonegotiation
205 * 1 - Enable autonegotiation
206 */
207 #define DO_AUTO_NEG 1
208
209 /*
210 * This parameter control whether or not the driver will wait for
211 * autonegotiation to complete.
212 * 1 - Wait for autonegotiation to complete
213 * 0 - Don't wait for autonegotiation to complete
214 */
215 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
216
217 /* Tunables -- End */
218
219 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
220 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
221 ADVERTISE_1000_FULL)
222
223 #define AUTO_ALL_MODES 0
224
225 /* PHY master/slave setting */
226 #define EM_MASTER_SLAVE e1000_ms_hw_default
227
228 /*
229 * Miscellaneous constants
230 */
231 #define EM_VENDOR_ID 0x8086
232 #define EM_FLASH 0x0014
233
234 #define EM_JUMBO_PBA 0x00000028
235 #define EM_DEFAULT_PBA 0x00000030
236 #define EM_SMARTSPEED_DOWNSHIFT 3
237 #define EM_SMARTSPEED_MAX 15
238 #define EM_MAX_LOOP 10
239
240 #define MAX_NUM_MULTICAST_ADDRESSES 128
241 #define PCI_ANY_ID (~0U)
242 #define ETHER_ALIGN 2
243 #define EM_FC_PAUSE_TIME 0x0680
244 #define EM_EEPROM_APME 0x400;
245 #define EM_82544_APME 0x0004;
246
247 /* Support AutoMediaDetect for Marvell M88 PHY in i354 */
248 #define IGB_MEDIA_RESET (1 << 0)
249
250 /* Define the interrupt rates and ITR helpers */
251 #define EM_INTS_4K 4000
252 #define EM_INTS_20K 20000
253 #define EM_INTS_70K 70000
254 #define EM_INTS_DEFAULT 8000
255 #define EM_INTS_MULTIPLIER 256
256 #define EM_ITR_DIVIDEND 1000000000
257 #define EM_INTS_TO_ITR(i) (EM_ITR_DIVIDEND/(i * EM_INTS_MULTIPLIER))
258 #define IGB_EITR_DIVIDEND 1000000
259 #define IGB_EITR_SHIFT 2
260 #define IGB_QVECTOR_MASK 0x7FFC
261 #define IGB_INTS_TO_EITR(i) \
262 (((IGB_EITR_DIVIDEND / (i)) << IGB_EITR_SHIFT) & IGB_QVECTOR_MASK)
263 #define IGB_EITR_TO_INTS(i) ((IGB_EITR_DIVIDEND << IGB_EITR_SHIFT) / \
264 ((i) & IGB_QVECTOR_MASK))
265
266 /*
267 * The average packet size calculation in em_ring_itr() yields an EITR
268 * interval field value. That field is quarter microsecond granular (see
269 * IGB_EITR_SHIFT), so an interval of V is 1000000 / (V / 4) interrupts per
270 * second.
271 */
272 #define EM_AIM_DIVIDEND (IGB_EITR_DIVIDEND << IGB_EITR_SHIFT)
273
274 #define IGB_LINK_ITR 2000
275 #define I210_LINK_DELAY 1000
276
277 #define IGB_TXPBSIZE 20408
278 #define IGB_HDR_BUF 128
279 #define IGB_PKTTYPE_MASK 0x0000FFF0
280 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
281
282 /*
283 * Driver state logic for the detection of a hung state
284 * in hardware. Set TX_HUNG whenever a TX packet is used
285 * (data is sent) and clear it when txeof() is invoked if
286 * any descriptors from the ring are cleaned/reclaimed.
287 * Increment internal counter if no descriptors are cleaned
288 * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES,
289 * reset adapter.
290 */
291 #define EM_TX_IDLE 0x00000000
292 #define EM_TX_BUSY 0x00000001
293 #define EM_TX_HUNG 0x80000000
294 #define EM_TX_MAXTRIES 10
295
296 #define PCICFG_DESC_RING_STATUS 0xe4
297 #define FLUSH_DESC_REQUIRED 0x100
298
299 #define EM_TX_PTHRESH 31
300 #define EM_TX_HTHRESH 1
301 #define EM_TX_WTHRESH 1
302
303 #define EM_RXDCTL_PTHRESH_MASK 0x0000003F
304 #define EM_RXDCTL_HTHRESH_MASK 0x00003F00
305 #define EM_RXDCTL_WTHRESH_MASK 0x003F0000
306 #define EM_RXDCTL_THRESH_MASK (EM_RXDCTL_PTHRESH_MASK | \
307 EM_RXDCTL_HTHRESH_MASK | \
308 EM_RXDCTL_WTHRESH_MASK)
309
310 #define EM_JUMBO_RX_PTHRESH 3
311 #define EM_JUMBO_RX_HTHRESH 1
312 #define EM_82574_RX_PTHRESH 32
313 #define EM_82574_RX_HTHRESH 4
314 #define EM_82574_RX_WTHRESH 4
315
316 #define IGB_RXDCTL_PTHRESH_MASK 0x0000001F
317 #define IGB_RXDCTL_HTHRESH_MASK 0x00001F00
318 #define IGB_RXDCTL_WTHRESH_MASK 0x001F0000
319 #define IGB_RXDCTL_THRESH_MASK (IGB_RXDCTL_PTHRESH_MASK | \
320 IGB_RXDCTL_HTHRESH_MASK | \
321 IGB_RXDCTL_WTHRESH_MASK)
322 #define IGB_82575_RXDCTL_THRESH_MASK 0x003F3F3F
323
324 #define IGB_RX_PTHRESH 8
325 #define I354_RX_PTHRESH 12
326 #define IGB_RX_HTHRESH 8
327 #define IGB_RX_WTHRESH 4
328 #define IGB_82576_RX_WTHRESH 1
329
330 #define IGB_TX_PTHRESH 8
331 #define I354_TX_PTHRESH 20
332 #define IGB_TX_HTHRESH 1
333
334 /*
335 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
336 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
337 * also optimize cache line size effect. H/W supports up to cache line size 128.
338 */
339 #define EM_DBA_ALIGN 128
340
341 /*
342 * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9
343 */
344 #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */
345 #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
346 #define TARC_MQ_FIX (1 << 23) | \
347 (1 << 24) | \
348 (1 << 25) /* Handle errata in MQ mode */
349 #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */
350
351 /* PCI Config defines */
352 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
353 #define EM_BAR_TYPE_MASK 0x00000001
354 #define EM_BAR_TYPE_MMEM 0x00000000
355 #define EM_BAR_TYPE_IO 0x00000001
356 #define EM_BAR_TYPE_FLASH 0x0014
357 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
358 #define EM_BAR_MEM_TYPE_MASK 0x00000006
359 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
360 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
361
362 /* Defines for printing debug information */
363 #define DEBUG_INIT 0
364 #define DEBUG_IOCTL 0
365 #define DEBUG_HW 0
366
367 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
368 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
369 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
370 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
371 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
372 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
373 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
374 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
375 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
376
377 #define EM_MAX_SCATTER 40
378 #define EM_VFTA_SIZE 128
379 #define EM_TSO_SIZE 65535
380 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
381 #define ETH_ZLEN 60
382
383 /* Offload bits in mbuf flag */
384 #define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \
385 CSUM_IP6_UDP | CSUM_IP6_TCP)
386 #define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \
387 CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \
388 CSUM_IP6_SCTP)
389
390 #define IGB_PKTTYPE_MASK 0x0000FFF0
391 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
392
393 /*
394 * 82574 has a nonstandard address for EIAC
395 * and since its only used in MSI-X, and in
396 * the em driver only 82574 uses MSI-X we can
397 * solve it just using this define.
398 */
399 #define EM_EIAC 0x000DC
400 /*
401 * 82574 only reports 3 MSI-X vectors by default;
402 * defines assisting with making it report 5 are
403 * located here.
404 */
405 #define EM_NVM_PCIE_CTRL 0x1B
406 #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT)
407 #define EM_NVM_MSIX_N_SHIFT 7
408
409 /*
410 * VFs use 32-bit counter that rolls over.
411 */
412 #define UPDATE_VF_REG(reg, last, cur) \
413 do { \
414 u32 new = E1000_READ_REG(&sc->hw, reg); \
415 cur += (u32)(new - last); \
416 last = new; \
417 } while (0)
418
419 struct e1000_softc;
420
421 struct em_int_delay_info {
422 struct e1000_softc *sc; /* Back-pointer to the sc struct */
423 int offset; /* Register offset to read/write */
424 int value; /* Current value in usecs */
425 };
426
427 /*
428 * The transmit ring, one per tx queue
429 */
430 struct tx_ring {
431 struct e1000_softc *sc;
432 struct e1000_tx_desc *tx_base;
433 uint64_t tx_paddr;
434 qidx_t *tx_rsq;
435 bool tx_tso; /* last tx was tso */
436 uint8_t me;
437 qidx_t tx_rs_cidx;
438 qidx_t tx_rs_pidx;
439 qidx_t tx_cidx_processed;
440 /* Interrupt resources */
441 void *tag;
442 struct resource *res;
443
444 /* Soft stats */
445 unsigned long tx_irq;
446
447 /*
448 * Free running AIM counters. The producer updates these while
449 * encapsulating packets, then publishes both together at the TX
450 * doorbell. The interrupt handler samples only the published value,
451 * so it cannot observe one counter without the other.
452 */
453 u32 tx_packets;
454 u32 tx_bytes;
455 uint64_t tx_aim_snapshot __aligned(8);
456 u32 tx_packets_last;
457 u32 tx_bytes_last;
458
459 /* Saved csum offloading context information */
460 int csum_flags;
461 int csum_lhlen;
462 int csum_iphlen;
463
464 int csum_thlen;
465 int csum_mss;
466 int csum_pktlen;
467
468 uint32_t csum_txd_upper;
469 uint32_t csum_txd_lower; /* last field */
470 };
471
472 static __inline void
em_aim_publish(struct tx_ring * txr)473 em_aim_publish(struct tx_ring *txr)
474 {
475 uint64_t snapshot;
476
477 snapshot = ((uint64_t)txr->tx_bytes << 32) | txr->tx_packets;
478 atomic_store_rel_64(&txr->tx_aim_snapshot, snapshot);
479 }
480
481 /*
482 * The Receive ring, one per rx queue
483 */
484 struct rx_ring {
485 struct e1000_softc *sc;
486 struct em_rx_queue *que;
487 u32 me;
488 u32 payload;
489 union e1000_rx_desc_extended *rx_base;
490 uint64_t rx_paddr;
491
492 /* Interrupt resources */
493 void *tag;
494 struct resource *res;
495 bool discard;
496
497 /* Soft stats */
498 unsigned long rx_irq;
499 unsigned long rx_discarded;
500
501 /*
502 * Free running AIM counters. RX publishes both together when iflib
503 * returns descriptors to hardware. The interrupt handler samples only
504 * the published value, so watchdog-driven RX processing cannot expose
505 * one counter without the other.
506 */
507 u32 rx_packets;
508 u32 rx_bytes;
509 uint64_t rx_aim_snapshot __aligned(8);
510 u32 rx_packets_last;
511 u32 rx_bytes_last;
512 };
513
514 static __inline void
em_aim_publish_rx(struct rx_ring * rxr)515 em_aim_publish_rx(struct rx_ring *rxr)
516 {
517 uint64_t snapshot;
518
519 snapshot = ((uint64_t)rxr->rx_bytes << 32) | rxr->rx_packets;
520 atomic_store_rel_64(&rxr->rx_aim_snapshot, snapshot);
521 }
522
523 struct em_tx_queue {
524 struct e1000_softc *sc;
525 u32 msix;
526 u32 eims; /* This queue's EIMS bit */
527 u32 me;
528 struct tx_ring txr;
529 };
530
531 struct em_rx_queue {
532 struct e1000_softc *sc;
533 u32 me;
534 u32 msix;
535 u32 eims;
536 u32 itr_setting;
537 struct rx_ring rxr;
538 u64 irqs;
539 struct if_irq que_irq;
540 };
541
542 /* Driver-observed link state and its publication barrier. */
543 enum em_link_state {
544 EM_LINK_STATE_DOWN = 0,
545 EM_LINK_STATE_DOWN_RESET_PENDING,
546 EM_LINK_STATE_UP,
547 EM_LINK_STATE_UP_RESET_PENDING,
548 };
549
550 /* Our softc structure */
551 struct e1000_softc {
552 struct e1000_hw hw;
553
554 if_softc_ctx_t shared;
555 if_ctx_t ctx;
556 #define tx_num_queues shared->isc_ntxqsets
557 #define rx_num_queues shared->isc_nrxqsets
558 #define intr_type shared->isc_intr
559 /* FreeBSD operating-system-specific structures. */
560 struct e1000_osdep osdep;
561 device_t dev;
562 struct cdev *led_dev;
563
564 struct em_tx_queue *tx_queues;
565 struct em_rx_queue *rx_queues;
566 struct if_irq irq;
567
568 struct resource *memory;
569 struct resource *flash;
570 struct resource *ioport;
571
572 struct resource *res;
573 void *tag;
574 u32 linkvec;
575 u32 ivars;
576
577 struct ifmedia *media;
578 int msix;
579 int if_flags;
580 int em_insert_vlan_header;
581 u32 ims;
582 bool allow_64bit_dma;
583 bool in_detach;
584
585 u32 flags;
586 /* Task for FAST handling */
587 struct grouptask link_task;
588
589 u16 num_vlans;
590 u32 txd_cmd;
591
592 u32 rx_mbuf_sz;
593
594 int enable_aim;
595 /* Management and WOL features */
596 u32 wol;
597 bool has_manage;
598 bool has_amt;
599
600 /* Multicast array memory */
601 u8 *mta;
602
603 /*
604 ** Shadow VFTA table, this is needed because
605 ** the real vlan filter table gets cleared during
606 ** a soft reset and the driver needs to be able
607 ** to repopulate it.
608 */
609 u32 shadow_vfta[EM_VFTA_SIZE];
610 u32 vf_vfta_stale[EM_VFTA_SIZE];
611 u32 vf_vfta_retry[EM_VFTA_SIZE];
612 sbintime_t vf_vlan_retry_deadline;
613 u16 vf_vlan_retry_cursor;
614
615 /* Info about the interface */
616 enum em_link_state link_state;
617 u16 fc;
618 u16 link_speed;
619 u16 link_duplex;
620 u32 smartspeed;
621 u32 dmac;
622 u32 pba;
623 int link_mask;
624 int tso_automasked;
625 u32 phy_hang_count;
626 u32 promisc_pending;
627 u32 stats_pending;
628 u32 fatal_error_state;
629 u32 fatal_error_icr;
630 u32 fatal_error_pbeccsts;
631 u32 fatal_error_peind;
632 u32 fatal_error_pcie;
633 u32 fatal_error_pcie_ecc;
634 u32 fatal_error_lan;
635 u32 fatal_error_dma_tx;
636 u32 fatal_error_dma_rx;
637 u32 fatal_error_dma_host;
638 u64 fatal_error_reset_count;
639 u64 fatal_error_lan_count;
640 u64 fatal_error_mng_count;
641 u64 fatal_error_pcie_count;
642 u64 fatal_error_dma_count;
643 u64 fatal_error_unknown_count;
644 u64 corrected_error_dma_count;
645 u64 corrected_error_pcie_tx_data_count;
646 u64 corrected_error_pcie_retry_count;
647 u64 corrected_error_pcie_other_count;
648 u64 corrected_error_packet_buffer_count;
649 u64 uncorrected_error_packet_buffer_count;
650 u64 uncorrected_error_dma_count;
651 u64 uncorrected_error_pcie_count;
652
653 #ifdef PCI_IOV
654 struct igb_vf *vfs;
655 struct igb_vf_mac_filter *vf_mac_filters;
656 struct callout iov_mbx_retry;
657 u32 iov_vfta[EM_VFTA_SIZE];
658 u32 iov_mdd_cause;
659 u32 iov_pending;
660 u32 iov_spoof_pending;
661 u32 iov_blocked_pending;
662 u32 iov_intr_drain_pending;
663 u32 iov_teardown;
664 struct timeval iov_last_mdd_log;
665 u16 num_vfs;
666 u16 num_vf_mac_filters;
667 u16 pool;
668 bool iov_hw_active;
669 bool iov_mta_valid;
670 bool iov_mbx_retry_initialized;
671 bool iov_pf_mdd_blocked;
672 bool iov_pf_vlan_promisc;
673 bool iov_vfta_valid;
674 #endif
675
676 u64 que_mask;
677
678 /* We need to store this at attach due to e1000 hw/sw locking model */
679 struct e1000_fw_version fw_ver;
680
681 struct em_int_delay_info tx_int_delay;
682 struct em_int_delay_info tx_abs_int_delay;
683 struct em_int_delay_info rx_int_delay;
684 struct em_int_delay_info rx_abs_int_delay;
685 struct em_int_delay_info tx_itr;
686
687 /* Misc stats maintained by the driver */
688 unsigned long dropped_pkts;
689 unsigned long link_irq;
690 unsigned long rx_overruns;
691 u64 rx_csum_good;
692 u64 rx_csum_errors;
693
694 union {
695 struct e1000_hw_stats stats; /* !sc->vf_ifp */
696 struct e1000_vf_stats vf_stats; /* sc->vf_ifp */
697 } ustats;
698
699 struct callout vf_queue_retry;
700 struct callout vf_mbx_retry;
701 struct timeval vf_last_queue_log;
702 struct timeval vf_last_mbx_log;
703 u32 vf_queue_retry_new_epoch;
704 u32 vf_queue_retry_pending;
705 u32 vf_mbx_ready;
706 u32 vf_mbx_retry_pending;
707 u16 vf_ifp;
708 u8 vf_queue_failures;
709 u8 vf_mbx_retry_stage;
710 bool vf_queue_gave_up;
711 bool vf_queue_retry_initialized;
712 bool vf_mbx_retry_initialized;
713 bool vf_queues_sanitized;
714 bool vf_reset_pending;
715 /* A PF can retain auxiliary filters across a VF reset. */
716 bool vf_uc_filters_set;
717 };
718
719 /*
720 * Shared PF/VF mechanisms and VF policy entry points. The latter live in
721 * if_igbv.c so the VF method table cannot accidentally select PF policy.
722 */
723 int em_if_attach_pre(if_ctx_t);
724 int em_if_attach_post(if_ctx_t);
725 void em_add_device_sysctls(struct e1000_softc *);
726 int em_if_set_promisc_impl(if_ctx_t, int);
727 bool em_is_valid_ether_addr(const u8 *);
728 void em_initialize_transmit_rings(if_ctx_t);
729 void em_update_stats_counters(struct e1000_softc *);
730 void igb_initialize_receive_rings(if_ctx_t, bool);
731
732 int igbv_get_regs(SYSCTL_HANDLER_ARGS);
733 int igbv_if_attach_pre(if_ctx_t);
734 int igbv_if_attach_post(if_ctx_t);
735 int igbv_if_media_change(if_ctx_t);
736 void igbv_if_intr_enable(if_ctx_t);
737 void igbv_if_intr_disable(if_ctx_t);
738 void igbv_if_update_admin_status(if_ctx_t);
739 void igbv_initialize_receive_unit(if_ctx_t);
740 void igbv_initialize_transmit_unit(if_ctx_t);
741 void igbv_mbx_retry_detach(struct e1000_softc *);
742 void igbv_mbx_retry_failed(if_ctx_t);
743 void igbv_mbx_retry_prepare(struct e1000_softc *);
744 void igbv_mbx_retry_stop(struct e1000_softc *);
745 void igbv_queue_retry_detach(struct e1000_softc *);
746 void igbv_queue_retry_failed(if_ctx_t);
747 void igbv_queue_retry_prepare(struct e1000_softc *);
748 void igbv_queue_retry_stop(struct e1000_softc *);
749 void igbv_reconcile_mac(struct e1000_softc *, if_t);
750 bool igbv_reset(if_ctx_t);
751 void igbv_log_reset_failure(struct e1000_softc *, s32, bool);
752 void igbv_update_uc_addr_list(struct e1000_softc *, if_t);
753 void igbv_vlan_retry_add(struct e1000_softc *, u16);
754 void igbv_vlan_retry_clear(struct e1000_softc *, u16);
755
756 /********************************************************************************
757 * vendor_info_array
758 *
759 * This array contains the list of Subvendor/Subdevice IDs on which the driver
760 * should load.
761 *
762 ********************************************************************************/
763 typedef struct _em_vendor_info_t {
764 unsigned int vendor_id;
765 unsigned int device_id;
766 unsigned int subvendor_id;
767 unsigned int subdevice_id;
768 unsigned int index;
769 } em_vendor_info_t;
770
771 void em_dump_rs(struct e1000_softc *);
772
773 #define EM_RSSRK_SIZE 4
774 #define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \
775 key[(i) * EM_RSSRK_SIZE + 1] << 8 | \
776 key[(i) * EM_RSSRK_SIZE + 2] << 16 | \
777 key[(i) * EM_RSSRK_SIZE + 3] << 24)
778 #endif /* _EM_H_DEFINED_ */
779