1 /*-
2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/rman.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <machine/bus.h>
40
41 #include <arm64/coresight/coresight.h>
42
43 static struct mtx cs_mtx;
44 struct coresight_device_list cs_devs;
45
46 int
coresight_register(struct coresight_desc * desc)47 coresight_register(struct coresight_desc *desc)
48 {
49 struct coresight_device *cs_dev;
50
51 cs_dev = malloc(sizeof(struct coresight_device),
52 M_CORESIGHT, M_WAITOK | M_ZERO);
53 cs_dev->dev = desc->dev;
54 cs_dev->pdata = desc->pdata;
55 cs_dev->dev_type = desc->dev_type;
56
57 mtx_lock(&cs_mtx);
58 TAILQ_INSERT_TAIL(&cs_devs, cs_dev, link);
59 mtx_unlock(&cs_mtx);
60
61 return (0);
62 }
63
64 struct endpoint *
coresight_get_output_endpoint(struct coresight_platform_data * pdata)65 coresight_get_output_endpoint(struct coresight_platform_data *pdata)
66 {
67 struct endpoint *endp;
68
69 if (pdata->out_ports != 1)
70 return (NULL);
71
72 TAILQ_FOREACH(endp, &pdata->endpoints, link) {
73 if (endp->input == 0)
74 return (endp);
75 }
76
77 return (NULL);
78 }
79
80 struct coresight_device *
coresight_get_output_device(struct endpoint * endp,struct endpoint ** out_endp)81 coresight_get_output_device(struct endpoint *endp, struct endpoint **out_endp)
82 {
83 struct coresight_platform_data *pdata;
84 struct coresight_device *cs_dev;
85 struct endpoint *endp2;
86
87 TAILQ_FOREACH(cs_dev, &cs_devs, link) {
88 pdata = cs_dev->pdata;
89 TAILQ_FOREACH(endp2, &cs_dev->pdata->endpoints, link) {
90 switch (pdata->bus_type) {
91 case CORESIGHT_BUS_FDT:
92 #ifdef FDT
93 if (endp->their_node == endp2->my_node) {
94 *out_endp = endp2;
95 return (cs_dev);
96 }
97 #endif
98 break;
99
100 case CORESIGHT_BUS_ACPI:
101 #ifdef DEV_ACPI
102 if (endp->their_handle == endp2->my_handle) {
103 *out_endp = endp2;
104 return (cs_dev);
105 }
106 #endif
107 break;
108 }
109 }
110 }
111
112 return (NULL);
113 }
114
115 static void
coresight_init(void)116 coresight_init(void)
117 {
118
119 mtx_init(&cs_mtx, "ARM Coresight", NULL, MTX_DEF);
120 TAILQ_INIT(&cs_devs);
121 }
122
123 SYSINIT(coresight, SI_SUB_DRIVERS, SI_ORDER_FIRST, coresight_init, NULL);
124