1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright 2023 Mobileye Vision Technologies Ltd. 4 */ 5 6#include <dt-bindings/clock/mobileye,eyeq5-clk.h> 7 8/ { 9 /* Fixed clock */ 10 xtal: xtal { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <30000000>; 14 }; 15 16/* PLL_CPU derivatives */ 17 occ_cpu: occ-cpu { 18 compatible = "fixed-factor-clock"; 19 clocks = <&olb EQ5C_PLL_CPU>; 20 #clock-cells = <0>; 21 clock-div = <1>; 22 clock-mult = <1>; 23 }; 24 si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ 25 compatible = "fixed-factor-clock"; 26 clocks = <&occ_cpu>; 27 #clock-cells = <0>; 28 clock-div = <1>; 29 clock-mult = <1>; 30 }; 31 cpc_clk: cpc-clk { 32 compatible = "fixed-factor-clock"; 33 clocks = <&si_css0_ref_clk>; 34 #clock-cells = <0>; 35 clock-div = <1>; 36 clock-mult = <1>; 37 }; 38 core0_clk: core0-clk { 39 compatible = "fixed-factor-clock"; 40 clocks = <&si_css0_ref_clk>; 41 #clock-cells = <0>; 42 clock-div = <1>; 43 clock-mult = <1>; 44 }; 45 core1_clk: core1-clk { 46 compatible = "fixed-factor-clock"; 47 clocks = <&si_css0_ref_clk>; 48 #clock-cells = <0>; 49 clock-div = <1>; 50 clock-mult = <1>; 51 }; 52 core2_clk: core2-clk { 53 compatible = "fixed-factor-clock"; 54 clocks = <&si_css0_ref_clk>; 55 #clock-cells = <0>; 56 clock-div = <1>; 57 clock-mult = <1>; 58 }; 59 core3_clk: core3-clk { 60 compatible = "fixed-factor-clock"; 61 clocks = <&si_css0_ref_clk>; 62 #clock-cells = <0>; 63 clock-div = <1>; 64 clock-mult = <1>; 65 }; 66 cm_clk: cm-clk { 67 compatible = "fixed-factor-clock"; 68 clocks = <&si_css0_ref_clk>; 69 #clock-cells = <0>; 70 clock-div = <1>; 71 clock-mult = <1>; 72 }; 73 mem_clk: mem-clk { 74 compatible = "fixed-factor-clock"; 75 clocks = <&si_css0_ref_clk>; 76 #clock-cells = <0>; 77 clock-div = <1>; 78 clock-mult = <1>; 79 }; 80 occ_isram: occ-isram { 81 compatible = "fixed-factor-clock"; 82 clocks = <&olb EQ5C_PLL_CPU>; 83 #clock-cells = <0>; 84 clock-div = <2>; 85 clock-mult = <1>; 86 }; 87 isram_clk: isram-clk { /* gate ClkRstGen_isram */ 88 compatible = "fixed-factor-clock"; 89 clocks = <&occ_isram>; 90 #clock-cells = <0>; 91 clock-div = <1>; 92 clock-mult = <1>; 93 }; 94 occ_dbu: occ-dbu { 95 compatible = "fixed-factor-clock"; 96 clocks = <&olb EQ5C_PLL_CPU>; 97 #clock-cells = <0>; 98 clock-div = <10>; 99 clock-mult = <1>; 100 }; 101 si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ 102 compatible = "fixed-factor-clock"; 103 clocks = <&occ_dbu>; 104 #clock-cells = <0>; 105 clock-div = <1>; 106 clock-mult = <1>; 107 }; 108/* PLL_VDI derivatives */ 109 occ_vdi: occ-vdi { 110 compatible = "fixed-factor-clock"; 111 clocks = <&olb EQ5C_PLL_VDI>; 112 #clock-cells = <0>; 113 clock-div = <2>; 114 clock-mult = <1>; 115 }; 116 vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ 117 compatible = "fixed-factor-clock"; 118 clocks = <&occ_vdi>; 119 #clock-cells = <0>; 120 clock-div = <1>; 121 clock-mult = <1>; 122 }; 123 occ_can_ser: occ-can-ser { 124 compatible = "fixed-factor-clock"; 125 clocks = <&olb EQ5C_PLL_VDI>; 126 #clock-cells = <0>; 127 clock-div = <16>; 128 clock-mult = <1>; 129 }; 130 can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ 131 compatible = "fixed-factor-clock"; 132 clocks = <&occ_can_ser>; 133 #clock-cells = <0>; 134 clock-div = <1>; 135 clock-mult = <1>; 136 }; 137 i2c_ser_clk: i2c-ser-clk { 138 compatible = "fixed-factor-clock"; 139 clocks = <&olb EQ5C_PLL_VDI>; 140 #clock-cells = <0>; 141 clock-div = <20>; 142 clock-mult = <1>; 143 }; 144/* PLL_PER derivatives */ 145 occ_periph: occ-periph { 146 compatible = "fixed-factor-clock"; 147 clocks = <&olb EQ5C_PLL_PER>; 148 #clock-cells = <0>; 149 clock-div = <16>; 150 clock-mult = <1>; 151 }; 152 periph_clk: periph-clk { 153 compatible = "fixed-factor-clock"; 154 clocks = <&occ_periph>; 155 #clock-cells = <0>; 156 clock-div = <1>; 157 clock-mult = <1>; 158 }; 159 can_clk: can-clk { 160 compatible = "fixed-factor-clock"; 161 clocks = <&occ_periph>; 162 #clock-cells = <0>; 163 clock-div = <1>; 164 clock-mult = <1>; 165 }; 166 spi_clk: spi-clk { 167 compatible = "fixed-factor-clock"; 168 clocks = <&occ_periph>; 169 #clock-cells = <0>; 170 clock-div = <1>; 171 clock-mult = <1>; 172 }; 173 uart_clk: uart-clk { 174 compatible = "fixed-factor-clock"; 175 clocks = <&occ_periph>; 176 #clock-cells = <0>; 177 clock-div = <1>; 178 clock-mult = <1>; 179 }; 180 i2c_clk: i2c-clk { 181 compatible = "fixed-factor-clock"; 182 clocks = <&occ_periph>; 183 #clock-cells = <0>; 184 clock-div = <1>; 185 clock-mult = <1>; 186 clock-output-names = "i2c_clk"; 187 }; 188 timer_clk: timer-clk { 189 compatible = "fixed-factor-clock"; 190 clocks = <&occ_periph>; 191 #clock-cells = <0>; 192 clock-div = <1>; 193 clock-mult = <1>; 194 clock-output-names = "timer_clk"; 195 }; 196 gpio_clk: gpio-clk { 197 compatible = "fixed-factor-clock"; 198 clocks = <&occ_periph>; 199 #clock-cells = <0>; 200 clock-div = <1>; 201 clock-mult = <1>; 202 clock-output-names = "gpio_clk"; 203 }; 204 emmc_sys_clk: emmc-sys-clk { 205 compatible = "fixed-factor-clock"; 206 clocks = <&olb EQ5C_PLL_PER>; 207 #clock-cells = <0>; 208 clock-div = <10>; 209 clock-mult = <1>; 210 clock-output-names = "emmc_sys_clk"; 211 }; 212 ccf_ctrl_clk: ccf-ctrl-clk { 213 compatible = "fixed-factor-clock"; 214 clocks = <&olb EQ5C_PLL_PER>; 215 #clock-cells = <0>; 216 clock-div = <4>; 217 clock-mult = <1>; 218 clock-output-names = "ccf_ctrl_clk"; 219 }; 220 occ_mjpeg_core: occ-mjpeg-core { 221 compatible = "fixed-factor-clock"; 222 clocks = <&olb EQ5C_PLL_PER>; 223 #clock-cells = <0>; 224 clock-div = <2>; 225 clock-mult = <1>; 226 clock-output-names = "occ_mjpeg_core"; 227 }; 228 hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ 229 compatible = "fixed-factor-clock"; 230 clocks = <&occ_mjpeg_core>; 231 #clock-cells = <0>; 232 clock-div = <1>; 233 clock-mult = <1>; 234 clock-output-names = "hsm_clk"; 235 }; 236 mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ 237 compatible = "fixed-factor-clock"; 238 clocks = <&occ_mjpeg_core>; 239 #clock-cells = <0>; 240 clock-div = <1>; 241 clock-mult = <1>; 242 clock-output-names = "mjpeg_core_clk"; 243 }; 244 fcmu_a_clk: fcmu-a-clk { 245 compatible = "fixed-factor-clock"; 246 clocks = <&olb EQ5C_PLL_PER>; 247 #clock-cells = <0>; 248 clock-div = <20>; 249 clock-mult = <1>; 250 clock-output-names = "fcmu_a_clk"; 251 }; 252 occ_pci_sys: occ-pci-sys { 253 compatible = "fixed-factor-clock"; 254 clocks = <&olb EQ5C_PLL_PER>; 255 #clock-cells = <0>; 256 clock-div = <8>; 257 clock-mult = <1>; 258 clock-output-names = "occ_pci_sys"; 259 }; 260 pclk: pclk { 261 compatible = "fixed-clock"; 262 #clock-cells = <0>; 263 clock-frequency = <250000000>; /* 250MHz */ 264 }; 265 tsu_clk: tsu-clk { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 clock-frequency = <125000000>; /* 125MHz */ 269 }; 270}; 271