1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
3
4 #ifndef __SOUNDWIRE_H
5 #define __SOUNDWIRE_H
6
7 #include <linux/bitfield.h>
8 #include <linux/bug.h>
9 #include <linux/completion.h>
10 #include <linux/device.h>
11 #include <linux/idr.h>
12 #include <linux/irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/lockdep_types.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/mutex.h>
17 #include <linux/types.h>
18 #include <sound/sdca.h>
19
20 struct dentry;
21 struct fwnode_handle;
22
23 struct sdw_bus;
24 struct sdw_slave;
25
26 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
27
28 /* SDW Broadcast Device Number */
29 #define SDW_BROADCAST_DEV_NUM 15
30
31 /* SDW Enumeration Device Number */
32 #define SDW_ENUM_DEV_NUM 0
33
34 /* SDW Group Device Numbers */
35 #define SDW_GROUP12_DEV_NUM 12
36 #define SDW_GROUP13_DEV_NUM 13
37
38 /* SDW Master Device Number, not supported yet */
39 #define SDW_MASTER_DEV_NUM 14
40
41 #define SDW_NUM_DEV_ID_REGISTERS 6
42 /* frame shape defines */
43
44 /*
45 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
46 * fill hole with 0, one more dummy entry is added
47 */
48 #define SDW_FRAME_ROWS 24
49 #define SDW_FRAME_COLS 8
50 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
51
52 #define SDW_FRAME_CTRL_BITS 48
53 #define SDW_MAX_DEVICES 11
54 #define SDW_FW_MAX_DEVICES 16
55
56 #define SDW_MAX_PORTS 15
57 #define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1)
58
59 #define SDW_MAX_LANES 8
60
61 enum {
62 SDW_PORT_DIRN_SINK = 0,
63 SDW_PORT_DIRN_SOURCE,
64 SDW_PORT_DIRN_MAX,
65 };
66
67 /*
68 * constants for flow control, ports and transport
69 *
70 * these are bit masks as devices can have multiple capabilities
71 */
72
73 /*
74 * flow modes for SDW port. These can be isochronous, tx controlled,
75 * rx controlled or async
76 */
77 #define SDW_PORT_FLOW_MODE_ISOCH 0
78 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
79 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
80 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
81
82 /* sample packaging for block. It can be per port or per channel */
83 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
84 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
85
86 /**
87 * enum sdw_slave_status - Slave status
88 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
89 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
90 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
91 * @SDW_SLAVE_RESERVED: Reserved for future use
92 */
93 enum sdw_slave_status {
94 SDW_SLAVE_UNATTACHED = 0,
95 SDW_SLAVE_ATTACHED = 1,
96 SDW_SLAVE_ALERT = 2,
97 SDW_SLAVE_RESERVED = 3,
98 };
99
100 /**
101 * enum sdw_clk_stop_type: clock stop operations
102 *
103 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
104 * @SDW_CLK_POST_PREPARE: post clock stop prepare
105 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
106 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
107 */
108 enum sdw_clk_stop_type {
109 SDW_CLK_PRE_PREPARE = 0,
110 SDW_CLK_POST_PREPARE,
111 SDW_CLK_PRE_DEPREPARE,
112 SDW_CLK_POST_DEPREPARE,
113 };
114
115 /**
116 * enum sdw_command_response - Command response as defined by SDW spec
117 * @SDW_CMD_OK: cmd was successful
118 * @SDW_CMD_IGNORED: cmd was ignored
119 * @SDW_CMD_FAIL: cmd was NACKed
120 * @SDW_CMD_TIMEOUT: cmd timedout
121 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
122 *
123 * NOTE: The enum is different than actual Spec as response in the Spec is
124 * combination of ACK/NAK bits
125 *
126 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
127 */
128 enum sdw_command_response {
129 SDW_CMD_OK = 0,
130 SDW_CMD_IGNORED = 1,
131 SDW_CMD_FAIL = 2,
132 SDW_CMD_TIMEOUT = 3,
133 SDW_CMD_FAIL_OTHER = 4,
134 };
135
136 /* block group count enum */
137 enum sdw_dpn_grouping {
138 SDW_BLK_GRP_CNT_1 = 0,
139 SDW_BLK_GRP_CNT_2 = 1,
140 SDW_BLK_GRP_CNT_3 = 2,
141 SDW_BLK_GRP_CNT_4 = 3,
142 };
143
144 /* block packing mode enum */
145 enum sdw_dpn_pkg_mode {
146 SDW_BLK_PKG_PER_PORT = 0,
147 SDW_BLK_PKG_PER_CHANNEL = 1
148 };
149
150 /**
151 * enum sdw_stream_type: data stream type
152 *
153 * @SDW_STREAM_PCM: PCM data stream
154 * @SDW_STREAM_PDM: PDM data stream
155 * @SDW_STREAM_BPT: BPT data stream
156 *
157 * spec doesn't define this, but is used in implementation
158 */
159 enum sdw_stream_type {
160 SDW_STREAM_PCM = 0,
161 SDW_STREAM_PDM = 1,
162 SDW_STREAM_BPT = 2,
163 };
164
165 /**
166 * enum sdw_data_direction: Data direction
167 *
168 * @SDW_DATA_DIR_RX: Data into Port
169 * @SDW_DATA_DIR_TX: Data out of Port
170 */
171 enum sdw_data_direction {
172 SDW_DATA_DIR_RX = 0,
173 SDW_DATA_DIR_TX = 1,
174 };
175
176 /**
177 * enum sdw_port_data_mode: Data Port mode
178 *
179 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
180 * and transmitted.
181 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
182 * a pseudo random data pattern that is transferred
183 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
184 * logic 0. The encoding will result in no signal transitions
185 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
186 * logic 1. The encoding will result in signal transitions at every bitslot
187 * owned by this Port
188 */
189 enum sdw_port_data_mode {
190 SDW_PORT_DATA_MODE_NORMAL = 0,
191 SDW_PORT_DATA_MODE_PRBS = 1,
192 SDW_PORT_DATA_MODE_STATIC_0 = 2,
193 SDW_PORT_DATA_MODE_STATIC_1 = 3,
194 };
195
196 /*
197 * SDW properties, defined in MIPI DisCo spec v1.0
198 */
199 enum sdw_clk_stop_reset_behave {
200 SDW_CLK_STOP_KEEP_STATUS = 1,
201 };
202
203 /**
204 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
205 * read
206 * @SDW_P15_READ_IGNORED: Read is ignored
207 * @SDW_P15_CMD_OK: Command is ok
208 */
209 enum sdw_p15_behave {
210 SDW_P15_READ_IGNORED = 0,
211 SDW_P15_CMD_OK = 1,
212 };
213
214 /**
215 * enum sdw_dpn_type - Data port types
216 * @SDW_DPN_FULL: Full Data Port is supported
217 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
218 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
219 * are not implemented.
220 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
221 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
222 */
223 enum sdw_dpn_type {
224 SDW_DPN_FULL = 0,
225 SDW_DPN_SIMPLE = 1,
226 SDW_DPN_REDUCED = 2,
227 };
228
229 /**
230 * enum sdw_clk_stop_mode - Clock Stop modes
231 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
232 * restart
233 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
234 * not capable of continuing operation seamlessly when the clock restarts
235 */
236 enum sdw_clk_stop_mode {
237 SDW_CLK_STOP_MODE0 = 0,
238 SDW_CLK_STOP_MODE1 = 1,
239 };
240
241 /**
242 * struct sdw_dp0_prop - DP0 properties
243 * @words: wordlengths supported
244 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
245 * (inclusive)
246 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
247 * (inclusive)
248 * @num_words: number of wordlengths supported
249 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
250 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
251 * response
252 * @simple_ch_prep_sm: If channel prepare sequence is required
253 * @imp_def_interrupts: If set, each bit corresponds to support for
254 * implementation-defined interrupts
255 * @num_lanes: array size of @lane_list
256 * @lane_list: indicates which Lanes can be used by DP0
257 *
258 * The wordlengths are specified by Spec as max, min AND number of
259 * discrete values, implementation can define based on the wordlengths they
260 * support
261 */
262 struct sdw_dp0_prop {
263 u32 *words;
264 u32 max_word;
265 u32 min_word;
266 u32 num_words;
267 u32 ch_prep_timeout;
268 bool BRA_flow_controlled;
269 bool simple_ch_prep_sm;
270 bool imp_def_interrupts;
271 int num_lanes;
272 u32 *lane_list;
273 };
274
275 /**
276 * struct sdw_dpn_prop - Data Port DPn properties
277 * @num: port number
278 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
279 * (inclusive)
280 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
281 * (inclusive)
282 * @num_words: Number of discrete supported wordlengths
283 * @words: Discrete supported wordlength
284 * @type: Data port type. Full, Simplified or Reduced
285 * @max_grouping: Maximum number of samples that can be grouped together for
286 * a full data port
287 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
288 * @imp_def_interrupts: If set, each bit corresponds to support for
289 * implementation-defined interrupts
290 * @max_ch: Maximum channels supported
291 * @min_ch: Minimum channels supported
292 * @num_channels: Number of discrete channels supported
293 * @num_ch_combinations: Number of channel combinations supported
294 * @channels: Discrete channels supported
295 * @ch_combinations: Channel combinations supported
296 * @lane_list: indicates which Lanes can be used by DPn
297 * @num_lanes: array size of @lane_list
298 * @modes: SDW mode supported
299 * @max_async_buffer: Number of samples that this port can buffer in
300 * asynchronous modes
301 * @port_encoding: Payload Channel Sample encoding schemes supported
302 * @block_pack_mode: Type of block port mode supported
303 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register
304 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
305 * machine
306 */
307 struct sdw_dpn_prop {
308 u32 num;
309 u32 max_word;
310 u32 min_word;
311 u32 num_words;
312 u32 *words;
313 enum sdw_dpn_type type;
314 u32 max_grouping;
315 u32 ch_prep_timeout;
316 u32 imp_def_interrupts;
317 u32 max_ch;
318 u32 min_ch;
319 u32 num_channels;
320 u32 num_ch_combinations;
321 u32 *channels;
322 u32 *ch_combinations;
323 u32 *lane_list;
324 int num_lanes;
325 u32 modes;
326 u32 max_async_buffer;
327 u32 port_encoding;
328 bool block_pack_mode;
329 bool read_only_wordlength;
330 bool simple_ch_prep_sm;
331 };
332
333 /**
334 * struct sdw_slave_prop - SoundWire Slave properties
335 * @dp0_prop: Data Port 0 properties
336 * @src_dpn_prop: Source Data Port N properties
337 * @sink_dpn_prop: Sink Data Port N properties
338 * @mipi_revision: Spec version of the implementation
339 * @wake_capable: Wake-up events are supported
340 * @test_mode_capable: If test mode is supported
341 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
342 * @simple_clk_stop_capable: Simple clock mode is supported
343 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
344 * Machine transitions, in milliseconds
345 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
346 * transitions, in milliseconds
347 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
348 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
349 * @high_PHY_capable: Slave is HighPHY capable
350 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
351 * SCP_AddrPage2
352 * @bank_delay_support: Slave implements bank delay/bridge support registers
353 * SCP_BankDelay and SCP_NextFrame
354 * @lane_control_support: Slave supports lane control
355 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
356 * alias
357 * @master_count: Number of Masters present on this Slave
358 * @source_ports: Bitmap identifying source ports
359 * @sink_ports: Bitmap identifying sink ports
360 * @quirks: bitmask identifying deltas from the MIPI specification
361 * @sdca_interrupt_register_list: indicates which sets of SDCA interrupt status
362 * and masks are supported
363 * @commit_register_supported: is PCP_Commit register supported
364 * @scp_int1_mask: SCP_INT1_MASK desired settings
365 * @lane_maps: Lane mapping for the slave, only valid if lane_control_support is set
366 * @clock_reg_supported: the Peripheral implements the clock base and scale
367 * registers introduced with the SoundWire 1.2 specification. SDCA devices
368 * do not need to set this boolean property as the registers are required.
369 * @use_domain_irq: call actual IRQ handler on slave, as well as callback
370 */
371 struct sdw_slave_prop {
372 struct sdw_dp0_prop *dp0_prop;
373 struct sdw_dpn_prop *src_dpn_prop;
374 struct sdw_dpn_prop *sink_dpn_prop;
375 u32 mipi_revision;
376 bool wake_capable;
377 bool test_mode_capable;
378 bool clk_stop_mode1;
379 bool simple_clk_stop_capable;
380 u32 clk_stop_timeout;
381 u32 ch_prep_timeout;
382 enum sdw_clk_stop_reset_behave reset_behave;
383 bool high_PHY_capable;
384 bool paging_support;
385 bool bank_delay_support;
386 bool lane_control_support;
387 enum sdw_p15_behave p15_behave;
388 u32 master_count;
389 u32 source_ports;
390 u32 sink_ports;
391 u32 quirks;
392 u32 sdca_interrupt_register_list;
393 u8 commit_register_supported;
394 u8 scp_int1_mask;
395 u8 lane_maps[SDW_MAX_LANES];
396 bool clock_reg_supported;
397 bool use_domain_irq;
398 };
399
400 #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0)
401
402 /**
403 * struct sdw_master_prop - Master properties
404 * @clk_gears: Clock gears supported
405 * @clk_freq: Clock frequencies supported, in Hz
406 * @quirks: bitmask identifying optional behavior beyond the scope of the MIPI specification
407 * @revision: MIPI spec version of the implementation
408 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
409 * @max_clk_freq: Maximum Bus clock frequency, in Hz
410 * @num_clk_gears: Number of clock gears supported
411 * @num_clk_freq: Number of clock frequencies supported, in Hz
412 * @default_frame_rate: Controller default Frame rate, in Hz
413 * @default_row: Number of rows
414 * @default_col: Number of columns
415 * @dynamic_frame: Dynamic frame shape supported
416 * @err_threshold: Number of times that software may retry sending a single
417 * command
418 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
419 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
420 */
421 struct sdw_master_prop {
422 u32 *clk_gears;
423 u32 *clk_freq;
424 u64 quirks;
425 u32 revision;
426 u32 clk_stop_modes;
427 u32 max_clk_freq;
428 u32 num_clk_gears;
429 u32 num_clk_freq;
430 u32 default_frame_rate;
431 u32 default_row;
432 u32 default_col;
433 u32 err_threshold;
434 u32 mclk_freq;
435 bool dynamic_frame;
436 bool hw_disabled;
437 };
438
439 /* Definitions for Master quirks */
440
441 /*
442 * In a number of platforms bus clashes are reported after a hardware
443 * reset but without any explanations or evidence of a real problem.
444 * The following quirk will discard all initial bus clash interrupts
445 * but will leave the detection on should real bus clashes happen
446 */
447 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH BIT(0)
448
449 /*
450 * Some Slave devices have known issues with incorrect parity errors
451 * reported after a hardware reset. However during integration unexplained
452 * parity errors can be reported by Slave devices, possibly due to electrical
453 * issues at the Master level.
454 * The following quirk will discard all initial parity errors but will leave
455 * the detection on should real parity errors happen.
456 */
457 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY BIT(1)
458
459 int sdw_master_read_prop(struct sdw_bus *bus);
460 int sdw_slave_read_prop(struct sdw_slave *slave);
461 int sdw_slave_read_lane_mapping(struct sdw_slave *slave);
462
463 /*
464 * SDW Slave Structures and APIs
465 */
466
467 #define SDW_IGNORED_UNIQUE_ID 0xFF
468
469 /**
470 * struct sdw_slave_id - Slave ID
471 * @mfg_id: MIPI Manufacturer ID
472 * @part_id: Device Part ID
473 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec)
474 * @unique_id: Device unique ID
475 * @sdw_version: SDW version implemented
476 *
477 * The order of the IDs here does not follow the DisCo spec definitions
478 */
479 struct sdw_slave_id {
480 __u16 mfg_id;
481 __u16 part_id;
482 __u8 class_id;
483 __u8 unique_id;
484 __u8 sdw_version:4;
485 };
486
487 struct sdw_peripherals {
488 int num_peripherals;
489 struct sdw_slave *array[];
490 };
491
492 /*
493 * Helper macros to extract the MIPI-defined IDs
494 *
495 * Spec definition
496 * Register Bit Contents
497 * DevId_0 [7:4] 47:44 sdw_version
498 * DevId_0 [3:0] 43:40 unique_id
499 * DevId_1 39:32 mfg_id [15:8]
500 * DevId_2 31:24 mfg_id [7:0]
501 * DevId_3 23:16 part_id [15:8]
502 * DevId_4 15:08 part_id [7:0]
503 * DevId_5 07:00 class_id
504 *
505 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48
506 */
507 #define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48)
508 #define SDW_VERSION_MASK GENMASK_ULL(47, 44)
509 #define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40)
510 #define SDW_MFG_ID_MASK GENMASK_ULL(39, 24)
511 #define SDW_PART_ID_MASK GENMASK_ULL(23, 8)
512 #define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0)
513
514 #define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr)
515 #define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr)
516 #define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr)
517 #define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr)
518 #define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr)
519 #define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr)
520
521 /**
522 * struct sdw_slave_intr_status - Slave interrupt status
523 * @sdca_cascade: set if the Slave device reports an SDCA interrupt
524 * @control_port: control port status
525 * @port: data port status
526 */
527 struct sdw_slave_intr_status {
528 bool sdca_cascade;
529 u8 control_port;
530 u8 port[15];
531 };
532
533 /**
534 * sdw_reg_bank - SoundWire register banks
535 * @SDW_BANK0: Soundwire register bank 0
536 * @SDW_BANK1: Soundwire register bank 1
537 */
538 enum sdw_reg_bank {
539 SDW_BANK0,
540 SDW_BANK1,
541 };
542
543 /**
544 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
545 *
546 * @num: Port number
547 * @ch_mask: Active channel mask
548 * @prepare: Prepare (true) /de-prepare (false) channel
549 * @bank: Register bank, which bank Slave/Master driver should program for
550 * implementation defined registers. This is always updated to next_bank
551 * value read from bus params.
552 *
553 */
554 struct sdw_prepare_ch {
555 unsigned int num;
556 unsigned int ch_mask;
557 bool prepare;
558 unsigned int bank;
559 };
560
561 /**
562 * enum sdw_port_prep_ops: Prepare operations for Data Port
563 *
564 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
565 * @SDW_OPS_PORT_PRE_DEPREP: Pre deprepare operation for the Port
566 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
567 * @SDW_OPS_PORT_POST_DEPREP: Post deprepare operation for the Port
568 */
569 enum sdw_port_prep_ops {
570 SDW_OPS_PORT_PRE_PREP = 0,
571 SDW_OPS_PORT_PRE_DEPREP,
572 SDW_OPS_PORT_POST_PREP,
573 SDW_OPS_PORT_POST_DEPREP,
574 };
575
576 /**
577 * struct sdw_bus_params: Structure holding bus configuration
578 *
579 * @curr_bank: Current bank in use (BANK0/BANK1)
580 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
581 * set to !curr_bank
582 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
583 * @curr_dr_freq: Current double rate clock frequency, in Hz
584 * @bandwidth: Current bandwidth
585 * @col: Active columns
586 * @row: Active rows
587 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports
588 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value
589 * should be the same to detect transmission issues, but can be different to
590 * test the interrupt reports
591 */
592 struct sdw_bus_params {
593 enum sdw_reg_bank curr_bank;
594 enum sdw_reg_bank next_bank;
595 unsigned int max_dr_freq;
596 unsigned int curr_dr_freq;
597 unsigned int bandwidth;
598 unsigned int col;
599 unsigned int row;
600 int s_data_mode;
601 int m_data_mode;
602 };
603
604 /**
605 * struct sdw_slave_ops: Slave driver callback ops
606 *
607 * @read_prop: Read Slave properties
608 * @interrupt_callback: Device interrupt notification (invoked in thread
609 * context)
610 * @update_status: Update Slave status
611 * @bus_config: Update the bus config for Slave
612 * @port_prep: Prepare the port with parameters
613 * @clk_stop: handle imp-def sequences before and after prepare and de-prepare
614 */
615 struct sdw_slave_ops {
616 int (*read_prop)(struct sdw_slave *sdw);
617 int (*interrupt_callback)(struct sdw_slave *slave,
618 struct sdw_slave_intr_status *status);
619 int (*update_status)(struct sdw_slave *slave,
620 enum sdw_slave_status status);
621 int (*bus_config)(struct sdw_slave *slave,
622 struct sdw_bus_params *params);
623 int (*port_prep)(struct sdw_slave *slave,
624 struct sdw_prepare_ch *prepare_ch,
625 enum sdw_port_prep_ops pre_ops);
626 int (*clk_stop)(struct sdw_slave *slave,
627 enum sdw_clk_stop_mode mode,
628 enum sdw_clk_stop_type type);
629 };
630
631 /**
632 * struct sdw_slave - SoundWire Slave
633 * @id: MIPI device ID
634 * @dev: Linux device
635 * @index: internal ID for this slave
636 * @irq: IRQ number
637 * @status: Status reported by the Slave
638 * @bus: Bus handle
639 * @prop: Slave properties
640 * @debugfs: Slave debugfs
641 * @node: node for bus list
642 * @port_ready: Port ready completion flag for each Slave port
643 * @m_port_map: static Master port map for each Slave port
644 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky
645 * @dev_num_sticky: one-time static Device Number assigned by Bus
646 * @probed: boolean tracking driver state
647 * @enumeration_complete: completion utility to control potential races
648 * on startup between device enumeration and read/write access to the
649 * Slave device
650 * @initialization_complete: completion utility to control potential races
651 * on startup between device enumeration and settings being restored
652 * @unattach_request: mask field to keep track why the Slave re-attached and
653 * was re-initialized. This is useful to deal with potential race conditions
654 * between the Master suspending and the codec resuming, and make sure that
655 * when the Master triggered a reset the Slave is properly enumerated and
656 * initialized
657 * @first_interrupt_done: status flag tracking if the interrupt handling
658 * for a Slave happens for the first time after enumeration
659 * @is_mockup_device: status flag used to squelch errors in the command/control
660 * protocol for SoundWire mockup devices
661 * @sdw_dev_lock: mutex used to protect callbacks/remove races
662 * @sdca_data: structure containing all device data for SDCA helpers
663 */
664 struct sdw_slave {
665 struct sdw_slave_id id;
666 struct device dev;
667 int index;
668 int irq;
669 enum sdw_slave_status status;
670 struct sdw_bus *bus;
671 struct sdw_slave_prop prop;
672 #ifdef CONFIG_DEBUG_FS
673 struct dentry *debugfs;
674 #endif
675 struct list_head node;
676 struct completion port_ready[SDW_MAX_PORTS];
677 unsigned int m_port_map[SDW_MAX_PORTS];
678 u16 dev_num;
679 u16 dev_num_sticky;
680 bool probed;
681 struct completion enumeration_complete;
682 struct completion initialization_complete;
683 u32 unattach_request;
684 bool first_interrupt_done;
685 bool is_mockup_device;
686 struct mutex sdw_dev_lock; /* protect callbacks/remove races */
687 struct sdca_device_data sdca_data;
688 };
689
690 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
691
692 /**
693 * struct sdw_master_device - SoundWire 'Master Device' representation
694 * @dev: Linux device for this Master
695 * @bus: Bus handle shortcut
696 */
697 struct sdw_master_device {
698 struct device dev;
699 struct sdw_bus *bus;
700 };
701
702 #define dev_to_sdw_master_device(d) \
703 container_of(d, struct sdw_master_device, dev)
704
705 struct sdw_driver {
706 int (*probe)(struct sdw_slave *sdw, const struct sdw_device_id *id);
707 int (*remove)(struct sdw_slave *sdw);
708 void (*shutdown)(struct sdw_slave *sdw);
709
710 const struct sdw_device_id *id_table;
711 const struct sdw_slave_ops *ops;
712
713 struct device_driver driver;
714 };
715
716 #define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \
717 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
718 .sdw_version = (_version), .class_id = (_c_id), \
719 .driver_data = (unsigned long)(_drv_data) }
720
721 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
722 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data))
723
724 int sdw_handle_slave_status(struct sdw_bus *bus,
725 enum sdw_slave_status status[]);
726
727 /*
728 * SDW master structures and APIs
729 */
730
731 /**
732 * struct sdw_port_params: Data Port parameters
733 *
734 * @num: Port number
735 * @bps: Word length of the Port
736 * @flow_mode: Port Data flow mode
737 * @data_mode: Test modes or normal mode
738 *
739 * This is used to program the Data Port based on Data Port stream
740 * parameters.
741 */
742 struct sdw_port_params {
743 unsigned int num;
744 unsigned int bps;
745 unsigned int flow_mode;
746 unsigned int data_mode;
747 };
748
749 /**
750 * struct sdw_transport_params: Data Port Transport Parameters
751 *
752 * @blk_grp_ctrl_valid: Port implements block group control
753 * @num: Port number
754 * @blk_grp_ctrl: Block group control value
755 * @sample_interval: Sample interval
756 * @offset1: Blockoffset of the payload data
757 * @offset2: Blockoffset of the payload data
758 * @hstart: Horizontal start of the payload data
759 * @hstop: Horizontal stop of the payload data
760 * @blk_pkg_mode: Block per channel or block per port
761 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
762 * data lane is supported in bus
763 *
764 * This is used to program the Data Port based on Data Port transport
765 * parameters. All these parameters are banked and can be modified
766 * during a bank switch without any artifacts in audio stream.
767 */
768 struct sdw_transport_params {
769 bool blk_grp_ctrl_valid;
770 unsigned int port_num;
771 unsigned int blk_grp_ctrl;
772 unsigned int sample_interval;
773 unsigned int offset1;
774 unsigned int offset2;
775 unsigned int hstart;
776 unsigned int hstop;
777 unsigned int blk_pkg_mode;
778 unsigned int lane_ctrl;
779 };
780
781 /**
782 * struct sdw_enable_ch: Enable/disable Data Port channel
783 *
784 * @num: Port number
785 * @ch_mask: Active channel mask
786 * @enable: Enable (true) /disable (false) channel
787 */
788 struct sdw_enable_ch {
789 unsigned int port_num;
790 unsigned int ch_mask;
791 bool enable;
792 };
793
794 /**
795 * struct sdw_master_port_ops: Callback functions from bus to Master
796 * driver to set Master Data ports.
797 *
798 * @dpn_set_port_params: Set the Port parameters for the Master Port.
799 * Mandatory callback
800 * @dpn_set_port_transport_params: Set transport parameters for the Master
801 * Port. Mandatory callback
802 * @dpn_port_prep: Port prepare operations for the Master Data Port.
803 * @dpn_port_enable_ch: Enable the channels of Master Port.
804 */
805 struct sdw_master_port_ops {
806 int (*dpn_set_port_params)(struct sdw_bus *bus,
807 struct sdw_port_params *port_params,
808 unsigned int bank);
809 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
810 struct sdw_transport_params *transport_params,
811 enum sdw_reg_bank bank);
812 int (*dpn_port_prep)(struct sdw_bus *bus, struct sdw_prepare_ch *prepare_ch);
813 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
814 struct sdw_enable_ch *enable_ch, unsigned int bank);
815 };
816
817 struct sdw_msg;
818
819 /**
820 * struct sdw_defer - SDW deferred message
821 * @complete: message completion
822 * @msg: SDW message
823 * @length: message length
824 */
825 struct sdw_defer {
826 struct sdw_msg *msg;
827 int length;
828 struct completion complete;
829 };
830
831 /*
832 * Add a practical limit to BPT transfer sizes. BPT is typically used
833 * to transfer firmware, and larger firmware transfers will increase
834 * the cold latency beyond typical OS or user requirements.
835 */
836 #define SDW_BPT_MSG_MAX_BYTES (1024 * 1024)
837
838 struct sdw_bpt_msg;
839
840 /**
841 * struct sdw_master_ops - Master driver ops
842 * @read_prop: Read Master properties
843 * @override_adr: Override value read from firmware (quirk for buggy firmware)
844 * @xfer_msg: Transfer message callback
845 * @xfer_msg_defer: Defer version of transfer message callback. The message is handled with the
846 * bus struct @sdw_defer
847 * @set_bus_conf: Set the bus configuration
848 * @pre_bank_switch: Callback for pre bank switch
849 * @post_bank_switch: Callback for post bank switch
850 * @read_ping_status: Read status from PING frames, reported with two bits per Device.
851 * Bits 31:24 are reserved.
852 * @get_device_num: Callback for vendor-specific device_number allocation
853 * @put_device_num: Callback for vendor-specific device_number release
854 * @new_peripheral_assigned: Callback to handle enumeration of new peripheral.
855 * @bpt_send_async: reserve resources for BPT stream and send message
856 * using BTP protocol
857 * @bpt_wait: wait for message completion using BTP protocol
858 * and release resources
859 */
860 struct sdw_master_ops {
861 int (*read_prop)(struct sdw_bus *bus);
862 u64 (*override_adr)(struct sdw_bus *bus, u64 addr);
863 enum sdw_command_response (*xfer_msg)(struct sdw_bus *bus, struct sdw_msg *msg);
864 enum sdw_command_response (*xfer_msg_defer)(struct sdw_bus *bus);
865 int (*set_bus_conf)(struct sdw_bus *bus,
866 struct sdw_bus_params *params);
867 int (*pre_bank_switch)(struct sdw_bus *bus);
868 int (*post_bank_switch)(struct sdw_bus *bus);
869 u32 (*read_ping_status)(struct sdw_bus *bus);
870 int (*get_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
871 void (*put_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
872 void (*new_peripheral_assigned)(struct sdw_bus *bus,
873 struct sdw_slave *slave,
874 int dev_num);
875 int (*bpt_send_async)(struct sdw_bus *bus, struct sdw_slave *slave,
876 struct sdw_bpt_msg *msg);
877 int (*bpt_wait)(struct sdw_bus *bus, struct sdw_slave *slave, struct sdw_bpt_msg *msg);
878 };
879
880 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
881 struct fwnode_handle *fwnode);
882 void sdw_bus_master_delete(struct sdw_bus *bus);
883
884 void sdw_show_ping_status(struct sdw_bus *bus, bool sync_delay);
885
886 /**
887 * sdw_port_config: Master or Slave Port configuration
888 *
889 * @num: Port number
890 * @ch_mask: channels mask for port
891 */
892 struct sdw_port_config {
893 unsigned int num;
894 unsigned int ch_mask;
895 };
896
897 /**
898 * sdw_stream_config: Master or Slave stream configuration
899 *
900 * @frame_rate: Audio frame rate of the stream, in Hz
901 * @ch_count: Channel count of the stream
902 * @bps: Number of bits per audio sample
903 * @direction: Data direction
904 * @type: Stream type PCM, PDM or BPT
905 */
906 struct sdw_stream_config {
907 unsigned int frame_rate;
908 unsigned int ch_count;
909 unsigned int bps;
910 enum sdw_data_direction direction;
911 enum sdw_stream_type type;
912 };
913
914 /**
915 * sdw_stream_state: Stream states
916 *
917 * @SDW_STREAM_ALLOCATED: New stream allocated.
918 * @SDW_STREAM_CONFIGURED: Stream configured
919 * @SDW_STREAM_PREPARED: Stream prepared
920 * @SDW_STREAM_ENABLED: Stream enabled
921 * @SDW_STREAM_DISABLED: Stream disabled
922 * @SDW_STREAM_DEPREPARED: Stream de-prepared
923 * @SDW_STREAM_RELEASED: Stream released
924 */
925 enum sdw_stream_state {
926 SDW_STREAM_ALLOCATED = 0,
927 SDW_STREAM_CONFIGURED = 1,
928 SDW_STREAM_PREPARED = 2,
929 SDW_STREAM_ENABLED = 3,
930 SDW_STREAM_DISABLED = 4,
931 SDW_STREAM_DEPREPARED = 5,
932 SDW_STREAM_RELEASED = 6,
933 };
934
935 /**
936 * sdw_stream_params: Stream parameters
937 *
938 * @rate: Sampling frequency, in Hz
939 * @ch_count: Number of channels
940 * @bps: bits per channel sample
941 */
942 struct sdw_stream_params {
943 unsigned int rate;
944 unsigned int ch_count;
945 unsigned int bps;
946 };
947
948 /**
949 * sdw_stream_runtime: Runtime stream parameters
950 *
951 * @name: SoundWire stream name
952 * @params: Stream parameters
953 * @state: Current state of the stream
954 * @type: Stream type PCM, PDM or BPT
955 * @m_rt_count: Count of Master runtime(s) in this stream
956 * @master_list: List of Master runtime(s) in this stream.
957 * master_list can contain only one m_rt per Master instance
958 * for a stream
959 */
960 struct sdw_stream_runtime {
961 const char *name;
962 struct sdw_stream_params params;
963 enum sdw_stream_state state;
964 enum sdw_stream_type type;
965 int m_rt_count;
966 struct list_head master_list;
967 };
968
969 /**
970 * struct sdw_bus - SoundWire bus
971 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
972 * @md: Master device
973 * @bus_lock_key: bus lock key associated to @bus_lock
974 * @bus_lock: bus lock
975 * @slave_ida: IDA for allocating internal slave IDs
976 * @slaves: list of Slaves on this bus
977 * @msg_lock_key: message lock key associated to @msg_lock
978 * @msg_lock: message lock
979 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
980 * is used to compute and program bus bandwidth, clock, frame shape,
981 * transport and port parameters
982 * @defer_msg: Defer message
983 * @params: Current bus parameters
984 * @stream_refcount: number of streams currently using this bus
985 * @btp_stream_refcount: number of BTP streams currently using this bus (should
986 * be zero or one, multiple streams per link is not supported).
987 * @bpt_stream: pointer stored to handle BTP streams.
988 * @ops: Master callback ops
989 * @port_ops: Master port callback ops
990 * @prop: Master properties
991 * @vendor_specific_prop: pointer to non-standard properties
992 * @hw_sync_min_links: Number of links used by a stream above which
993 * hardware-based synchronization is required. This value is only
994 * meaningful if multi_link is set. If set to 1, hardware-based
995 * synchronization will be used even if a stream only uses a single
996 * SoundWire segment.
997 * @controller_id: system-unique controller ID. If set to -1, the bus @id will be used.
998 * @link_id: Link id number, can be 0 to N, unique for each Controller
999 * @id: bus system-wide unique id
1000 * @compute_params: points to Bus resource management implementation
1001 * @assigned: Bitmap for Slave device numbers.
1002 * Bit set implies used number, bit clear implies unused number.
1003 * @clk_stop_timeout: Clock stop timeout computed
1004 * @bank_switch_timeout: Bank switch timeout computed
1005 * @domain: IRQ domain
1006 * @irq_chip: IRQ chip
1007 * @debugfs: Bus debugfs (optional)
1008 * @multi_link: Store bus property that indicates if multi links
1009 * are supported. This flag is populated by drivers after reading
1010 * appropriate firmware (ACPI/DT).
1011 * @lane_used_bandwidth: how much bandwidth in bits per second is used by each lane
1012 */
1013 struct sdw_bus {
1014 struct device *dev;
1015 struct sdw_master_device *md;
1016 struct lock_class_key bus_lock_key;
1017 struct mutex bus_lock;
1018 struct ida slave_ida;
1019 struct list_head slaves;
1020 struct lock_class_key msg_lock_key;
1021 struct mutex msg_lock;
1022 struct list_head m_rt_list;
1023 struct sdw_defer defer_msg;
1024 struct sdw_bus_params params;
1025 int stream_refcount;
1026 int bpt_stream_refcount;
1027 struct sdw_stream_runtime *bpt_stream;
1028 const struct sdw_master_ops *ops;
1029 const struct sdw_master_port_ops *port_ops;
1030 struct sdw_master_prop prop;
1031 void *vendor_specific_prop;
1032 int hw_sync_min_links;
1033 int controller_id;
1034 unsigned int link_id;
1035 int id;
1036 int (*compute_params)(struct sdw_bus *bus, struct sdw_stream_runtime *stream);
1037 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
1038 unsigned int clk_stop_timeout;
1039 u32 bank_switch_timeout;
1040 struct irq_chip irq_chip;
1041 struct irq_domain *domain;
1042 #ifdef CONFIG_DEBUG_FS
1043 struct dentry *debugfs;
1044 #endif
1045 bool multi_link;
1046 unsigned int lane_used_bandwidth[SDW_MAX_LANES];
1047 };
1048
1049 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name, enum sdw_stream_type type);
1050 void sdw_release_stream(struct sdw_stream_runtime *stream);
1051
1052 int sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream);
1053
1054 int sdw_stream_add_master(struct sdw_bus *bus,
1055 struct sdw_stream_config *stream_config,
1056 const struct sdw_port_config *port_config,
1057 unsigned int num_ports,
1058 struct sdw_stream_runtime *stream);
1059 int sdw_stream_remove_master(struct sdw_bus *bus,
1060 struct sdw_stream_runtime *stream);
1061 int sdw_startup_stream(void *sdw_substream);
1062 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
1063 int sdw_enable_stream(struct sdw_stream_runtime *stream);
1064 int sdw_disable_stream(struct sdw_stream_runtime *stream);
1065 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
1066 void sdw_shutdown_stream(void *sdw_substream);
1067 int sdw_bus_prep_clk_stop(struct sdw_bus *bus);
1068 int sdw_bus_clk_stop(struct sdw_bus *bus);
1069 int sdw_bus_exit_clk_stop(struct sdw_bus *bus);
1070
1071 int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id);
1072 void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id);
1073 bool is_clock_scaling_supported_by_slave(struct sdw_slave *slave);
1074
1075 int sdw_bpt_send_async(struct sdw_bus *bus, struct sdw_slave *slave, struct sdw_bpt_msg *msg);
1076 int sdw_bpt_wait(struct sdw_bus *bus, struct sdw_slave *slave, struct sdw_bpt_msg *msg);
1077 int sdw_bpt_send_sync(struct sdw_bus *bus, struct sdw_slave *slave, struct sdw_bpt_msg *msg);
1078
1079 #if IS_ENABLED(CONFIG_SOUNDWIRE)
1080
1081 int sdw_stream_add_slave(struct sdw_slave *slave,
1082 struct sdw_stream_config *stream_config,
1083 const struct sdw_port_config *port_config,
1084 unsigned int num_ports,
1085 struct sdw_stream_runtime *stream);
1086 int sdw_stream_remove_slave(struct sdw_slave *slave,
1087 struct sdw_stream_runtime *stream);
1088
1089 int sdw_slave_get_scale_index(struct sdw_slave *slave, u8 *base);
1090
1091 /* messaging and data APIs */
1092 int sdw_read(struct sdw_slave *slave, u32 addr);
1093 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
1094 int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value);
1095 int sdw_read_no_pm(struct sdw_slave *slave, u32 addr);
1096 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1097 int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1098 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1099 int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1100 int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1101 int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1102
1103 #else
1104
sdw_stream_add_slave(struct sdw_slave * slave,struct sdw_stream_config * stream_config,const struct sdw_port_config * port_config,unsigned int num_ports,struct sdw_stream_runtime * stream)1105 static inline int sdw_stream_add_slave(struct sdw_slave *slave,
1106 struct sdw_stream_config *stream_config,
1107 const struct sdw_port_config *port_config,
1108 unsigned int num_ports,
1109 struct sdw_stream_runtime *stream)
1110 {
1111 WARN_ONCE(1, "SoundWire API is disabled");
1112 return -EINVAL;
1113 }
1114
sdw_stream_remove_slave(struct sdw_slave * slave,struct sdw_stream_runtime * stream)1115 static inline int sdw_stream_remove_slave(struct sdw_slave *slave,
1116 struct sdw_stream_runtime *stream)
1117 {
1118 WARN_ONCE(1, "SoundWire API is disabled");
1119 return -EINVAL;
1120 }
1121
1122 /* messaging and data APIs */
sdw_read(struct sdw_slave * slave,u32 addr)1123 static inline int sdw_read(struct sdw_slave *slave, u32 addr)
1124 {
1125 WARN_ONCE(1, "SoundWire API is disabled");
1126 return -EINVAL;
1127 }
1128
sdw_write(struct sdw_slave * slave,u32 addr,u8 value)1129 static inline int sdw_write(struct sdw_slave *slave, u32 addr, u8 value)
1130 {
1131 WARN_ONCE(1, "SoundWire API is disabled");
1132 return -EINVAL;
1133 }
1134
sdw_write_no_pm(struct sdw_slave * slave,u32 addr,u8 value)1135 static inline int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value)
1136 {
1137 WARN_ONCE(1, "SoundWire API is disabled");
1138 return -EINVAL;
1139 }
1140
sdw_read_no_pm(struct sdw_slave * slave,u32 addr)1141 static inline int sdw_read_no_pm(struct sdw_slave *slave, u32 addr)
1142 {
1143 WARN_ONCE(1, "SoundWire API is disabled");
1144 return -EINVAL;
1145 }
1146
sdw_nread(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1147 static inline int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1148 {
1149 WARN_ONCE(1, "SoundWire API is disabled");
1150 return -EINVAL;
1151 }
1152
sdw_nread_no_pm(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1153 static inline int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1154 {
1155 WARN_ONCE(1, "SoundWire API is disabled");
1156 return -EINVAL;
1157 }
1158
sdw_nwrite(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1159 static inline int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1160 {
1161 WARN_ONCE(1, "SoundWire API is disabled");
1162 return -EINVAL;
1163 }
1164
sdw_nwrite_no_pm(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1165 static inline int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1166 {
1167 WARN_ONCE(1, "SoundWire API is disabled");
1168 return -EINVAL;
1169 }
1170
sdw_update(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1171 static inline int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1172 {
1173 WARN_ONCE(1, "SoundWire API is disabled");
1174 return -EINVAL;
1175 }
1176
sdw_update_no_pm(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1177 static inline int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1178 {
1179 WARN_ONCE(1, "SoundWire API is disabled");
1180 return -EINVAL;
1181 }
1182
1183 #endif /* CONFIG_SOUNDWIRE */
1184
1185 #endif /* __SOUNDWIRE_H */
1186